esp32c2.svd

<?xml version="1.0" encoding="UTF-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
  <vendor>ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.</vendor>
  <vendorID>ESPRESSIF</vendorID>
  <name>ESP32-C2</name>
  <series>ESP32-C2</series>
  <version>4</version>
  <description>32-bit RISC-V MCU</description>
  <licenseText>
    Copyright 2022 Espressif Systems (Shanghai) PTE LTD

    Licensed under the Apache License, Version 2.0 (the "License");
    you may not use this file except in compliance with the License.
    You may obtain a copy of the License at

        http://www.apache.org/licenses/LICENSE-2.0

    Unless required by applicable law or agreed to in writing, software
    distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    See the License for the specific language governing permissions and
    limitations under the License.
</licenseText>
  <cpu>
    <name>RV32IMC</name>
    <revision>r0p0</revision>
    <endian>little</endian>
    <mpuPresent>false</mpuPresent>
    <fpuPresent>false</fpuPresent>
    <nvicPrioBits>4</nvicPrioBits>
    <vendorSystickConfig>false</vendorSystickConfig>
  </cpu>
  <addressUnitBits>32</addressUnitBits>
  <width>32</width>
  <resetValue>0x00000000</resetValue>
  <resetMask>0xFFFFFFFF</resetMask>
  <peripherals>
    <peripheral>
      <name>APB_CTRL</name>
      <description>Advanced Peripheral Bus Controller</description>
      <groupName>APB_CTRL</groupName>
      <baseAddress>0x60026000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0xA0</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>APB_CTRL</name>
        <value>12</value>
      </interrupt>
      <registers>
        <register>
          <name>SYSCLK_CONF</name>
          <description>APB_CTRL_SYSCLK_CONF_REG</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>PRE_DIV_CNT</name>
              <description>reg_pre_div_cnt</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_320M_EN</name>
              <description>reg_clk_320m_en</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_EN</name>
              <description>reg_clk_en</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RST_TICK_CNT</name>
              <description>reg_rst_tick_cnt</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TICK_CONF</name>
          <description>APB_CTRL_TICK_CONF_REG</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <resetValue>0x00010727</resetValue>
          <fields>
            <field>
              <name>XTAL_TICK_NUM</name>
              <description>reg_xtal_tick_num</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CK8M_TICK_NUM</name>
              <description>reg_ck8m_tick_num</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TICK_ENABLE</name>
              <description>reg_tick_enable</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLK_OUT_EN</name>
          <description>APB_CTRL_CLK_OUT_EN_REG</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <resetValue>0x000007FF</resetValue>
          <fields>
            <field>
              <name>CLK20_OEN</name>
              <description>reg_clk20_oen</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK22_OEN</name>
              <description>reg_clk22_oen</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK44_OEN</name>
              <description>reg_clk44_oen</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_BB_OEN</name>
              <description>reg_clk_bb_oen</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK80_OEN</name>
              <description>reg_clk80_oen</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK160_OEN</name>
              <description>reg_clk160_oen</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_320M_OEN</name>
              <description>reg_clk_320m_oen</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_ADC_INF_OEN</name>
              <description>reg_clk_adc_inf_oen</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_DAC_CPU_OEN</name>
              <description>reg_clk_dac_cpu_oen</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK40X_BB_OEN</name>
              <description>reg_clk40x_bb_oen</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_XTAL_OEN</name>
              <description>reg_clk_xtal_oen</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WIFI_BB_CFG</name>
          <description>APB_CTRL_WIFI_BB_CFG_REG</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>WIFI_BB_CFG</name>
              <description>reg_wifi_bb_cfg</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WIFI_BB_CFG_2</name>
          <description>APB_CTRL_WIFI_BB_CFG_2_REG</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>WIFI_BB_CFG_2</name>
              <description>reg_wifi_bb_cfg_2</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WIFI_CLK_EN</name>
          <description>APB_CTRL_WIFI_CLK_EN_REG</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <resetValue>0xFFFCE030</resetValue>
          <fields>
            <field>
              <name>WIFI_CLK_EN</name>
              <description>reg_wifi_clk_en</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WIFI_RST_EN</name>
          <description>APB_CTRL_WIFI_RST_EN_REG</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>WIFI_RST</name>
              <description>reg_wifi_rst</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>HOST_INF_SEL</name>
          <description>APB_CTRL_HOST_INF_SEL_REG</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PERI_IO_SWAP</name>
              <description>reg_peri_io_swap</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>EXT_MEM_PMS_LOCK</name>
          <description>APB_CTRL_EXT_MEM_PMS_LOCK_REG</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>EXT_MEM_PMS_LOCK</name>
              <description>reg_ext_mem_pms_lock</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FLASH_ACE0_ATTR</name>
          <description>APB_CTRL_FLASH_ACE0_ATTR_REG</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000003</resetValue>
          <fields>
            <field>
              <name>FLASH_ACE0_ATTR</name>
              <description>reg_flash_ace0_attr</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FLASH_ACE1_ATTR</name>
          <description>APB_CTRL_FLASH_ACE1_ATTR_REG</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000003</resetValue>
          <fields>
            <field>
              <name>FLASH_ACE1_ATTR</name>
              <description>reg_flash_ace1_attr</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FLASH_ACE2_ATTR</name>
          <description>APB_CTRL_FLASH_ACE2_ATTR_REG</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000003</resetValue>
          <fields>
            <field>
              <name>FLASH_ACE2_ATTR</name>
              <description>reg_flash_ace2_attr</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FLASH_ACE3_ATTR</name>
          <description>APB_CTRL_FLASH_ACE3_ATTR_REG</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000003</resetValue>
          <fields>
            <field>
              <name>FLASH_ACE3_ATTR</name>
              <description>reg_flash_ace3_attr</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FLASH_ACE0_ADDR</name>
          <description>APB_CTRL_FLASH_ACE0_ADDR_REG</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>S</name>
              <description>reg_flash_ace0_addr_s</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FLASH_ACE1_ADDR</name>
          <description>APB_CTRL_FLASH_ACE1_ADDR_REG</description>
          <addressOffset>0x3C</addressOffset>
          <size>0x20</size>
          <resetValue>0x00400000</resetValue>
          <fields>
            <field>
              <name>S</name>
              <description>reg_flash_ace1_addr_s</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FLASH_ACE2_ADDR</name>
          <description>APB_CTRL_FLASH_ACE2_ADDR_REG</description>
          <addressOffset>0x40</addressOffset>
          <size>0x20</size>
          <resetValue>0x00800000</resetValue>
          <fields>
            <field>
              <name>S</name>
              <description>reg_flash_ace2_addr_s</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FLASH_ACE3_ADDR</name>
          <description>APB_CTRL_FLASH_ACE3_ADDR_REG</description>
          <addressOffset>0x44</addressOffset>
          <size>0x20</size>
          <resetValue>0x00C00000</resetValue>
          <fields>
            <field>
              <name>S</name>
              <description>reg_flash_ace3_addr_s</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FLASH_ACE0_SIZE</name>
          <description>APB_CTRL_FLASH_ACE0_SIZE_REG</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000400</resetValue>
          <fields>
            <field>
              <name>FLASH_ACE0_SIZE</name>
              <description>reg_flash_ace0_size</description>
              <bitOffset>0</bitOffset>
              <bitWidth>13</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FLASH_ACE1_SIZE</name>
          <description>APB_CTRL_FLASH_ACE1_SIZE_REG</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000400</resetValue>
          <fields>
            <field>
              <name>FLASH_ACE1_SIZE</name>
              <description>reg_flash_ace1_size</description>
              <bitOffset>0</bitOffset>
              <bitWidth>13</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FLASH_ACE2_SIZE</name>
          <description>APB_CTRL_FLASH_ACE2_SIZE_REG</description>
          <addressOffset>0x50</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000400</resetValue>
          <fields>
            <field>
              <name>FLASH_ACE2_SIZE</name>
              <description>reg_flash_ace2_size</description>
              <bitOffset>0</bitOffset>
              <bitWidth>13</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FLASH_ACE3_SIZE</name>
          <description>APB_CTRL_FLASH_ACE3_SIZE_REG</description>
          <addressOffset>0x54</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000400</resetValue>
          <fields>
            <field>
              <name>FLASH_ACE3_SIZE</name>
              <description>reg_flash_ace3_size</description>
              <bitOffset>0</bitOffset>
              <bitWidth>13</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SPI_MEM_PMS_CTRL</name>
          <description>APB_CTRL_SPI_MEM_PMS_CTRL_REG</description>
          <addressOffset>0x88</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SPI_MEM_REJECT_INT</name>
              <description>reg_spi_mem_reject_int</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SPI_MEM_REJECT_CLR</name>
              <description>reg_spi_mem_reject_clr</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SPI_MEM_REJECT_CDE</name>
              <description>reg_spi_mem_reject_cde</description>
              <bitOffset>2</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SPI_MEM_REJECT_ADDR</name>
          <description>APB_CTRL_SPI_MEM_REJECT_ADDR_REG</description>
          <addressOffset>0x8C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SPI_MEM_REJECT_ADDR</name>
              <description>reg_spi_mem_reject_addr</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SDIO_CTRL</name>
          <description>APB_CTRL_SDIO_CTRL_REG</description>
          <addressOffset>0x90</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SDIO_WIN_ACCESS_EN</name>
              <description>reg_sdio_win_access_en</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>REDCY_SIG0_REG</name>
          <description>APB_CTRL_REDCY_SIG0_REG_REG</description>
          <addressOffset>0x94</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>REDCY_SIG0</name>
              <description>reg_redcy_sig0</description>
              <bitOffset>0</bitOffset>
              <bitWidth>31</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>REDCY_ANDOR</name>
              <description>reg_redcy_andor</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>REDCY_SIG1_REG</name>
          <description>APB_CTRL_REDCY_SIG1_REG_REG</description>
          <addressOffset>0x98</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>REDCY_SIG1</name>
              <description>reg_redcy_sig1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>31</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>REDCY_NANDOR</name>
              <description>reg_redcy_nandor</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FRONT_END_MEM_PD</name>
          <description>APB_CTRL_FRONT_END_MEM_PD_REG</description>
          <addressOffset>0x9C</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000055</resetValue>
          <fields>
            <field>
              <name>AGC_MEM_FORCE_PU</name>
              <description>reg_agc_mem_force_pu</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>AGC_MEM_FORCE_PD</name>
              <description>reg_agc_mem_force_pd</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PBUS_MEM_FORCE_PU</name>
              <description>reg_pbus_mem_force_pu</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PBUS_MEM_FORCE_PD</name>
              <description>reg_pbus_mem_force_pd</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DC_MEM_FORCE_PU</name>
              <description>reg_dc_mem_force_pu</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DC_MEM_FORCE_PD</name>
              <description>reg_dc_mem_force_pd</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FREQ_MEM_FORCE_PU</name>
              <description>reg_freq_mem_force_pu</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FREQ_MEM_FORCE_PD</name>
              <description>reg_freq_mem_force_pd</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RETENTION_CTRL</name>
          <description>APB_CTRL_RETENTION_CTRL_REG</description>
          <addressOffset>0xA0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RETENTION_LINK_ADDR</name>
              <description>reg_retention_link_addr</description>
              <bitOffset>0</bitOffset>
              <bitWidth>27</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>NOBYPASS_CPU_ISO_RST</name>
              <description>reg_nobypass_cpu_iso_rst</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLKGATE_FORCE_ON</name>
          <description>Memory power configuration registers</description>
          <addressOffset>0xA4</addressOffset>
          <size>0x20</size>
          <resetValue>0x0000007F</resetValue>
          <fields>
            <field>
              <name>ROM_CLKGATE_FORCE_ON</name>
              <description>Set the bit to 1 to force rom always have clock, for low power can clear to 0 then only when have access the rom have clock</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SRAM_CLKGATE_FORCE_ON</name>
              <description>Set the bit to 1 to force sram always have clock, for low power can clear to 0 then only when have access the sram have clock</description>
              <bitOffset>3</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MEM_POWER_DOWN</name>
          <description>Memory power configuration registers</description>
          <addressOffset>0xA8</addressOffset>
          <size>0x20</size>
          <resetValue>0x0000007F</resetValue>
          <fields>
            <field>
              <name>ROM_POWER_DOWN</name>
              <description>Set 1 to let rom power down</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SRAM_POWER_DOWN</name>
              <description>Set 1 to let sram power down</description>
              <bitOffset>3</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MEM_POWER_UP</name>
          <description>Memory power configuration registers</description>
          <addressOffset>0xAC</addressOffset>
          <size>0x20</size>
          <resetValue>0x0000007F</resetValue>
          <fields>
            <field>
              <name>ROM_POWER_UP</name>
              <description>Set 1 to let rom power up</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SRAM_POWER_UP</name>
              <description>Set 1 to let sram power up</description>
              <bitOffset>3</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RND_DATA</name>
          <description>APB_CTRL_RND_DATA_REG</description>
          <addressOffset>0xB0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RND_DATA</name>
              <description>reg_rnd_data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PERI_BACKUP_CONFIG_REG</name>
          <description>APB_CTRL_PERI_BACKUP_CONFIG_REG_REG</description>
          <addressOffset>0xB4</addressOffset>
          <size>0x20</size>
          <resetValue>0x00006480</resetValue>
          <fields>
            <field>
              <name>PERI_BACKUP_FLOW_ERR</name>
              <description>reg_peri_backup_flow_err</description>
              <bitOffset>1</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PERI_BACKUP_BURST_LIMIT</name>
              <description>reg_peri_backup_burst_limit</description>
              <bitOffset>4</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PERI_BACKUP_TOUT_THRES</name>
              <description>reg_peri_backup_tout_thres</description>
              <bitOffset>9</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PERI_BACKUP_SIZE</name>
              <description>reg_peri_backup_size</description>
              <bitOffset>19</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PERI_BACKUP_START</name>
              <description>reg_peri_backup_start</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>PERI_BACKUP_TO_MEM</name>
              <description>reg_peri_backup_to_mem</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PERI_BACKUP_ENA</name>
              <description>reg_peri_backup_ena</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PERI_BACKUP_APB_ADDR_REG</name>
          <description>APB_CTRL_PERI_BACKUP_APB_ADDR_REG_REG</description>
          <addressOffset>0xB8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BACKUP_APB_START_ADDR</name>
              <description>reg_backup_apb_start_addr</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PERI_BACKUP_MEM_ADDR_REG</name>
          <description>APB_CTRL_PERI_BACKUP_MEM_ADDR_REG_REG</description>
          <addressOffset>0xBC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BACKUP_MEM_START_ADDR</name>
              <description>reg_backup_mem_start_addr</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PERI_BACKUP_INT_RAW</name>
          <description>APB_CTRL_PERI_BACKUP_INT_RAW_REG</description>
          <addressOffset>0xC0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PERI_BACKUP_DONE_INT_RAW</name>
              <description>reg_peri_backup_done_int_raw</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PERI_BACKUP_ERR_INT_RAW</name>
              <description>reg_peri_backup_err_int_raw</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PERI_BACKUP_INT_ST</name>
          <description>APB_CTRL_PERI_BACKUP_INT_ST_REG</description>
          <addressOffset>0xC4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PERI_BACKUP_DONE_INT_ST</name>
              <description>reg_peri_backup_done_int_st</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PERI_BACKUP_ERR_INT_ST</name>
              <description>reg_peri_backup_err_int_st</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PERI_BACKUP_INT_ENA</name>
          <description>APB_CTRL_PERI_BACKUP_INT_ENA_REG</description>
          <addressOffset>0xC8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PERI_BACKUP_DONE_INT_ENA</name>
              <description>reg_peri_backup_done_int_ena</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PERI_BACKUP_ERR_INT_ENA</name>
              <description>reg_peri_backup_err_int_ena</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PERI_BACKUP_INT_CLR</name>
          <description>APB_CTRL_PERI_BACKUP_INT_CLR_REG</description>
          <addressOffset>0xD0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PERI_BACKUP_DONE_INT_CLR</name>
              <description>reg_peri_backup_done_int_clr</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>PERI_BACKUP_ERR_INT_CLR</name>
              <description>reg_peri_backup_err_int_clr</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DATE</name>
          <description>APB_CTRL_DATE_REG</description>
          <addressOffset>0x3FC</addressOffset>
          <size>0x20</size>
          <resetValue>0x02106080</resetValue>
          <fields>
            <field>
              <name>DATE</name>
              <description>reg_dateVersion control</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>APB_SARADC</name>
      <description>Successive Approximation Register Analog to Digital Converter</description>
      <groupName>APB_SARADC</groupName>
      <baseAddress>0x60040000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x68</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>APB_ADC</name>
        <value>32</value>
      </interrupt>
      <registers>
        <register>
          <name>CTRL</name>
          <description>register description</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <resetValue>0x40038240</resetValue>
          <fields>
            <field>
              <name>SARADC_START_FORCE</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SARADC_START</name>
              <description>Need add description</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SARADC_SAR_CLK_GATED</name>
              <description>Need add description</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SARADC_SAR_CLK_DIV</name>
              <description>SAR clock divider</description>
              <bitOffset>7</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SARADC_SAR_PATT_LEN</name>
              <description>0 ~ 15 means length 1 ~ 16</description>
              <bitOffset>15</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SARADC_SAR_PATT_P_CLEAR</name>
              <description>clear the pointer of pattern table for DIG ADC1 CTRL</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SARADC_XPD_SAR_FORCE</name>
              <description>force option to xpd sar blocks</description>
              <bitOffset>27</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SARADC_WAIT_ARB_CYCLE</name>
              <description>wait arbit signal stable after sar_done</description>
              <bitOffset>30</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL2</name>
          <description>register description</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <resetValue>0x0000A1FE</resetValue>
          <fields>
            <field>
              <name>SARADC_MEAS_NUM_LIMIT</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SARADC_MAX_MEAS_NUM</name>
              <description>max conversion number</description>
              <bitOffset>1</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SARADC_SAR1_INV</name>
              <description>1: data to DIG ADC1 CTRL is inverted, otherwise not</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SARADC_SAR2_INV</name>
              <description>1: data to DIG ADC2 CTRL is inverted, otherwise not</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SARADC_TIMER_TARGET</name>
              <description>to set saradc timer target</description>
              <bitOffset>12</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SARADC_TIMER_EN</name>
              <description>to enable saradc timer trigger</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FILTER_CTRL1</name>
          <description>register description</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>FILTER_FACTOR1</name>
              <description>Need add description</description>
              <bitOffset>26</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FILTER_FACTOR0</name>
              <description>Need add description</description>
              <bitOffset>29</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FSM_WAIT</name>
          <description>register description</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <resetValue>0x00FF0808</resetValue>
          <fields>
            <field>
              <name>SARADC_XPD_WAIT</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SARADC_RSTB_WAIT</name>
              <description>Need add description</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SARADC_STANDBY_WAIT</name>
              <description>Need add description</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SAR1_STATUS</name>
          <description>register description</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SARADC_SAR1_STATUS</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SAR2_STATUS</name>
          <description>register description</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SARADC_SAR2_STATUS</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SAR_PATT_TAB1</name>
          <description>register description</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <resetValue>0x00FFFFFF</resetValue>
          <fields>
            <field>
              <name>SARADC_SAR_PATT_TAB1</name>
              <description>item 0 ~ 3 for pattern table 1 (each item one byte)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>24</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SAR_PATT_TAB2</name>
          <description>register description</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <resetValue>0x00FFFFFF</resetValue>
          <fields>
            <field>
              <name>SARADC_SAR_PATT_TAB2</name>
              <description>Item 4 ~ 7 for pattern table 1 (each item one byte)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>24</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ONETIME_SAMPLE</name>
          <description>register description</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <resetValue>0x1A000000</resetValue>
          <fields>
            <field>
              <name>SARADC_ONETIME_ATTEN</name>
              <description>Need add description</description>
              <bitOffset>23</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SARADC_ONETIME_CHANNEL</name>
              <description>Need add description</description>
              <bitOffset>25</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SARADC_ONETIME_START</name>
              <description>Need add description</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SARADC2_ONETIME_SAMPLE</name>
              <description>Need add description</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SARADC1_ONETIME_SAMPLE</name>
              <description>Need add description</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>APB_ADC_ARB_CTRL</name>
          <description>register description</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000900</resetValue>
          <fields>
            <field>
              <name>ADC_ARB_APB_FORCE</name>
              <description>adc2 arbiter force to enableapb controller</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADC_ARB_RTC_FORCE</name>
              <description>adc2 arbiter force to enable rtc controller</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADC_ARB_WIFI_FORCE</name>
              <description>adc2 arbiter force to enable wifi controller</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADC_ARB_GRANT_FORCE</name>
              <description>adc2 arbiter force grant</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADC_ARB_APB_PRIORITY</name>
              <description>Set adc2 arbiterapb priority</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADC_ARB_RTC_PRIORITY</name>
              <description>Set adc2 arbiter rtc priority</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADC_ARB_WIFI_PRIORITY</name>
              <description>Set adc2 arbiter wifi priority</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADC_ARB_FIX_PRIORITY</name>
              <description>adc2 arbiter uses fixed priority</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FILTER_CTRL0</name>
          <description>register description</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <resetValue>0x03740000</resetValue>
          <fields>
            <field>
              <name>FILTER_CHANNEL1</name>
              <description>Need add description</description>
              <bitOffset>18</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FILTER_CHANNEL0</name>
              <description>apb_adc1_filter_factor</description>
              <bitOffset>22</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FILTER_RESET</name>
              <description>enable apb_adc1_filter</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SAR1DATA_STATUS</name>
          <description>register description</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>APB_SARADC1_DATA</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>17</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SAR2DATA_STATUS</name>
          <description>register description</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>APB_SARADC2_DATA</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>17</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>THRES0_CTRL</name>
          <description>register description</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <resetValue>0x0003FFED</resetValue>
          <fields>
            <field>
              <name>THRES0_CHANNEL</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THRES0_HIGH</name>
              <description>saradc1's thres0 monitor thres</description>
              <bitOffset>5</bitOffset>
              <bitWidth>13</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THRES0_LOW</name>
              <description>saradc1's thres0 monitor thres</description>
              <bitOffset>18</bitOffset>
              <bitWidth>13</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>THRES1_CTRL</name>
          <description>register description</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <resetValue>0x0003FFED</resetValue>
          <fields>
            <field>
              <name>THRES1_CHANNEL</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THRES1_HIGH</name>
              <description>saradc1's thres0 monitor thres</description>
              <bitOffset>5</bitOffset>
              <bitWidth>13</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THRES1_LOW</name>
              <description>saradc1's thres0 monitor thres</description>
              <bitOffset>18</bitOffset>
              <bitWidth>13</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>THRES_CTRL</name>
          <description>register description</description>
          <addressOffset>0x3C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>THRES_ALL_EN</name>
              <description>Need add description</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THRES3_EN</name>
              <description>Need add description</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THRES2_EN</name>
              <description>Need add description</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THRES1_EN</name>
              <description>Need add description</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THRES0_EN</name>
              <description>Need add description</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_ENA</name>
          <description>register description</description>
          <addressOffset>0x40</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>THRES1_LOW_INT_ENA</name>
              <description>Need add description</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THRES0_LOW_INT_ENA</name>
              <description>Need add description</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THRES1_HIGH_INT_ENA</name>
              <description>Need add description</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THRES0_HIGH_INT_ENA</name>
              <description>Need add description</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>APB_SARADC2_DONE_INT_ENA</name>
              <description>Need add description</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>APB_SARADC1_DONE_INT_ENA</name>
              <description>Need add description</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_RAW</name>
          <description>register description</description>
          <addressOffset>0x44</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>THRES1_LOW_INT_RAW</name>
              <description>Need add description</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THRES0_LOW_INT_RAW</name>
              <description>Need add description</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THRES1_HIGH_INT_RAW</name>
              <description>Need add description</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THRES0_HIGH_INT_RAW</name>
              <description>Need add description</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>APB_SARADC2_DONE_INT_RAW</name>
              <description>Need add description</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>APB_SARADC1_DONE_INT_RAW</name>
              <description>Need add description</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_ST</name>
          <description>register description</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>THRES1_LOW_INT_ST</name>
              <description>Need add description</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THRES0_LOW_INT_ST</name>
              <description>Need add description</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THRES1_HIGH_INT_ST</name>
              <description>Need add description</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THRES0_HIGH_INT_ST</name>
              <description>Need add description</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>APB_SARADC2_DONE_INT_ST</name>
              <description>Need add description</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>APB_SARADC1_DONE_INT_ST</name>
              <description>Need add description</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_CLR</name>
          <description>register description</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>THRES1_LOW_INT_CLR</name>
              <description>Need add description</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>THRES0_LOW_INT_CLR</name>
              <description>Need add description</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>THRES1_HIGH_INT_CLR</name>
              <description>Need add description</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>THRES0_HIGH_INT_CLR</name>
              <description>Need add description</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>APB_SARADC2_DONE_INT_CLR</name>
              <description>Need add description</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>APB_SARADC1_DONE_INT_CLR</name>
              <description>Need add description</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_CONF</name>
          <description>register description</description>
          <addressOffset>0x50</addressOffset>
          <size>0x20</size>
          <resetValue>0x000000FF</resetValue>
          <fields>
            <field>
              <name>APB_ADC_EOF_NUM</name>
              <description>the dma_in_suc_eof gen when sample cnt = spi_eof_num</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>APB_ADC_RESET_FSM</name>
              <description>reset_apb_adc_state</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>APB_ADC_TRANS</name>
              <description>enable apb_adc use spi_dma</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>APB_ADC_CLKM_CONF</name>
          <description>register description</description>
          <addressOffset>0x54</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000004</resetValue>
          <fields>
            <field>
              <name>REG_CLKM_DIV_NUM</name>
              <description>Integral I2S clock divider value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>REG_CLKM_DIV_B</name>
              <description>Fractional clock divider numerator value</description>
              <bitOffset>8</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>REG_CLKM_DIV_A</name>
              <description>Fractional clock divider denominator value</description>
              <bitOffset>14</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_EN</name>
              <description>Need add description</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>REG_CLK_SEL</name>
              <description>Set this bit to enable clk_apll</description>
              <bitOffset>21</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>APB_TSENS_CTRL</name>
          <description>register description</description>
          <addressOffset>0x58</addressOffset>
          <size>0x20</size>
          <resetValue>0x00018000</resetValue>
          <fields>
            <field>
              <name>REG_TSENS_OUT</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>REG_TSENS_IN_INV</name>
              <description>Need add description</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>REG_TSENS_CLK_DIV</name>
              <description>Need add description</description>
              <bitOffset>14</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>REG_TSENS_PU</name>
              <description>Need add description</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>APB_TSENS_CTRL2</name>
          <description>register description</description>
          <addressOffset>0x5C</addressOffset>
          <size>0x20</size>
          <resetValue>0x00004002</resetValue>
          <fields>
            <field>
              <name>REG_TSENS_XPD_WAIT</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>REG_TSENS_XPD_FORCE</name>
              <description>Need add description</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>REG_TSENS_CLK_INV</name>
              <description>Need add description</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TSENS_CLK_SEL</name>
              <description>Need add description</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CALI</name>
          <description>register description</description>
          <addressOffset>0x60</addressOffset>
          <size>0x20</size>
          <resetValue>0x00008000</resetValue>
          <fields>
            <field>
              <name>CFG</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>17</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>APB_CTRL_DATE</name>
          <description>register description</description>
          <addressOffset>0x3FC</addressOffset>
          <size>0x20</size>
          <resetValue>0x02107210</resetValue>
          <fields>
            <field>
              <name>DATE</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>ASSIST_DEBUG</name>
      <description>Debug Assist</description>
      <groupName>ASSIST_DEBUG</groupName>
      <baseAddress>0x600CE000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x38</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>CORE_0_INTR_ENA</name>
          <description>core0 monitor enable configuration register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CORE_0_AREA_DRAM0_0_RD_ENA</name>
              <description>enbale sp underlow monitor</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CORE_0_AREA_DRAM0_0_WR_ENA</name>
              <description>enbale sp overflow monitor</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORE_0_INTR_RAW</name>
          <description>core0 monitor interrupt status register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CORE_0_AREA_DRAM0_0_RD_RAW</name>
              <description>sp underlow monitor interrupt status register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CORE_0_AREA_DRAM0_0_WR_RAW</name>
              <description>sp overflow monitor interupt status register</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORE_0_INTR_RLS</name>
          <description>core0 monitor interrupt enable register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CORE_0_AREA_DRAM0_0_RD_RLS</name>
              <description>enbale sp underlow monitor interrupt</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CORE_0_AREA_DRAM0_0_WR_RLS</name>
              <description>enbale sp overflow monitor interrupt</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORE_0_INTR_CLR</name>
          <description>core0 monitor interrupt clr register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CORE_0_AREA_DRAM0_0_RD_CLR</name>
              <description>clr sp underlow monitor interrupt</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORE_0_AREA_DRAM0_0_WR_CLR</name>
              <description>clr sp overflow monitor interrupt</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORE_0_SP_MIN</name>
          <description>stack min value</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CORE_0_SP_MIN</name>
              <description>core0 sp region configuration regsiter</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORE_0_SP_MAX</name>
          <description>stack max value</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <resetValue>0xFFFFFFFF</resetValue>
          <fields>
            <field>
              <name>CORE_0_SP_MAX</name>
              <description>core0 sp pc status register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORE_0_SP_PC</name>
          <description>stack monitor pc status register</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CORE_0_SP_PC</name>
              <description>This regsiter stores the PC when trigger stack monitor.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORE_0_RCD_EN</name>
          <description>record enable configuration register</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CORE_0_RCD_RECORDEN</name>
              <description>Set 1 to enable record PC</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CORE_0_RCD_PDEBUGEN</name>
              <description>Set 1 to enable cpu pdebug function, must set this bit can get cpu PC</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORE_0_RCD_PDEBUGPC</name>
          <description>record status regsiter</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CORE_0_RCD_PDEBUGPC</name>
              <description>recorded PC</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORE_0_RCD_PDEBUGSP</name>
          <description>record status regsiter</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CORE_0_RCD_PDEBUGSP</name>
              <description>recorded sp</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORE_0_LASTPC_BEFORE_EXCEPTION</name>
          <description>cpu status register</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CORE_0_LASTPC_BEFORE_EXC</name>
              <description>cpu's lastpc before exception</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORE_0_DEBUG_MODE</name>
          <description>cpu status register</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CORE_0_DEBUG_MODE</name>
              <description>cpu debug mode status, 1 means cpu enter debug mode.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CORE_0_DEBUG_MODULE_ACTIVE</name>
              <description>cpu debug_module active status</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLOCK_GATE</name>
          <description>clock gate register</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>CLK_EN</name>
              <description>clock gate register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DATE</name>
          <description>version register</description>
          <addressOffset>0x1FC</addressOffset>
          <size>0x20</size>
          <resetValue>0x02106020</resetValue>
          <fields>
            <field>
              <name>DATE</name>
              <description>version register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>28</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>DMA</name>
      <description>DMA (Direct Memory Access) Controller</description>
      <groupName>DMA</groupName>
      <baseAddress>0x6003F000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x84</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>DMA_CH0</name>
        <value>33</value>
      </interrupt>
      <registers>
        <register>
          <name>INT_RAW_CH0</name>
          <description>DMA_INT_RAW_CH0_REG.</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>IN_DONE</name>
              <description>The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>IN_SUC_EOF</name>
              <description>The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>IN_ERR_EOF</name>
              <description>The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OUT_DONE</name>
              <description>The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OUT_EOF</name>
              <description>The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>IN_DSCR_ERR</name>
              <description>The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OUT_DSCR_ERR</name>
              <description>The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>IN_DSCR_EMPTY</name>
              <description>The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OUT_TOTAL_EOF</name>
              <description>The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>INFIFO_OVF</name>
              <description>This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>INFIFO_UDF</name>
              <description>This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OUTFIFO_OVF</name>
              <description>This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OUTFIFO_UDF</name>
              <description>This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_ST_CH0</name>
          <description>DMA_INT_ST_CH0_REG.</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>IN_DONE</name>
              <description>The raw interrupt status bit for the IN_DONE_CH_INT interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>IN_SUC_EOF</name>
              <description>The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>IN_ERR_EOF</name>
              <description>The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OUT_DONE</name>
              <description>The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OUT_EOF</name>
              <description>The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>IN_DSCR_ERR</name>
              <description>The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OUT_DSCR_ERR</name>
              <description>The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>IN_DSCR_EMPTY</name>
              <description>The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OUT_TOTAL_EOF</name>
              <description>The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>INFIFO_OVF</name>
              <description>The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>INFIFO_UDF</name>
              <description>The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OUTFIFO_OVF</name>
              <description>The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OUTFIFO_UDF</name>
              <description>The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_ENA_CH0</name>
          <description>DMA_INT_ENA_CH0_REG.</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>IN_DONE</name>
              <description>The interrupt enable bit for the IN_DONE_CH_INT interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IN_SUC_EOF</name>
              <description>The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IN_ERR_EOF</name>
              <description>The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OUT_DONE</name>
              <description>The interrupt enable bit for the OUT_DONE_CH_INT interrupt.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OUT_EOF</name>
              <description>The interrupt enable bit for the OUT_EOF_CH_INT interrupt.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IN_DSCR_ERR</name>
              <description>The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OUT_DSCR_ERR</name>
              <description>The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IN_DSCR_EMPTY</name>
              <description>The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OUT_TOTAL_EOF</name>
              <description>The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INFIFO_OVF</name>
              <description>The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INFIFO_UDF</name>
              <description>The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OUTFIFO_OVF</name>
              <description>The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OUTFIFO_UDF</name>
              <description>The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_CLR_CH0</name>
          <description>DMA_INT_CLR_CH0_REG.</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>IN_DONE</name>
              <description>Set this bit to clear the IN_DONE_CH_INT interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>IN_SUC_EOF</name>
              <description>Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>IN_ERR_EOF</name>
              <description>Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>OUT_DONE</name>
              <description>Set this bit to clear the OUT_DONE_CH_INT interrupt.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>OUT_EOF</name>
              <description>Set this bit to clear the OUT_EOF_CH_INT interrupt.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>IN_DSCR_ERR</name>
              <description>Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>OUT_DSCR_ERR</name>
              <description>Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>IN_DSCR_EMPTY</name>
              <description>Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>OUT_TOTAL_EOF</name>
              <description>Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>INFIFO_OVF</name>
              <description>Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>INFIFO_UDF</name>
              <description>Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>OUTFIFO_OVF</name>
              <description>Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>OUTFIFO_UDF</name>
              <description>Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>AHB_TEST</name>
          <description>DMA_AHB_TEST_REG.</description>
          <addressOffset>0x40</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>AHB_TESTMODE</name>
              <description>reserved</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>AHB_TESTADDR</name>
              <description>reserved</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MISC_CONF</name>
          <description>DMA_MISC_CONF_REG.</description>
          <addressOffset>0x44</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>AHBM_RST_INTER</name>
              <description>Set this bit, then clear this bit to reset the internal ahb FSM.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ARB_PRI_DIS</name>
              <description>Set this bit to disable priority arbitration function.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_EN</name>
              <description>reg_clk_en</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DATE</name>
          <description>DMA_DATE_REG.</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <resetValue>0x02105280</resetValue>
          <fields>
            <field>
              <name>DATE</name>
              <description>register version.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IN_CONF0_CH0</name>
          <description>DMA_IN_CONF0_CH0_REG.</description>
          <addressOffset>0x70</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>IN_RST</name>
              <description>This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IN_LOOP_TEST</name>
              <description>reserved</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INDSCR_BURST_EN</name>
              <description>Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IN_DATA_BURST_EN</name>
              <description>Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MEM_TRANS_EN</name>
              <description>Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IN_CONF1_CH0</name>
          <description>DMA_IN_CONF1_CH0_REG.</description>
          <addressOffset>0x74</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>IN_CHECK_OWNER</name>
              <description>Set this bit to enable checking the owner attribute of the link descriptor.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INFIFO_STATUS_CH0</name>
          <description>DMA_INFIFO_STATUS_CH0_REG.</description>
          <addressOffset>0x78</addressOffset>
          <size>0x20</size>
          <resetValue>0x07800003</resetValue>
          <fields>
            <field>
              <name>INFIFO_FULL</name>
              <description>L1 Rx FIFO full signal for Rx channel 0.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>INFIFO_EMPTY</name>
              <description>L1 Rx FIFO empty signal for Rx channel 0.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>INFIFO_CNT</name>
              <description>The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>IN_REMAIN_UNDER_1B</name>
              <description>reserved</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>IN_REMAIN_UNDER_2B</name>
              <description>reserved</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>IN_REMAIN_UNDER_3B</name>
              <description>reserved</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>IN_REMAIN_UNDER_4B</name>
              <description>reserved</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>IN_BUF_HUNGRY</name>
              <description>reserved</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IN_POP_CH0</name>
          <description>DMA_IN_POP_CH0_REG.</description>
          <addressOffset>0x7C</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000800</resetValue>
          <fields>
            <field>
              <name>INFIFO_RDATA</name>
              <description>This register stores the data popping from DMA FIFO.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>INFIFO_POP</name>
              <description>Set this bit to pop data from DMA FIFO.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IN_LINK_CH0</name>
          <description>DMA_IN_LINK_CH0_REG.</description>
          <addressOffset>0x80</addressOffset>
          <size>0x20</size>
          <resetValue>0x01100000</resetValue>
          <fields>
            <field>
              <name>INLINK_ADDR</name>
              <description>This register stores the 20 least significant bits of the first inlink descriptor's address.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>20</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INLINK_AUTO_RET</name>
              <description>Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INLINK_STOP</name>
              <description>Set this bit to stop dealing with the inlink descriptors.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INLINK_START</name>
              <description>Set this bit to start dealing with the inlink descriptors.</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INLINK_RESTART</name>
              <description>Set this bit to mount a new inlink descriptor.</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INLINK_PARK</name>
              <description>1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IN_STATE_CH0</name>
          <description>DMA_IN_STATE_CH0_REG.</description>
          <addressOffset>0x84</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>INLINK_DSCR_ADDR</name>
              <description>This register stores the current inlink descriptor's address.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>18</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>IN_DSCR_STATE</name>
              <description>reserved</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>IN_STATE</name>
              <description>reserved</description>
              <bitOffset>20</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IN_SUC_EOF_DES_ADDR_CH0</name>
          <description>DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.</description>
          <addressOffset>0x88</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>IN_SUC_EOF_DES_ADDR</name>
              <description>This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IN_ERR_EOF_DES_ADDR_CH0</name>
          <description>DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.</description>
          <addressOffset>0x8C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>IN_ERR_EOF_DES_ADDR</name>
              <description>This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IN_DSCR_CH0</name>
          <description>DMA_IN_DSCR_CH0_REG.</description>
          <addressOffset>0x90</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>INLINK_DSCR</name>
              <description>The address of the current inlink descriptor x.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IN_DSCR_BF0_CH0</name>
          <description>DMA_IN_DSCR_BF0_CH0_REG.</description>
          <addressOffset>0x94</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>INLINK_DSCR_BF0</name>
              <description>The address of the last inlink descriptor x-1.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IN_DSCR_BF1_CH0</name>
          <description>DMA_IN_DSCR_BF1_CH0_REG.</description>
          <addressOffset>0x98</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>INLINK_DSCR_BF1</name>
              <description>The address of the second-to-last inlink descriptor x-2.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IN_PRI_CH0</name>
          <description>DMA_IN_PRI_CH0_REG.</description>
          <addressOffset>0x9C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RX_PRI</name>
              <description>The priority of Rx channel 0. The larger of the value, the higher of the priority.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IN_PERI_SEL_CH0</name>
          <description>DMA_IN_PERI_SEL_CH0_REG.</description>
          <addressOffset>0xA0</addressOffset>
          <size>0x20</size>
          <resetValue>0x0000003F</resetValue>
          <fields>
            <field>
              <name>PERI_IN_SEL</name>
              <description>This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OUT_CONF0_CH0</name>
          <description>DMA_OUT_CONF0_CH0_REG.</description>
          <addressOffset>0xD0</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000008</resetValue>
          <fields>
            <field>
              <name>OUT_RST</name>
              <description>This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OUT_LOOP_TEST</name>
              <description>reserved</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OUT_AUTO_WRBACK</name>
              <description>Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OUT_EOF_MODE</name>
              <description>EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OUTDSCR_BURST_EN</name>
              <description>Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OUT_DATA_BURST_EN</name>
              <description>Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OUT_CONF1_CH0</name>
          <description>DMA_OUT_CONF1_CH0_REG.</description>
          <addressOffset>0xD4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>OUT_CHECK_OWNER</name>
              <description>Set this bit to enable checking the owner attribute of the link descriptor.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OUTFIFO_STATUS_CH0</name>
          <description>DMA_OUTFIFO_STATUS_CH0_REG.</description>
          <addressOffset>0xD8</addressOffset>
          <size>0x20</size>
          <resetValue>0x07800002</resetValue>
          <fields>
            <field>
              <name>OUTFIFO_FULL</name>
              <description>L1 Tx FIFO full signal for Tx channel 0.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OUTFIFO_EMPTY</name>
              <description>L1 Tx FIFO empty signal for Tx channel 0.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OUTFIFO_CNT</name>
              <description>The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OUT_REMAIN_UNDER_1B</name>
              <description>reserved</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OUT_REMAIN_UNDER_2B</name>
              <description>reserved</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OUT_REMAIN_UNDER_3B</name>
              <description>reserved</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OUT_REMAIN_UNDER_4B</name>
              <description>reserved</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OUT_PUSH_CH0</name>
          <description>DMA_OUT_PUSH_CH0_REG.</description>
          <addressOffset>0xDC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>OUTFIFO_WDATA</name>
              <description>This register stores the data that need to be pushed into DMA FIFO.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OUTFIFO_PUSH</name>
              <description>Set this bit to push data into DMA FIFO.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OUT_LINK_CH0</name>
          <description>DMA_OUT_LINK_CH0_REG.</description>
          <addressOffset>0xE0</addressOffset>
          <size>0x20</size>
          <resetValue>0x00800000</resetValue>
          <fields>
            <field>
              <name>OUTLINK_ADDR</name>
              <description>This register stores the 20 least significant bits of the first outlink descriptor's address.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>20</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OUTLINK_STOP</name>
              <description>Set this bit to stop dealing with the outlink descriptors.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OUTLINK_START</name>
              <description>Set this bit to start dealing with the outlink descriptors.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OUTLINK_RESTART</name>
              <description>Set this bit to restart a new outlink from the last address.</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OUTLINK_PARK</name>
              <description>1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OUT_STATE_CH0</name>
          <description>DMA_OUT_STATE_CH0_REG.</description>
          <addressOffset>0xE4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>OUTLINK_DSCR_ADDR</name>
              <description>This register stores the current outlink descriptor's address.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>18</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OUT_DSCR_STATE</name>
              <description>reserved</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OUT_STATE</name>
              <description>reserved</description>
              <bitOffset>20</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OUT_EOF_DES_ADDR_CH0</name>
          <description>DMA_OUT_EOF_DES_ADDR_CH0_REG.</description>
          <addressOffset>0xE8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>OUT_EOF_DES_ADDR</name>
              <description>This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OUT_EOF_BFR_DES_ADDR_CH0</name>
          <description>DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.</description>
          <addressOffset>0xEC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>OUT_EOF_BFR_DES_ADDR</name>
              <description>This register stores the address of the outlink descriptor before the last outlink descriptor.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OUT_DSCR_CH0</name>
          <description>DMA_OUT_DSCR_CH0_REG.</description>
          <addressOffset>0xF0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>OUTLINK_DSCR</name>
              <description>The address of the current outlink descriptor y.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OUT_DSCR_BF0_CH0</name>
          <description>DMA_OUT_DSCR_BF0_CH0_REG.</description>
          <addressOffset>0xF4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>OUTLINK_DSCR_BF0</name>
              <description>The address of the last outlink descriptor y-1.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OUT_DSCR_BF1_CH0</name>
          <description>DMA_OUT_DSCR_BF1_CH0_REG.</description>
          <addressOffset>0xF8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>OUTLINK_DSCR_BF1</name>
              <description>The address of the second-to-last inlink descriptor x-2.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OUT_PRI_CH0</name>
          <description>DMA_OUT_PRI_CH0_REG.</description>
          <addressOffset>0xFC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TX_PRI</name>
              <description>The priority of Tx channel 0. The larger of the value, the higher of the priority.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OUT_PERI_SEL_CH0</name>
          <description>DMA_OUT_PERI_SEL_CH0_REG.</description>
          <addressOffset>0x100</addressOffset>
          <size>0x20</size>
          <resetValue>0x0000003F</resetValue>
          <fields>
            <field>
              <name>PERI_OUT_SEL</name>
              <description>This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>ECC</name>
      <description>ECC (ECC Hardware Accelerator)</description>
      <groupName>ECC</groupName>
      <baseAddress>0x6003E000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x18</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>MULT_INT_RAW</name>
          <description>I2S interrupt raw register, valid in level.</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CALC_DONE_INT_RAW</name>
              <description>The raw interrupt status bit  for the i2s_tx_hung_int interrupt</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MULT_INT_ST</name>
          <description>I2S interrupt status register.</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CALC_DONE_INT_ST</name>
              <description>The masked interrupt status bit  for the i2s_rx_done_int interrupt</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MULT_INT_ENA</name>
          <description>I2S interrupt enable register.</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CALC_DONE_INT_ENA</name>
              <description>The interrupt enable bit  for the i2s_rx_done_int interrupt</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MULT_INT_CLR</name>
          <description>I2S interrupt clear register.</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CALC_DONE_INT_CLR</name>
              <description>Set this bit to clear the i2s_rx_done_int interrupt</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MULT_CONF</name>
          <description>I2S RX configure register</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>START</name>
              <description>Set this bit to reset receiver</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RESET</name>
              <description>Set this bit to reset Rx AFIFO</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>KEY_LENGTH</name>
              <description>Set this bit to start receiving data</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SECURITY_MODE</name>
              <description>Set this bit to enable slave receiver mode</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_EN</name>
              <description>clk gate</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WORK_MODE</name>
              <description>Reserved</description>
              <bitOffset>5</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VERIFICATION_RESULT</name>
              <description>Reserve</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MULT_DATE</name>
          <description>Version control register</description>
          <addressOffset>0xFC</addressOffset>
          <size>0x20</size>
          <resetValue>0x02012230</resetValue>
          <fields>
            <field>
              <name>DATE</name>
              <description>ECC mult version control register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>28</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>EFUSE</name>
      <description>eFuse Controller</description>
      <groupName>EFUSE</groupName>
      <baseAddress>0x60008800</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0xC0</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>EFUSE</name>
        <value>20</value>
      </interrupt>
      <registers>
        <register>
          <name>PGM_DATA0</name>
          <description>Register 0 that stores data to be programmed.</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PGM_DATA_0</name>
              <description>The content of the 0th 32-bit data to be programmed.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PGM_DATA1</name>
          <description>Register 1 that stores data to be programmed.</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PGM_DATA_1</name>
              <description>The content of the 1st 32-bit data to be programmed.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PGM_DATA2</name>
          <description>Register 2 that stores data to be programmed.</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PGM_DATA_2</name>
              <description>The content of the 2nd 32-bit data to be programmed.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PGM_DATA3</name>
          <description>Register 3 that stores data to be programmed.</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PGM_DATA_3</name>
              <description>The content of the 3rd 32-bit data to be programmed.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PGM_DATA4</name>
          <description>Register 4 that stores data to be programmed.</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PGM_DATA_4</name>
              <description>The content of the 4th 32-bit data to be programmed.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PGM_DATA5</name>
          <description>Register 5 that stores data to be programmed.</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PGM_DATA_5</name>
              <description>The content of the 5th 32-bit data to be programmed.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PGM_DATA6</name>
          <description>Register 6 that stores data to be programmed.</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PGM_DATA_6</name>
              <description>The content of the 6th 32-bit data to be programmed.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PGM_DATA7</name>
          <description>Register 7 that stores data to be programmed.</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PGM_DATA_7</name>
              <description>The content of the 7th 32-bit data to be programmed.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PGM_CHECK_VALUE0</name>
          <description>Register 0 that stores the RS code to be programmed.</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PGM_RS_DATA_0</name>
              <description>The content of the 0th 32-bit RS code to be programmed.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PGM_CHECK_VALUE1</name>
          <description>Register 1 that stores the RS code to be programmed.</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PGM_RS_DATA_1</name>
              <description>The content of the 1st 32-bit RS code to be programmed.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PGM_CHECK_VALUE2</name>
          <description>Register 2 that stores the RS code to be programmed.</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PGM_RS_DATA_2</name>
              <description>The content of the 2nd 32-bit RS code to be programmed.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_WR_DIS</name>
          <description>BLOCK0 data register 0.</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>WR_DIS</name>
              <description>Disable programming of individual eFuses.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_REPEAT_DATA0</name>
          <description>BLOCK0 data register 1.</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RD_DIS</name>
              <description>The bit be set to disable software read high/low 128-bit of BLK3.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>WDT_DELAY_SEL</name>
              <description>Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIS_PAD_JTAG</name>
              <description>Set this bit to disable pad jtag.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIS_DOWNLOAD_ICACHE</name>
              <description>The bit be set to disable icache in download mode.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIS_DOWNLOAD_MANUAL_ENCRYPT</name>
              <description>The bit be set to disable manual encryption.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SPI_BOOT_ENCRYPT_DECRYPT_CNT</name>
              <description>These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>XTS_KEY_LENGTH_256</name>
              <description>The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwise, XTS_AES use 128-bit eFuse data in BLOCK3.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>UART_PRINT_CONTROL</name>
              <description>Set this bit to disable usb printing.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FORCE_SEND_RESUME</name>
              <description>Set this bit to force ROM code to send a resume command during SPI boot.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIS_DOWNLOAD_MODE</name>
              <description>Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7).</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIS_DIRECT_BOOT</name>
              <description>This bit set means disable direct_boot mode.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ENABLE_SECURITY_DOWNLOAD</name>
              <description>Set this bit to enable secure UART download mode.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FLASH_TPUW</name>
              <description>Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value.  Otherwise, the waiting time is twice the configurable value.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SECURE_BOOT_EN</name>
              <description>The bit be set to enable secure boot.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RPT4_RESERVED</name>
              <description>Reserved (used for four backups method).</description>
              <bitOffset>22</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_BLK1_DATA0</name>
          <description>BLOCK1 data register 0.</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SYSTEM_DATA0</name>
              <description>Stores the bits [0:31] of system data.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_BLK1_DATA1</name>
          <description>BLOCK1 data register 1.</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SYSTEM_DATA1</name>
              <description>Stores the bits [32:63] of system data.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_BLK1_DATA2</name>
          <description>BLOCK1 data register 2.</description>
          <addressOffset>0x3C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SYSTEM_DATA2</name>
              <description>Stores the bits [64:87] of system data.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>24</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_BLK2_DATA0</name>
          <description>Register 0 of BLOCK2.</description>
          <addressOffset>0x40</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BLK2_DATA0</name>
              <description>Store the bit [0:31] of MAC.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_BLK2_DATA1</name>
          <description>Register 1 of BLOCK2.</description>
          <addressOffset>0x44</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>MAC_ID_HIGH</name>
              <description>Store the bit [31:47] of MAC.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>WAFER_VERSION</name>
              <description>Store wafer version.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PKG_VERSION</name>
              <description>Store package version.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BLK2_EFUSE_VERSION</name>
              <description>Store efuse version.</description>
              <bitOffset>22</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RF_REF_I_BIAS_CONFIG</name>
              <description>Store rf configuration parameters.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>LDO_VOL_BIAS_CONFIG_LOW</name>
              <description>Store the bit [0:2] of ido configuration parameters.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_BLK2_DATA2</name>
          <description>Register 2 of BLOCK2.</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>LDO_VOL_BIAS_CONFIG_HIGH</name>
              <description>Store the bit [3:29] of ido configuration parameters.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>27</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PVT_LOW</name>
              <description>Store the bit [0:4] of pvt.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_BLK2_DATA3</name>
          <description>Register 3 of BLOCK2.</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PVT_HIGH</name>
              <description>Store the bit [5:14] of pvt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ADC_CALIBRATION_0</name>
              <description>Store the bit [0:21] of ADC calibration data.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>22</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_BLK2_DATA4</name>
          <description>Register 4 of BLOCK2.</description>
          <addressOffset>0x50</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ADC_CALIBRATION_1</name>
              <description>Store the bit [22:53] of ADC calibration data.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_BLK2_DATA5</name>
          <description>Register 5 of BLOCK2.</description>
          <addressOffset>0x54</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ADC_CALIBRATION_2</name>
              <description>Store the bit [54:85] of ADC calibration data.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_BLK2_DATA6</name>
          <description>Register 6 of BLOCK2.</description>
          <addressOffset>0x58</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ADC_CALIBRATION_3</name>
              <description>Store the bit [86:96] of ADC calibration data.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>11</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BLK2_RESERVED_DATA_0</name>
              <description>Store the bit [0:20] of block2 reserved data.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>21</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_BLK2_DATA7</name>
          <description>Register 7 of BLOCK2.</description>
          <addressOffset>0x5C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BLK2_RESERVED_DATA_1</name>
              <description>Store the bit [21:52] of block2 reserved data.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_BLK3_DATA0</name>
          <description>Register 0 of BLOCK3.</description>
          <addressOffset>0x60</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BLK3_DATA0</name>
              <description>Store the first 32-bit of Block3.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_BLK3_DATA1</name>
          <description>Register 1 of BLOCK3.</description>
          <addressOffset>0x64</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BLK3_DATA1</name>
              <description>Store the second 32-bit of Block3.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_BLK3_DATA2</name>
          <description>Register 2 of BLOCK3.</description>
          <addressOffset>0x68</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BLK3_DATA2</name>
              <description>Store the third 32-bit of Block3.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_BLK3_DATA3</name>
          <description>Register 3 of BLOCK3.</description>
          <addressOffset>0x6C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BLK3_DATA3</name>
              <description>Store the fourth 32-bit of Block3.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_BLK3_DATA4</name>
          <description>Register 4 of BLOCK3.</description>
          <addressOffset>0x70</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BLK3_DATA4</name>
              <description>Store the fifth 32-bit of Block3.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_BLK3_DATA5</name>
          <description>Register 5 of BLOCK3.</description>
          <addressOffset>0x74</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BLK3_DATA5</name>
              <description>Store the sixth 32-bit of Block3.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_BLK3_DATA6</name>
          <description>Register 6 of BLOCK3.</description>
          <addressOffset>0x78</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BLK3_DATA6</name>
              <description>Store the seventh 32-bit of Block3.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_BLK3_DATA7</name>
          <description>Register 7 of BLOCK3.</description>
          <addressOffset>0x7C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BLK3_DATA7</name>
              <description>Store the eighth 32-bit of Block3.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_REPEAT_ERR</name>
          <description>Programming error record register 0 of BLOCK0.</description>
          <addressOffset>0x80</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RD_DIS_ERR</name>
              <description>If any bit in RD_DIS is 1, then it indicates a programming error.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>WDT_DELAY_SEL_ERR</name>
              <description>If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIS_PAD_JTAG_ERR</name>
              <description>If any bit in DIS_PAD_JTAG is 1, then it indicates a programming error.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIS_DOWNLOAD_ICACHE_ERR</name>
              <description>If any bit in this filed is 1, then it indicates a programming error.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR</name>
              <description>If any bit in DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR</name>
              <description>If any bit in SPI_BOOT_ENCRYPT_DECRYPT_CNT is 1, then it indicates a programming error.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>XTS_KEY_LENGTH_256_ERR</name>
              <description>If any bit in XTS_KEY_LENGTH_256 is 1, then it indicates a programming error.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>UART_PRINT_CONTROL_ERR</name>
              <description>If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FORCE_SEND_RESUME_ERR</name>
              <description>If any bit in FORCE_SEND_RESUME is 1, then it indicates a programming error.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIS_DOWNLOAD_MODE_ERR</name>
              <description>If any bit in this filed is 1, then it indicates a programming error.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIS_DIRECT_BOOT_ERR</name>
              <description>If any bit in this filed is 1, then it indicates a programming error.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ENABLE_SECURITY_DOWNLOAD_ERR</name>
              <description>If any bit in this filed is 1, then it indicates a programming error.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FLASH_TPUW_ERR</name>
              <description>If any bit in this filed is 1, then it indicates a programming error.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SECURE_BOOT_EN_ERR</name>
              <description>If any bit in this filed is 1, then it indicates a programming error.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RPT4_RESERVED_ERR</name>
              <description>Reserved.</description>
              <bitOffset>22</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_RS_ERR</name>
          <description>Programming error record register 0 of BLOCK1-10.</description>
          <addressOffset>0x84</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BLK1_ERR_NUM</name>
              <description>The value of this signal means the number of error bytes in block1.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BLK1_FAIL</name>
              <description>0: Means no failure and that the data of block1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BLK2_ERR_NUM</name>
              <description>The value of this signal means the number of error bytes in block2.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BLK2_FAIL</name>
              <description>0: Means no failure and that the data of block2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BLK3_ERR_NUM</name>
              <description>The value of this signal means the number of error bytes in block3.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BLK3_FAIL</name>
              <description>0: Means no failure and that the block3 data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLK</name>
          <description>eFuse clcok configuration register.</description>
          <addressOffset>0x88</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000002</resetValue>
          <fields>
            <field>
              <name>EFUSE_MEM_FORCE_PD</name>
              <description>Set this bit to force eFuse SRAM into power-saving mode.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MEM_CLK_FORCE_ON</name>
              <description>Set this bit and force to activate clock signal of eFuse SRAM.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EFUSE_MEM_FORCE_PU</name>
              <description>Set this bit to force eFuse SRAM into working mode.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EN</name>
              <description>Set this bit and force to enable clock signal of eFuse memory.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CONF</name>
          <description>eFuse operation mode configuraiton register</description>
          <addressOffset>0x8C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>OP_CODE</name>
              <description>0x5A5A: Operate programming command 0x5AA5: Operate read command.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STATUS</name>
          <description>eFuse status register.</description>
          <addressOffset>0x90</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>STATE</name>
              <description>Indicates the state of the eFuse state machine.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OTP_LOAD_SW</name>
              <description>The value of OTP_LOAD_SW.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OTP_VDDQ_C_SYNC2</name>
              <description>The value of OTP_VDDQ_C_SYNC2.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OTP_STROBE_SW</name>
              <description>The value of OTP_STROBE_SW.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OTP_CSB_SW</name>
              <description>The value of OTP_CSB_SW.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OTP_PGENB_SW</name>
              <description>The value of OTP_PGENB_SW.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OTP_VDDQ_IS_SW</name>
              <description>The value of OTP_VDDQ_IS_SW.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BLK0_VALID_BIT_CNT</name>
              <description>Record the number of bit '1' in BLOCK0.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CMD</name>
          <description>eFuse command register.</description>
          <addressOffset>0x94</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>READ_CMD</name>
              <description>Set this bit to send read command.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PGM_CMD</name>
              <description>Set this bit to send programming command.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BLK_NUM</name>
              <description>The serial number of the block to be programmed. Value 0-3 corresponds to block number 0-3, respectively.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_RAW</name>
          <description>eFuse raw interrupt register.</description>
          <addressOffset>0x98</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>READ_DONE_INT_RAW</name>
              <description>The raw bit signal for read_done interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PGM_DONE_INT_RAW</name>
              <description>The raw bit signal for pgm_done interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_ST</name>
          <description>eFuse interrupt status register.</description>
          <addressOffset>0x9C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>READ_DONE_INT_ST</name>
              <description>The status signal for read_done interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PGM_DONE_INT_ST</name>
              <description>The status signal for pgm_done interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_ENA</name>
          <description>eFuse interrupt enable register.</description>
          <addressOffset>0x100</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>READ_DONE_INT_ENA</name>
              <description>The enable signal for read_done interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PGM_DONE_INT_ENA</name>
              <description>The enable signal for pgm_done interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_CLR</name>
          <description>eFuse interrupt clear register.</description>
          <addressOffset>0x104</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>READ_DONE_INT_CLR</name>
              <description>The clear signal for read_done interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>PGM_DONE_INT_CLR</name>
              <description>The clear signal for pgm_done interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DAC_CONF</name>
          <description>Controls the eFuse programming voltage.</description>
          <addressOffset>0x108</addressOffset>
          <size>0x20</size>
          <resetValue>0x0001FE1C</resetValue>
          <fields>
            <field>
              <name>DAC_CLK_DIV</name>
              <description>Controls the division factor of the rising clock of the programming voltage.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DAC_CLK_PAD_SEL</name>
              <description>Don't care.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DAC_NUM</name>
              <description>Controls the rising period of the programming voltage.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OE_CLR</name>
              <description>Reduces the power supply of the programming voltage.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_TIM_CONF</name>
          <description>Configures read timing parameters.</description>
          <addressOffset>0x10C</addressOffset>
          <size>0x20</size>
          <resetValue>0x12010201</resetValue>
          <fields>
            <field>
              <name>THR_A</name>
              <description>Configures hold time for efuse read.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TRD</name>
              <description>Configures pulse time for efuse read.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TSUR_A</name>
              <description>Configures setup time for efuse read.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>READ_INIT_NUM</name>
              <description>Configures the initial read time of eFuse.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WR_TIM_CONF0</name>
          <description>Configurarion register 0 of eFuse programming timing parameters.</description>
          <addressOffset>0x110</addressOffset>
          <size>0x20</size>
          <resetValue>0x00C80101</resetValue>
          <fields>
            <field>
              <name>THP_A</name>
              <description>Configures hold time for efuse program.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TPGM_INACTIVE</name>
              <description>Configures pulse time for burning '0' bit.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TPGM</name>
              <description>Configures pulse time for burning '1' bit.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WR_TIM_CONF1</name>
          <description>Configurarion register 1 of eFuse programming timing parameters.</description>
          <addressOffset>0x114</addressOffset>
          <size>0x20</size>
          <resetValue>0x00300001</resetValue>
          <fields>
            <field>
              <name>TSUP_A</name>
              <description>Configures setup time for efuse program.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PWR_ON_NUM</name>
              <description>Configures the power up time for VDDQ.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WR_TIM_CONF2</name>
          <description>Configurarion register 2 of eFuse programming timing parameters.</description>
          <addressOffset>0x118</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000190</resetValue>
          <fields>
            <field>
              <name>PWR_OFF_NUM</name>
              <description>Configures the power outage time for VDDQ.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DATE</name>
          <description>eFuse version register.</description>
          <addressOffset>0x1FC</addressOffset>
          <size>0x20</size>
          <resetValue>0x02108190</resetValue>
          <fields>
            <field>
              <name>DATE</name>
              <description>Stores eFuse version.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>28</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>EXTMEM</name>
      <description>External Memory</description>
      <groupName>EXTMEM</groupName>
      <baseAddress>0x600C4000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x94</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>ICACHE_CTRL</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ICACHE_ENABLE</name>
              <description>The bit is used to activate the data cache. 0: disable, 1: enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ICACHE_CTRL1</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000003</resetValue>
          <fields>
            <field>
              <name>ICACHE_SHUT_IBUS</name>
              <description>The bit is used to disable core0 ibus, 0: enable, 1: disable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ICACHE_SHUT_DBUS</name>
              <description>The bit is used to disable core1 ibus, 0: enable, 1: disable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ICACHE_TAG_POWER_CTRL</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000005</resetValue>
          <fields>
            <field>
              <name>ICACHE_TAG_MEM_FORCE_ON</name>
              <description>The bit is used to close clock gating of  icache tag memory. 1: close gating, 0: open clock gating.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ICACHE_TAG_MEM_FORCE_PD</name>
              <description>The bit is used to power  icache tag memory down, 0: follow rtc_lslp, 1: power down</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ICACHE_TAG_MEM_FORCE_PU</name>
              <description>The bit is used to power  icache tag memory up, 0: follow rtc_lslp, 1: power up</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ICACHE_SYNC_CTRL</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>ICACHE_INVALIDATE_ENA</name>
              <description>The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ICACHE_SYNC_DONE</name>
              <description>The bit is used to indicate invalidate operation is finished.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ICACHE_SYNC_ADDR</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ICACHE_SYNC_ADDR</name>
              <description>The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ICACHE_SYNC_SIZE</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ICACHE_SYNC_SIZE</name>
              <description>The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>23</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IBUS_TO_FLASH_START_VADDR</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x54</addressOffset>
          <size>0x20</size>
          <resetValue>0x42000000</resetValue>
          <fields>
            <field>
              <name>IBUS_TO_FLASH_START_VADDR</name>
              <description>The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IBUS_TO_FLASH_END_VADDR</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x58</addressOffset>
          <size>0x20</size>
          <resetValue>0x423FFFFF</resetValue>
          <fields>
            <field>
              <name>IBUS_TO_FLASH_END_VADDR</name>
              <description>The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DBUS_TO_FLASH_START_VADDR</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x5C</addressOffset>
          <size>0x20</size>
          <resetValue>0x3C000000</resetValue>
          <fields>
            <field>
              <name>DBUS_TO_FLASH_START_VADDR</name>
              <description>The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DBUS_TO_FLASH_END_VADDR</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x60</addressOffset>
          <size>0x20</size>
          <resetValue>0x3C3FFFFF</resetValue>
          <fields>
            <field>
              <name>DBUS_TO_FLASH_END_VADDR</name>
              <description>The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_ACS_CNT_CLR</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x64</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>IBUS_ACS_CNT_CLR</name>
              <description>The bit is used to clear ibus counter.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>DBUS_ACS_CNT_CLR</name>
              <description>The bit is used to clear dbus counter.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_ILG_INT_ENA</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x78</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ICACHE_SYNC_OP_FAULT_INT_ENA</name>
              <description>The bit is used to enable interrupt by sync configurations fault.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ICACHE_PRELOAD_OP_FAULT_INT_ENA</name>
              <description>The bit is used to enable interrupt by preload configurations fault.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MMU_ENTRY_FAULT_INT_ENA</name>
              <description>The bit is used to enable interrupt by mmu entry fault.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IBUS_CNT_OVF_INT_ENA</name>
              <description>The bit is used to enable interrupt by ibus counter overflow.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DBUS_CNT_OVF_INT_ENA</name>
              <description>The bit is used to enable interrupt by dbus counter overflow.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_ILG_INT_CLR</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x7C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ICACHE_SYNC_OP_FAULT_INT_CLR</name>
              <description>The bit is used to clear interrupt by sync configurations fault.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>ICACHE_PRELOAD_OP_FAULT_INT_CLR</name>
              <description>The bit is used to clear interrupt by preload configurations fault.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MMU_ENTRY_FAULT_INT_CLR</name>
              <description>The bit is used to clear interrupt by mmu entry fault.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>IBUS_CNT_OVF_INT_CLR</name>
              <description>The bit is used to clear interrupt by ibus counter overflow.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>DBUS_CNT_OVF_INT_CLR</name>
              <description>The bit is used to clear interrupt by dbus counter overflow.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_ILG_INT_ST</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x80</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ICACHE_SYNC_OP_FAULT_ST</name>
              <description>The bit is used to indicate interrupt by sync configurations fault.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ICACHE_PRELOAD_OP_FAULT_ST</name>
              <description>The bit is used to indicate interrupt by preload configurations fault.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MMU_ENTRY_FAULT_ST</name>
              <description>The bit is used to indicate interrupt by mmu entry fault.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>IBUS_ACS_CNT_OVF_ST</name>
              <description>The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>IBUS_ACS_MISS_CNT_OVF_ST</name>
              <description>The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DBUS_ACS_CNT_OVF_ST</name>
              <description>The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DBUS_ACS_FLASH_MISS_CNT_OVF_ST</name>
              <description>The bit is used to indicate interrupt by dbus access flash miss counter overflow.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORE0_ACS_CACHE_INT_ENA</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x84</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CORE0_IBUS_ACS_MSK_IC_INT_ENA</name>
              <description>The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CORE0_IBUS_WR_IC_INT_ENA</name>
              <description>The bit is used to enable interrupt by ibus trying to write icache</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CORE0_IBUS_REJECT_INT_ENA</name>
              <description>The bit is used to enable interrupt by authentication fail.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CORE0_DBUS_ACS_MSK_IC_INT_ENA</name>
              <description>The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CORE0_DBUS_REJECT_INT_ENA</name>
              <description>The bit is used to enable interrupt by authentication fail.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CORE0_DBUS_WR_IC_INT_ENA</name>
              <description>The bit is used to enable interrupt by dbus trying to write icache</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORE0_ACS_CACHE_INT_CLR</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x88</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CORE0_IBUS_ACS_MSK_IC_INT_CLR</name>
              <description>The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORE0_IBUS_WR_IC_INT_CLR</name>
              <description>The bit is used to clear interrupt by ibus trying to write icache</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORE0_IBUS_REJECT_INT_CLR</name>
              <description>The bit is used to clear interrupt by authentication fail.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORE0_DBUS_ACS_MSK_IC_INT_CLR</name>
              <description>The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORE0_DBUS_REJECT_INT_CLR</name>
              <description>The bit is used to clear interrupt by authentication fail.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORE0_DBUS_WR_IC_INT_CLR</name>
              <description>The bit is used to clear interrupt by dbus trying to write icache</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORE0_ACS_CACHE_INT_ST</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x8C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CORE0_IBUS_ACS_MSK_ICACHE_ST</name>
              <description>The bit is used to indicate interrupt by cpu access  icache while the core0_ibus is disabled or icache is disabled which include speculative access.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CORE0_IBUS_WR_ICACHE_ST</name>
              <description>The bit is used to indicate interrupt by ibus trying to write icache</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CORE0_IBUS_REJECT_ST</name>
              <description>The bit is used to indicate interrupt by authentication fail.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CORE0_DBUS_ACS_MSK_ICACHE_ST</name>
              <description>The bit is used to indicate interrupt by cpu access icache while the core0_dbus is disabled or icache is disabled which include speculative access.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CORE0_DBUS_REJECT_ST</name>
              <description>The bit is used to indicate interrupt by authentication fail.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CORE0_DBUS_WR_ICACHE_ST</name>
              <description>The bit is used to indicate interrupt by dbus trying to write icache</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORE0_DBUS_REJECT_ST</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x90</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CORE0_DBUS_ATTR</name>
              <description>The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CORE0_DBUS_WORLD</name>
              <description>The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORE0_DBUS_REJECT_VADDR</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x94</addressOffset>
          <size>0x20</size>
          <resetValue>0xFFFFFFFF</resetValue>
          <fields>
            <field>
              <name>CORE0_DBUS_VADDR</name>
              <description>The bits are used to indicate the virtual address of CPU access dbus when authentication fail.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORE0_IBUS_REJECT_ST</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x98</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CORE0_IBUS_ATTR</name>
              <description>The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CORE0_IBUS_WORLD</name>
              <description>The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORE0_IBUS_REJECT_VADDR</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x9C</addressOffset>
          <size>0x20</size>
          <resetValue>0xFFFFFFFF</resetValue>
          <fields>
            <field>
              <name>CORE0_IBUS_VADDR</name>
              <description>The bits are used to indicate the virtual address of CPU access  ibus when authentication fail.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_MMU_FAULT_CONTENT</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0xA0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CACHE_MMU_FAULT_CONTENT</name>
              <description>The bits are used to indicate the content of mmu entry which cause mmu fault..</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CACHE_MMU_FAULT_CODE</name>
              <description>The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_MMU_FAULT_VADDR</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0xA4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CACHE_MMU_FAULT_VADDR</name>
              <description>The bits are used to indicate the virtual address which cause mmu fault..</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_WRAP_AROUND_CTRL</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0xA8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CACHE_FLASH_WRAP_AROUND</name>
              <description>The bit is used to enable wrap around mode when read data from flash.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_MMU_POWER_CTRL</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0xAC</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000005</resetValue>
          <fields>
            <field>
              <name>CACHE_MMU_MEM_FORCE_ON</name>
              <description>The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CACHE_MMU_MEM_FORCE_PD</name>
              <description>The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CACHE_MMU_MEM_FORCE_PU</name>
              <description>The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_STATE</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0xB0</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>ICACHE_STATE</name>
              <description>The bit is used to indicate whether  icache main fsm is in idle state or not. 1: in idle state,  0: not in idle state</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0xB4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RECORD_DISABLE_DB_ENCRYPT</name>
              <description>Reserved.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RECORD_DISABLE_G0CB_DECRYPT</name>
              <description>Reserved.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0xB8</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000007</resetValue>
          <fields>
            <field>
              <name>CLK_FORCE_ON_MANUAL_CRYPT</name>
              <description>The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_FORCE_ON_AUTO_CRYPT</name>
              <description>The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_FORCE_ON_CRYPT</name>
              <description>The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_PRELOAD_INT_CTRL</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0xBC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ICACHE_PRELOAD_INT_ST</name>
              <description>The bit is used to indicate the interrupt by  icache pre-load done.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ICACHE_PRELOAD_INT_ENA</name>
              <description>The bit is used to enable the interrupt by  icache pre-load done.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ICACHE_PRELOAD_INT_CLR</name>
              <description>The bit is used to clear the interrupt by  icache pre-load done.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_SYNC_INT_CTRL</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0xC0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ICACHE_SYNC_INT_ST</name>
              <description>The bit is used to indicate the interrupt by  icache sync done.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ICACHE_SYNC_INT_ENA</name>
              <description>The bit is used to enable the interrupt by  icache sync done.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ICACHE_SYNC_INT_CLR</name>
              <description>The bit is used to clear the interrupt by  icache sync done.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_MMU_OWNER</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0xC4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CACHE_MMU_OWNER</name>
              <description>The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_CONF_MISC</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0xC8</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000007</resetValue>
          <fields>
            <field>
              <name>CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT</name>
              <description>The bit is used to disable checking mmu entry fault by preload operation.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT</name>
              <description>The bit is used to disable checking mmu entry fault by sync operation.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CACHE_TRACE_ENA</name>
              <description>The bit is used to enable cache trace function.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CACHE_MMU_PAGE_SIZE</name>
              <description>This bit is used to choose mmu page size. 2:64KB. 1. 32KB. 0: 16KB</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ICACHE_FREEZE</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0xCC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ENA</name>
              <description>The bit is used to enable icache freeze mode</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MODE</name>
              <description>The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert hit if CPU miss</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DONE</name>
              <description>The bit is used to indicate icache freeze success</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ICACHE_ATOMIC_OPERATE_ENA</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0xD0</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>ICACHE_ATOMIC_OPERATE_ENA</name>
              <description>The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_REQUEST</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0xD4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BYPASS</name>
              <description>The bit is used to disable request recording which could cause performance issue</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLOCK_GATE</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x100</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>CLK_EN</name>
              <description>clock gate enable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>REG_DATE</name>
          <description>This description will be updated in the near future.</description>
          <addressOffset>0x3FC</addressOffset>
          <size>0x20</size>
          <resetValue>0x02107050</resetValue>
          <fields>
            <field>
              <name>DATE</name>
              <description>version information</description>
              <bitOffset>0</bitOffset>
              <bitWidth>28</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>GPIO</name>
      <description>General Purpose Input/Output</description>
      <groupName>GPIO</groupName>
      <baseAddress>0x60004000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x314</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>GPIO</name>
        <value>13</value>
      </interrupt>
      <interrupt>
        <name>GPIO_NMI</name>
        <value>14</value>
      </interrupt>
      <registers>
        <register>
          <name>BT_SELECT</name>
          <description>GPIO bit select register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BT_SEL</name>
              <description>GPIO bit select register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OUT</name>
          <description>GPIO output register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DATA_ORIG</name>
              <description>GPIO output register for GPIO0-24</description>
              <bitOffset>0</bitOffset>
              <bitWidth>25</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OUT_W1TS</name>
          <description>GPIO output set register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>OUT_W1TS</name>
              <description>GPIO output set register for GPIO0-24</description>
              <bitOffset>0</bitOffset>
              <bitWidth>25</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OUT_W1TC</name>
          <description>GPIO output clear register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>OUT_W1TC</name>
              <description>GPIO output clear register for GPIO0-24</description>
              <bitOffset>0</bitOffset>
              <bitWidth>25</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SDIO_SELECT</name>
          <description>GPIO sdio select register</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SDIO_SEL</name>
              <description>GPIO sdio select register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ENABLE</name>
          <description>GPIO output enable register</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DATA</name>
              <description>GPIO output enable register for GPIO0-24</description>
              <bitOffset>0</bitOffset>
              <bitWidth>25</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ENABLE_W1TS</name>
          <description>GPIO output enable set register</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ENABLE_W1TS</name>
              <description>GPIO output enable set register for GPIO0-24</description>
              <bitOffset>0</bitOffset>
              <bitWidth>25</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ENABLE_W1TC</name>
          <description>GPIO output enable clear register</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ENABLE_W1TC</name>
              <description>GPIO output enable clear register for GPIO0-24</description>
              <bitOffset>0</bitOffset>
              <bitWidth>25</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STRAP</name>
          <description>pad strapping register</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>STRAPPING</name>
              <description>pad strapping register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IN</name>
          <description>GPIO input register</description>
          <addressOffset>0x3C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DATA_NEXT</name>
              <description>GPIO input register for GPIO0-24</description>
              <bitOffset>0</bitOffset>
              <bitWidth>25</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STATUS</name>
          <description>GPIO interrupt status register</description>
          <addressOffset>0x44</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>INTERRUPT</name>
              <description>GPIO interrupt status register for GPIO0-24</description>
              <bitOffset>0</bitOffset>
              <bitWidth>25</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STATUS_W1TS</name>
          <description>GPIO interrupt status set register</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>STATUS_W1TS</name>
              <description>GPIO interrupt status set register for GPIO0-24</description>
              <bitOffset>0</bitOffset>
              <bitWidth>25</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STATUS_W1TC</name>
          <description>GPIO interrupt status clear register</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>STATUS_W1TC</name>
              <description>GPIO interrupt status clear register for GPIO0-24</description>
              <bitOffset>0</bitOffset>
              <bitWidth>25</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PCPU_INT</name>
          <description>GPIO PRO_CPU interrupt status register</description>
          <addressOffset>0x5C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PROCPU_INT</name>
              <description>GPIO PRO_CPU interrupt status register for GPIO0-24</description>
              <bitOffset>0</bitOffset>
              <bitWidth>25</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PCPU_NMI_INT</name>
          <description>GPIO PRO_CPU(not shielded) interrupt status register</description>
          <addressOffset>0x60</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PROCPU_NMI_INT</name>
              <description>GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-24</description>
              <bitOffset>0</bitOffset>
              <bitWidth>25</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPUSDIO_INT</name>
          <description>GPIO CPUSDIO interrupt status register</description>
          <addressOffset>0x64</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SDIO_INT</name>
              <description>GPIO CPUSDIO interrupt status register for GPIO0-24</description>
              <bitOffset>0</bitOffset>
              <bitWidth>25</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>25</dim>
          <dimIncrement>0x4</dimIncrement>
          <dimIndex>0-24</dimIndex>
          <name>PIN%s</name>
          <description>GPIO pin configuration register</description>
          <addressOffset>0x74</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SYNC2_BYPASS</name>
              <description>set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PAD_DRIVER</name>
              <description>set this bit to select pad driver. 1:open-drain. 0:normal.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SYNC1_BYPASS</name>
              <description>set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INT_TYPE</name>
              <description>set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level</description>
              <bitOffset>7</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WAKEUP_ENABLE</name>
              <description>set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CONFIG</name>
              <description>reserved</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INT_ENA</name>
              <description>set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STATUS_NEXT</name>
          <description>GPIO interrupt source register</description>
          <addressOffset>0x14C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>STATUS_INTERRUPT_NEXT</name>
              <description>GPIO interrupt source register for GPIO0-24</description>
              <bitOffset>0</bitOffset>
              <bitWidth>26</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>128</dim>
          <dimIncrement>0x4</dimIncrement>
          <dimIndex>0-127</dimIndex>
          <name>FUNC%s_IN_SEL_CFG</name>
          <description>GPIO input function configuration register</description>
          <addressOffset>0x154</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>IN_SEL</name>
              <description>set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IN_INV_SEL</name>
              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SEL</name>
              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>25</dim>
          <dimIncrement>0x4</dimIncrement>
          <dimIndex>0-24</dimIndex>
          <name>FUNC%s_OUT_SEL_CFG</name>
          <description>GPIO output function select register</description>
          <addressOffset>0x554</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000080</resetValue>
          <fields>
            <field>
              <name>OUT_SEL</name>
              <description>The value of the bits: 0&lt;=s&lt;=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n].</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INV_SEL</name>
              <description>set this bit to invert output signal.1:invert.0:not invert.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OEN_SEL</name>
              <description>set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OEN_INV_SEL</name>
              <description>set this bit to invert output enable signal.1:invert.0:not invert.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLOCK_GATE_REG</name>
          <description>GPIO clock gate register</description>
          <addressOffset>0x62C</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>CLK_EN</name>
              <description>set this bit to enable GPIO clock gate</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>REG_DATE_REG</name>
          <description>GPIO version register</description>
          <addressOffset>0x6FC</addressOffset>
          <size>0x20</size>
          <resetValue>0x02106190</resetValue>
          <fields>
            <field>
              <name>REG_DATE</name>
              <description>version register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>28</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>I2C0</name>
      <description>I2C (Inter-Integrated Circuit) Controller</description>
      <groupName>I2C</groupName>
      <baseAddress>0x60013000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x88</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>I2C_MST</name>
        <value>11</value>
      </interrupt>
      <interrupt>
        <name>I2C_EXT0</name>
        <value>22</value>
      </interrupt>
      <registers>
        <register>
          <name>SCL_LOW_PERIOD</name>
          <description>Configures the low level width of the SCL
Clock</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SCL_LOW_PERIOD</name>
              <description>This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTR</name>
          <description>Transmission setting</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <resetValue>0x0000020B</resetValue>
          <fields>
            <field>
              <name>SDA_FORCE_OUT</name>
              <description>0: direct output, 1: open drain output.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCL_FORCE_OUT</name>
              <description>0: direct output, 1: open drain output.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SAMPLE_SCL_LEVEL</name>
              <description>This register is used to select the sample mode.
1: sample SDA data on the SCL low level.
0: sample SDA data on the SCL high level.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_FULL_ACK_LEVEL</name>
              <description>This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MS_MODE</name>
              <description>Set this bit to configure the module as an I2C Master. Clear this bit to configure the
module as an I2C Slave.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TRANS_START</name>
              <description>Set this bit to start sending the data in txfifo.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>TX_LSB_FIRST</name>
              <description>This bit is used to control the sending mode for data needing to be sent.
1: send data from the least significant bit,
0: send data from the most significant bit.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_LSB_FIRST</name>
              <description>This bit is used to control the storage mode for received data.
1: receive data from the least significant bit,
0: receive data from the most significant bit.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_EN</name>
              <description>Reserved</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ARBITRATION_EN</name>
              <description>This is the enable bit for arbitration_lost.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FSM_RST</name>
              <description>This register is used to reset the scl FMS.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CONF_UPGATE</name>
              <description>synchronization bit</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_TX_AUTO_START_EN</name>
              <description>This is the enable bit for slave to send data automatically</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SR</name>
          <description>Describe I2C work status.</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RESP_REC</name>
              <description>The received ACK value in master mode or slave mode. 0: ACK, 1: NACK.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ARB_LOST</name>
              <description>When the I2C controller loses control of SCL line, this register changes to 1.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BUS_BUSY</name>
              <description>1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXFIFO_CNT</name>
              <description>This field represents the amount of data needed to be sent.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXFIFO_CNT</name>
              <description>This field stores the amount of received data in RAM.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SCL_MAIN_STATE_LAST</name>
              <description>This field indicates the states of the I2C module state machine.
0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK</description>
              <bitOffset>24</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SCL_STATE_LAST</name>
              <description>This field indicates the states of the state machine used to produce SCL.
0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop</description>
              <bitOffset>28</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TO</name>
          <description>Setting time out control for receiving data.</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000010</resetValue>
          <fields>
            <field>
              <name>TIME_OUT_VALUE</name>
              <description>This register is used to configure the timeout for receiving a data bit in APB
clock cycles.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TIME_OUT_EN</name>
              <description>This is the enable bit for time out control.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIFO_ST</name>
          <description>FIFO status register.</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RXFIFO_RADDR</name>
              <description>This is the offset address of the APB reading from rxfifo</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXFIFO_WADDR</name>
              <description>This is the offset address of i2c module receiving data and writing to rxfifo.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXFIFO_RADDR</name>
              <description>This is the offset address of i2c module reading from txfifo.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXFIFO_WADDR</name>
              <description>This is the offset address of APB bus writing to txfifo.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIFO_CONF</name>
          <description>FIFO configuration register.</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <resetValue>0x00004046</resetValue>
          <fields>
            <field>
              <name>RXFIFO_WM_THRHD</name>
              <description>The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TXFIFO_WM_THRHD</name>
              <description>The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>NONFIFO_EN</name>
              <description>Set this bit to enable APB nonfifo access.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_FIFO_RST</name>
              <description>Set this bit to reset rx-fifo.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_FIFO_RST</name>
              <description>Set this bit to reset tx-fifo.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIFO_PRT_EN</name>
              <description>The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DATA</name>
          <description>Rx FIFO read data.</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>FIFO_RDATA</name>
              <description>The value of rx FIFO read data.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_RAW</name>
          <description>Raw interrupt status</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000002</resetValue>
          <fields>
            <field>
              <name>RXFIFO_WM_INT_RAW</name>
              <description>The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXFIFO_WM_INT_RAW</name>
              <description>The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXFIFO_OVF_INT_RAW</name>
              <description>The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>END_DETECT_INT_RAW</name>
              <description>The raw interrupt bit for the I2C_END_DETECT_INT interrupt.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BYTE_TRANS_DONE_INT_RAW</name>
              <description>The raw interrupt bit for the I2C_END_DETECT_INT interrupt.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ARBITRATION_LOST_INT_RAW</name>
              <description>The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MST_TXFIFO_UDF_INT_RAW</name>
              <description>The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TRANS_COMPLETE_INT_RAW</name>
              <description>The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TIME_OUT_INT_RAW</name>
              <description>The raw interrupt bit for the I2C_TIME_OUT_INT interrupt.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TRANS_START_INT_RAW</name>
              <description>The raw interrupt bit for the I2C_TRANS_START_INT interrupt.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>NACK_INT_RAW</name>
              <description>The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXFIFO_OVF_INT_RAW</name>
              <description>The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXFIFO_UDF_INT_RAW</name>
              <description>The raw interrupt bit for I2C_RXFIFO_UDF_INT  interrupt.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SCL_ST_TO_INT_RAW</name>
              <description>The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SCL_MAIN_ST_TO_INT_RAW</name>
              <description>The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DET_START_INT_RAW</name>
              <description>The raw interrupt bit for I2C_DET_START_INT interrupt.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_CLR</name>
          <description>Interrupt clear bits</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RXFIFO_WM_INT_CLR</name>
              <description>Set this bit to clear I2C_RXFIFO_WM_INT interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>TXFIFO_WM_INT_CLR</name>
              <description>Set this bit to clear I2C_TXFIFO_WM_INT interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>RXFIFO_OVF_INT_CLR</name>
              <description>Set this bit to clear I2C_RXFIFO_OVF_INT interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>END_DETECT_INT_CLR</name>
              <description>Set this bit to clear the I2C_END_DETECT_INT interrupt.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>BYTE_TRANS_DONE_INT_CLR</name>
              <description>Set this bit to clear the I2C_END_DETECT_INT interrupt.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>ARBITRATION_LOST_INT_CLR</name>
              <description>Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MST_TXFIFO_UDF_INT_CLR</name>
              <description>Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>TRANS_COMPLETE_INT_CLR</name>
              <description>Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>TIME_OUT_INT_CLR</name>
              <description>Set this bit to clear the I2C_TIME_OUT_INT interrupt.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>TRANS_START_INT_CLR</name>
              <description>Set this bit to clear the I2C_TRANS_START_INT interrupt.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>NACK_INT_CLR</name>
              <description>Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>TXFIFO_OVF_INT_CLR</name>
              <description>Set this bit to clear I2C_TXFIFO_OVF_INT interrupt.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>RXFIFO_UDF_INT_CLR</name>
              <description>Set this bit to clear I2C_RXFIFO_UDF_INT  interrupt.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SCL_ST_TO_INT_CLR</name>
              <description>Set this bit to clear I2C_SCL_ST_TO_INT interrupt.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SCL_MAIN_ST_TO_INT_CLR</name>
              <description>Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>DET_START_INT_CLR</name>
              <description>Set this bit to clear I2C_DET_START_INT interrupt.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_ENA</name>
          <description>Interrupt enable bits</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RXFIFO_WM_INT_ENA</name>
              <description>The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TXFIFO_WM_INT_ENA</name>
              <description>The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RXFIFO_OVF_INT_ENA</name>
              <description>The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>END_DETECT_INT_ENA</name>
              <description>The interrupt enable bit for the I2C_END_DETECT_INT interrupt.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BYTE_TRANS_DONE_INT_ENA</name>
              <description>The interrupt enable bit for the I2C_END_DETECT_INT interrupt.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ARBITRATION_LOST_INT_ENA</name>
              <description>The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MST_TXFIFO_UDF_INT_ENA</name>
              <description>The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TRANS_COMPLETE_INT_ENA</name>
              <description>The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TIME_OUT_INT_ENA</name>
              <description>The interrupt enable bit for the I2C_TIME_OUT_INT interrupt.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TRANS_START_INT_ENA</name>
              <description>The interrupt enable bit for the I2C_TRANS_START_INT interrupt.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>NACK_INT_ENA</name>
              <description>The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TXFIFO_OVF_INT_ENA</name>
              <description>The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RXFIFO_UDF_INT_ENA</name>
              <description>The interrupt enable bit for I2C_RXFIFO_UDF_INT  interrupt.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCL_ST_TO_INT_ENA</name>
              <description>The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCL_MAIN_ST_TO_INT_ENA</name>
              <description>The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DET_START_INT_ENA</name>
              <description>The interrupt enable bit for I2C_DET_START_INT interrupt.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_STATUS</name>
          <description>Status of captured I2C communication events</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RXFIFO_WM_INT_ST</name>
              <description>The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXFIFO_WM_INT_ST</name>
              <description>The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXFIFO_OVF_INT_ST</name>
              <description>The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>END_DETECT_INT_ST</name>
              <description>The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BYTE_TRANS_DONE_INT_ST</name>
              <description>The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ARBITRATION_LOST_INT_ST</name>
              <description>The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MST_TXFIFO_UDF_INT_ST</name>
              <description>The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TRANS_COMPLETE_INT_ST</name>
              <description>The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TIME_OUT_INT_ST</name>
              <description>The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TRANS_START_INT_ST</name>
              <description>The masked interrupt status bit for the I2C_TRANS_START_INT interrupt.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>NACK_INT_ST</name>
              <description>The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXFIFO_OVF_INT_ST</name>
              <description>The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXFIFO_UDF_INT_ST</name>
              <description>The masked interrupt status bit for I2C_RXFIFO_UDF_INT  interrupt.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SCL_ST_TO_INT_ST</name>
              <description>The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SCL_MAIN_ST_TO_INT_ST</name>
              <description>The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DET_START_INT_ST</name>
              <description>The masked interrupt status bit for I2C_DET_START_INT interrupt.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SDA_HOLD</name>
          <description>Configures the hold time after a negative SCL edge.</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIME</name>
              <description>This register is used to configure the time to hold the data after the negative
edge of SCL, in I2C module clock cycles.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SDA_SAMPLE</name>
          <description>Configures the sample time after a positive SCL edge.</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIME</name>
              <description>This register is used to configure for how long SDA is sampled, in I2C module clock cycles.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SCL_HIGH_PERIOD</name>
          <description>Configures the high level width of SCL</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SCL_HIGH_PERIOD</name>
              <description>This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCL_WAIT_HIGH_PERIOD</name>
              <description>This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SCL_START_HOLD</name>
          <description>Configures the delay between the SDA and SCL negative edge for a start condition</description>
          <addressOffset>0x40</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000008</resetValue>
          <fields>
            <field>
              <name>TIME</name>
              <description>This register is used to configure the time between the negative edge
of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SCL_RSTART_SETUP</name>
          <description>Configures the delay between the positive
edge of SCL and the negative edge of SDA</description>
          <addressOffset>0x44</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000008</resetValue>
          <fields>
            <field>
              <name>TIME</name>
              <description>This register is used to configure the time between the positive
edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SCL_STOP_HOLD</name>
          <description>Configures the delay after the SCL clock
edge for a stop condition</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000008</resetValue>
          <fields>
            <field>
              <name>TIME</name>
              <description>This register is used to configure the delay after the STOP condition,
in I2C module clock cycles.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SCL_STOP_SETUP</name>
          <description>Configures the delay between the SDA and
SCL positive edge for a stop condition</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000008</resetValue>
          <fields>
            <field>
              <name>TIME</name>
              <description>This register is used to configure the time between the positive edge
of SCL and the positive edge of SDA, in I2C module clock cycles.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FILTER_CFG</name>
          <description>SCL and SDA filter configuration register</description>
          <addressOffset>0x50</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000300</resetValue>
          <fields>
            <field>
              <name>SCL_FILTER_THRES</name>
              <description>When a pulse on the SCL input has smaller width than this register value
in I2C module clock cycles, the I2C controller will ignore that pulse.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SDA_FILTER_THRES</name>
              <description>When a pulse on the SDA input has smaller width than this register value
in I2C module clock cycles, the I2C controller will ignore that pulse.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCL_FILTER_EN</name>
              <description>This is the filter enable bit for SCL.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SDA_FILTER_EN</name>
              <description>This is the filter enable bit for SDA.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLK_CONF</name>
          <description>I2C CLK configuration register</description>
          <addressOffset>0x54</addressOffset>
          <size>0x20</size>
          <resetValue>0x00200000</resetValue>
          <fields>
            <field>
              <name>SCLK_DIV_NUM</name>
              <description>the integral part of the fractional divisor for i2c module</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCLK_DIV_A</name>
              <description>the numerator of the fractional part of the fractional divisor for i2c module</description>
              <bitOffset>8</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCLK_DIV_B</name>
              <description>the denominator of the fractional part of the fractional divisor for i2c module</description>
              <bitOffset>14</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCLK_SEL</name>
              <description>The clock selection for i2c module:0-XTAL,1-CLK_8MHz.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCLK_ACTIVE</name>
              <description>The clock switch for i2c module</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>8</dim>
          <dimIncrement>0x4</dimIncrement>
          <dimIndex>0-7</dimIndex>
          <name>COMD%s</name>
          <description>I2C command register %s</description>
          <addressOffset>0x58</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>COMMAND</name>
              <description>This is the content of command 0. It consists of three parts:
op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
Byte_num represents the number of bytes that need to be sent or received.
ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
Information.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>14</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>COMMAND_DONE</name>
              <description>When command 0 is done in I2C Master mode, this bit changes to high
level.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SCL_ST_TIME_OUT</name>
          <description>SCL status time out register</description>
          <addressOffset>0x78</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000010</resetValue>
          <fields>
            <field>
              <name>SCL_ST_TO_I2C</name>
              <description>The threshold value of SCL_FSM state unchanged period. It should be o more than 23</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SCL_MAIN_ST_TIME_OUT</name>
          <description>SCL main status time out register</description>
          <addressOffset>0x7C</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000010</resetValue>
          <fields>
            <field>
              <name>SCL_MAIN_ST_TO_I2C</name>
              <description>The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SCL_SP_CONF</name>
          <description>Power configuration register</description>
          <addressOffset>0x80</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SCL_RST_SLV_EN</name>
              <description>When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0].</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCL_RST_SLV_NUM</name>
              <description>Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCL_PD_EN</name>
              <description>The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SDA_PD_EN</name>
              <description>The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DATE</name>
          <description>Version register</description>
          <addressOffset>0xF8</addressOffset>
          <size>0x20</size>
          <resetValue>0x02106243</resetValue>
          <fields>
            <field>
              <name>DATE</name>
              <description>This is the the version register.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TXFIFO_START_ADDR</name>
          <description>I2C TXFIFO base address register</description>
          <addressOffset>0x100</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TXFIFO_START_ADDR</name>
              <description>This is the I2C txfifo first address.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RXFIFO_START_ADDR</name>
          <description>I2C RXFIFO base address register</description>
          <addressOffset>0x180</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RXFIFO_START_ADDR</name>
              <description>This is the I2C rxfifo first address.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>INTERRUPT_CORE0</name>
      <description>Interrupt Core</description>
      <groupName>INTERRUPT_CORE0</groupName>
      <baseAddress>0x600C2000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x150</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>MAC_INTR_MAP</name>
          <description>register description</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>WIFI_MAC_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WIFI_MAC_NMI_MAP</name>
          <description>register description</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>WIFI_MAC_NMI_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WIFI_PWR_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>WIFI_PWR_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WIFI_BB_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>WIFI_BB_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>BT_MAC_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BT_MAC_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>BT_BB_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BT_BB_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>BT_BB_NMI_MAP</name>
          <description>register description</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BT_BB_NMI_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LP_TIMER_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>LP_TIMER_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COEX_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>COEX_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>BLE_TIMER_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BLE_TIMER_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>BLE_SEC_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BLE_SEC_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_MST_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>I2C_MST_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>APB_CTRL_INTR_MAP</name>
          <description>register description</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>APB_CTRL_INTR_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>GPIO_INTERRUPT_PRO_MAP</name>
          <description>register description</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>GPIO_INTERRUPT_PRO_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>GPIO_INTERRUPT_PRO_NMI_MAP</name>
          <description>register description</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>GPIO_INTERRUPT_PRO_NMI_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SPI_INTR_1_MAP</name>
          <description>register description</description>
          <addressOffset>0x3C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SPI_INTR_1_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SPI_INTR_2_MAP</name>
          <description>register description</description>
          <addressOffset>0x40</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SPI_INTR_2_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>UART_INTR_MAP</name>
          <description>register description</description>
          <addressOffset>0x44</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>UART_INTR_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>UART1_INTR_MAP</name>
          <description>register description</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>UART1_INTR_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LEDC_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>LEDC_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>EFUSE_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x50</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>EFUSE_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RTC_CORE_INTR_MAP</name>
          <description>register description</description>
          <addressOffset>0x54</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RTC_CORE_INTR_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_EXT0_INTR_MAP</name>
          <description>register description</description>
          <addressOffset>0x58</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>I2C_EXT0_INTR_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TG_T0_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x5C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TG_T0_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TG_WDT_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x60</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TG_WDT_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_IA_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x64</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CACHE_IA_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SYSTIMER_TARGET0_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x68</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SYSTIMER_TARGET0_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SYSTIMER_TARGET1_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x6C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SYSTIMER_TARGET1_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SYSTIMER_TARGET2_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x70</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SYSTIMER_TARGET2_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SPI_MEM_REJECT_INTR_MAP</name>
          <description>register description</description>
          <addressOffset>0x74</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SPI_MEM_REJECT_INTR_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ICACHE_PRELOAD_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x78</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ICACHE_PRELOAD_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ICACHE_SYNC_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x7C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ICACHE_SYNC_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>APB_ADC_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x80</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>APB_ADC_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_CH0_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x84</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DMA_CH0_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SHA_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x88</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SHA_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ECC_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0x8C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ECC_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INTR_FROM_CPU_0_MAP</name>
          <description>register description</description>
          <addressOffset>0x90</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_INTR_FROM_CPU_0_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INTR_FROM_CPU_1_MAP</name>
          <description>register description</description>
          <addressOffset>0x94</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_INTR_FROM_CPU_1_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INTR_FROM_CPU_2_MAP</name>
          <description>register description</description>
          <addressOffset>0x98</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_INTR_FROM_CPU_2_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INTR_FROM_CPU_3_MAP</name>
          <description>register description</description>
          <addressOffset>0x9C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_INTR_FROM_CPU_3_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ASSIST_DEBUG_INTR_MAP</name>
          <description>register description</description>
          <addressOffset>0xA0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ASSIST_DEBUG_INTR_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP</name>
          <description>register description</description>
          <addressOffset>0xA4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_CORE0_ACS_INT_MAP</name>
          <description>register description</description>
          <addressOffset>0xA8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CACHE_CORE0_ACS_INT_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTR_STATUS_REG_0</name>
          <description>register description</description>
          <addressOffset>0xAC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>INTR_STATUS_0</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTR_STATUS_REG_1</name>
          <description>register description</description>
          <addressOffset>0xB0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>INTR_STATUS_1</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLOCK_GATE</name>
          <description>register description</description>
          <addressOffset>0xB4</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>REG_CLK_EN</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_ENABLE</name>
          <description>register description</description>
          <addressOffset>0xB8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_INT_ENABLE</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_TYPE</name>
          <description>register description</description>
          <addressOffset>0xBC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_INT_TYPE</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_CLEAR</name>
          <description>register description</description>
          <addressOffset>0xC0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_INT_CLEAR</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_EIP_STATUS</name>
          <description>register description</description>
          <addressOffset>0xC4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_INT_EIP_STATUS</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_0</name>
          <description>register description</description>
          <addressOffset>0xC8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_0_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_1</name>
          <description>register description</description>
          <addressOffset>0xCC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_1_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_2</name>
          <description>register description</description>
          <addressOffset>0xD0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_2_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_3</name>
          <description>register description</description>
          <addressOffset>0xD4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_3_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_4</name>
          <description>register description</description>
          <addressOffset>0xD8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_4_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_5</name>
          <description>register description</description>
          <addressOffset>0xDC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_5_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_6</name>
          <description>register description</description>
          <addressOffset>0xE0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_6_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_7</name>
          <description>register description</description>
          <addressOffset>0xE4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_7_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_8</name>
          <description>register description</description>
          <addressOffset>0xE8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_8_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_9</name>
          <description>register description</description>
          <addressOffset>0xEC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_9_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_10</name>
          <description>register description</description>
          <addressOffset>0xF0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_10_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_11</name>
          <description>register description</description>
          <addressOffset>0xF4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_11_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_12</name>
          <description>register description</description>
          <addressOffset>0xF8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_12_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_13</name>
          <description>register description</description>
          <addressOffset>0xFC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_13_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_14</name>
          <description>register description</description>
          <addressOffset>0x100</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_14_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_15</name>
          <description>register description</description>
          <addressOffset>0x104</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_15_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_16</name>
          <description>register description</description>
          <addressOffset>0x108</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_16_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_17</name>
          <description>register description</description>
          <addressOffset>0x10C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_17_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_18</name>
          <description>register description</description>
          <addressOffset>0x110</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_18_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_19</name>
          <description>register description</description>
          <addressOffset>0x114</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_19_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_20</name>
          <description>register description</description>
          <addressOffset>0x118</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_20_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_21</name>
          <description>register description</description>
          <addressOffset>0x11C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_21_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_22</name>
          <description>register description</description>
          <addressOffset>0x120</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_22_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_23</name>
          <description>register description</description>
          <addressOffset>0x124</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_23_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_24</name>
          <description>register description</description>
          <addressOffset>0x128</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_24_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_25</name>
          <description>register description</description>
          <addressOffset>0x12C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_25_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_26</name>
          <description>register description</description>
          <addressOffset>0x130</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_26_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_27</name>
          <description>register description</description>
          <addressOffset>0x134</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_27_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_28</name>
          <description>register description</description>
          <addressOffset>0x138</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_28_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_29</name>
          <description>register description</description>
          <addressOffset>0x13C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_29_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_30</name>
          <description>register description</description>
          <addressOffset>0x140</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_30_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_PRI_31</name>
          <description>register description</description>
          <addressOffset>0x144</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_PRI_31_MAP</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INT_THRESH</name>
          <description>register description</description>
          <addressOffset>0x148</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_INT_THRESH</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTERRUPT_REG_DATE</name>
          <description>register description</description>
          <addressOffset>0x7FC</addressOffset>
          <size>0x20</size>
          <resetValue>0x02108190</resetValue>
          <fields>
            <field>
              <name>INTERRUPT_REG_DATE</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>28</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>IO_MUX</name>
      <description>Input/Output Multiplexer</description>
      <groupName>IO_MUX</groupName>
      <baseAddress>0x60009000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x5C</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>PIN_CTRL</name>
          <description>Clock Output Configuration Register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <resetValue>0x000007FF</resetValue>
          <fields>
            <field>
              <name>CLK_OUT1</name>
              <description>If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_OUT2</name>
              <description>If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_OUT3</name>
              <description>If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>21</dim>
          <dimIncrement>0x4</dimIncrement>
          <name>GPIO%s</name>
          <description>IO MUX Configure Register for pad XTAL_32K_P</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000B00</resetValue>
          <fields>
            <field>
              <name>MCU_OE</name>
              <description>Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLP_SEL</name>
              <description>Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MCU_WPD</name>
              <description>Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MCU_WPU</name>
              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MCU_IE</name>
              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FUN_WPD</name>
              <description>Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FUN_WPU</name>
              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FUN_IE</name>
              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FUN_DRV</name>
              <description>Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MCU_SEL</name>
              <description>Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FILTER_EN</name>
              <description>Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DATE</name>
          <description>IO MUX Version Control Register</description>
          <addressOffset>0xFC</addressOffset>
          <size>0x20</size>
          <resetValue>0x02106190</resetValue>
          <fields>
            <field>
              <name>REG_DATE</name>
              <description>Version control register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>28</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>LEDC</name>
      <description>LED PWM (Pulse Width Modulation) Controller</description>
      <groupName>LEDC</groupName>
      <baseAddress>0x60019000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0xB0</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>LEDC</name>
        <value>19</value>
      </interrupt>
      <registers>
        <register>
          <dim>6</dim>
          <dimIncrement>0x14</dimIncrement>
          <name>CH%s_CONF0</name>
          <description>Configuration register 0 for channel %s</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_SEL</name>
              <description>This field is used to select one of timers for channel %s.

0: select timer0; 1: select timer1; 2: select timer2; 3: select timer3</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SIG_OUT_EN</name>
              <description>Set this bit to enable signal output on channel %s.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IDLE_LV</name>
              <description>This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PARA_UP</name>
              <description>This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>OVF_NUM</name>
              <description>This register is used to configure the maximum times of overflow minus 1.

The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OVF_CNT_EN</name>
              <description>This bit is used to enable the ovf_cnt of channel %s.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OVF_CNT_RESET</name>
              <description>Set this bit to reset the ovf_cnt of channel %s.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>6</dim>
          <dimIncrement>0x14</dimIncrement>
          <name>CH%s_HPOINT</name>
          <description>High point register for channel %s</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>HPOINT</name>
              <description>The output value changes to high when the selected timers has reached the value specified by this register.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>14</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>6</dim>
          <dimIncrement>0x14</dimIncrement>
          <name>CH%s_DUTY</name>
          <description>Initial duty cycle for channel %s</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DUTY</name>
              <description>This register is used to change the output duty by controlling the Lpoint.

The output value turns to low when the selected timers has reached the Lpoint.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>19</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>6</dim>
          <dimIncrement>0x14</dimIncrement>
          <name>CH%s_CONF1</name>
          <description>Configuration register 1 for channel %s</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <resetValue>0x40000000</resetValue>
          <fields>
            <field>
              <name>DUTY_SCALE</name>
              <description>This register is used to configure the changing step scale of duty on channel %s.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DUTY_CYCLE</name>
              <description>The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DUTY_NUM</name>
              <description>This register is used to control the number of times the duty cycle will be changed.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DUTY_INC</name>
              <description>This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase; 0: Decrease.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DUTY_START</name>
              <description>Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>6</dim>
          <dimIncrement>0x14</dimIncrement>
          <name>CH%s_DUTY_R</name>
          <description>Current duty cycle for channel %s</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DUTY_CH0_R</name>
              <description>This register stores the current duty of output signal on channel %s.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>19</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>4</dim>
          <dimIncrement>0x8</dimIncrement>
          <name>TIMER%s_CONF</name>
          <description>Timer %s configuration</description>
          <addressOffset>0xA0</addressOffset>
          <size>0x20</size>
          <resetValue>0x00800000</resetValue>
          <fields>
            <field>
              <name>DUTY_RES</name>
              <description>This register is used to control the range of the counter in timer %s.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>This register is used to configure the divisor for the divider in timer %s.

The least significant eight bits represent the fractional part.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>18</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PAUSE</name>
              <description>This bit is used to suspend the counter in timer %s.</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RST</name>
              <description>This bit is used to reset timer %s. The counter will show 0 after reset.</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TICK_SEL</name>
              <description>This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate.

1'h0: SLOW_CLK 1'h1: REF_TICK</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PARA_UP</name>
              <description>Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>4</dim>
          <dimIncrement>0x8</dimIncrement>
          <name>TIMER%s_VALUE</name>
          <description>Timer %s current counter value</description>
          <addressOffset>0xA4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CNT</name>
              <description>This register stores the current counter value of timer %s.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>14</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_RAW</name>
          <description>Raw interrupt status</description>
          <addressOffset>0xC0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>OVF_INT_RAW</name>
              <description>Triggered when the timer0 has reached its maximum counter value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TIMER1_OVF_INT_RAW</name>
              <description>Triggered when the timer1 has reached its maximum counter value.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TIMER2_OVF_INT_RAW</name>
              <description>Triggered when the timer2 has reached its maximum counter value.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TIMER3_OVF_INT_RAW</name>
              <description>Triggered when the timer3 has reached its maximum counter value.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH0_INT_RAW</name>
              <description>Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH1_INT_RAW</name>
              <description>Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH2_INT_RAW</name>
              <description>Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH3_INT_RAW</name>
              <description>Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH4_INT_RAW</name>
              <description>Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH5_INT_RAW</name>
              <description>Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVF_CNT_CH0_INT_RAW</name>
              <description>Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVF_CNT_CH1_INT_RAW</name>
              <description>Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVF_CNT_CH2_INT_RAW</name>
              <description>Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVF_CNT_CH3_INT_RAW</name>
              <description>Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVF_CNT_CH4_INT_RAW</name>
              <description>Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVF_CNT_CH5_INT_RAW</name>
              <description>Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_ST</name>
          <description>Masked interrupt status</description>
          <addressOffset>0xC4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>OVF_INT_ST</name>
              <description>This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TIMER1_OVF_INT_ST</name>
              <description>This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TIMER2_OVF_INT_ST</name>
              <description>This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TIMER3_OVF_INT_ST</name>
              <description>This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH0_INT_ST</name>
              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENAIS set to 1.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH1_INT_ST</name>
              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENAIS set to 1.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH2_INT_ST</name>
              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENAIS set to 1.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH3_INT_ST</name>
              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENAIS set to 1.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH4_INT_ST</name>
              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENAIS set to 1.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH5_INT_ST</name>
              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENAIS set to 1.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVF_CNT_CH0_INT_ST</name>
              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVF_CNT_CH1_INT_ST</name>
              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVF_CNT_CH2_INT_ST</name>
              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVF_CNT_CH3_INT_ST</name>
              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVF_CNT_CH4_INT_ST</name>
              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OVF_CNT_CH5_INT_ST</name>
              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_ENA</name>
          <description>Interrupt enable bits</description>
          <addressOffset>0xC8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>OVF_INT_ENA</name>
              <description>The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TIMER1_OVF_INT_ENA</name>
              <description>The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TIMER2_OVF_INT_ENA</name>
              <description>The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TIMER3_OVF_INT_ENA</name>
              <description>The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH0_INT_ENA</name>
              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH1_INT_ENA</name>
              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH2_INT_ENA</name>
              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH3_INT_ENA</name>
              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH4_INT_ENA</name>
              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH5_INT_ENA</name>
              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OVF_CNT_CH0_INT_ENA</name>
              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OVF_CNT_CH1_INT_ENA</name>
              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OVF_CNT_CH2_INT_ENA</name>
              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OVF_CNT_CH3_INT_ENA</name>
              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OVF_CNT_CH4_INT_ENA</name>
              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OVF_CNT_CH5_INT_ENA</name>
              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_CLR</name>
          <description>Interrupt clear bits</description>
          <addressOffset>0xCC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>OVF_INT_CLR</name>
              <description>Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>TIMER1_OVF_INT_CLR</name>
              <description>Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>TIMER2_OVF_INT_CLR</name>
              <description>Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>TIMER3_OVF_INT_CLR</name>
              <description>Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH0_INT_CLR</name>
              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH1_INT_CLR</name>
              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH2_INT_CLR</name>
              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH3_INT_CLR</name>
              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH4_INT_CLR</name>
              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>DUTY_CHNG_END_CH5_INT_CLR</name>
              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>OVF_CNT_CH0_INT_CLR</name>
              <description>Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>OVF_CNT_CH1_INT_CLR</name>
              <description>Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>OVF_CNT_CH2_INT_CLR</name>
              <description>Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>OVF_CNT_CH3_INT_CLR</name>
              <description>Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>OVF_CNT_CH4_INT_CLR</name>
              <description>Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>OVF_CNT_CH5_INT_CLR</name>
              <description>Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CONF</name>
          <description>Global ledc configuration register</description>
          <addressOffset>0xD0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>APB_CLK_SEL</name>
              <description>This bit is used to select clock source for the 4 timers .

2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_EN</name>
              <description>This bit is used to control clock.

1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DATE</name>
          <description>Version control register</description>
          <addressOffset>0xFC</addressOffset>
          <size>0x20</size>
          <resetValue>0x19061700</resetValue>
          <fields>
            <field>
              <name>LEDC_DATE</name>
              <description>This is the version control register.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>RNG</name>
      <description>Hardware random number generator</description>
      <groupName>RNG</groupName>
      <baseAddress>0x60026000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x4</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>DATA</name>
          <description>Random number data</description>
          <addressOffset>0xB0</addressOffset>
          <size>0x20</size>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>RTC_CNTL</name>
      <description>Real Time Controller</description>
      <groupName>RTC_CNTL</groupName>
      <baseAddress>0x60008000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x114</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>RTC_CORE</name>
        <value>21</value>
      </interrupt>
      <registers>
        <register>
          <name>OPTIONS0</name>
          <description>register description</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <resetValue>0x1000A000</resetValue>
          <fields>
            <field>
              <name>SW_STALL_PROCPU_C0</name>
              <description>{reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SW_PROCPU_RST</name>
              <description>PRO CPU SW reset</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BB_I2C_FORCE_PD</name>
              <description>BB_I2C force power down</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BB_I2C_FORCE_PU</name>
              <description>BB_I2C force power up</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BBPLL_I2C_FORCE_PD</name>
              <description>BB_PLL _I2C force power down</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BBPLL_I2C_FORCE_PU</name>
              <description>BB_PLL_I2C force power up</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BBPLL_FORCE_PD</name>
              <description>BB_PLL force power down</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BBPLL_FORCE_PU</name>
              <description>BB_PLL force power up</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTL_FORCE_PD</name>
              <description>crystall force power down</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTL_FORCE_PU</name>
              <description>crystall force power up</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTL_EN_WAIT</name>
              <description>wait bias_sleep and current source wakeup</description>
              <bitOffset>14</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTL_EXT_CTR_SEL</name>
              <description>Need add desc</description>
              <bitOffset>20</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ANALOG_FORCE_ISO</name>
              <description>Need add desc</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ANALOG_FORCE_NOISO</name>
              <description>Need add desc</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DG_WRAP_FORCE_RST</name>
              <description>digital wrap force reset in deep sleep</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DG_WRAP_FORCE_NORST</name>
              <description>digital core force no reset in deep sleep</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SW_SYS_RST</name>
              <description>SW system reset</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLP_TIMER0</name>
          <description>register description</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SLP_VAL_LO</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLP_TIMER1</name>
          <description>register description</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SLP_VAL_HI</name>
              <description>RTC sleep timer high 16 bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MAIN_TIMER_ALARM_EN</name>
              <description>timer alarm enable bit</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TIME_UPDATE</name>
          <description>register description</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_SYS_STALL</name>
              <description>Enable to record system stall time</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TIMER_XTL_OFF</name>
              <description>Enable to record 40M XTAL OFF time</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TIMER_SYS_RST</name>
              <description>enable to record system reset time</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TIME_UPDATE</name>
              <description>Set 1: to update register with RTC timer</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TIME_LOW0</name>
          <description>register description</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_VALUE0_LOW</name>
              <description>RTC timer low 32 bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TIME_HIGH0</name>
          <description>register description</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_VALUE0_HIGH</name>
              <description>RTC timer high 16 bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STATE0</name>
          <description>register description</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SW_CPU_INT</name>
              <description>rtc software interrupt to main cpu</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLP_REJECT_CAUSE_CLR</name>
              <description>clear rtc sleep reject cause</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>APB2RTC_BRIDGE_SEL</name>
              <description>1: APB to RTC using bridge</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SDIO_ACTIVE_IND</name>
              <description>SDIO active indication</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLP_WAKEUP</name>
              <description>leep wakeup bit</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLP_REJECT</name>
              <description>leep reject bit</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLEEP_EN</name>
              <description>sleep enable bit</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TIMER1</name>
          <description>register description</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <resetValue>0x28140403</resetValue>
          <fields>
            <field>
              <name>CPU_STALL_EN</name>
              <description>CPU stall enable bit</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CPU_STALL_WAIT</name>
              <description>CPU stall wait cycles in fast_clk_rtc</description>
              <bitOffset>1</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CK8M_WAIT</name>
              <description>CK8M wait cycles in slow_clk_rtc</description>
              <bitOffset>6</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTL_BUF_WAIT</name>
              <description>XTAL wait cycles in slow_clk_rtc</description>
              <bitOffset>14</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PLL_BUF_WAIT</name>
              <description>PLL wait cycles in slow_clk_rtc</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TIMER2</name>
          <description>register description</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <resetValue>0x01000000</resetValue>
          <fields>
            <field>
              <name>MIN_TIME_CK8M_OFF</name>
              <description>minimal cycles in slow_clk_rtc for CK8M in power down state</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TIMER4</name>
          <description>register description</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <resetValue>0x10200000</resetValue>
          <fields>
            <field>
              <name>DG_WRAP_WAIT_TIMER</name>
              <description>Need add desc</description>
              <bitOffset>16</bitOffset>
              <bitWidth>9</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DG_WRAP_POWERUP_TIMER</name>
              <description>Need add desc</description>
              <bitOffset>25</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TIMER5</name>
          <description>register description</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <resetValue>0x00008000</resetValue>
          <fields>
            <field>
              <name>MIN_SLP_VAL</name>
              <description>minimal sleep cycles in slow_clk_rtc</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ANA_CONF</name>
          <description>register description</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <resetValue>0x00440000</resetValue>
          <fields>
            <field>
              <name>I2C_RESET_POR_FORCE_PD</name>
              <description>Need add desc</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>I2C_RESET_POR_FORCE_PU</name>
              <description>Need add desc</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SAR_I2C_PU</name>
              <description>PLLA force power up</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BBPLL_CAL_SLP_START</name>
              <description>start BBPLL calibration during sleep</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TXRF_I2C_PU</name>
              <description>1: TXRF_I2C power up</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RFRX_PBUS_PU</name>
              <description>1: RFRX_PBUS power up</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CKGEN_I2C_PU</name>
              <description>1: CKGEN_I2C power up</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PLL_I2C_PU</name>
              <description>Need add desc</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PLLA_FORCE_PD</name>
              <description>PLLA force power down</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PLLA_FORCE_PU</name>
              <description>PLLA force power up</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RESET_STATE</name>
          <description>register description</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <resetValue>0x00002000</resetValue>
          <fields>
            <field>
              <name>RESET_CAUSE_PROCPU</name>
              <description>reset cause of PRO CPU</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>STAT_VECTOR_SEL_PROCPU</name>
              <description>PRO CPU state vector sel</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OCD_HALT_ON_RESET_PROCPU</name>
              <description>PROCPU OcdHaltOnReset</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DRESET_MASK_PROCPU</name>
              <description>Need add desc</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WAKEUP_STATE</name>
          <description>register description</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <resetValue>0x00060000</resetValue>
          <fields>
            <field>
              <name>WAKEUP_ENA</name>
              <description>wakeup enable bitmap</description>
              <bitOffset>15</bitOffset>
              <bitWidth>17</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_ENA_RTC</name>
          <description>register description</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SLP_WAKEUP_INT_ENA</name>
              <description>enable sleep wakeup interrupt</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SLP_REJECT_INT_ENA</name>
              <description>enable sleep reject interrupt</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>WDT_INT_ENA</name>
              <description>enable RTC WDT interrupt</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BROWN_OUT_INT_ENA</name>
              <description>enable brown out interrupt</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>MAIN_TIMER_INT_ENA</name>
              <description>enable RTC main timer interrupt</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>SWD_INT_ENA</name>
              <description>enable super watch dog interrupt</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BBPLL_CAL_INT_ENA</name>
              <description>Need add desc</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_RAW_RTC</name>
          <description>register description</description>
          <addressOffset>0x3C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SLP_WAKEUP_INT_RAW</name>
              <description>sleep wakeup interrupt raw</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLP_REJECT_INT_RAW</name>
              <description>sleep reject interrupt raw</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_INT_RAW</name>
              <description>RTC WDT interrupt raw</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BROWN_OUT_INT_RAW</name>
              <description>brown out interrupt raw</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MAIN_TIMER_INT_RAW</name>
              <description>RTC main timer interrupt raw</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SWD_INT_RAW</name>
              <description>super watch dog interrupt raw</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BBPLL_CAL_INT_RAW</name>
              <description>Need add desc</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_ST_RTC</name>
          <description>register description</description>
          <addressOffset>0x40</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SLP_WAKEUP_INT_ST</name>
              <description>sleep wakeup interrupt state</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLP_REJECT_INT_ST</name>
              <description>sleep reject interrupt state</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_INT_ST</name>
              <description>RTC WDT interrupt state</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BROWN_OUT_INT_ST</name>
              <description>brown out interrupt state</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MAIN_TIMER_INT_ST</name>
              <description>RTC main timer interrupt state</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SWD_INT_ST</name>
              <description>super watch dog interrupt state</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BBPLL_CAL_INT_ST</name>
              <description>Need add desc</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_CLR_RTC</name>
          <description>register description</description>
          <addressOffset>0x44</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SLP_WAKEUP_INT_CLR</name>
              <description>Clear sleep wakeup interrupt state</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLP_REJECT_INT_CLR</name>
              <description>Clear sleep reject interrupt state</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_INT_CLR</name>
              <description>Clear RTC WDT interrupt state</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BROWN_OUT_INT_CLR</name>
              <description>Clear brown out interrupt state</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MAIN_TIMER_INT_CLR</name>
              <description>Clear RTC main timer interrupt state</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SWD_INT_CLR</name>
              <description>Clear super watch dog interrupt state</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BBPLL_CAL_INT_CLR</name>
              <description>Need add desc</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STORE0</name>
          <description>register description</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SCRATCH0</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STORE1</name>
          <description>register description</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SCRATCH1</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STORE2</name>
          <description>register description</description>
          <addressOffset>0x50</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SCRATCH2</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STORE3</name>
          <description>register description</description>
          <addressOffset>0x54</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SCRATCH3</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>EXT_XTL_CONF</name>
          <description>register description</description>
          <addressOffset>0x58</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>XTL_EXT_CTR_LV</name>
              <description>0: power down XTAL at high level</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTL_EXT_CTR_EN</name>
              <description>Need add desc</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>EXT_WAKEUP_CONF</name>
          <description>register description</description>
          <addressOffset>0x5C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>GPIO_WAKEUP_FILTER</name>
              <description>enable filter for gpio wakeup event</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLP_REJECT_CONF</name>
          <description>register description</description>
          <addressOffset>0x60</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SLEEP_REJECT_ENA</name>
              <description>sleep reject enable</description>
              <bitOffset>12</bitOffset>
              <bitWidth>18</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LIGHT_SLP_REJECT_EN</name>
              <description>enable reject for light sleep</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DEEP_SLP_REJECT_EN</name>
              <description>enable reject for deep sleep</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_PERIOD_CONF</name>
          <description>register description</description>
          <addressOffset>0x64</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPUSEL_CONF</name>
              <description>CPU sel option</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CPUPERIOD_SEL</name>
              <description>Need add desc</description>
              <bitOffset>30</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLK_CONF</name>
          <description>register description</description>
          <addressOffset>0x68</addressOffset>
          <size>0x20</size>
          <resetValue>0x11583218</resetValue>
          <fields>
            <field>
              <name>EFUSE_CLK_FORCE_GATING</name>
              <description>Need add desc</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EFUSE_CLK_FORCE_NOGATING</name>
              <description>Need add desc</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CK8M_DIV_SEL_VLD</name>
              <description>used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CK8M_DIV</name>
              <description>CK8M_D256_OUT divider. 00: div128</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ENB_CK8M</name>
              <description>disable CK8M and CK8M_D256_OUT</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ENB_CK8M_DIV</name>
              <description>1: CK8M_D256_OUT is actually CK8M</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DIG_XTAL32K_EN</name>
              <description>enable CK_XTAL_32K for digital core (no relationship with RTC core)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DIG_CLK8M_D256_EN</name>
              <description>enable CK8M_D256_OUT for digital core (no relationship with RTC core)</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DIG_CLK8M_EN</name>
              <description>enable CK8M for digital core (no relationship with RTC core)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CK8M_DIV_SEL</name>
              <description>divider = reg_ck8m_div_sel + 1</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL_FORCE_NOGATING</name>
              <description>XTAL force no gating during sleep</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CK8M_FORCE_NOGATING</name>
              <description>CK8M force no gating during sleep</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CK8M_DFREQ</name>
              <description>CK8M_DFREQ</description>
              <bitOffset>17</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CK8M_FORCE_PD</name>
              <description>CK8M force power down</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CK8M_FORCE_PU</name>
              <description>CK8M force power up</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL_GLOBAL_FORCE_GATING</name>
              <description>Need add desc</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL_GLOBAL_FORCE_NOGATING</name>
              <description>Need add desc</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FAST_CLK_RTC_SEL</name>
              <description>fast_clk_rtc sel. 0: XTAL div 4</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ANA_CLK_RTC_SEL</name>
              <description>Need add desc</description>
              <bitOffset>30</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLOW_CLK_CONF</name>
          <description>register description</description>
          <addressOffset>0x6C</addressOffset>
          <size>0x20</size>
          <resetValue>0x00400000</resetValue>
          <fields>
            <field>
              <name>ANA_CLK_DIV_VLD</name>
              <description>used to sync div bus. clear vld before set reg_rtc_ana_clk_div</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ANA_CLK_DIV</name>
              <description>Need add desc</description>
              <bitOffset>23</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLOW_CLK_NEXT_EDGE</name>
              <description>Need add desc</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>BIAS_CONF</name>
          <description>register description</description>
          <addressOffset>0x70</addressOffset>
          <size>0x20</size>
          <resetValue>0x00010800</resetValue>
          <fields>
            <field>
              <name>DG_VDD_DRV_B_SLP</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DG_VDD_DRV_B_SLP_EN</name>
              <description>Need add desc</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BIAS_BUF_IDLE</name>
              <description>Need add desc</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BIAS_BUF_WAKE</name>
              <description>Need add desc</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BIAS_BUF_DEEP_SLP</name>
              <description>Need add desc</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BIAS_BUF_MONITOR</name>
              <description>Need add desc</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PD_CUR_DEEP_SLP</name>
              <description>xpd cur when rtc in sleep_state</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PD_CUR_MONITOR</name>
              <description>xpd cur when rtc in monitor state</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BIAS_SLEEP_DEEP_SLP</name>
              <description>bias_sleep when rtc in sleep_state</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BIAS_SLEEP_MONITOR</name>
              <description>bias_sleep when rtc in monitor state</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DBG_ATTEN_DEEP_SLP</name>
              <description>DBG_ATTEN when rtc in sleep state</description>
              <bitOffset>18</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DBG_ATTEN_MONITOR</name>
              <description>DBG_ATTEN when rtc in active state</description>
              <bitOffset>22</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DBG_ATTEN_ACTIVE</name>
              <description>Need add desc</description>
              <bitOffset>26</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RTC_CNTL</name>
          <description>register description</description>
          <addressOffset>0x74</addressOffset>
          <size>0x20</size>
          <resetValue>0x80000000</resetValue>
          <fields>
            <field>
              <name>DIG_REG_CAL_EN</name>
              <description>Need add desc</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCK_DCAP</name>
              <description>SCK_DCAP</description>
              <bitOffset>14</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>REGULATOR_FORCE_PD</name>
              <description>RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>REGULATOR_FORCE_PU</name>
              <description>Need add desc</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PWC</name>
          <description>register description</description>
          <addressOffset>0x78</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PAD_FORCE_HOLD</name>
              <description>rtc pad force hold</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DIG_PWC</name>
          <description>register description</description>
          <addressOffset>0x7C</addressOffset>
          <size>0x20</size>
          <resetValue>0x00100020</resetValue>
          <fields>
            <field>
              <name>VDD_SPI_PWR_DRV</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VDD_SPI_PWR_FORCE</name>
              <description>Need add desc</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VDD_SPI_PD_EN</name>
              <description>Need add desc</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LSLP_MEM_FORCE_PD</name>
              <description>memories in digital core force PD in sleep</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LSLP_MEM_FORCE_PU</name>
              <description>memories in digital core force no PD in sleep</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DG_WRAP_FORCE_PD</name>
              <description>digital core force power down</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DG_WRAP_FORCE_PU</name>
              <description>digital core force power up</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DG_WRAP_PD_EN</name>
              <description>Need add desc</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DIG_ISO</name>
          <description>register description</description>
          <addressOffset>0x80</addressOffset>
          <size>0x20</size>
          <resetValue>0x80005080</resetValue>
          <fields>
            <field>
              <name>FORCE_OFF</name>
              <description>Need add desc</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FORCE_ON</name>
              <description>Need add desc</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DG_PAD_AUTOHOLD</name>
              <description>read only register to indicate digital pad auto-hold status</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLR_DG_PAD_AUTOHOLD</name>
              <description>wtite only register to clear digital pad auto-hold</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DG_PAD_AUTOHOLD_EN</name>
              <description>digital pad enable auto-hold</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DG_PAD_FORCE_NOISO</name>
              <description>digital pad force no ISO</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DG_PAD_FORCE_ISO</name>
              <description>digital pad force ISO</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DG_PAD_FORCE_UNHOLD</name>
              <description>digital pad force un-hold</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DG_PAD_FORCE_HOLD</name>
              <description>digital pad force hold</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DG_WRAP_FORCE_ISO</name>
              <description>digital core force ISO</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DG_WRAP_FORCE_NOISO</name>
              <description>Need add desc</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WDTCONFIG0</name>
          <description>register description</description>
          <addressOffset>0x84</addressOffset>
          <size>0x20</size>
          <resetValue>0x00013214</resetValue>
          <fields>
            <field>
              <name>WDT_CHIP_RESET_WIDTH</name>
              <description>chip reset siginal pulse width</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_CHIP_RESET_EN</name>
              <description>wdt reset whole chip enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_PAUSE_IN_SLP</name>
              <description>pause WDT in sleep</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_PROCPU_RESET_EN</name>
              <description>enable WDT reset PRO CPU</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_FLASHBOOT_MOD_EN</name>
              <description>enable WDT in flash boot</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_SYS_RESET_LENGTH</name>
              <description>system reset counter length</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_CPU_RESET_LENGTH</name>
              <description>CPU reset counter length</description>
              <bitOffset>16</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_STG3</name>
              <description>1: interrupt stage en</description>
              <bitOffset>19</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_STG2</name>
              <description>1: interrupt stage en</description>
              <bitOffset>22</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_STG1</name>
              <description>1: interrupt stage en</description>
              <bitOffset>25</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_STG0</name>
              <description>1: interrupt stage en</description>
              <bitOffset>28</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_EN</name>
              <description>Need add desc</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WDTCONFIG1</name>
          <description>register description</description>
          <addressOffset>0x88</addressOffset>
          <size>0x20</size>
          <resetValue>0x00030D40</resetValue>
          <fields>
            <field>
              <name>WDT_STG0_HOLD</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WDTCONFIG2</name>
          <description>register description</description>
          <addressOffset>0x8C</addressOffset>
          <size>0x20</size>
          <resetValue>0x00013880</resetValue>
          <fields>
            <field>
              <name>WDT_STG1_HOLD</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WDTCONFIG3</name>
          <description>register description</description>
          <addressOffset>0x90</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000FFF</resetValue>
          <fields>
            <field>
              <name>WDT_STG2_HOLD</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WDTCONFIG4</name>
          <description>register description</description>
          <addressOffset>0x94</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000FFF</resetValue>
          <fields>
            <field>
              <name>WDT_STG3_HOLD</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WDTFEED</name>
          <description>register description</description>
          <addressOffset>0x98</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>WDT_FEED</name>
              <description>Need add desc</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WDTWPROTECT</name>
          <description>register description</description>
          <addressOffset>0x9C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>WDT_WKEY</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SWD_CONF</name>
          <description>register description</description>
          <addressOffset>0xA0</addressOffset>
          <size>0x20</size>
          <resetValue>0x04B00000</resetValue>
          <fields>
            <field>
              <name>SWD_RESET_FLAG</name>
              <description>swd reset flag</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SWD_FEED_INT</name>
              <description>swd interrupt for feeding</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SWD_BYPASS_RST</name>
              <description>Need add desc</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SWD_SIGNAL_WIDTH</name>
              <description>adjust signal width send to swd</description>
              <bitOffset>18</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SWD_RST_FLAG_CLR</name>
              <description>reset swd reset flag</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SWD_FEED</name>
              <description>Sw feed swd</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SWD_DISABLE</name>
              <description>disabel SWD</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SWD_AUTO_FEED_EN</name>
              <description>automatically feed swd when int comes</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SWD_WPROTECT</name>
          <description>register description</description>
          <addressOffset>0xA4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SWD_WKEY</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SW_CPU_STALL</name>
          <description>register description</description>
          <addressOffset>0xA8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SW_STALL_PROCPU_C1</name>
              <description>Need add desc</description>
              <bitOffset>26</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STORE4</name>
          <description>register description</description>
          <addressOffset>0xAC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SCRATCH4</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STORE5</name>
          <description>register description</description>
          <addressOffset>0xB0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SCRATCH5</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STORE6</name>
          <description>register description</description>
          <addressOffset>0xB4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SCRATCH6</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STORE7</name>
          <description>register description</description>
          <addressOffset>0xB8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SCRATCH7</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LOW_POWER_ST</name>
          <description>register description</description>
          <addressOffset>0xBC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>XPD_DIG</name>
              <description>digital wrap power down</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TOUCH_STATE_START</name>
              <description>touch should start to work</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TOUCH_STATE_SWITCH</name>
              <description>touch is about to working. Switch rtc main state</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TOUCH_STATE_SLP</name>
              <description>touch is in sleep state</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TOUCH_STATE_DONE</name>
              <description>touch is done</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>COCPU_STATE_START</name>
              <description>ulp/cocpu should start to work</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>COCPU_STATE_SWITCH</name>
              <description>ulp/cocpu is about to working. Switch rtc main state</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>COCPU_STATE_SLP</name>
              <description>ulp/cocpu is in sleep state</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>COCPU_STATE_DONE</name>
              <description>ulp/cocpu is done</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MAIN_STATE_XTAL_ISO</name>
              <description>no use any more</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MAIN_STATE_PLL_ON</name>
              <description>rtc main state machine is in states that pll should be running</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RDY_FOR_WAKEUP</name>
              <description>rtc is ready to receive wake up trigger from wake up source</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MAIN_STATE_WAIT_END</name>
              <description>rtc main state machine has been waited for some cycles</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IN_WAKEUP_STATE</name>
              <description>rtc main state machine is in the states of wakeup process</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IN_LOW_POWER_STATE</name>
              <description>rtc main state machine is in the states of low power</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MAIN_STATE_IN_WAIT_8M</name>
              <description>rtc main state machine is in wait 8m state</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MAIN_STATE_IN_WAIT_PLL</name>
              <description>rtc main state machine is in wait pll state</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MAIN_STATE_IN_WAIT_XTL</name>
              <description>rtc main state machine is in wait xtal state</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MAIN_STATE_IN_SLP</name>
              <description>rtc main state machine is in sleep state</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MAIN_STATE_IN_IDLE</name>
              <description>rtc main state machine is in idle state</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MAIN_STATE</name>
              <description>rtc main state machine status</description>
              <bitOffset>28</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DIAG0</name>
          <description>register description</description>
          <addressOffset>0xC0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>LOW_POWER_DIAG1</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PAD_HOLD</name>
          <description>register description</description>
          <addressOffset>0xC4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>GPIO_PIN0_HOLD</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN1_HOLD</name>
              <description>Need add desc</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN2_HOLD</name>
              <description>Need add desc</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN3_HOLD</name>
              <description>Need add desc</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN4_HOLD</name>
              <description>Need add desc</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN5_HOLD</name>
              <description>Need add desc</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DIG_PAD_HOLD</name>
          <description>register description</description>
          <addressOffset>0xC8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DIG_PAD_HOLD</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>BROWN_OUT</name>
          <description>register description</description>
          <addressOffset>0xCC</addressOffset>
          <size>0x20</size>
          <resetValue>0x43FF0010</resetValue>
          <fields>
            <field>
              <name>BROWN_OUT_INT_WAIT</name>
              <description>brown out interrupt wait cycles</description>
              <bitOffset>4</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BROWN_OUT_CLOSE_FLASH_ENA</name>
              <description>enable close flash when brown out happens</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BROWN_OUT_PD_RF_ENA</name>
              <description>enable power down RF when brown out happens</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BROWN_OUT_RST_WAIT</name>
              <description>brown out reset wait cycles</description>
              <bitOffset>16</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BROWN_OUT_RST_ENA</name>
              <description>enable brown out reset</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BROWN_OUT_RST_SEL</name>
              <description>1:  4-pos reset</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BROWN_OUT_ANA_RST_EN</name>
              <description>Need add desc</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BROWN_OUT_CNT_CLR</name>
              <description>clear brown out counter</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BROWN_OUT_ENA</name>
              <description>enable brown out</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DET</name>
              <description>Need add desc</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TIME_LOW1</name>
          <description>register description</description>
          <addressOffset>0xD0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_VALUE1_LOW</name>
              <description>RTC timer low 32 bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TIME_HIGH1</name>
          <description>register description</description>
          <addressOffset>0xD4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_VALUE1_HIGH</name>
              <description>RTC timer high 16 bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>USB_CONF</name>
          <description>register description</description>
          <addressOffset>0xD8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>IO_MUX_RESET_DISABLE</name>
              <description>Need add desc</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLP_REJECT_CAUSE</name>
          <description>register description</description>
          <addressOffset>0xDC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>REJECT_CAUSE</name>
              <description>sleep reject cause</description>
              <bitOffset>0</bitOffset>
              <bitWidth>18</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OPTION1</name>
          <description>register description</description>
          <addressOffset>0xE0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>FORCE_DOWNLOAD_BOOT</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLP_WAKEUP_CAUSE</name>
          <description>register description</description>
          <addressOffset>0xE4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>WAKEUP_CAUSE</name>
              <description>sleep wakeup cause</description>
              <bitOffset>0</bitOffset>
              <bitWidth>17</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ULP_CP_TIMER_1</name>
          <description>register description</description>
          <addressOffset>0xE8</addressOffset>
          <size>0x20</size>
          <resetValue>0x0000C800</resetValue>
          <fields>
            <field>
              <name>ULP_CP_TIMER_SLP_CYCLE</name>
              <description>sleep cycles for ULP-coprocessor timer</description>
              <bitOffset>8</bitOffset>
              <bitWidth>24</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_ENA_RTC_W1TS</name>
          <description>register description</description>
          <addressOffset>0xEC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SLP_WAKEUP_INT_ENA_W1TS</name>
              <description>enable sleep wakeup interrupt</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLP_REJECT_INT_ENA_W1TS</name>
              <description>enable sleep reject interrupt</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_INT_ENA_W1TS</name>
              <description>enable RTC WDT interrupt</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BROWN_OUT_INT_ENA_W1TS</name>
              <description>enable brown out interrupt</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MAIN_TIMER_INT_ENA_W1TS</name>
              <description>enable RTC main timer interrupt</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SWD_INT_ENA_W1TS</name>
              <description>enable super watch dog interrupt</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BBPLL_CAL_INT_ENA_W1TS</name>
              <description>Need add desc</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_ENA_RTC_W1TC</name>
          <description>register description</description>
          <addressOffset>0xF0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SLP_WAKEUP_INT_ENA_W1TC</name>
              <description>enable sleep wakeup interrupt</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLP_REJECT_INT_ENA_W1TC</name>
              <description>enable sleep reject interrupt</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_INT_ENA_W1TC</name>
              <description>enable RTC WDT interrupt</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BROWN_OUT_INT_ENA_W1TC</name>
              <description>enable brown out interrupt</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MAIN_TIMER_INT_ENA_W1TC</name>
              <description>enable RTC main timer interrupt</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SWD_INT_ENA_W1TC</name>
              <description>enable super watch dog interrupt</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BBPLL_CAL_INT_ENA_W1TC</name>
              <description>Need add desc</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CNTL_RETENTION_CTRL</name>
          <description>register description</description>
          <addressOffset>0xF4</addressOffset>
          <size>0x20</size>
          <resetValue>0xA0D00000</resetValue>
          <fields>
            <field>
              <name>RETENTION_CLK_SEL</name>
              <description>Need add desc</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RETENTION_DONE_WAIT</name>
              <description>Need add desc</description>
              <bitOffset>19</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RETENTION_CLKOFF_WAIT</name>
              <description>Need add desc</description>
              <bitOffset>22</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RETENTION_EN</name>
              <description>Need add desc</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RETENTION_WAIT</name>
              <description>wait cycles for rention operation</description>
              <bitOffset>27</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIB_SEL</name>
          <description>register description</description>
          <addressOffset>0xF8</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000007</resetValue>
          <fields>
            <field>
              <name>FIB_SEL</name>
              <description>select use analog fib signal</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CNTL_GPIO_WAKEUP</name>
          <description>register description</description>
          <addressOffset>0xFC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>GPIO_WAKEUP_STATUS</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_WAKEUP_STATUS_CLR</name>
              <description>Need add desc</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN_CLK_GATE</name>
              <description>Need add desc</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN5_INT_TYPE</name>
              <description>Need add desc</description>
              <bitOffset>8</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN4_INT_TYPE</name>
              <description>Need add desc</description>
              <bitOffset>11</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN3_INT_TYPE</name>
              <description>Need add desc</description>
              <bitOffset>14</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN2_INT_TYPE</name>
              <description>Need add desc</description>
              <bitOffset>17</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN1_INT_TYPE</name>
              <description>Need add desc</description>
              <bitOffset>20</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN0_INT_TYPE</name>
              <description>Need add desc</description>
              <bitOffset>23</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN5_WAKEUP_ENABLE</name>
              <description>Need add desc</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN4_WAKEUP_ENABLE</name>
              <description>Need add desc</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN3_WAKEUP_ENABLE</name>
              <description>Need add desc</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN2_WAKEUP_ENABLE</name>
              <description>Need add desc</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN1_WAKEUP_ENABLE</name>
              <description>Need add desc</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN0_WAKEUP_ENABLE</name>
              <description>Need add desc</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CNTL_DBG_SEL</name>
          <description>register description</description>
          <addressOffset>0x100</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DEBUG_12M_NO_GATING</name>
              <description>Need add desc</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DEBUG_BIT_SEL</name>
              <description>Need add desc</description>
              <bitOffset>2</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DEBUG_SEL0</name>
              <description>Need add desc</description>
              <bitOffset>7</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DEBUG_SEL1</name>
              <description>Need add desc</description>
              <bitOffset>12</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DEBUG_SEL2</name>
              <description>Need add desc</description>
              <bitOffset>17</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DEBUG_SEL3</name>
              <description>Need add desc</description>
              <bitOffset>22</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DEBUG_SEL4</name>
              <description>Need add desc</description>
              <bitOffset>27</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CNTL_DBG_MAP</name>
          <description>register description</description>
          <addressOffset>0x104</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>GPIO_PIN5_MUX_SEL</name>
              <description>Need add desc</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN4_MUX_SEL</name>
              <description>Need add desc</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN3_MUX_SEL</name>
              <description>Need add desc</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN2_MUX_SEL</name>
              <description>Need add desc</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN1_MUX_SEL</name>
              <description>Need add desc</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN0_MUX_SEL</name>
              <description>Need add desc</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN5_FUN_SEL</name>
              <description>Need add desc</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN4_FUN_SEL</name>
              <description>Need add desc</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN3_FUN_SEL</name>
              <description>Need add desc</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN2_FUN_SEL</name>
              <description>Need add desc</description>
              <bitOffset>20</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN1_FUN_SEL</name>
              <description>Need add desc</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GPIO_PIN0_FUN_SEL</name>
              <description>Need add desc</description>
              <bitOffset>28</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CNTL_SENSOR_CTRL</name>
          <description>register description</description>
          <addressOffset>0x108</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SAR2_PWDET_CCT</name>
              <description>Need add desc</description>
              <bitOffset>27</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FORCE_XPD_SAR</name>
              <description>Need add desc</description>
              <bitOffset>30</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CNTL_DBG_SAR_SEL</name>
          <description>register description</description>
          <addressOffset>0x10C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SAR_DEBUG_SEL</name>
              <description>Need add desc</description>
              <bitOffset>27</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CNTL_DATE</name>
          <description>register description</description>
          <addressOffset>0x1FC</addressOffset>
          <size>0x20</size>
          <resetValue>0x02107190</resetValue>
          <fields>
            <field>
              <name>CNTL_DATE</name>
              <description>Need add desc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>28</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>SENSITIVE</name>
      <description>Sensitive</description>
      <groupName>SENSITIVE</groupName>
      <baseAddress>0x600C1000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x48</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>ROM_TABLE_LOCK</name>
          <description>register description</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ROM_TABLE_LOCK</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ROM_TABLE</name>
          <description>register description</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ROM_TABLE</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>APB_PERIPHERAL_ACCESS_0</name>
          <description>register description</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>APB_PERIPHERAL_ACCESS_LOCK</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>APB_PERIPHERAL_ACCESS_1</name>
          <description>register description</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>APB_PERIPHERAL_ACCESS_SPLIT_BURST</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTERNAL_SRAM_USAGE_0</name>
          <description>register description</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>INTERNAL_SRAM_USAGE_LOCK</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTERNAL_SRAM_USAGE_1</name>
          <description>register description</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <resetValue>0x0000000F</resetValue>
          <fields>
            <field>
              <name>INTERNAL_SRAM_USAGE_CPU_CACHE</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INTERNAL_SRAM_USAGE_CPU_SRAM</name>
              <description>Need add description</description>
              <bitOffset>1</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTERNAL_SRAM_USAGE_3</name>
          <description>register description</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INTERNAL_SRAM_ALLOC_MAC_DUMP</name>
              <description>Need add description</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_TAG_ACCESS_0</name>
          <description>register description</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CACHE_TAG_ACCESS_LOCK</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_TAG_ACCESS_1</name>
          <description>register description</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <resetValue>0x0000000F</resetValue>
          <fields>
            <field>
              <name>PRO_I_TAG_RD_ACS</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PRO_I_TAG_WR_ACS</name>
              <description>Need add description</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PRO_D_TAG_RD_ACS</name>
              <description>Need add description</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PRO_D_TAG_WR_ACS</name>
              <description>Need add description</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_MMU_ACCESS_0</name>
          <description>register description</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CACHE_MMU_ACCESS_LOCK</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_MMU_ACCESS_1</name>
          <description>register description</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000003</resetValue>
          <fields>
            <field>
              <name>PRO_MMU_RD_ACS</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PRO_MMU_WR_ACS</name>
              <description>Need add description</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIF_ACCESS_MONITOR_0</name>
          <description>register description</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PIF_ACCESS_MONITOR_LOCK</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIF_ACCESS_MONITOR_1</name>
          <description>register description</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000003</resetValue>
          <fields>
            <field>
              <name>PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN</name>
              <description>Need add description</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIF_ACCESS_MONITOR_2</name>
          <description>register description</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE</name>
              <description>Need add description</description>
              <bitOffset>1</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIF_ACCESS_MONITOR_3</name>
          <description>register description</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>XTS_AES_KEY_UPDATE</name>
          <description>register description</description>
          <addressOffset>0x3C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>XTS_AES_KEY_UPDATE</name>
              <description>Set this bit to update xts_aes key</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLOCK_GATE</name>
          <description>register description</description>
          <addressOffset>0x40</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>CLK_EN</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SENSITIVE_REG_DATE</name>
          <description>register description</description>
          <addressOffset>0xFFC</addressOffset>
          <size>0x20</size>
          <resetValue>0x02106301</resetValue>
          <fields>
            <field>
              <name>SENSITIVE_REG_DATE</name>
              <description>Need add description</description>
              <bitOffset>0</bitOffset>
              <bitWidth>28</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>SHA</name>
      <description>SHA (Secure Hash Algorithm) Accelerator</description>
      <groupName>SHA</groupName>
      <baseAddress>0x6003B000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0xB0</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>SHA</name>
        <value>34</value>
      </interrupt>
      <registers>
        <register>
          <name>MODE</name>
          <description>Initial configuration register.</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>MODE</name>
              <description>Sha mode.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>T_STRING</name>
          <description>SHA 512/t configuration register 0.</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>T_STRING</name>
              <description>Sha t_string (used if and only if mode == SHA_512/t).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>T_LENGTH</name>
          <description>SHA 512/t configuration register 1.</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>T_LENGTH</name>
              <description>Sha t_length (used if and only if mode == SHA_512/t).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_BLOCK_NUM</name>
          <description>DMA configuration register 0.</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DMA_BLOCK_NUM</name>
              <description>Dma-sha block number.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>START</name>
          <description>Typical SHA configuration register 0.</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>START</name>
              <description>Reserved.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>31</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CONTINUE</name>
          <description>Typical SHA configuration register 1.</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CONTINUE</name>
              <description>Reserved.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>31</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>BUSY</name>
          <description>Busy register.</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>STATE</name>
              <description>Sha busy state. 1'b0: idle. 1'b1: busy.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_START</name>
          <description>DMA configuration register 1.</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DMA_START</name>
              <description>Start dma-sha.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_CONTINUE</name>
          <description>DMA configuration register 2.</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DMA_CONTINUE</name>
              <description>Continue dma-sha.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLEAR_IRQ</name>
          <description>Interrupt clear register.</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CLEAR_INTERRUPT</name>
              <description>Clear sha interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IRQ_ENA</name>
          <description>Interrupt enable register.</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>INTERRUPT_ENA</name>
              <description>Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DATE</name>
          <description>Date register.</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <resetValue>0x20200616</resetValue>
          <fields>
            <field>
              <name>DATE</name>
              <description>Sha date information/ sha version information.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>30</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>64</dim>
          <dimIncrement>0x1</dimIncrement>
          <name>H_MEM[%s]</name>
          <description>Sha H memory which contains intermediate hash or finial hash.</description>
          <addressOffset>0x40</addressOffset>
          <size>0x8</size>
        </register>
        <register>
          <dim>64</dim>
          <dimIncrement>0x1</dimIncrement>
          <name>M_MEM[%s]</name>
          <description>Sha M memory which contains message.</description>
          <addressOffset>0x80</addressOffset>
          <size>0x8</size>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>SPI0</name>
      <description>SPI (Serial Peripheral Interface) Controller</description>
      <groupName>SPI0</groupName>
      <baseAddress>0x60003000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x48</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>SPI_MEM_REJECT_CACHE</name>
        <value>29</value>
      </interrupt>
      <registers>
        <register>
          <name>CTRL</name>
          <description>SPI0 control register.</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <resetValue>0x002C2000</resetValue>
          <fields>
            <field>
              <name>FDUMMY_OUT</name>
              <description>In the dummy phase the signal level of spi is output by the spi controller.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FCMD_DUAL</name>
              <description>Apply 2 signals during command phase 1:enable 0: disable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FCMD_QUAD</name>
              <description>Apply 4 signals during command phase 1:enable 0: disable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FASTRD_MODE</name>
              <description>This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT AND SPI_MEM_FREAD_DOUT. 1: enable 0: disable.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FREAD_DUAL</name>
              <description>In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>Q_POL</name>
              <description>The bit is used to set MISO line polarity, 1: high 0, low</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>D_POL</name>
              <description>The bit is used to set MOSI line polarity, 1: high 0, low</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FREAD_QUAD</name>
              <description>In the read operations read-data phase apply 4 signals. 1: enable 0: disable.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WP</name>
              <description>Write protect signal output when SPI is idle.  1: output high, 0: output low.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FREAD_DIO</name>
              <description>In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FREAD_QIO</name>
              <description>In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL1</name>
          <description>SPI0 control1 register.</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CLK_MODE</name>
              <description>SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RXFIFO_RST</name>
              <description>SPI0 RX FIFO reset signal.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL2</name>
          <description>SPI0 control2 register.</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000021</resetValue>
          <fields>
            <field>
              <name>CS_SETUP_TIME</name>
              <description>(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CS_HOLD_TIME</name>
              <description>Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CS_HOLD_DELAY</name>
              <description>These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SYNC_RESET</name>
              <description>The FSM will be reset.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLOCK</name>
          <description>SPI clock division control register.</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <resetValue>0x00030103</resetValue>
          <fields>
            <field>
              <name>CLKCNT_L</name>
              <description>In the master mode it must be equal to spi_mem_clkcnt_N.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLKCNT_H</name>
              <description>In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLKCNT_N</name>
              <description>In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_EQU_SYSCLK</name>
              <description>Set this bit in 1-division mode.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>USER</name>
          <description>SPI0 user register.</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CS_HOLD</name>
              <description>spi cs keep low when spi is in  done  phase. 1: enable 0: disable.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CS_SETUP</name>
              <description>spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CK_OUT_EDGE</name>
              <description>the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_DUMMY_IDLE</name>
              <description>spi clock is disable in dummy phase when the bit is enable.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_DUMMY</name>
              <description>This bit enable the dummy phase of an operation.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>USER1</name>
          <description>SPI0 user1 register.</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <resetValue>0x5C000007</resetValue>
          <fields>
            <field>
              <name>USR_DUMMY_CYCLELEN</name>
              <description>The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_ADDR_BITLEN</name>
              <description>The length in bits of address phase. The register value shall be (bit_num-1).</description>
              <bitOffset>26</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>USER2</name>
          <description>SPI0 user2 register.</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <resetValue>0x70000000</resetValue>
          <fields>
            <field>
              <name>USR_COMMAND_VALUE</name>
              <description>The value of  command.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_COMMAND_BITLEN</name>
              <description>The length in bits of command phase. The register value shall be (bit_num-1)</description>
              <bitOffset>28</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_STATUS</name>
          <description>SPI0 read control register.</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>WB_MODE</name>
              <description>Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MISC</name>
          <description>SPI0 misc register</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TRANS_END</name>
              <description>The bit is used to indicate the  spi0_mst_st controlled transmitting is done.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TRANS_END_INT_ENA</name>
              <description>The bit is used to enable the interrupt of  spi0_mst_st controlled transmitting is done.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CSPI_ST_TRANS_END</name>
              <description>The bit is used to indicate the  spi0_slv_st controlled transmitting is done.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CSPI_ST_TRANS_END_INT_ENA</name>
              <description>The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CK_IDLE_EDGE</name>
              <description>1: spi clk line is high when idle     0: spi clk line is low when idle</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CS_KEEP_ACTIVE</name>
              <description>spi cs line keep low when the bit is set.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_FCTRL</name>
          <description>SPI0 bit mode control register.</description>
          <addressOffset>0x3C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CACHE_REQ_EN</name>
              <description>For SPI0, Cache access enable, 1: enable, 0:disable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CACHE_USR_ADDR_4BYTE</name>
              <description>For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CACHE_FLASH_USR_CMD</name>
              <description>For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FDIN_DUAL</name>
              <description>For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FDOUT_DUAL</name>
              <description>For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FADDR_DUAL</name>
              <description>For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FDIN_QUAD</name>
              <description>For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FDOUT_QUAD</name>
              <description>For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FADDR_QUAD</name>
              <description>For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FSM</name>
          <description>SPI0 FSM status register</description>
          <addressOffset>0x54</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000200</resetValue>
          <fields>
            <field>
              <name>CSPI_ST</name>
              <description>The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>EM_ST</name>
              <description>The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CSPI_LOCK_DELAY_TIME</name>
              <description>The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TIMING_CALI</name>
          <description>SPI0 timing calibration register</description>
          <addressOffset>0xA8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMING_CLK_ENA</name>
              <description>The bit is used to enable timing adjust clock for all reading operations.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TIMING_CALI</name>
              <description>The bit is used to enable timing auto-calibration for all reading operations.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>EXTRA_DUMMY_CYCLELEN</name>
              <description>add extra dummy spi clock cycle length for spi clock calibration.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DIN_MODE</name>
          <description>SPI0 input delay mode control register</description>
          <addressOffset>0xAC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DIN0_MODE</name>
              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIN1_MODE</name>
              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIN2_MODE</name>
              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIN3_MODE</name>
              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DIN_NUM</name>
          <description>SPI0 input delay number control register</description>
          <addressOffset>0xB0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DIN0_NUM</name>
              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIN1_NUM</name>
              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIN2_NUM</name>
              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIN3_NUM</name>
              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DOUT_MODE</name>
          <description>SPI0 output delay mode control register</description>
          <addressOffset>0xB4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DOUT0_MODE</name>
              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DOUT1_MODE</name>
              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DOUT2_MODE</name>
              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DOUT3_MODE</name>
              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLOCK_GATE</name>
          <description>SPI0 clk_gate register</description>
          <addressOffset>0xDC</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>CLK_EN</name>
              <description>Register clock gate enable signal. 1: Enable. 0: Disable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORE_CLK_SEL</name>
          <description>SPI0 module clock select register</description>
          <addressOffset>0xE0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SPI01_CLK_SEL</name>
              <description>When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DATE</name>
          <description>Version control register</description>
          <addressOffset>0x3FC</addressOffset>
          <size>0x20</size>
          <resetValue>0x02106191</resetValue>
          <fields>
            <field>
              <name>DATE</name>
              <description>SPI register version.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>28</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>SPI1</name>
      <description>SPI (Serial Peripheral Interface) Controller</description>
      <groupName>SPI1</groupName>
      <baseAddress>0x60002000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0xA8</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>CMD</name>
          <description>SPI1 memory command register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SPI1_MST_ST</name>
              <description>The current status of SPI1 master FSM.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MSPI_ST</name>
              <description>The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FLASH_PE</name>
              <description>In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR</name>
              <description>User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_HPM</name>
              <description>Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_RES</name>
              <description>This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_DP</name>
              <description>Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_CE</name>
              <description>Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_BE</name>
              <description>Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_SE</name>
              <description>Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_PP</name>
              <description>Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_WRSR</name>
              <description>Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_RDSR</name>
              <description>Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_RDID</name>
              <description>Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_WRDI</name>
              <description>Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_WREN</name>
              <description>Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_READ</name>
              <description>Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ADDR</name>
          <description>SPI1 address register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>USR_ADDR_VALUE</name>
              <description>In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL</name>
          <description>SPI1 control register.</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <resetValue>0x002CA000</resetValue>
          <fields>
            <field>
              <name>FDUMMY_OUT</name>
              <description>In the dummy phase the signal level of spi is output by the spi controller.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FCMD_DUAL</name>
              <description>Apply 2 signals during command phase 1:enable 0: disable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FCMD_QUAD</name>
              <description>Apply 4 signals during command phase 1:enable 0: disable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FCS_CRC_EN</name>
              <description>For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_CRC_EN</name>
              <description>For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FASTRD_MODE</name>
              <description>This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FREAD_DUAL</name>
              <description>In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RESANDRES</name>
              <description>The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>Q_POL</name>
              <description>The bit is used to set MISO line polarity, 1: high 0, low</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>D_POL</name>
              <description>The bit is used to set MOSI line polarity, 1: high 0, low</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FREAD_QUAD</name>
              <description>In the read operations read-data phase apply 4 signals. 1: enable 0: disable.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WP</name>
              <description>Write protect signal output when SPI is idle.  1: output high, 0: output low.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WRSR_2B</name>
              <description>two bytes data will be written to status register when it is set. 1: enable 0: disable.</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FREAD_DIO</name>
              <description>In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FREAD_QIO</name>
              <description>In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL1</name>
          <description>SPI1 control1 register.</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000FFC</resetValue>
          <fields>
            <field>
              <name>CLK_MODE</name>
              <description>SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CS_HOLD_DLY_RES</name>
              <description>After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL2</name>
          <description>SPI1 control2 register.</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SYNC_RESET</name>
              <description>The FSM will be reset.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLOCK</name>
          <description>SPI1 clock division control register.</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <resetValue>0x00030103</resetValue>
          <fields>
            <field>
              <name>CLKCNT_L</name>
              <description>In the master mode it must be equal to spi_mem_clkcnt_N.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLKCNT_H</name>
              <description>In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLKCNT_N</name>
              <description>In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_EQU_SYSCLK</name>
              <description>reserved</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>USER</name>
          <description>SPI1 user register.</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <resetValue>0x80000000</resetValue>
          <fields>
            <field>
              <name>CK_OUT_EDGE</name>
              <description>the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FWRITE_DUAL</name>
              <description>In the write operations read-data phase apply 2 signals</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FWRITE_QUAD</name>
              <description>In the write operations read-data phase apply 4 signals</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FWRITE_DIO</name>
              <description>In the write operations address phase and read-data phase apply 2 signals.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FWRITE_QIO</name>
              <description>In the write operations address phase and read-data phase apply 4 signals.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_MISO_HIGHPART</name>
              <description>read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_MOSI_HIGHPART</name>
              <description>write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_DUMMY_IDLE</name>
              <description>SPI clock is disable in dummy phase when the bit is enable.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_MOSI</name>
              <description>This bit enable the write-data phase of an operation.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_MISO</name>
              <description>This bit enable the read-data phase of an operation.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_DUMMY</name>
              <description>This bit enable the dummy phase of an operation.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_ADDR</name>
              <description>This bit enable the address phase of an operation.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_COMMAND</name>
              <description>This bit enable the command phase of an operation.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>USER1</name>
          <description>SPI1 user1 register.</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <resetValue>0x5C000007</resetValue>
          <fields>
            <field>
              <name>USR_DUMMY_CYCLELEN</name>
              <description>The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_ADDR_BITLEN</name>
              <description>The length in bits of address phase. The register value shall be (bit_num-1).</description>
              <bitOffset>26</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>USER2</name>
          <description>SPI1 user2 register.</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <resetValue>0x70000000</resetValue>
          <fields>
            <field>
              <name>USR_COMMAND_VALUE</name>
              <description>The value of  command.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_COMMAND_BITLEN</name>
              <description>The length in bits of command phase. The register value shall be (bit_num-1)</description>
              <bitOffset>28</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MOSI_DLEN</name>
          <description>SPI1 send data bit length control register.</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>USR_MOSI_DBITLEN</name>
              <description>The length in bits of write-data. The register value shall be (bit_num-1).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MISO_DLEN</name>
          <description>SPI1 receive data bit length control register.</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>USR_MISO_DBITLEN</name>
              <description>The length in bits of  read-data. The register value shall be (bit_num-1).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RD_STATUS</name>
          <description>SPI1 status register.</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>STATUS</name>
              <description>The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WB_MODE</name>
              <description>Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MISC</name>
          <description>SPI1 misc register</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000002</resetValue>
          <fields>
            <field>
              <name>CS0_DIS</name>
              <description>SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CS1_DIS</name>
              <description>SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CK_IDLE_EDGE</name>
              <description>1: spi clk line is high when idle     0: spi clk line is low when idle</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CS_KEEP_ACTIVE</name>
              <description>spi cs line keep low when the bit is set.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TX_CRC</name>
          <description>SPI1 TX CRC data register.</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <resetValue>0xFFFFFFFF</resetValue>
          <fields>
            <field>
              <name>DATA</name>
              <description>For SPI1, the value of crc32.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_FCTRL</name>
          <description>SPI1 bit mode control register.</description>
          <addressOffset>0x3C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CACHE_USR_ADDR_4BYTE</name>
              <description>For SPI1,  cache  read flash with 4 bytes address, 1: enable, 0:disable.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FDIN_DUAL</name>
              <description>For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FDOUT_DUAL</name>
              <description>For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FADDR_DUAL</name>
              <description>For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FDIN_QUAD</name>
              <description>For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FDOUT_QUAD</name>
              <description>For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FADDR_QUAD</name>
              <description>For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W0</name>
          <description>SPI1 memory data buffer0</description>
          <addressOffset>0x58</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF0</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W1</name>
          <description>SPI1 memory data buffer1</description>
          <addressOffset>0x5C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF1</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W2</name>
          <description>SPI1 memory data buffer2</description>
          <addressOffset>0x60</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF2</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W3</name>
          <description>SPI1 memory data buffer3</description>
          <addressOffset>0x64</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF3</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W4</name>
          <description>SPI1 memory data buffer4</description>
          <addressOffset>0x68</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF4</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W5</name>
          <description>SPI1 memory data buffer5</description>
          <addressOffset>0x6C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF5</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W6</name>
          <description>SPI1 memory data buffer6</description>
          <addressOffset>0x70</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF6</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W7</name>
          <description>SPI1 memory data buffer7</description>
          <addressOffset>0x74</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF7</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W8</name>
          <description>SPI1 memory data buffer8</description>
          <addressOffset>0x78</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF8</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W9</name>
          <description>SPI1 memory data buffer9</description>
          <addressOffset>0x7C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF9</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W10</name>
          <description>SPI1 memory data buffer10</description>
          <addressOffset>0x80</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF10</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W11</name>
          <description>SPI1 memory data buffer11</description>
          <addressOffset>0x84</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF11</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W12</name>
          <description>SPI1 memory data buffer12</description>
          <addressOffset>0x88</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF12</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W13</name>
          <description>SPI1 memory data buffer13</description>
          <addressOffset>0x8C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF13</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W14</name>
          <description>SPI1 memory data buffer14</description>
          <addressOffset>0x90</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF14</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W15</name>
          <description>SPI1 memory data buffer15</description>
          <addressOffset>0x94</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF15</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FLASH_WAITI_CTRL</name>
          <description>SPI1 wait idle control register</description>
          <addressOffset>0x98</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000014</resetValue>
          <fields>
            <field>
              <name>WAITI_DUMMY</name>
              <description>The dummy phase enable when wait flash idle (RDSR)</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WAITI_CMD</name>
              <description>The command to wait flash idle(RDSR).</description>
              <bitOffset>2</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WAITI_DUMMY_CYCLELEN</name>
              <description>The dummy cycle length when wait flash idle(RDSR).</description>
              <bitOffset>10</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FLASH_SUS_CTRL</name>
          <description>SPI1 flash suspend control register</description>
          <addressOffset>0x9C</addressOffset>
          <size>0x20</size>
          <resetValue>0x08002000</resetValue>
          <fields>
            <field>
              <name>FLASH_PER</name>
              <description>program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_PES</name>
              <description>program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_PER_WAIT_EN</name>
              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_PES_WAIT_EN</name>
              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PES_PER_EN</name>
              <description>Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_PES_EN</name>
              <description>Set this bit to enable Auto-suspending function.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PESR_END_MSK</name>
              <description>The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].</description>
              <bitOffset>6</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SPI_FMEM_RD_SUS_2B</name>
              <description>1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PER_END_EN</name>
              <description>1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PES_END_EN</name>
              <description>1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SUS_TIMEOUT_CNT</name>
              <description>When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FLASH_SUS_CMD</name>
          <description>SPI1 flash suspend command register</description>
          <addressOffset>0xA0</addressOffset>
          <size>0x20</size>
          <resetValue>0x0005757A</resetValue>
          <fields>
            <field>
              <name>FLASH_PER_COMMAND</name>
              <description>Program/Erase resume command.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_PES_COMMAND</name>
              <description>Program/Erase suspend command.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WAIT_PESR_COMMAND</name>
              <description>Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SUS_STATUS</name>
          <description>SPI1 flash suspend status register</description>
          <addressOffset>0xA4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>FLASH_SUS</name>
              <description>The status of flash suspend, only used in SPI1.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WAIT_PESR_CMD_2B</name>
              <description>1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_HPM_DLY_128</name>
              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_RES_DLY_128</name>
              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_DP_DLY_128</name>
              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_PER_DLY_128</name>
              <description>Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_PES_DLY_128</name>
              <description>Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SPI0_LOCK_EN</name>
              <description>1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TIMING_CALI</name>
          <description>SPI1 timing control register</description>
          <addressOffset>0xA8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMING_CALI</name>
              <description>The bit is used to enable timing auto-calibration for all reading operations.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>EXTRA_DUMMY_CYCLELEN</name>
              <description>add extra dummy spi clock cycle length for spi clock calibration.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_ENA</name>
          <description>SPI1 interrupt enable register</description>
          <addressOffset>0xC0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PER_END_INT_ENA</name>
              <description>The enable bit for SPI_MEM_PER_END_INT interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PES_END_INT_ENA</name>
              <description>The enable bit for SPI_MEM_PES_END_INT interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WPE_END_INT_ENA</name>
              <description>The enable bit for SPI_MEM_WPE_END_INT interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLV_ST_END_INT_ENA</name>
              <description>The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MST_ST_END_INT_ENA</name>
              <description>The enable bit for SPI_MEM_MST_ST_END_INT interrupt.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BROWN_OUT_INT_ENA</name>
              <description>The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_CLR</name>
          <description>SPI1 interrupt clear register</description>
          <addressOffset>0xC4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PER_END_INT_CLR</name>
              <description>The clear bit for SPI_MEM_PER_END_INT interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>PES_END_INT_CLR</name>
              <description>The clear bit for SPI_MEM_PES_END_INT interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>WPE_END_INT_CLR</name>
              <description>The clear bit for SPI_MEM_WPE_END_INT interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_ST_END_INT_CLR</name>
              <description>The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MST_ST_END_INT_CLR</name>
              <description>The clear bit for SPI_MEM_MST_ST_END_INT interrupt.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>BROWN_OUT_INT_CLR</name>
              <description>The status bit for SPI_MEM_BROWN_OUT_INT interrupt.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_RAW</name>
          <description>SPI1 interrupt raw register</description>
          <addressOffset>0xC8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PER_END_INT_RAW</name>
              <description>The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PES_END_INT_RAW</name>
              <description>The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>WPE_END_INT_RAW</name>
              <description>The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_ST_END_INT_RAW</name>
              <description>The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MST_ST_END_INT_RAW</name>
              <description>The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BROWN_OUT_INT_RAW</name>
              <description>The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_ST</name>
          <description>SPI1 interrupt status register</description>
          <addressOffset>0xCC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PER_END_INT_ST</name>
              <description>The status bit for SPI_MEM_PER_END_INT interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PES_END_INT_ST</name>
              <description>The status bit for SPI_MEM_PES_END_INT interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>WPE_END_INT_ST</name>
              <description>The status bit for SPI_MEM_WPE_END_INT interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_ST_END_INT_ST</name>
              <description>The status bit for SPI_MEM_SLV_ST_END_INT interrupt.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MST_ST_END_INT_ST</name>
              <description>The status bit for SPI_MEM_MST_ST_END_INT interrupt.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BROWN_OUT_INT_ST</name>
              <description>The status bit for SPI_MEM_BROWN_OUT_INT interrupt.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLOCK_GATE</name>
          <description>SPI1 clk_gate register</description>
          <addressOffset>0xDC</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>CLK_EN</name>
              <description>Register clock gate enable signal. 1: Enable. 0: Disable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DATE</name>
          <description>Version control register</description>
          <addressOffset>0x3FC</addressOffset>
          <size>0x20</size>
          <resetValue>0x02107013</resetValue>
          <fields>
            <field>
              <name>DATE</name>
              <description>Version control register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>28</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>SPI2</name>
      <description>SPI (Serial Peripheral Interface) Controller</description>
      <groupName>SPI2</groupName>
      <baseAddress>0x60024000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x98</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>SPI_INTR_1</name>
        <value>15</value>
      </interrupt>
      <interrupt>
        <name>SPI_INTR_2</name>
        <value>16</value>
      </interrupt>
      <registers>
        <register>
          <name>CMD</name>
          <description>Command control register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CONF_BITLEN</name>
              <description>Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>18</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>UPDATE</name>
              <description>Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR</name>
              <description>User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ADDR</name>
          <description>Address value register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>USR_ADDR_VALUE</name>
              <description>Address to slave. Can be configured in CONF state.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL</name>
          <description>SPI control register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <resetValue>0x003C0000</resetValue>
          <fields>
            <field>
              <name>DUMMY_OUT</name>
              <description>0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FADDR_DUAL</name>
              <description>Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FADDR_QUAD</name>
              <description>Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FADDR_OCT</name>
              <description>Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FCMD_DUAL</name>
              <description>Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FCMD_QUAD</name>
              <description>Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FCMD_OCT</name>
              <description>Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FREAD_DUAL</name>
              <description>In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FREAD_QUAD</name>
              <description>In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can be configured in CONF state.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FREAD_OCT</name>
              <description>In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can be configured in CONF state.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>Q_POL</name>
              <description>The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>D_POL</name>
              <description>The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>HOLD_POL</name>
              <description>SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WP_POL</name>
              <description>Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RD_BIT_ORDER</name>
              <description>In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.</description>
              <bitOffset>23</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WR_BIT_ORDER</name>
              <description>In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLOCK</name>
          <description>SPI clock control register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <resetValue>0x80003043</resetValue>
          <fields>
            <field>
              <name>CLKCNT_L</name>
              <description>In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLKCNT_H</name>
              <description>In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLKCNT_N</name>
              <description>In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLKDIV_PRE</name>
              <description>In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_EQU_SYSCLK</name>
              <description>In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>USER</name>
          <description>SPI USER control register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <resetValue>0x800000C0</resetValue>
          <fields>
            <field>
              <name>DOUTDIN</name>
              <description>Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>QPI_MODE</name>
              <description>Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OPI_MODE</name>
              <description>Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TSCK_I_EDGE</name>
              <description>In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CS_HOLD</name>
              <description>spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be configured in CONF state.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CS_SETUP</name>
              <description>spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be configured in CONF state.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RSCK_I_EDGE</name>
              <description>In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CK_OUT_EDGE</name>
              <description>the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FWRITE_DUAL</name>
              <description>In the write operations read-data phase apply 2 signals. Can be configured in CONF state.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FWRITE_QUAD</name>
              <description>In the write operations read-data phase apply 4 signals. Can be configured in CONF state.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FWRITE_OCT</name>
              <description>In the write operations read-data phase apply 8 signals. Can be configured in CONF state.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>USR_CONF_NXT</name>
              <description>1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SIO</name>
              <description>Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_MISO_HIGHPART</name>
              <description>read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_MOSI_HIGHPART</name>
              <description>write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.  Can be configured in CONF state.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_DUMMY_IDLE</name>
              <description>spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_MOSI</name>
              <description>This bit enable the write-data phase of an operation. Can be configured in CONF state.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_MISO</name>
              <description>This bit enable the read-data phase of an operation. Can be configured in CONF state.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_DUMMY</name>
              <description>This bit enable the dummy phase of an operation. Can be configured in CONF state.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_ADDR</name>
              <description>This bit enable the address phase of an operation. Can be configured in CONF state.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_COMMAND</name>
              <description>This bit enable the command phase of an operation. Can be configured in CONF state.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>USER1</name>
          <description>SPI USER control register 1</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <resetValue>0xB8410007</resetValue>
          <fields>
            <field>
              <name>USR_DUMMY_CYCLELEN</name>
              <description>The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MST_WFULL_ERR_END_EN</name>
              <description>1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CS_SETUP_TIME</name>
              <description>(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CS_HOLD_TIME</name>
              <description>delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.</description>
              <bitOffset>22</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_ADDR_BITLEN</name>
              <description>The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>USER2</name>
          <description>SPI USER control register 2</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <resetValue>0x78000000</resetValue>
          <fields>
            <field>
              <name>USR_COMMAND_VALUE</name>
              <description>The value of  command. Can be configured in CONF state.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MST_REMPTY_ERR_END_EN</name>
              <description>1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USR_COMMAND_BITLEN</name>
              <description>The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MS_DLEN</name>
          <description>SPI data bit length control register</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>MS_DATA_BITLEN</name>
              <description>The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>18</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MISC</name>
          <description>SPI misc register</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <resetValue>0x0000003E</resetValue>
          <fields>
            <field>
              <name>CS0_DIS</name>
              <description>SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CS1_DIS</name>
              <description>SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CS2_DIS</name>
              <description>SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CS3_DIS</name>
              <description>SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CS4_DIS</name>
              <description>SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CS5_DIS</name>
              <description>SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CK_DIS</name>
              <description>1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MASTER_CS_POL</name>
              <description>In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_DATA_DTR_EN</name>
              <description>1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DATA_DTR_EN</name>
              <description>1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ADDR_DTR_EN</name>
              <description>1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CMD_DTR_EN</name>
              <description>1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLAVE_CS_POL</name>
              <description>spi slave input cs polarity select. 1: inv  0: not change. Can be configured in CONF state.</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DQS_IDLE_EDGE</name>
              <description>The default value of spi_dqs. Can be configured in CONF state.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CK_IDLE_EDGE</name>
              <description>1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CS_KEEP_ACTIVE</name>
              <description>spi cs line keep low when the bit is set. Can be configured in CONF state.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>QUAD_DIN_PIN_SWAP</name>
              <description>1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:  spi quad input swap disable. Can be configured in CONF state.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DIN_MODE</name>
          <description>SPI input delay mode configuration</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DIN0_MODE</name>
              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIN1_MODE</name>
              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIN2_MODE</name>
              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIN3_MODE</name>
              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIN4_MODE</name>
              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIN5_MODE</name>
              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIN6_MODE</name>
              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIN7_MODE</name>
              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TIMING_HCLK_ACTIVE</name>
              <description>1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF state.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DIN_NUM</name>
          <description>SPI input delay number configuration</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DIN0_NUM</name>
              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIN1_NUM</name>
              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIN2_NUM</name>
              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIN3_NUM</name>
              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIN4_NUM</name>
              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIN5_NUM</name>
              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIN6_NUM</name>
              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DIN7_NUM</name>
              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DOUT_MODE</name>
          <description>SPI output delay mode configuration</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DOUT0_MODE</name>
              <description>The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DOUT1_MODE</name>
              <description>The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DOUT2_MODE</name>
              <description>The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DOUT3_MODE</name>
              <description>The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DOUT4_MODE</name>
              <description>The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DOUT5_MODE</name>
              <description>The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DOUT6_MODE</name>
              <description>The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DOUT7_MODE</name>
              <description>The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>D_DQS_MODE</name>
              <description>The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_CONF</name>
          <description>SPI DMA control register</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000003</resetValue>
          <fields>
            <field>
              <name>DMA_OUTFIFO_EMPTY</name>
              <description>Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DMA_INFIFO_FULL</name>
              <description>Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DMA_SLV_SEG_TRANS_EN</name>
              <description>Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLV_RX_SEG_TRANS_CLR_EN</name>
              <description>1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLV_TX_SEG_TRANS_CLR_EN</name>
              <description>1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_EOF_EN</name>
              <description>1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_RX_ENA</name>
              <description>Set this bit to enable SPI DMA controlled receive data mode.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_TX_ENA</name>
              <description>Set this bit to enable SPI DMA controlled send data mode.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_AFIFO_RST</name>
              <description>Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>BUF_AFIFO_RST</name>
              <description>Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>DMA_AFIFO_RST</name>
              <description>Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_INT_ENA</name>
          <description>SPI interrupt enable register</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DMA_INFIFO_FULL_ERR_INT_ENA</name>
              <description>The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_OUTFIFO_EMPTY_ERR_INT_ENA</name>
              <description>The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLV_EX_QPI_INT_ENA</name>
              <description>The enable bit for SPI slave Ex_QPI interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLV_EN_QPI_INT_ENA</name>
              <description>The enable bit for SPI slave En_QPI interrupt.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLV_CMD7_INT_ENA</name>
              <description>The enable bit for SPI slave CMD7 interrupt.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLV_CMD8_INT_ENA</name>
              <description>The enable bit for SPI slave CMD8 interrupt.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLV_CMD9_INT_ENA</name>
              <description>The enable bit for SPI slave CMD9 interrupt.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLV_CMDA_INT_ENA</name>
              <description>The enable bit for SPI slave CMDA interrupt.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLV_RD_DMA_DONE_INT_ENA</name>
              <description>The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLV_WR_DMA_DONE_INT_ENA</name>
              <description>The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLV_RD_BUF_DONE_INT_ENA</name>
              <description>The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLV_WR_BUF_DONE_INT_ENA</name>
              <description>The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TRANS_DONE_INT_ENA</name>
              <description>The enable bit for SPI_TRANS_DONE_INT interrupt.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_SEG_TRANS_DONE_INT_ENA</name>
              <description>The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SEG_MAGIC_ERR_INT_ENA</name>
              <description>The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLV_BUF_ADDR_ERR_INT_ENA</name>
              <description>The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLV_CMD_ERR_INT_ENA</name>
              <description>The enable bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MST_RX_AFIFO_WFULL_ERR_INT_ENA</name>
              <description>The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MST_TX_AFIFO_REMPTY_ERR_INT_ENA</name>
              <description>The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>APP2_INT_ENA</name>
              <description>The enable bit for SPI_APP2_INT interrupt.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>APP1_INT_ENA</name>
              <description>The enable bit for SPI_APP1_INT interrupt.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_INT_CLR</name>
          <description>SPI interrupt clear register</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DMA_INFIFO_FULL_ERR_INT_CLR</name>
              <description>The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>DMA_OUTFIFO_EMPTY_ERR_INT_CLR</name>
              <description>The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_EX_QPI_INT_CLR</name>
              <description>The clear bit for SPI slave Ex_QPI interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_EN_QPI_INT_CLR</name>
              <description>The clear bit for SPI slave En_QPI interrupt.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_CMD7_INT_CLR</name>
              <description>The clear bit for SPI slave CMD7 interrupt.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_CMD8_INT_CLR</name>
              <description>The clear bit for SPI slave CMD8 interrupt.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_CMD9_INT_CLR</name>
              <description>The clear bit for SPI slave CMD9 interrupt.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_CMDA_INT_CLR</name>
              <description>The clear bit for SPI slave CMDA interrupt.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_RD_DMA_DONE_INT_CLR</name>
              <description>The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_WR_DMA_DONE_INT_CLR</name>
              <description>The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_RD_BUF_DONE_INT_CLR</name>
              <description>The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_WR_BUF_DONE_INT_CLR</name>
              <description>The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>TRANS_DONE_INT_CLR</name>
              <description>The clear bit for SPI_TRANS_DONE_INT interrupt.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>DMA_SEG_TRANS_DONE_INT_CLR</name>
              <description>The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SEG_MAGIC_ERR_INT_CLR</name>
              <description>The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_BUF_ADDR_ERR_INT_CLR</name>
              <description>The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_CMD_ERR_INT_CLR</name>
              <description>The clear bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MST_RX_AFIFO_WFULL_ERR_INT_CLR</name>
              <description>The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MST_TX_AFIFO_REMPTY_ERR_INT_CLR</name>
              <description>The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>APP2_INT_CLR</name>
              <description>The clear bit for SPI_APP2_INT interrupt.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>APP1_INT_CLR</name>
              <description>The clear bit for SPI_APP1_INT interrupt.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_INT_RAW</name>
          <description>SPI interrupt raw register</description>
          <addressOffset>0x3C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DMA_INFIFO_FULL_ERR_INT_RAW</name>
              <description>1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data.  0: Others.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DMA_OUTFIFO_EMPTY_ERR_INT_RAW</name>
              <description>1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode.  0: Others.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_EX_QPI_INT_RAW</name>
              <description>The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_EN_QPI_INT_RAW</name>
              <description>The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_CMD7_INT_RAW</name>
              <description>The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_CMD8_INT_RAW</name>
              <description>The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_CMD9_INT_RAW</name>
              <description>The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_CMDA_INT_RAW</name>
              <description>The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_RD_DMA_DONE_INT_RAW</name>
              <description>The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_WR_DMA_DONE_INT_RAW</name>
              <description>The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_RD_BUF_DONE_INT_RAW</name>
              <description>The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_WR_BUF_DONE_INT_RAW</name>
              <description>The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TRANS_DONE_INT_RAW</name>
              <description>The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DMA_SEG_TRANS_DONE_INT_RAW</name>
              <description>The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is not ended or not occurred.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SEG_MAGIC_ERR_INT_RAW</name>
              <description>The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_BUF_ADDR_ERR_INT_RAW</name>
              <description>The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_CMD_ERR_INT_RAW</name>
              <description>The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MST_RX_AFIFO_WFULL_ERR_INT_RAW</name>
              <description>The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MST_TX_AFIFO_REMPTY_ERR_INT_RAW</name>
              <description>The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>APP2_INT_RAW</name>
              <description>The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>APP1_INT_RAW</name>
              <description>The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_INT_ST</name>
          <description>SPI interrupt status register</description>
          <addressOffset>0x40</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DMA_INFIFO_FULL_ERR_INT_ST</name>
              <description>The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DMA_OUTFIFO_EMPTY_ERR_INT_ST</name>
              <description>The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_EX_QPI_INT_ST</name>
              <description>The status bit for SPI slave Ex_QPI interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_EN_QPI_INT_ST</name>
              <description>The status bit for SPI slave En_QPI interrupt.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_CMD7_INT_ST</name>
              <description>The status bit for SPI slave CMD7 interrupt.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_CMD8_INT_ST</name>
              <description>The status bit for SPI slave CMD8 interrupt.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_CMD9_INT_ST</name>
              <description>The status bit for SPI slave CMD9 interrupt.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_CMDA_INT_ST</name>
              <description>The status bit for SPI slave CMDA interrupt.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_RD_DMA_DONE_INT_ST</name>
              <description>The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_WR_DMA_DONE_INT_ST</name>
              <description>The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_RD_BUF_DONE_INT_ST</name>
              <description>The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_WR_BUF_DONE_INT_ST</name>
              <description>The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TRANS_DONE_INT_ST</name>
              <description>The status bit for SPI_TRANS_DONE_INT interrupt.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DMA_SEG_TRANS_DONE_INT_ST</name>
              <description>The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SEG_MAGIC_ERR_INT_ST</name>
              <description>The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_BUF_ADDR_ERR_INT_ST</name>
              <description>The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLV_CMD_ERR_INT_ST</name>
              <description>The status bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MST_RX_AFIFO_WFULL_ERR_INT_ST</name>
              <description>The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MST_TX_AFIFO_REMPTY_ERR_INT_ST</name>
              <description>The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>APP2_INT_ST</name>
              <description>The status bit for SPI_APP2_INT interrupt.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>APP1_INT_ST</name>
              <description>The status bit for SPI_APP1_INT interrupt.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA_INT_SET</name>
          <description>SPI interrupt software set register</description>
          <addressOffset>0x44</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DMA_INFIFO_FULL_ERR_INT_SET</name>
              <description>The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>DMA_OUTFIFO_EMPTY_ERR_INT_SET</name>
              <description>The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_EX_QPI_INT_SET</name>
              <description>The software set bit for SPI slave Ex_QPI interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_EN_QPI_INT_SET</name>
              <description>The software set bit for SPI slave En_QPI interrupt.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_CMD7_INT_SET</name>
              <description>The software set bit for SPI slave CMD7 interrupt.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_CMD8_INT_SET</name>
              <description>The software set bit for SPI slave CMD8 interrupt.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_CMD9_INT_SET</name>
              <description>The software set bit for SPI slave CMD9 interrupt.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_CMDA_INT_SET</name>
              <description>The software set bit for SPI slave CMDA interrupt.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_RD_DMA_DONE_INT_SET</name>
              <description>The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_WR_DMA_DONE_INT_SET</name>
              <description>The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_RD_BUF_DONE_INT_SET</name>
              <description>The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_WR_BUF_DONE_INT_SET</name>
              <description>The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>TRANS_DONE_INT_SET</name>
              <description>The software set bit for SPI_TRANS_DONE_INT interrupt.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>DMA_SEG_TRANS_DONE_INT_SET</name>
              <description>The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SEG_MAGIC_ERR_INT_SET</name>
              <description>The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_BUF_ADDR_ERR_INT_SET</name>
              <description>The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLV_CMD_ERR_INT_SET</name>
              <description>The software set bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MST_RX_AFIFO_WFULL_ERR_INT_SET</name>
              <description>The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MST_TX_AFIFO_REMPTY_ERR_INT_SET</name>
              <description>The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>APP2_INT_SET</name>
              <description>The software set bit for SPI_APP2_INT interrupt.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>APP1_INT_SET</name>
              <description>The software set bit for SPI_APP1_INT interrupt.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W0</name>
          <description>SPI CPU-controlled buffer0</description>
          <addressOffset>0x98</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF0</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W1</name>
          <description>SPI CPU-controlled buffer1</description>
          <addressOffset>0x9C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF1</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W2</name>
          <description>SPI CPU-controlled buffer2</description>
          <addressOffset>0xA0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF2</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W3</name>
          <description>SPI CPU-controlled buffer3</description>
          <addressOffset>0xA4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF3</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W4</name>
          <description>SPI CPU-controlled buffer4</description>
          <addressOffset>0xA8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF4</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W5</name>
          <description>SPI CPU-controlled buffer5</description>
          <addressOffset>0xAC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF5</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W6</name>
          <description>SPI CPU-controlled buffer6</description>
          <addressOffset>0xB0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF6</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W7</name>
          <description>SPI CPU-controlled buffer7</description>
          <addressOffset>0xB4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF7</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W8</name>
          <description>SPI CPU-controlled buffer8</description>
          <addressOffset>0xB8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF8</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W9</name>
          <description>SPI CPU-controlled buffer9</description>
          <addressOffset>0xBC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF9</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W10</name>
          <description>SPI CPU-controlled buffer10</description>
          <addressOffset>0xC0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF10</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W11</name>
          <description>SPI CPU-controlled buffer11</description>
          <addressOffset>0xC4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF11</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W12</name>
          <description>SPI CPU-controlled buffer12</description>
          <addressOffset>0xC8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF12</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W13</name>
          <description>SPI CPU-controlled buffer13</description>
          <addressOffset>0xCC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF13</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W14</name>
          <description>SPI CPU-controlled buffer14</description>
          <addressOffset>0xD0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF14</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>W15</name>
          <description>SPI CPU-controlled buffer15</description>
          <addressOffset>0xD4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>BUF15</name>
              <description>data buffer</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLAVE</name>
          <description>SPI slave control register</description>
          <addressOffset>0xE0</addressOffset>
          <size>0x20</size>
          <resetValue>0x02800000</resetValue>
          <fields>
            <field>
              <name>CLK_MODE</name>
              <description>SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_MODE_13</name>
              <description>{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RSCK_DATA_OUT</name>
              <description>It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLV_RDDMA_BITLEN_EN</name>
              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLV_WRDMA_BITLEN_EN</name>
              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLV_RDBUF_BITLEN_EN</name>
              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLV_WRBUF_BITLEN_EN</name>
              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_SEG_MAGIC_VALUE</name>
              <description>The magic value of BM table in master DMA seg-trans.</description>
              <bitOffset>22</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MODE</name>
              <description>Set SPI work mode. 1: slave mode 0: master mode.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SOFT_RESET</name>
              <description>Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>USR_CONF</name>
              <description>1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLAVE1</name>
          <description>SPI slave control register 1</description>
          <addressOffset>0xE4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SLV_DATA_BITLEN</name>
              <description>The transferred data bit length in SPI slave FD and HD mode.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>18</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLV_LAST_COMMAND</name>
              <description>In the slave mode it is the value of command.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SLV_LAST_ADDR</name>
              <description>In the slave mode it is the value of address.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLK_GATE</name>
          <description>SPI module clock and register clock control</description>
          <addressOffset>0xE8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CLK_EN</name>
              <description>Set this bit to enable clk gate</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MST_CLK_ACTIVE</name>
              <description>Set this bit to power on the SPI module clock.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MST_CLK_SEL</name>
              <description>This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DATE</name>
          <description>Version control</description>
          <addressOffset>0xF0</addressOffset>
          <size>0x20</size>
          <resetValue>0x02106070</resetValue>
          <fields>
            <field>
              <name>DATE</name>
              <description>SPI register version.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>28</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>SYSTEM</name>
      <description>System</description>
      <groupName>SYSTEM</groupName>
      <baseAddress>0x600C0000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0xA0</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>CPU_PERI_CLK_EN</name>
          <description>cpu_peripheral clock gating register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CLK_EN_ASSIST_DEBUG</name>
              <description>Set 1 to open assist_debug module clock</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_EN_DEDICATED_GPIO</name>
              <description>Set 1 to open dedicated_gpio module clk</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_PERI_RST_EN</name>
          <description>cpu_peripheral reset register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <resetValue>0x000000C0</resetValue>
          <fields>
            <field>
              <name>RST_EN_ASSIST_DEBUG</name>
              <description>Set 1 to let assist_debug module reset</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RST_EN_DEDICATED_GPIO</name>
              <description>Set 1 to let dedicated_gpio module reset</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_PER_CONF</name>
          <description>cpu clock config register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <resetValue>0x0000000C</resetValue>
          <fields>
            <field>
              <name>CPUPERIOD_SEL</name>
              <description>This field used to sel cpu clock frequent.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PLL_FREQ_SEL</name>
              <description>This field used to sel pll frequent.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CPU_WAIT_MODE_FORCE_ON</name>
              <description>Set 1 to force cpu_waiti_clk enable.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CPU_WAITI_DELAY_NUM</name>
              <description>This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MEM_PD_MASK</name>
          <description>memory power down mask register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>LSLP_MEM_PD_MASK</name>
              <description>Set 1 to mask memory power down.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PERIP_CLK_EN0</name>
          <description>peripheral clock gating register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <resetValue>0x71002066</resetValue>
          <fields>
            <field>
              <name>SPI01_CLK_EN</name>
              <description>Set 1 to enable SPI01 clock</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>UART_CLK_EN</name>
              <description>Set 1 to enable UART clock</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>UART1_CLK_EN</name>
              <description>Set 1 to enable UART1 clock</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SPI2_CLK_EN</name>
              <description>Set 1 to enable SPI2 clock</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>I2C_EXT0_CLK_EN</name>
              <description>Set 1 to enable I2C_EXT0 clock</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LEDC_CLK_EN</name>
              <description>Set 1 to enable LEDC clock</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TIMERGROUP_CLK_EN</name>
              <description>Set 1 to enable TIMERGROUP clock</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>UART_MEM_CLK_EN</name>
              <description>Set 1 to enable UART_MEM clock</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>APB_SARADC_CLK_EN</name>
              <description>Set 1 to enable APB_SARADC clock</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SYSTIMER_CLK_EN</name>
              <description>Set 1 to enable SYSTEMTIMER clock</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADC2_ARB_CLK_EN</name>
              <description>Set 1 to enable ADC2_ARB clock</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PERIP_CLK_EN1</name>
          <description>peripheral clock gating register</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CRYPTO_ECC_CLK_EN</name>
              <description>Set 1 to enable ECC clock</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CRYPTO_SHA_CLK_EN</name>
              <description>Set 1 to enable SHA clock</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_CLK_EN</name>
              <description>Set 1 to enable DMA clock</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TSENS_CLK_EN</name>
              <description>Set 1 to enable TSENS clock</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PERIP_RST_EN0</name>
          <description>reserved</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SPI01_RST</name>
              <description>Set 1 to let SPI01 reset</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>UART_RST</name>
              <description>Set 1 to let UART reset</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>UART1_RST</name>
              <description>Set 1 to let UART1 reset</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SPI2_RST</name>
              <description>Set 1 to let SPI2 reset</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>I2C_EXT0_RST</name>
              <description>Set 1 to let I2C_EXT0 reset</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LEDC_RST</name>
              <description>Set 1 to let LEDC reset</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TIMERGROUP_RST</name>
              <description>Set 1 to let TIMERGROUP reset</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>UART_MEM_RST</name>
              <description>Set 1 to let UART_MEM reset</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>APB_SARADC_RST</name>
              <description>Set 1 to let APB_SARADC reset</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SYSTIMER_RST</name>
              <description>Set 1 to let SYSTIMER reset</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADC2_ARB_RST</name>
              <description>Set 1 to let ADC2_ARB reset</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PERIP_RST_EN1</name>
          <description>peripheral reset register</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000046</resetValue>
          <fields>
            <field>
              <name>CRYPTO_ECC_RST</name>
              <description>Set 1 to let CRYPTO_ECC reset</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CRYPTO_SHA_RST</name>
              <description>Set 1 to let CRYPTO_SHA reset</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_RST</name>
              <description>Set 1 to let DMA reset</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TSENS_RST</name>
              <description>Set 1 to let TSENS reset</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>BT_LPCK_DIV_INT</name>
          <description>clock config register</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <resetValue>0x000000FF</resetValue>
          <fields>
            <field>
              <name>BT_LPCK_DIV_NUM</name>
              <description>This field is lower power clock frequent division factor</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>BT_LPCK_DIV_FRAC</name>
          <description>low power clock configuration register</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <resetValue>0x02001001</resetValue>
          <fields>
            <field>
              <name>BT_LPCK_DIV_B</name>
              <description>This field is lower power clock frequent division factor b</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BT_LPCK_DIV_A</name>
              <description>This field is lower power clock frequent division factor a</description>
              <bitOffset>12</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LPCLK_SEL_RTC_SLOW</name>
              <description>Set 1 to select rtc-slow clock as rtc low power clock</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LPCLK_SEL_8M</name>
              <description>Set 1 to select 8m clock as rtc low power clock</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LPCLK_SEL_XTAL</name>
              <description>Set 1 to select xtal clock as rtc low power clock</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LPCLK_SEL_XTAL32K</name>
              <description>Set 1 to select xtal32k clock as low power clock</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LPCLK_RTC_EN</name>
              <description>Set 1 to enable RTC low power clock</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INTR_FROM_CPU_0</name>
          <description>interrupt generate register</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_INTR_FROM_CPU_0</name>
              <description>Set 1 to generate cpu interrupt 0</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INTR_FROM_CPU_1</name>
          <description>interrupt generate register</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_INTR_FROM_CPU_1</name>
              <description>Set 1 to generate cpu interrupt 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INTR_FROM_CPU_2</name>
          <description>interrupt generate register</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_INTR_FROM_CPU_2</name>
              <description>Set 1 to generate cpu interrupt 2</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CPU_INTR_FROM_CPU_3</name>
          <description>interrupt generate register</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>CPU_INTR_FROM_CPU_3</name>
              <description>Set 1 to generate cpu interrupt 3</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RSA_PD_CTRL</name>
          <description>rsa memory power control register</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>RSA_MEM_PD</name>
              <description>Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA. This bit is invalid.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RSA_MEM_FORCE_PU</name>
              <description>Set 1 to force power up RSA memory. This bit has the second highest priority.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RSA_MEM_FORCE_PD</name>
              <description>Set 1 to force power down RSA memory. This bit has the highest priority.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>EDMA_CTRL</name>
          <description>edma clcok and reset register</description>
          <addressOffset>0x3C</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>EDMA_CLK_ON</name>
              <description>Set 1 to enable EDMA clock.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EDMA_RESET</name>
              <description>Set 1 to let EDMA reset</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CACHE_CONTROL</name>
          <description>cache control register</description>
          <addressOffset>0x40</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000005</resetValue>
          <fields>
            <field>
              <name>ICACHE_CLK_ON</name>
              <description>Set 1 to enable icache clock</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ICACHE_RESET</name>
              <description>Set 1 to let icache reset</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DCACHE_CLK_ON</name>
              <description>Set 1 to enable dcache clock</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DCACHE_RESET</name>
              <description>Set 1 to let dcache reset</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL</name>
          <description>SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG</description>
          <addressOffset>0x44</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ENABLE_SPI_MANUAL_ENCRYPT</name>
              <description>Set 1 to enable the SPI manual encrypt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ENABLE_DOWNLOAD_DB_ENCRYPT</name>
              <description>Set 1 to enable download DB encrypt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ENABLE_DOWNLOAD_G0CB_DECRYPT</name>
              <description>Set 1 to enable download G0CB decrypt</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ENABLE_DOWNLOAD_MANUAL_ENCRYPT</name>
              <description>Set 1 to enable download manual encrypt</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RTC_FASTMEM_CONFIG</name>
          <description>fast memory config register</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <resetValue>0x7FF00000</resetValue>
          <fields>
            <field>
              <name>RTC_MEM_CRC_START</name>
              <description>Set 1 to start the CRC of RTC memory</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RTC_MEM_CRC_ADDR</name>
              <description>This field is used to set address of RTC memory for CRC.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>11</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RTC_MEM_CRC_LEN</name>
              <description>This field is used to set length of RTC memory for CRC based on start address.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>11</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RTC_MEM_CRC_FINISH</name>
              <description>This bit stores the status of RTC memory CRC.1 means finished.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RTC_FASTMEM_CRC</name>
          <description>reserved</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RTC_MEM_CRC_RES</name>
              <description>This field stores the CRC result of RTC memory.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>REDUNDANT_ECO_CTRL</name>
          <description>eco register</description>
          <addressOffset>0x50</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>REDUNDANT_ECO_DRIVE</name>
              <description>reg_redundant_eco_drive</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>REDUNDANT_ECO_RESULT</name>
              <description>reg_redundant_eco_result</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLOCK_GATE</name>
          <description>clock gating register</description>
          <addressOffset>0x54</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>CLK_EN</name>
              <description>reg_clk_en</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SYSCLK_CONF</name>
          <description>system clock config register</description>
          <addressOffset>0x58</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000001</resetValue>
          <fields>
            <field>
              <name>PRE_DIV_CNT</name>
              <description>This field is used to set the count of prescaler of XTAL_CLK.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SOC_CLK_SEL</name>
              <description>This field is used to select soc clock.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_XTAL_FREQ</name>
              <description>This field is used to read xtal frequency in MHz.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CLK_DIV_EN</name>
              <description>reg_clk_div_en</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MEM_PVT</name>
          <description>mem pvt register</description>
          <addressOffset>0x5C</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000003</resetValue>
          <fields>
            <field>
              <name>MEM_PATH_LEN</name>
              <description>reg_mem_path_len</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MEM_ERR_CNT_CLR</name>
              <description>reg_mem_err_cnt_clr</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MONITOR_EN</name>
              <description>reg_mem_pvt_monitor_en</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MEM_TIMING_ERR_CNT</name>
              <description>reg_mem_timing_err_cnt</description>
              <bitOffset>6</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MEM_VT_SEL</name>
              <description>reg_mem_vt_sel</description>
              <bitOffset>22</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COMB_PVT_LVT_CONF</name>
          <description>mem pvt register</description>
          <addressOffset>0x60</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000003</resetValue>
          <fields>
            <field>
              <name>COMB_PATH_LEN_LVT</name>
              <description>reg_comb_path_len_lvt</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>COMB_ERR_CNT_CLR_LVT</name>
              <description>reg_comb_err_cnt_clr_lvt</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>COMB_PVT_MONITOR_EN_LVT</name>
              <description>reg_comb_pvt_monitor_en_lvt</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COMB_PVT_NVT_CONF</name>
          <description>mem pvt register</description>
          <addressOffset>0x64</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000003</resetValue>
          <fields>
            <field>
              <name>COMB_PATH_LEN_NVT</name>
              <description>reg_comb_path_len_nvt</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>COMB_ERR_CNT_CLR_NVT</name>
              <description>reg_comb_err_cnt_clr_nvt</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>COMB_PVT_MONITOR_EN_NVT</name>
              <description>reg_comb_pvt_monitor_en_nvt</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COMB_PVT_HVT_CONF</name>
          <description>mem pvt register</description>
          <addressOffset>0x68</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000003</resetValue>
          <fields>
            <field>
              <name>COMB_PATH_LEN_HVT</name>
              <description>reg_comb_path_len_hvt</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>COMB_ERR_CNT_CLR_HVT</name>
              <description>reg_comb_err_cnt_clr_hvt</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>COMB_PVT_MONITOR_EN_HVT</name>
              <description>reg_comb_pvt_monitor_en_hvt</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COMB_PVT_ERR_LVT_SITE0</name>
          <description>mem pvt register</description>
          <addressOffset>0x6C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>COMB_TIMING_ERR_CNT_LVT_SITE0</name>
              <description>reg_comb_timing_err_cnt_lvt_site0</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COMB_PVT_ERR_NVT_SITE0</name>
          <description>mem pvt register</description>
          <addressOffset>0x70</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>COMB_TIMING_ERR_CNT_NVT_SITE0</name>
              <description>reg_comb_timing_err_cnt_nvt_site0</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COMB_PVT_ERR_HVT_SITE0</name>
          <description>mem pvt register</description>
          <addressOffset>0x74</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>COMB_TIMING_ERR_CNT_HVT_SITE0</name>
              <description>reg_comb_timing_err_cnt_hvt_site0</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COMB_PVT_ERR_LVT_SITE1</name>
          <description>mem pvt register</description>
          <addressOffset>0x78</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>COMB_TIMING_ERR_CNT_LVT_SITE1</name>
              <description>reg_comb_timing_err_cnt_lvt_site1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COMB_PVT_ERR_NVT_SITE1</name>
          <description>mem pvt register</description>
          <addressOffset>0x7C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>COMB_TIMING_ERR_CNT_NVT_SITE1</name>
              <description>reg_comb_timing_err_cnt_nvt_site1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COMB_PVT_ERR_HVT_SITE1</name>
          <description>mem pvt register</description>
          <addressOffset>0x80</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>COMB_TIMING_ERR_CNT_HVT_SITE1</name>
              <description>reg_comb_timing_err_cnt_hvt_site1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COMB_PVT_ERR_LVT_SITE2</name>
          <description>mem pvt register</description>
          <addressOffset>0x84</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>COMB_TIMING_ERR_CNT_LVT_SITE2</name>
              <description>reg_comb_timing_err_cnt_lvt_site2</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COMB_PVT_ERR_NVT_SITE2</name>
          <description>mem pvt register</description>
          <addressOffset>0x88</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>COMB_TIMING_ERR_CNT_NVT_SITE2</name>
              <description>reg_comb_timing_err_cnt_nvt_site2</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COMB_PVT_ERR_HVT_SITE2</name>
          <description>mem pvt register</description>
          <addressOffset>0x8C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>COMB_TIMING_ERR_CNT_HVT_SITE2</name>
              <description>reg_comb_timing_err_cnt_hvt_site2</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COMB_PVT_ERR_LVT_SITE3</name>
          <description>mem pvt register</description>
          <addressOffset>0x90</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>COMB_TIMING_ERR_CNT_LVT_SITE3</name>
              <description>reg_comb_timing_err_cnt_lvt_site3</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COMB_PVT_ERR_NVT_SITE3</name>
          <description>mem pvt register</description>
          <addressOffset>0x94</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>COMB_TIMING_ERR_CNT_NVT_SITE3</name>
              <description>reg_comb_timing_err_cnt_nvt_site3</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COMB_PVT_ERR_HVT_SITE3</name>
          <description>mem pvt register</description>
          <addressOffset>0x98</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>COMB_TIMING_ERR_CNT_HVT_SITE3</name>
              <description>reg_comb_timing_err_cnt_hvt_site3</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>REG_DATE</name>
          <description>Version register</description>
          <addressOffset>0xFFC</addressOffset>
          <size>0x20</size>
          <resetValue>0x02108190</resetValue>
          <fields>
            <field>
              <name>SYSTEM_REG_DATE</name>
              <description>reg_system_reg_date</description>
              <bitOffset>0</bitOffset>
              <bitWidth>28</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>SYSTIMER</name>
      <description>System Timer</description>
      <groupName>SYSTIMER</groupName>
      <baseAddress>0x60023000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x78</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>SYSTIMER_TARGET0</name>
        <value>26</value>
      </interrupt>
      <interrupt>
        <name>SYSTIMER_TARGET1</name>
        <value>27</value>
      </interrupt>
      <interrupt>
        <name>SYSTIMER_TARGET2</name>
        <value>28</value>
      </interrupt>
      <registers>
        <register>
          <name>CONF</name>
          <description>Configure system timer clock</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <resetValue>0x46000000</resetValue>
          <fields>
            <field>
              <name>SYSTIMER_CLK_FO</name>
              <description>systimer clock force on</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TARGET2_WORK_EN</name>
              <description>target2 work enable</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TARGET1_WORK_EN</name>
              <description>target1 work enable</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TARGET0_WORK_EN</name>
              <description>target0 work enable</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TIMER_UNIT1_CORE1_STALL_EN</name>
              <description>If timer unit1 is stalled when core1 stalled</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TIMER_UNIT1_CORE0_STALL_EN</name>
              <description>If timer unit1 is stalled when core0 stalled</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TIMER_UNIT0_CORE1_STALL_EN</name>
              <description>If timer unit0 is stalled when core1 stalled</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TIMER_UNIT0_CORE0_STALL_EN</name>
              <description>If timer unit0 is stalled when core0 stalled</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TIMER_UNIT1_WORK_EN</name>
              <description>timer unit1 work enable</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TIMER_UNIT0_WORK_EN</name>
              <description>timer unit0 work enable</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_EN</name>
              <description>register file clk gating</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>UNIT0_OP</name>
          <description>system timer unit0 value update register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_UNIT0_VALUE_VALID</name>
              <description>timer value is sync and valid</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TIMER_UNIT0_UPDATE</name>
              <description>update timer_unit0</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>UNIT1_OP</name>
          <description>system timer unit1 value update register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_UNIT1_VALUE_VALID</name>
              <description>timer value is sync and valid</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TIMER_UNIT1_UPDATE</name>
              <description>update timer unit1</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>UNIT0_LOAD_HI</name>
          <description>system timer unit0 value high load register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_UNIT0_LOAD_HI</name>
              <description>timer unit0 load high 20 bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>20</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>UNIT0_LOAD_LO</name>
          <description>system timer unit0 value low load register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_UNIT0_LOAD_LO</name>
              <description>timer unit0 load low 32 bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>UNIT1_LOAD_HI</name>
          <description>system timer unit1 value high load register</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_UNIT1_LOAD_HI</name>
              <description>timer unit1 load high 20 bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>20</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>UNIT1_LOAD_LO</name>
          <description>system timer unit1 value low load register</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_UNIT1_LOAD_LO</name>
              <description>timer unit1 load low 32 bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TARGET0_HI</name>
          <description>system timer comp0 value high register</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_TARGET0_HI</name>
              <description>timer taget0 high 20 bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>20</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TARGET0_LO</name>
          <description>system timer comp0 value low register</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_TARGET0_LO</name>
              <description>timer taget0 low 32 bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TARGET1_HI</name>
          <description>system timer comp1 value high register</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_TARGET1_HI</name>
              <description>timer taget1 high 20 bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>20</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TARGET1_LO</name>
          <description>system timer comp1 value low register</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_TARGET1_LO</name>
              <description>timer taget1 low 32 bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TARGET2_HI</name>
          <description>system timer comp2 value high register</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_TARGET2_HI</name>
              <description>timer taget2 high 20 bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>20</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TARGET2_LO</name>
          <description>system timer comp2 value low register</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_TARGET2_LO</name>
              <description>timer taget2 low 32 bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TARGET0_CONF</name>
          <description>system timer comp0 target mode register</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TARGET0_PERIOD</name>
              <description>target0 period</description>
              <bitOffset>0</bitOffset>
              <bitWidth>26</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TARGET0_PERIOD_MODE</name>
              <description>Set target0 to period mode</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TARGET0_TIMER_UNIT_SEL</name>
              <description>select which unit to compare</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TARGET1_CONF</name>
          <description>system timer comp1 target mode register</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TARGET1_PERIOD</name>
              <description>target1 period</description>
              <bitOffset>0</bitOffset>
              <bitWidth>26</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TARGET1_PERIOD_MODE</name>
              <description>Set target1 to period mode</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TARGET1_TIMER_UNIT_SEL</name>
              <description>select which unit to compare</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TARGET2_CONF</name>
          <description>system timer comp2 target mode register</description>
          <addressOffset>0x3C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TARGET2_PERIOD</name>
              <description>target2 period</description>
              <bitOffset>0</bitOffset>
              <bitWidth>26</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TARGET2_PERIOD_MODE</name>
              <description>Set target2 to period mode</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TARGET2_TIMER_UNIT_SEL</name>
              <description>select which unit to compare</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>UNIT0_VALUE_HI</name>
          <description>system timer unit0 value high register</description>
          <addressOffset>0x40</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_UNIT0_VALUE_HI</name>
              <description>timer read value high 20bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>20</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>UNIT0_VALUE_LO</name>
          <description>system timer unit0 value low register</description>
          <addressOffset>0x44</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_UNIT0_VALUE_LO</name>
              <description>timer read value low 32bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>UNIT1_VALUE_HI</name>
          <description>system timer unit1 value high register</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_UNIT1_VALUE_HI</name>
              <description>timer read value high 20bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>20</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>UNIT1_VALUE_LO</name>
          <description>system timer unit1 value low register</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_UNIT1_VALUE_LO</name>
              <description>timer read value low 32bits</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COMP0_LOAD</name>
          <description>system timer comp0 conf sync register</description>
          <addressOffset>0x50</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_COMP0_LOAD</name>
              <description>timer comp0 sync enable signal</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COMP1_LOAD</name>
          <description>system timer comp1 conf sync register</description>
          <addressOffset>0x54</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_COMP1_LOAD</name>
              <description>timer comp1 sync enable signal</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COMP2_LOAD</name>
          <description>system timer comp2 conf sync register</description>
          <addressOffset>0x58</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_COMP2_LOAD</name>
              <description>timer comp2 sync enable signal</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>UNIT0_LOAD</name>
          <description>system timer unit0 conf sync register</description>
          <addressOffset>0x5C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_UNIT0_LOAD</name>
              <description>timer unit0 sync enable signal</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>UNIT1_LOAD</name>
          <description>system timer unit1 conf sync register</description>
          <addressOffset>0x60</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TIMER_UNIT1_LOAD</name>
              <description>timer unit1 sync enable signal</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_ENA</name>
          <description>systimer interrupt enable register</description>
          <addressOffset>0x64</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TARGET0_INT_ENA</name>
              <description>interupt0 enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TARGET1_INT_ENA</name>
              <description>interupt1 enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TARGET2_INT_ENA</name>
              <description>interupt2 enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_RAW</name>
          <description>systimer interrupt raw register</description>
          <addressOffset>0x68</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TARGET0_INT_RAW</name>
              <description>interupt0 raw</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TARGET1_INT_RAW</name>
              <description>interupt1 raw</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TARGET2_INT_RAW</name>
              <description>interupt2 raw</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_CLR</name>
          <description>systimer interrupt clear register</description>
          <addressOffset>0x6C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TARGET0_INT_CLR</name>
              <description>interupt0 clear</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>TARGET1_INT_CLR</name>
              <description>interupt1 clear</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>TARGET2_INT_CLR</name>
              <description>interupt2 clear</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_ST</name>
          <description>systimer interrupt status register</description>
          <addressOffset>0x70</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TARGET0_INT_ST</name>
              <description>interupt0 status</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TARGET1_INT_ST</name>
              <description>interupt1 status</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TARGET2_INT_ST</name>
              <description>interupt2 status</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DATE</name>
          <description>system timer version control register</description>
          <addressOffset>0xFC</addressOffset>
          <size>0x20</size>
          <resetValue>0x02012251</resetValue>
          <fields>
            <field>
              <name>DATE</name>
              <description>systimer register version</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>TIMG0</name>
      <description>Timer Group</description>
      <groupName>TIMG</groupName>
      <baseAddress>0x6001F000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x68</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>TG0_T0_LEVEL</name>
        <value>23</value>
      </interrupt>
      <interrupt>
        <name>TG0_WDT_LEVEL</name>
        <value>24</value>
      </interrupt>
      <registers>
        <register>
          <name>T0CONFIG</name>
          <description>Timer %s configuration register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <resetValue>0x60002000</resetValue>
          <fields>
            <field>
              <name>USE_XTAL</name>
              <description>1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ALARM_EN</name>
              <description>When set, the alarm is enabled. This bit is automatically cleared once an
alarm occurs.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DIVCNT_RST</name>
              <description>When set, Timer %s 's clock divider counter will be reset.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>DIVIDER</name>
              <description>Timer %s clock (T%s_clk) prescaler value.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>AUTORELOAD</name>
              <description>When set, timer %s auto-reload at alarm is enabled.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INCREASE</name>
              <description>When set, the timer %s time-base counter will increment every clock tick. When
cleared, the timer %s time-base counter will decrement.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EN</name>
              <description>When set, the timer %s time-base counter is enabled.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>T0LO</name>
          <description>Timer %s current value, low 32 bits</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>LO</name>
              <description>After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter
of timer %s can be read here.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>T0HI</name>
          <description>Timer $x current value, high 22 bits</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>T0_HI</name>
              <description>After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter
of timer 0 can be read here.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>22</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>T0UPDATE</name>
          <description>Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>T0_UPDATE</name>
              <description>After writing 0 or 1 to TIMG_T31UPDATE_REG, the counter value is latched.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>T0ALARMLO</name>
          <description>Timer $x alarm value, low 32 bits</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ALARM_LO</name>
              <description>Timer 0 alarm trigger time-base counter value, low 32 bits.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>T0ALARMHI</name>
          <description>Timer $x alarm value, high bits</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ALARM_HI</name>
              <description>Timer 0 alarm trigger time-base counter value, high 22 bits.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>22</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>T0LOADLO</name>
          <description>Timer $x reload value, low 32 bits</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>LOAD_LO</name>
              <description>Low 32 bits of the value that a reload will load onto timer 0 time-base
Counter.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>T0LOADHI</name>
          <description>Timer $x reload value, high 22 bits</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>LOAD_HI</name>
              <description>High 22 bits of the value that a reload will load onto timer 0 time-base
counter.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>22</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>T0LOAD</name>
          <description>Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>LOAD</name>
              <description>
Write any value to trigger a timer 0 time-base counter reload.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WDTCONFIG0</name>
          <description>Watchdog timer configuration register</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <resetValue>0x0004C000</resetValue>
          <fields>
            <field>
              <name>WDT_APPCPU_RESET_EN</name>
              <description>WDT reset CPU enable.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_PROCPU_RESET_EN</name>
              <description>WDT reset CPU enable.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_FLASHBOOT_MOD_EN</name>
              <description>When set, Flash boot protection is enabled.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_SYS_RESET_LENGTH</name>
              <description>System reset signal length selection. 0: 100 ns, 1: 200 ns,
2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_CPU_RESET_LENGTH</name>
              <description>CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_USE_XTAL</name>
              <description>choose WDT clock:0-apb_clk; 1-xtal_clk.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_CONF_UPDATE_EN</name>
              <description>update the WDT configuration registers</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>WDT_STG3</name>
              <description>Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
</description>
              <bitOffset>23</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_STG2</name>
              <description>Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
</description>
              <bitOffset>25</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_STG1</name>
              <description>Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
</description>
              <bitOffset>27</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_STG0</name>
              <description>Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
</description>
              <bitOffset>29</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_EN</name>
              <description>When set, MWDT is enabled.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WDTCONFIG1</name>
          <description>Watchdog timer prescaler register</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <resetValue>0x00010000</resetValue>
          <fields>
            <field>
              <name>WDT_DIVCNT_RST</name>
              <description>When set, WDT 's clock divider counter will be reset.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>WDT_CLK_PRESCALE</name>
              <description>MWDT clock prescaler value. MWDT clock period = 12.5 ns *
TIMG_WDT_CLK_PRESCALE.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WDTCONFIG2</name>
          <description>Watchdog timer stage 0 timeout value</description>
          <addressOffset>0x50</addressOffset>
          <size>0x20</size>
          <resetValue>0x018CBA80</resetValue>
          <fields>
            <field>
              <name>WDT_STG0_HOLD</name>
              <description>Stage 0 timeout value, in MWDT clock cycles.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WDTCONFIG3</name>
          <description>Watchdog timer stage 1 timeout value</description>
          <addressOffset>0x54</addressOffset>
          <size>0x20</size>
          <resetValue>0x07FFFFFF</resetValue>
          <fields>
            <field>
              <name>WDT_STG1_HOLD</name>
              <description>Stage 1 timeout value, in MWDT clock cycles.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WDTCONFIG4</name>
          <description>Watchdog timer stage 2 timeout value</description>
          <addressOffset>0x58</addressOffset>
          <size>0x20</size>
          <resetValue>0x000FFFFF</resetValue>
          <fields>
            <field>
              <name>WDT_STG2_HOLD</name>
              <description>Stage 2 timeout value, in MWDT clock cycles.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WDTCONFIG5</name>
          <description>Watchdog timer stage 3 timeout value</description>
          <addressOffset>0x5C</addressOffset>
          <size>0x20</size>
          <resetValue>0x000FFFFF</resetValue>
          <fields>
            <field>
              <name>WDT_STG3_HOLD</name>
              <description>Stage 3 timeout value, in MWDT clock cycles.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WDTFEED</name>
          <description>Write to feed the watchdog timer</description>
          <addressOffset>0x60</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>WDT_FEED</name>
              <description>Write any value to feed the MWDT. (WO)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WDTWPROTECT</name>
          <description>Watchdog write protect register</description>
          <addressOffset>0x64</addressOffset>
          <size>0x20</size>
          <resetValue>0x50D83AA1</resetValue>
          <fields>
            <field>
              <name>WDT_WKEY</name>
              <description>If the register contains a different value than its reset value, write
protection is enabled.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RTCCALICFG</name>
          <description>RTC calibration configure register</description>
          <addressOffset>0x68</addressOffset>
          <size>0x20</size>
          <resetValue>0x00013000</resetValue>
          <fields>
            <field>
              <name>RTC_CALI_START_CYCLING</name>
              <description>Reserved</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RTC_CALI_CLK_SEL</name>
              <description>0:rtc slow clock. 1:clk_8m, 2:xtal_32k.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RTC_CALI_RDY</name>
              <description>Reserved</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RTC_CALI_MAX</name>
              <description>Reserved</description>
              <bitOffset>16</bitOffset>
              <bitWidth>15</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RTC_CALI_START</name>
              <description>Reserved</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RTCCALICFG1</name>
          <description>RTC calibration configure1 register</description>
          <addressOffset>0x6C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RTC_CALI_CYCLING_DATA_VLD</name>
              <description>Reserved</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RTC_CALI_VALUE</name>
              <description>Reserved</description>
              <bitOffset>7</bitOffset>
              <bitWidth>25</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_ENA_TIMERS</name>
          <description>Interrupt enable bits</description>
          <addressOffset>0x70</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>T0_INT_ENA</name>
              <description>The interrupt enable bit for the TIMG_T0_INT interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WDT_INT_ENA</name>
              <description>The interrupt enable bit for the TIMG_WDT_INT interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_RAW_TIMERS</name>
          <description>Raw interrupt status</description>
          <addressOffset>0x74</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>T0_INT_RAW</name>
              <description>The raw interrupt status bit for the TIMG_T0_INT interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>WDT_INT_RAW</name>
              <description>The raw interrupt status bit for the TIMG_WDT_INT interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_ST_TIMERS</name>
          <description>Masked interrupt status</description>
          <addressOffset>0x78</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>T0_INT_ST</name>
              <description>The masked interrupt status bit for the TIMG_T0_INT interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>WDT_INT_ST</name>
              <description>The masked interrupt status bit for the TIMG_WDT_INT interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_CLR_TIMERS</name>
          <description>Interrupt clear bits</description>
          <addressOffset>0x7C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>T0_INT_CLR</name>
              <description>Set this bit to clear the TIMG_T0_INT interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>WDT_INT_CLR</name>
              <description>Set this bit to clear the TIMG_WDT_INT interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RTCCALICFG2</name>
          <description>Timer group calibration register</description>
          <addressOffset>0x80</addressOffset>
          <size>0x20</size>
          <resetValue>0xFFFFFF98</resetValue>
          <fields>
            <field>
              <name>RTC_CALI_TIMEOUT</name>
              <description>RTC calibration timeout indicator</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RTC_CALI_TIMEOUT_RST_CNT</name>
              <description>Cycles that release calibration timeout reset</description>
              <bitOffset>3</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RTC_CALI_TIMEOUT_THRES</name>
              <description>Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>25</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>NTIMERS_DATE</name>
          <description>Timer version control register</description>
          <addressOffset>0xF8</addressOffset>
          <size>0x20</size>
          <resetValue>0x02006191</resetValue>
          <fields>
            <field>
              <name>NTIMGS_DATE</name>
              <description>Timer version control register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>28</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>REGCLK</name>
          <description>Timer group clock gate register</description>
          <addressOffset>0xFC</addressOffset>
          <size>0x20</size>
          <resetValue>0x60000000</resetValue>
          <fields>
            <field>
              <name>WDT_CLK_IS_ACTIVE</name>
              <description>enable WDT's clock</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TIMER_CLK_IS_ACTIVE</name>
              <description>enable Timer 30's clock</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_EN</name>
              <description>Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>UART0</name>
      <description>UART (Universal Asynchronous Receiver-Transmitter) Controller</description>
      <groupName>UART</groupName>
      <baseAddress>0x60000000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x84</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>UART0</name>
        <value>17</value>
      </interrupt>
      <registers>
        <register>
          <name>FIFO</name>
          <description>FIFO data register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RXFIFO_RD_BYTE</name>
              <description>UART 0 accesses FIFO via this register.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_RAW</name>
          <description>Raw interrupt status</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000002</resetValue>
          <fields>
            <field>
              <name>RXFIFO_FULL_INT_RAW</name>
              <description>This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXFIFO_EMPTY_INT_RAW</name>
              <description>This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PARITY_ERR_INT_RAW</name>
              <description>This interrupt raw bit turns to high level when receiver detects a parity error in the data.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FRM_ERR_INT_RAW</name>
              <description>This interrupt raw bit turns to high level when receiver detects a data frame error .</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXFIFO_OVF_INT_RAW</name>
              <description>This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DSR_CHG_INT_RAW</name>
              <description>This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CTS_CHG_INT_RAW</name>
              <description>This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BRK_DET_INT_RAW</name>
              <description>This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXFIFO_TOUT_INT_RAW</name>
              <description>This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SW_XON_INT_RAW</name>
              <description>This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SW_XOFF_INT_RAW</name>
              <description>This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>GLITCH_DET_INT_RAW</name>
              <description>This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TX_BRK_DONE_INT_RAW</name>
              <description>This interrupt raw bit turns to high level when transmitter completes  sending  NULL characters, after all data in Tx-FIFO are sent.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TX_BRK_IDLE_DONE_INT_RAW</name>
              <description>This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the  last data.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TX_DONE_INT_RAW</name>
              <description>This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RS485_PARITY_ERR_INT_RAW</name>
              <description>This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RS485_FRM_ERR_INT_RAW</name>
              <description>This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RS485_CLASH_INT_RAW</name>
              <description>This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>AT_CMD_CHAR_DET_INT_RAW</name>
              <description>This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>WAKEUP_INT_RAW</name>
              <description>This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_ST</name>
          <description>Masked interrupt status</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RXFIFO_FULL_INT_ST</name>
              <description>This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXFIFO_EMPTY_INT_ST</name>
              <description>This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PARITY_ERR_INT_ST</name>
              <description>This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FRM_ERR_INT_ST</name>
              <description>This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXFIFO_OVF_INT_ST</name>
              <description>This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DSR_CHG_INT_ST</name>
              <description>This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CTS_CHG_INT_ST</name>
              <description>This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BRK_DET_INT_ST</name>
              <description>This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXFIFO_TOUT_INT_ST</name>
              <description>This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SW_XON_INT_ST</name>
              <description>This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SW_XOFF_INT_ST</name>
              <description>This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>GLITCH_DET_INT_ST</name>
              <description>This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TX_BRK_DONE_INT_ST</name>
              <description>This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TX_BRK_IDLE_DONE_INT_ST</name>
              <description>This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TX_DONE_INT_ST</name>
              <description>This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RS485_PARITY_ERR_INT_ST</name>
              <description>This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RS485_FRM_ERR_INT_ST</name>
              <description>This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RS485_CLASH_INT_ST</name>
              <description>This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>AT_CMD_CHAR_DET_INT_ST</name>
              <description>This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>WAKEUP_INT_ST</name>
              <description>This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_ENA</name>
          <description>Interrupt enable bits</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RXFIFO_FULL_INT_ENA</name>
              <description>This is the enable bit for rxfifo_full_int_st register.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TXFIFO_EMPTY_INT_ENA</name>
              <description>This is the enable bit for txfifo_empty_int_st register.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PARITY_ERR_INT_ENA</name>
              <description>This is the enable bit for parity_err_int_st register.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FRM_ERR_INT_ENA</name>
              <description>This is the enable bit for frm_err_int_st register.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RXFIFO_OVF_INT_ENA</name>
              <description>This is the enable bit for rxfifo_ovf_int_st register.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DSR_CHG_INT_ENA</name>
              <description>This is the enable bit for dsr_chg_int_st register.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CTS_CHG_INT_ENA</name>
              <description>This is the enable bit for cts_chg_int_st register.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BRK_DET_INT_ENA</name>
              <description>This is the enable bit for brk_det_int_st register.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RXFIFO_TOUT_INT_ENA</name>
              <description>This is the enable bit for rxfifo_tout_int_st register.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SW_XON_INT_ENA</name>
              <description>This is the enable bit for sw_xon_int_st register.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SW_XOFF_INT_ENA</name>
              <description>This is the enable bit for sw_xoff_int_st register.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GLITCH_DET_INT_ENA</name>
              <description>This is the enable bit for glitch_det_int_st register.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_BRK_DONE_INT_ENA</name>
              <description>This is the enable bit for tx_brk_done_int_st register.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_BRK_IDLE_DONE_INT_ENA</name>
              <description>This is the enable bit for tx_brk_idle_done_int_st register.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_DONE_INT_ENA</name>
              <description>This is the enable bit for tx_done_int_st register.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RS485_PARITY_ERR_INT_ENA</name>
              <description>This is the enable bit for rs485_parity_err_int_st register.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RS485_FRM_ERR_INT_ENA</name>
              <description>This is the enable bit for rs485_parity_err_int_st register.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RS485_CLASH_INT_ENA</name>
              <description>This is the enable bit for rs485_clash_int_st register.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>AT_CMD_CHAR_DET_INT_ENA</name>
              <description>This is the enable bit for at_cmd_char_det_int_st register.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WAKEUP_INT_ENA</name>
              <description>This is the enable bit for uart_wakeup_int_st register.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_CLR</name>
          <description>Interrupt clear bits</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RXFIFO_FULL_INT_CLR</name>
              <description>Set this bit to clear the rxfifo_full_int_raw interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>TXFIFO_EMPTY_INT_CLR</name>
              <description>Set this bit to clear txfifo_empty_int_raw interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>PARITY_ERR_INT_CLR</name>
              <description>Set this bit to clear parity_err_int_raw interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>FRM_ERR_INT_CLR</name>
              <description>Set this bit to clear frm_err_int_raw interrupt.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>RXFIFO_OVF_INT_CLR</name>
              <description>Set this bit to clear rxfifo_ovf_int_raw interrupt.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>DSR_CHG_INT_CLR</name>
              <description>Set this bit to clear the dsr_chg_int_raw interrupt.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CTS_CHG_INT_CLR</name>
              <description>Set this bit to clear the cts_chg_int_raw interrupt.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>BRK_DET_INT_CLR</name>
              <description>Set this bit to clear the brk_det_int_raw interrupt.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>RXFIFO_TOUT_INT_CLR</name>
              <description>Set this bit to clear the rxfifo_tout_int_raw interrupt.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SW_XON_INT_CLR</name>
              <description>Set this bit to clear the sw_xon_int_raw interrupt.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SW_XOFF_INT_CLR</name>
              <description>Set this bit to clear the sw_xoff_int_raw interrupt.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>GLITCH_DET_INT_CLR</name>
              <description>Set this bit to clear the glitch_det_int_raw interrupt.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>TX_BRK_DONE_INT_CLR</name>
              <description>Set this bit to clear the tx_brk_done_int_raw interrupt..</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>TX_BRK_IDLE_DONE_INT_CLR</name>
              <description>Set this bit to clear the tx_brk_idle_done_int_raw interrupt.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>TX_DONE_INT_CLR</name>
              <description>Set this bit to clear the tx_done_int_raw interrupt.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>RS485_PARITY_ERR_INT_CLR</name>
              <description>Set this bit to clear the rs485_parity_err_int_raw interrupt.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>RS485_FRM_ERR_INT_CLR</name>
              <description>Set this bit to clear the rs485_frm_err_int_raw interrupt.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>RS485_CLASH_INT_CLR</name>
              <description>Set this bit to clear the rs485_clash_int_raw interrupt.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>AT_CMD_CHAR_DET_INT_CLR</name>
              <description>Set this bit to clear the at_cmd_char_det_int_raw interrupt.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>WAKEUP_INT_CLR</name>
              <description>Set this bit to clear the uart_wakeup_int_raw interrupt.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLKDIV</name>
          <description>Clock divider configuration</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <resetValue>0x000002B6</resetValue>
          <fields>
            <field>
              <name>CLKDIV</name>
              <description>The integral part of the frequency divider factor.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FRAG</name>
              <description>The decimal part of the frequency divider factor.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RX_FILT</name>
          <description>Rx Filter configuration</description>
          <addressOffset>0x18</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000008</resetValue>
          <fields>
            <field>
              <name>GLITCH_FILT</name>
              <description>when input pulse width is lower than this value, the pulse is ignored.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GLITCH_FILT_EN</name>
              <description>Set this bit to enable Rx signal filter.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STATUS</name>
          <description>UART status register</description>
          <addressOffset>0x1C</addressOffset>
          <size>0x20</size>
          <resetValue>0xE000C000</resetValue>
          <fields>
            <field>
              <name>RXFIFO_CNT</name>
              <description>Stores the byte number of valid data in Rx-FIFO.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DSRN</name>
              <description>The register represent the level value of the internal uart dsr signal.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CTSN</name>
              <description>This register represent the level value of the internal uart cts signal.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXD</name>
              <description>This register represent the  level value of the internal uart rxd signal.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXFIFO_CNT</name>
              <description>Stores the byte number of data in Tx-FIFO.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DTRN</name>
              <description>This bit represents the level of the internal uart dtr signal.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RTSN</name>
              <description>This bit represents the level of the internal uart rts signal.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXD</name>
              <description>This bit represents the  level of the internal uart txd signal.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CONF0</name>
          <description>a</description>
          <addressOffset>0x20</addressOffset>
          <size>0x20</size>
          <resetValue>0x1000001C</resetValue>
          <fields>
            <field>
              <name>PARITY</name>
              <description>This register is used to configure the parity check mode.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PARITY_EN</name>
              <description>Set this bit to enable uart parity check.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BIT_NUM</name>
              <description>This register is used to set the length of data.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>STOP_BIT_NUM</name>
              <description>This register is used to set the length of  stop bit.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SW_RTS</name>
              <description>This register is used to configure the software rts signal which is used in software flow control.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SW_DTR</name>
              <description>This register is used to configure the software dtr signal which is used in software flow control.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TXD_BRK</name>
              <description>Set this bit to enbale transmitter to  send NULL when the process of sending data is done.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IRDA_DPLX</name>
              <description>Set this bit to enable IrDA loopback mode.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IRDA_TX_EN</name>
              <description>This is the start enable bit for IrDA transmitter.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IRDA_WCTL</name>
              <description>1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IRDA_TX_INV</name>
              <description>Set this bit to invert the level of  IrDA transmitter.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IRDA_RX_INV</name>
              <description>Set this bit to invert the level of IrDA receiver.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LOOPBACK</name>
              <description>Set this bit to enable uart loopback test mode.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_FLOW_EN</name>
              <description>Set this bit to enable flow control function for transmitter.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IRDA_EN</name>
              <description>Set this bit to enable IrDA protocol.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RXFIFO_RST</name>
              <description>Set this bit to reset the uart receive-FIFO.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TXFIFO_RST</name>
              <description>Set this bit to reset the uart transmit-FIFO.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RXD_INV</name>
              <description>Set this bit to inverse the level value of uart rxd signal.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CTS_INV</name>
              <description>Set this bit to inverse the level value of uart cts signal.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DSR_INV</name>
              <description>Set this bit to inverse the level value of uart dsr signal.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TXD_INV</name>
              <description>Set this bit to inverse the level value of uart txd signal.</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RTS_INV</name>
              <description>Set this bit to inverse the level value of uart rts signal.</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DTR_INV</name>
              <description>Set this bit to inverse the level value of uart dtr signal.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_EN</name>
              <description>1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ERR_WR_MASK</name>
              <description>1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the  received data is wrong.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>AUTOBAUD_EN</name>
              <description>This is the enable bit for detecting baudrate.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MEM_CLK_EN</name>
              <description>UART memory clock gate enable signal.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CONF1</name>
          <description>Configuration register 1</description>
          <addressOffset>0x24</addressOffset>
          <size>0x20</size>
          <resetValue>0x0000C060</resetValue>
          <fields>
            <field>
              <name>RXFIFO_FULL_THRHD</name>
              <description>It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TXFIFO_EMPTY_THRHD</name>
              <description>It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>9</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DIS_RX_DAT_OVF</name>
              <description>Disable UART Rx data overflow detect.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_TOUT_FLOW_DIS</name>
              <description>Set this bit to stop accumulating idle_cnt when hardware flow control works.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_FLOW_EN</name>
              <description>This is the flow enable bit for UART receiver.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_TOUT_EN</name>
              <description>This is the enble bit for uart receiver's timeout function.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LOWPULSE</name>
          <description>Autobaud minimum low pulse duration register</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000FFF</resetValue>
          <fields>
            <field>
              <name>MIN_CNT</name>
              <description>This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>HIGHPULSE</name>
          <description>Autobaud minimum high pulse duration register</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000FFF</resetValue>
          <fields>
            <field>
              <name>MIN_CNT</name>
              <description>This register stores  the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RXD_CNT</name>
          <description>Autobaud edge change count register</description>
          <addressOffset>0x30</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RXD_EDGE_CNT</name>
              <description>This register stores the count of rxd edge change. It is used in baud rate-detect process.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FLOW_CONF</name>
          <description>Software flow-control configuration</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>SW_FLOW_CON_EN</name>
              <description>Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XONOFF_DEL</name>
              <description>Set this bit to remove flow control char from the received data.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FORCE_XON</name>
              <description>Set this bit to enable the transmitter to go on sending data.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FORCE_XOFF</name>
              <description>Set this bit to stop the  transmitter from sending data.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SEND_XON</name>
              <description>Set this bit to send Xon char. It is cleared by hardware automatically.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SEND_XOFF</name>
              <description>Set this bit to send Xoff char. It is cleared by hardware automatically.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLEEP_CONF</name>
          <description>Sleep-mode configuration</description>
          <addressOffset>0x38</addressOffset>
          <size>0x20</size>
          <resetValue>0x000000F0</resetValue>
          <fields>
            <field>
              <name>ACTIVE_THRESHOLD</name>
              <description>The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SWFC_CONF0</name>
          <description>Software flow-control character configuration</description>
          <addressOffset>0x3C</addressOffset>
          <size>0x20</size>
          <resetValue>0x000026E0</resetValue>
          <fields>
            <field>
              <name>XOFF_THRESHOLD</name>
              <description>When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XOFF_CHAR</name>
              <description>This register stores the Xoff flow control char.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SWFC_CONF1</name>
          <description>Software flow-control character configuration</description>
          <addressOffset>0x40</addressOffset>
          <size>0x20</size>
          <resetValue>0x00002200</resetValue>
          <fields>
            <field>
              <name>XON_THRESHOLD</name>
              <description>When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XON_CHAR</name>
              <description>This register stores the Xon flow control char.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TXBRK_CONF</name>
          <description>Tx Break character configuration</description>
          <addressOffset>0x44</addressOffset>
          <size>0x20</size>
          <resetValue>0x0000000A</resetValue>
          <fields>
            <field>
              <name>TX_BRK_NUM</name>
              <description>This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IDLE_CONF</name>
          <description>Frame-end idle configuration</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <resetValue>0x00040100</resetValue>
          <fields>
            <field>
              <name>RX_IDLE_THRHD</name>
              <description>It will produce frame end signal when receiver takes more time to receive one byte data than this register value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_IDLE_NUM</name>
              <description>This register is used to configure the duration time between transfers.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RS485_CONF</name>
          <description>RS485 mode configuration</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RS485_EN</name>
              <description>Set this bit to choose the rs485 mode.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DL0_EN</name>
              <description>Set this bit to delay the stop bit by 1 bit.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DL1_EN</name>
              <description>Set this bit to delay the stop bit by 1 bit.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RS485TX_RX_EN</name>
              <description>Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RS485RXBY_TX_EN</name>
              <description>1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RS485_RX_DLY_NUM</name>
              <description>This register is used to delay the receiver's internal data signal.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RS485_TX_DLY_NUM</name>
              <description>This register is used to delay the transmitter's internal data signal.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>AT_CMD_PRECNT</name>
          <description>Pre-sequence timing configuration</description>
          <addressOffset>0x50</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000901</resetValue>
          <fields>
            <field>
              <name>PRE_IDLE_NUM</name>
              <description>This register is used to configure the idle duration time before the first at_cmd is received by receiver.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>AT_CMD_POSTCNT</name>
          <description>Post-sequence timing configuration</description>
          <addressOffset>0x54</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000901</resetValue>
          <fields>
            <field>
              <name>POST_IDLE_NUM</name>
              <description>This register is used to configure the duration time between the last at_cmd and the next data.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>AT_CMD_GAPTOUT</name>
          <description>Timeout configuration</description>
          <addressOffset>0x58</addressOffset>
          <size>0x20</size>
          <resetValue>0x0000000B</resetValue>
          <fields>
            <field>
              <name>RX_GAP_TOUT</name>
              <description>This register is used to configure the duration time between the at_cmd chars.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>AT_CMD_CHAR</name>
          <description>AT escape sequence detection configuration</description>
          <addressOffset>0x5C</addressOffset>
          <size>0x20</size>
          <resetValue>0x0000032B</resetValue>
          <fields>
            <field>
              <name>AT_CMD_CHAR</name>
              <description>This register is used to configure the content of at_cmd char.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CHAR_NUM</name>
              <description>This register is used to configure the num of continuous at_cmd chars received by receiver.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MEM_CONF</name>
          <description>UART threshold and allocation configuration</description>
          <addressOffset>0x60</addressOffset>
          <size>0x20</size>
          <resetValue>0x000A0012</resetValue>
          <fields>
            <field>
              <name>RX_SIZE</name>
              <description>This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_SIZE</name>
              <description>This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_FLOW_THRHD</name>
              <description>This register is used to configure the maximum amount of data that can be received  when hardware flow control works.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>9</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_TOUT_THRHD</name>
              <description>This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MEM_FORCE_PD</name>
              <description>Set this bit to force power down UART memory.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MEM_FORCE_PU</name>
              <description>Set this bit to force power up UART memory.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MEM_TX_STATUS</name>
          <description>Tx-FIFO write and read offset address.</description>
          <addressOffset>0x64</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>APB_TX_WADDR</name>
              <description>This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TX_RADDR</name>
              <description>This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MEM_RX_STATUS</name>
          <description>Rx-FIFO write and read offset address.</description>
          <addressOffset>0x68</addressOffset>
          <size>0x20</size>
          <resetValue>0x00080100</resetValue>
          <fields>
            <field>
              <name>APB_RX_RADDR</name>
              <description>This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RX_WADDR</name>
              <description>This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FSM_STATUS</name>
          <description>UART transmit and receive status.</description>
          <addressOffset>0x6C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>ST_URX_OUT</name>
              <description>This is the status register of receiver.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ST_UTX_OUT</name>
              <description>This is the status register of transmitter.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>POSPULSE</name>
          <description>Autobaud high pulse register</description>
          <addressOffset>0x70</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000FFF</resetValue>
          <fields>
            <field>
              <name>POSEDGE_MIN_CNT</name>
              <description>This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>NEGPULSE</name>
          <description>Autobaud low pulse register</description>
          <addressOffset>0x74</addressOffset>
          <size>0x20</size>
          <resetValue>0x00000FFF</resetValue>
          <fields>
            <field>
              <name>NEGEDGE_MIN_CNT</name>
              <description>This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLK_CONF</name>
          <description>UART core clock configuration</description>
          <addressOffset>0x78</addressOffset>
          <size>0x20</size>
          <resetValue>0x03701000</resetValue>
          <fields>
            <field>
              <name>SCLK_DIV_B</name>
              <description>The  denominator of the frequency divider factor.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCLK_DIV_A</name>
              <description>The numerator of the frequency divider factor.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCLK_DIV_NUM</name>
              <description>The integral part of the frequency divider factor.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCLK_SEL</name>
              <description>UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCLK_EN</name>
              <description>Set this bit to enable UART Tx/Rx clock.</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RST_CORE</name>
              <description>Write 1 then write 0 to this bit, reset UART Tx/Rx.</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_SCLK_EN</name>
              <description>Set this bit to enable UART Tx clock.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_SCLK_EN</name>
              <description>Set this bit to enable UART Rx clock.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_RST_CORE</name>
              <description>Write 1 then write 0 to this bit, reset UART Tx.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_RST_CORE</name>
              <description>Write 1 then write 0 to this bit, reset UART Rx.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DATE</name>
          <description>UART Version register</description>
          <addressOffset>0x7C</addressOffset>
          <size>0x20</size>
          <resetValue>0x02008270</resetValue>
          <fields>
            <field>
              <name>DATE</name>
              <description>This is the version register.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ID</name>
          <description>UART ID register</description>
          <addressOffset>0x80</addressOffset>
          <size>0x20</size>
          <resetValue>0x40000500</resetValue>
          <fields>
            <field>
              <name>ID</name>
              <description>This register is used to configure the uart_id.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>30</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>HIGH_SPEED</name>
              <description>This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>REG_UPDATE</name>
              <description>Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral derivedFrom="UART0">
      <name>UART1</name>
      <description>UART (Universal Asynchronous Receiver-Transmitter) Controller</description>
      <baseAddress>0x60010000</baseAddress>
      <interrupt>
        <name>UART1</name>
        <value>18</value>
      </interrupt>
    </peripheral>
    <peripheral>
      <name>XTS_AES</name>
      <description>XTS-AES-128 Flash Encryption</description>
      <groupName>XTS_AES</groupName>
      <baseAddress>0x600CC000</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x30</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <dim>16</dim>
          <dimIncrement>0x1</dimIncrement>
          <name>PLAIN_MEM[%s]</name>
          <description>The memory that stores plaintext</description>
          <addressOffset>0x0</addressOffset>
          <size>0x8</size>
        </register>
        <register>
          <name>LINESIZE</name>
          <description>XTS-AES line-size register</description>
          <addressOffset>0x40</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>LINESIZE</name>
              <description>This bit stores the line size parameter. 0: 16Byte, 1: 32Byte.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DESTINATION</name>
          <description>XTS-AES destination register</description>
          <addressOffset>0x44</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DESTINATION</name>
              <description>This bit stores the destination. 0: flash(default). 1: reserved.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PHYSICAL_ADDRESS</name>
          <description>XTS-AES physical address register</description>
          <addressOffset>0x48</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>PHYSICAL_ADDRESS</name>
              <description>Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>30</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TRIGGER</name>
          <description>XTS-AES trigger register</description>
          <addressOffset>0x4C</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>TRIGGER</name>
              <description>Set this bit to start manual encryption calculation</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RELEASE</name>
          <description>XTS-AES release register</description>
          <addressOffset>0x50</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>RELEASE</name>
              <description>Set this bit to release the manual encrypted result, after that the result will be visible to spi</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DESTROY</name>
          <description>XTS-AES destroy register</description>
          <addressOffset>0x54</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>DESTROY</name>
              <description>Set this bit to destroy XTS-AES result.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STATE</name>
          <description>XTS-AES status register</description>
          <addressOffset>0x58</addressOffset>
          <size>0x20</size>
          <fields>
            <field>
              <name>STATE</name>
              <description>Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means the encrypted result is generated but not visible to mspi. USE means that the encrypted result is visible to mspi.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DATE</name>
          <description>XTS-AES version control register</description>
          <addressOffset>0x5C</addressOffset>
          <size>0x20</size>
          <resetValue>0x20200623</resetValue>
          <fields>
            <field>
              <name>DATE</name>
              <description>Those bits stores the version information of XTS-AES.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>30</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
  </peripherals>
</device>