Skip to content

Commit cb34c2c

Browse files
committed
update mb
1 parent f236cb3 commit cb34c2c

File tree

1 file changed

+9
-2
lines changed

1 file changed

+9
-2
lines changed

memory_barrier.md

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -200,16 +200,23 @@ mfence 会等待当前核心中的 store buffer 排空之后再执行后续指
200200

201201
https://stackoverflow.com/questions/27595595/when-are-x86-lfence-sfence-and-mfence-instructions-required
202202

203+
直接考虑硬件的 fence 指令太复杂了,思考过程应该是,先从程序逻辑出发,然后考虑需要使用哪种 barrier/fence(LL LS SS SL),然后再找对应硬件平台上对应的 fence 指令。
204+
203205
## acquire/release 语义
204206

207+
![barriers](https://preshing.com/images/acq-rel-barriers.png)
208+
205209
https://preshing.com/20130922/acquire-and-release-fences/
206210

207211

208212
## memory order
209213

210-
std::memory_order specifies how memory accesses, including regular, non-atomic memory accesses, are to be ordered around an atomic operation. Absent any constraints on a multi-core system, when multiple threads simultaneously read and write to several variables, one thread can observe the values change in an order different from the order another thread wrote them. Indeed, the apparent order of changes can even differ among multiple reader threads. Some similar effects can occur even on uniprocessor systems due to compiler transformations allowed by the memory model.
214+
硬件会提供其 memory order,而语言本身可能也会有自己的 memory order,在 C/C++ 语言中会根据传给 atomic 的参数来决定其使用的 memory order,从而进行一些重排,这里的重排不但有硬件重排,还有编译器级别的重排。
215+
216+
下面是 C++ 中对 memory_order 参数的描述:
217+
> std::memory_order specifies how memory accesses, including regular, non-atomic memory accesses, are to be ordered around an atomic operation. Absent any constraints on a multi-core system, when multiple threads simultaneously read and write to several variables, one thread can observe the values change in an order different from the order another thread wrote them. Indeed, the apparent order of changes can even differ among multiple reader threads. Some similar effects can occur even on uniprocessor systems due to compiler transformations allowed by the memory model.
211218
212-
The default behavior of all atomic operations in the library provides for sequentially consistent ordering (see discussion below). That default can hurt performance, but the library's atomic operations can be given an additional std::memory_order argument to specify the exact constraints, beyond atomicity, that the compiler and processor must enforce for that operation.
219+
> The default behavior of all atomic operations in the library provides for sequentially consistent ordering (see discussion below). That default can hurt performance, but the library's atomic operations can be given an additional std::memory_order argument to specify the exact constraints, beyond atomicity, that the compiler and processor must enforce for that operation.
213220
214221
## sequential consistency
215222

0 commit comments

Comments
 (0)