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facchinmfacchinm
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boards: add support for Arduino Portenta C33
Tested: * GPIO * UART * USB (using USB_DEVICE_NEXT) * BLE dts to be fixed and completed Signed-off-by: Martino Facchin <m.facchin@arduino.cc>
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‎boards/arduino/portenta_c33/CMakeLists.txt‎

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# Copyright 2025 Arduino SA
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources_ifdef(CONFIG_NETWORKING eth_pwm_clock.c)

‎boards/arduino/portenta_c33/Kconfig.arduino_portenta_c33‎

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# Copyright (c) 2025 Arduino SA
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_ARDUINO_PORTENTA_C33
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select SOC_R7FA6M5BH3CFC

‎boards/arduino/portenta_c33/Kconfig.defconfig‎

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# Copyright 2024 Rahul Arasikere <arasikere.rahul@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_ARDUINO_PORTENTA_C33
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if NETWORKING
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config NET_L2_ETHERNET
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default y
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endif # NETWORKING
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endif # BOARD_ARDUINO_PORTENTA_C33

‎boards/arduino/portenta_c33/arduino_portenta_c33-pinctrl.dtsi‎

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/*
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* Copyright (c) 2024 Arduino SA
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* SPDX-License-Identifier: Apache-2.0
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*/
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&pinctrl {
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sci7_default: sci7_default {
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group1 {
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/* tx rx */
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psels = <RA_PSEL(RA_PSEL_SCI_7, 6, 13)>,
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<RA_PSEL(RA_PSEL_SCI_7, 6, 14)>,
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<RA_PSEL(RA_PSEL_SCI_7, 6, 11)>,
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<RA_PSEL(RA_PSEL_SCI_7, 4, 4)>;
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};
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};
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sci9_default: sci9_default {
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group1 {
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/* tx rx */
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psels = <RA_PSEL(RA_PSEL_SCI_9, 6, 2)>,
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<RA_PSEL(RA_PSEL_SCI_9, 1, 10)>,
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<RA_PSEL(RA_PSEL_SCI_9, 6, 3)>,
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<RA_PSEL(RA_PSEL_SCI_9, 6, 4)>;
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};
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};
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sci5_default: sci5_default {
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group1 {
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/* tx rx */
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psels = <RA_PSEL(RA_PSEL_SCI_5, 8, 5)>,
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<RA_PSEL(RA_PSEL_SCI_5, 5, 13)>,
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<RA_PSEL(RA_PSEL_SCI_5, 5, 8)>,
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<RA_PSEL(RA_PSEL_SCI_5, 5, 0)>;
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};
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};
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sci6_default: sci6_default {
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group1 {
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/* tx rx */
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psels = <RA_PSEL(RA_PSEL_SCI_5, 8, 5)>,
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<RA_PSEL(RA_PSEL_SCI_5, 5, 13)>,
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<RA_PSEL(RA_PSEL_SCI_5, 5, 8)>,
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<RA_PSEL(RA_PSEL_SCI_5, 5, 0)>;
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};
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};
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sci8_default: sci8_default {
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group1 {
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/* tx rx rts cts - BLE */
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psels = <RA_PSEL(RA_PSEL_SCI_8, 10, 0)>,
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<RA_PSEL(RA_PSEL_SCI_8, 6, 7)>,
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<RA_PSEL(RA_PSEL_SCI_8, 6, 6)>,
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<RA_PSEL(RA_PSEL_SCI_8, 8, 1)>;
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};
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};
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iic1_default: iic1_default {
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group1 {
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/* SCL1 SDA1 */
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psels = <RA_PSEL(RA_PSEL_I2C, 5, 12)>,
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<RA_PSEL(RA_PSEL_I2C, 5, 11)>;
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drive-strength = "medium";
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};
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};
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spi1_default: spi1_default {
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group1 {
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/* MISO MOSI RSPCK SSL0 SSL1 */
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psels = <RA_PSEL(RA_PSEL_SPI, 1, 0)>,
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<RA_PSEL(RA_PSEL_SPI, 1, 1)>,
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<RA_PSEL(RA_PSEL_SPI, 1, 2)>,
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<RA_PSEL(RA_PSEL_SPI, 1, 3)>,
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<RA_PSEL(RA_PSEL_SPI, 1, 4)>;
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};
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};
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usbhs_default: usbhs_default {
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group1 {
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psels = <RA_PSEL(RA_PSEL_USBHS, 11, 1)>; /* USBHS-VBUS */
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drive-strength = "high";
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};
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};
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adc0_default: adc0_default {
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group1 {
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/* input */
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psels = <RA_PSEL(RA_PSEL_ADC, 0, 6)>,
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<RA_PSEL(RA_PSEL_ADC, 0, 5)>,
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<RA_PSEL(RA_PSEL_ADC, 0, 4)>,
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<RA_PSEL(RA_PSEL_ADC, 0, 2)>,
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<RA_PSEL(RA_PSEL_ADC, 0, 1)>,
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<RA_PSEL(RA_PSEL_ADC, 0, 15)>,
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<RA_PSEL(RA_PSEL_ADC, 0, 14)>,
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<RA_PSEL(RA_PSEL_ADC, 0, 0)>;
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renesas,analog-enable;
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};
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};
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ether_default: ether_default {
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group1 {
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psels = <RA_PSEL(RA_PSEL_ETH_RMII, 2, 14)>, /* ET0_MDC */
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<RA_PSEL(RA_PSEL_ETH_RMII, 2, 11)>, /* ET0_MDIO */
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<RA_PSEL(RA_PSEL_ETH_RMII, 4, 5)>, /* RMII0_TXD_EN_B */
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<RA_PSEL(RA_PSEL_ETH_RMII, 4, 6)>, /* RMII0_TXD1_BR */
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<RA_PSEL(RA_PSEL_ETH_RMII, 7, 0)>, /* RMII0_TXD0_B */
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<RA_PSEL(RA_PSEL_ETH_RMII, 7, 1)>, /* REF50CK0_B */
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<RA_PSEL(RA_PSEL_ETH_RMII, 7, 2)>, /* RMII0_RXD0_B */
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<RA_PSEL(RA_PSEL_ETH_RMII, 7, 3)>, /* RMII0_RXD1_B */
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<RA_PSEL(RA_PSEL_ETH_RMII, 7, 4)>, /* RMII0_RX_ER_B */
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<RA_PSEL(RA_PSEL_ETH_RMII, 7, 5)>; /* RMII0_CRS_DV_B */
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drive-strength = "high";
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};
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};
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pwm1_default: pwm1_default {
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group1 {
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psels = <RA_PSEL(RA_PSEL_GPT1, 1, 5)>;
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};
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};
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pwm3_default: pwm3_default {
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group1 {
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psels = <RA_PSEL(RA_PSEL_GPT1, 1, 11)>;
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};
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};
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pwm4_default: pwm4_default {
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group1 {
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psels = <RA_PSEL(RA_PSEL_GPT1, 6, 8)>;
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};
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};
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pwm6_default: pwm6_default {
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group1 {
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psels = <RA_PSEL(RA_PSEL_GPT1, 6, 0)>,
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<RA_PSEL(RA_PSEL_GPT1, 6, 1)>;
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};
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};
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pwm7_default: pwm7_default {
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group1 {
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psels = <RA_PSEL(RA_PSEL_GPT1, 3, 3)>;
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};
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};
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pwm8_default: pwm8_default {
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group1 {
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psels = <RA_PSEL(RA_PSEL_GPT1, 1, 6)>,
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<RA_PSEL(RA_PSEL_GPT1, 6, 5)>;
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};
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};
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};

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