@@ -954,11 +954,11 @@ typedef struct { /*!< (@ 0x50030A00) LRA Structur
954
954
__IOM uint32_t LRA_FLT_COEF3_REG; /*!< (@ 0x00000034) LRA Filter Coefficient Register */
955
955
__IOM uint32_t LRA_BRD_LS_REG; /*!< (@ 0x00000038) LRA Bridge Register */
956
956
__IOM uint32_t LRA_BRD_HS_REG; /*!< (@ 0x0000003C) LRA Bridge Register */
957
- __IOM uint32_t LRA_BRD_STAT_REG; /*!< (@ 0x00000040) LRA Bridge Staus Register */
957
+ __IOM uint32_t LRA_BRD_STAT_REG; /*!< (@ 0x00000040) LRA Bridge Status Register */
958
958
__IOM uint32_t LRA_ADC_CTRL1_REG; /*!< (@ 0x00000044) General Purpose ADC Control Register */
959
959
__IM uint32_t RESERVED[2];
960
960
__IOM uint32_t LRA_ADC_RESULT_REG; /*!< (@ 0x00000050) General Purpose ADC Result Register */
961
- __IOM uint32_t LRA_LDO_REG; /*!< (@ 0x00000054) LRA LDO Regsiter */
961
+ __IOM uint32_t LRA_LDO_REG; /*!< (@ 0x00000054) LRA LDO Register */
962
962
__IOM uint32_t LRA_DFT_REG; /*!< (@ 0x00000058) LRA test Register */
963
963
} LRA_Type; /*!< Size = 92 (0x5c) */
964
964
@@ -1043,7 +1043,7 @@ typedef struct { /*!< (@ 0x50000200) PDC Structur
1043
1043
__IOM uint32_t PDC_CTRL15_REG; /*!< (@ 0x0000003C) PDC control register */
1044
1044
__IM uint32_t RESERVED[16];
1045
1045
__IOM uint32_t PDC_ACKNOWLEDGE_REG; /*!< (@ 0x00000080) Clear a pending PDC bit */
1046
- __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakup event */
1046
+ __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakeup event */
1047
1047
__IOM uint32_t PDC_PENDING_SNC_REG; /*!< (@ 0x00000088) Shows any pending IRQ to SNC */
1048
1048
__IOM uint32_t PDC_PENDING_CM33_REG; /*!< (@ 0x0000008C) Shows any pending IRQ to CM33 */
1049
1049
__IOM uint32_t PDC_PENDING_CMAC_REG; /*!< (@ 0x00000090) Shows any pending IRQ to CM33 */
@@ -1752,8 +1752,8 @@ typedef struct { /*!< (@ 0x50000100) WAKEUP Struc
1752
1752
__IOM uint32_t WKUP_SELECT_P1_REG; /*!< (@ 0x00000018) select which inputs from P1 port can trigger
1753
1753
wkup counter */
1754
1754
__IM uint32_t RESERVED2[3];
1755
- __IOM uint32_t WKUP_POL_P0_REG; /*!< (@ 0x00000028) select the sesitivity polarity for each P0 input */
1756
- __IOM uint32_t WKUP_POL_P1_REG; /*!< (@ 0x0000002C) select the sesitivity polarity for each P1 input */
1755
+ __IOM uint32_t WKUP_POL_P0_REG; /*!< (@ 0x00000028) select the sensitivity polarity for each P0 input */
1756
+ __IOM uint32_t WKUP_POL_P1_REG; /*!< (@ 0x0000002C) select the sensitivity polarity for each P1 input */
1757
1757
__IM uint32_t RESERVED3[3];
1758
1758
__IOM uint32_t WKUP_STATUS_P0_REG; /*!< (@ 0x0000003C) Event status register for P0 */
1759
1759
__IOM uint32_t WKUP_STATUS_P1_REG; /*!< (@ 0x00000040) Event status register for P1 */
0 commit comments