Fix: Only return true for 'uart_is_writeable' if the TX FIFO is empty.

This allows the Arduino_Braccio_plusplus library to work again, since it depends on precisely trimmed timeouts to change data direction on the RS485 lines.

This means that when '_serial->flush();' is called, we do wait until the FIFO is empty before turning of DATA ENABLE. Currently if we call _serial->flush(); we are instead only waiting until at least one element has been removed from the transmit FIFO.

Author: aentinger

targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h

@@ -253,14 +253,14 @@ static inline void uart_set_fifo_enabled(uart_inst_t *uart, bool enabled) {
 // ----------------------------------------------------------------------------
 // Generic input/output
 
-/*! \brief Determine if space is available in the TX FIFO
+/*! \brief Determine if the TX FIFO is empty.
  *  \ingroup hardware_uart
  *
  * \param uart UART instance. \ref uart0 or \ref uart1
  * \return false if no space available, true otherwise
  */
 static inline bool uart_is_writable(uart_inst_t *uart) {
-    return !(uart_get_hw(uart)->fr & UART_UARTFR_TXFF_BITS);
+    return (uart_get_hw(uart)->fr & UART_UARTFR_TXFE_BITS);
 }
 
 /*! \brief Wait for the UART TX fifo to be drained

targets/TARGET_RASPBERRYPI/TARGET_RP2040/serial_api.c

@@ -212,4 +212,4 @@ const PinMap *serial_rts_pinmap(void)
     return PinMap_UART_RTS;
 }
 
-#endif
+#endif