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Merge pull request ARMmbed#9167 from TomoYamanaka/hanlder_without_RTOS
Modify IRQ handler processing when unusing RTOS at Cortex-A
2 parents 0f7381d + 3cdc314 commit d2e9136

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-98
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15 files changed

+729
-98
lines changed

‎cmsis/TARGET_CORTEX_A/TOOLCHAIN_IAR/cmain.S

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@@ -0,0 +1,101 @@
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/**************************************************
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*
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* Part two of the system initialization code, contains C-level
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* initialization, thumb-2 only variant.
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*
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* $Revision: 59783 $
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*
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**************************************************/
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/* Copyright 2008-2017, IAR Systems AB.
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This source code is the property of IAR Systems. The source code may only
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be used together with the IAR Embedded Workbench. Redistribution and use
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in source and binary forms, with or without modification, is permitted
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provided that the following conditions are met:
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- Redistributions of source code, in whole or in part, must retain the
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above copyright notice, this list of conditions and the disclaimer below.
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- IAR Systems name may not be used to endorse or promote products
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derived from this software without specific prior written permission.
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THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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; --------------------------------------------------
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; Module ?cmain, C-level initialization.
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;
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SECTION SHT$$PREINIT_ARRAY:CONST:NOROOT(2)
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SECTION SHT$$INIT_ARRAY:CONST:NOROOT(2)
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SECTION .text:CODE:NOROOT(2)
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PUBLIC __cmain
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;; Keep ?main for legacy reasons, it is accessed in countless instances of cstartup.s around the world...
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PUBLIC ?main
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EXTWEAK __iar_data_init3
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EXTWEAK __iar_argc_argv
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EXTERN __low_level_init
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EXTERN __call_ctors
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EXTERN main
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EXTERN exit
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EXTERN __iar_dynamic_initialization
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EXTERN mbed_sdk_init
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EXTERN mbed_main
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EXTERN SystemInit
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THUMB
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__cmain:
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?main:
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; Initialize segments.
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; __segment_init and __low_level_init are assumed to use the same
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; instruction set and to be reachable by BL from the ICODE segment
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; (it is safest to link them in segment ICODE).
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FUNCALL __cmain, __low_level_init
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bl __low_level_init
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cmp r0,#0
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beq ?l1
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FUNCALL __cmain, __iar_data_init3
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bl __iar_data_init3
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MOVS r0,#0 ; No parameters
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FUNCALL __cmain, mbed_sdk_init
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BL mbed_sdk_init
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MOVS r0,#0 ; No parameters
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FUNCALL __cmain, __iar_dynamic_initialization
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BL __iar_dynamic_initialization ; C++ dynamic initialization
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?l1:
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REQUIRE ?l3
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SECTION .text:CODE:NOROOT(2)
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PUBLIC _main
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PUBLIC _call_main
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THUMB
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__iar_init$$done: ; Copy initialization is done
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?l3:
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_call_main:
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MOVS r0,#0 ; No parameters
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FUNCALL __cmain, __iar_argc_argv
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BL __iar_argc_argv ; Maybe setup command line
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MOVS r0,#0 ; No parameters
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FUNCALL __cmain, mbed_main
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BL mbed_main
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FUNCALL __cmain, main
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BL main
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_main:
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FUNCALL __cmain, exit
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BL exit
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END

‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/MBRZA1LU.sct

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE ; load region size_region
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RW_IRAM1 +0 ALIGN 0x10
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{ * (+ZI) } ; Application ZI data (.bss)
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ARM_LIB_HEAP +0
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ARM_LIB_HEAP +0 ALIGN 0x8
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{ * (HEAP) } ; Application heap area (HEAP)
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ARM_LIB_STACK (__RAM_BASE + __NM_RAM_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down

‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/startup_RZ_A1LU.c

Lines changed: 0 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -45,16 +45,6 @@
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void Vectors (void) __attribute__ ((section("RESET")));
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void Reset_Handler(void);
4747

48-
/*----------------------------------------------------------------------------
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Exception / Interrupt Handler
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*----------------------------------------------------------------------------*/
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void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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/*----------------------------------------------------------------------------
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Exception / Interrupt Vector Table
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*----------------------------------------------------------------------------*/
@@ -153,10 +143,3 @@ goToSleep
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IMPORT __main
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BL __main
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}
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/*----------------------------------------------------------------------------
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Default Handler for Exceptions / Interrupts
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*----------------------------------------------------------------------------*/
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void Default_Handler(void) {
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while(1);
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}

‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/sys.cpp

Lines changed: 44 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -45,17 +45,54 @@ extern char Image$$ARM_LIB_HEAP$$Base[];
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extern char Image$$ARM_LIB_STACK$$Base[];
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extern __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
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uint32_t zi_limit = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
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uint32_t sp_limit = (uint32_t)Image$$ARM_LIB_STACK$$Base;
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zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
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struct __initial_stackheap r;
54-
r.heap_base = zi_limit;
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r.heap_limit = sp_limit;
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r.heap_base = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
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r.heap_limit = (uint32_t)Image$$ARM_LIB_STACK$$Base;
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return r;
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}
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#ifndef MBED_CONF_RTOS_PRESENT
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/* The single region memory model would check stack collision at run time, verifying that
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* the heap pointer is underneath the stack pointer. With two-region memory model/RTOS-less or
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* multiple threads(stacks)/RTOS, the check gets meaningless and we must disable it. */
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#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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__asm(".global __use_two_region_memory\n\t");
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__asm(".global __use_no_semihosting\n\t");
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#else
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#pragma import(__use_two_region_memory)
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#endif
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/* Fix __user_setup_stackheap and ARM_LIB_STACK/ARM_LIB_HEAP cannot co-exist in RTOS-less build
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*
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* According AN241 (http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0241b/index.html),
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* __rt_entry has the following call sequence:
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* 1. _platform_pre_stackheap_init
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* 2. __user_setup_stackheap or setup the Stack Pointer (SP) by another method
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* 3. _platform_post_stackheap_init
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* 4. __rt_lib_init
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* 5. _platform_post_lib_init
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* 6. main()
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* 7. exit()
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*
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* Per our check, when __user_setup_stackheap and ARM_LIB_STACK/ARM_LIB_HEAP co-exist, neither
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* does __user_setup_stackheap get called and nor is ARM_LIB_HEAP used to get heap base/limit,
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* which are required to pass to __rt_lib_init later. To fix the issue, by subclass'ing
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* __rt_lib_init, heap base/limit are replaced with Image$$ARM_LIB_HEAP$$ZI$$Base/Limit if
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* ARM_LIB_HEAP region is defined in scatter file.
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*
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* The overriding __rt_lib_init is needed only for rtos-less code. For rtos code, __rt_entry is
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* overridden and the overriding __rt_lib_init here gets meaningless.
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*/
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extern __value_in_regs struct __argc_argv $Super$$__rt_lib_init(unsigned heapbase, unsigned heaptop);
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__value_in_regs struct __argc_argv $Sub$$__rt_lib_init (unsigned heapbase, unsigned heaptop)
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{
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return $Super$$__rt_lib_init((unsigned)Image$$ARM_LIB_HEAP$$Base, (unsigned)Image$$ARM_LIB_STACK$$Base);
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}
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#endif
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#ifdef __cplusplus
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}
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#endif

‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/weak_handler.c

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/*
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* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* -----------------------------------------------------------------------------
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*
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* Project: CMSIS-RTOS RTX
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* Title: Cortex-A Exception handlers
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*
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* -----------------------------------------------------------------------------
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*/
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#include "core_ca.h"
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#define MODE_SVC 0x13
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/*----------------------------------------------------------------------------
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Exception / Interrupt Handler
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*----------------------------------------------------------------------------*/
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void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
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/*----------------------------------------------------------------------------
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Default Handler for Exceptions / Interrupts
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*----------------------------------------------------------------------------*/
42+
void Default_Handler(void) {
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while(1);
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}
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/*----------------------------------------------------------------------------
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Default IRQ Handler for Exceptions / Interrupts
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*----------------------------------------------------------------------------*/
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__WEAK __ASM void IRQ_Handler(void) {
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IMPORT IRQ_GetActiveIRQ
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IMPORT IRQ_GetHandler
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IMPORT IRQ_EndOfInterrupt
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SUB LR, LR, #4 // Pre-adjust LR
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SRSFD SP!, #MODE_SVC // Save LR_irq and SPSR_irq on to the SVC stack
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CPS #MODE_SVC // Change to SVC mode
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PUSH {R0-R3, R12, LR} // Save APCS corruptible registers
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MOV R3, SP // Move SP into R3
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AND R3, R3, #4 // Get stack adjustment to ensure 8-byte alignment
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SUB SP, SP, R3 // Adjust stack
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PUSH {R3, R4} // Store stack adjustment(R3) and user data(R4)
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BLX IRQ_GetActiveIRQ // Retrieve interrupt ID into R0
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MOV R4, R0 // Move interrupt ID to R4
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BLX IRQ_GetHandler // Retrieve interrupt handler address for current ID
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CMP R0, #0 // Check if handler address is 0
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BEQ IRQ_End // If 0, end interrupt and return
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CPSIE i // Re-enable interrupts
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BLX R0 // Call IRQ handler
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CPSID i // Disable interrupts
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IRQ_End
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MOV R0, R4 // Move interrupt ID to R0
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BLX IRQ_EndOfInterrupt // Signal end of interrupt
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POP {R3, R4} // Restore stack adjustment(R3) and user data(R4)
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ADD SP, SP, R3 // Unadjust stack
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POP {R0-R3, R12, LR} // Restore stacked APCS registers
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RFEFD SP! // Return from IRQ handler
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}

‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_GCC_ARM/startup_RZ1ALU.S

Lines changed: 1 addition & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -223,27 +223,4 @@ sf_boot:
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.pool
224224
.size Reset_Handler, . - Reset_Handler
225225

226-
227-
.text
228-
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/* Macro to define default handlers. Default handler
230-
* will be weak symbol and just dead loops. They can be
231-
* overwritten by other handlers */
232-
.macro def_default_handler handler_name
233-
.align 1
234-
.thumb_func
235-
.weak \handler_name
236-
.type \handler_name, %function
237-
\handler_name :
238-
b .
239-
.size \handler_name, . - \handler_name
240-
.endm
241-
242-
def_default_handler Undef_Handler
243-
def_default_handler SVC_Handler
244-
def_default_handler PAbt_Handler
245-
def_default_handler DAbt_Handler
246-
def_default_handler IRQ_Handler
247-
def_default_handler FIQ_Handler
248-
249-
.END
226+
.end

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