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Portenta: refactor clock configuration
1 parent 53103b6 commit a5ce84c

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1 file changed

+29
-8
lines changed

1 file changed

+29
-8
lines changed

targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c

+29-8
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@
4646
#define USE_PLL_HSI 0x2 // Use HSI internal clock
4747

4848
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
49-
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
49+
uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed);
5050
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
5151

5252
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
@@ -64,14 +64,20 @@ uint8_t SetSysClock_PLL_HSI(void);
6464

6565
void SetSysClock(void)
6666
{
67+
68+
bool lowspeed = false;
69+
#if defined(LOWSPEED) && (LOWSPEED == 1)
70+
lowspeed = true;
71+
#endif
72+
6773
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
6874
/* 1- Try to start with HSE and external clock (MCO from STLink PCB part) */
69-
if (SetSysClock_PLL_HSE(1) == 0)
75+
if (SetSysClock_PLL_HSE(1, lowspeed) == 0)
7076
#endif
7177
{
7278
#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
7379
/* 2- If fail try to start with HSE and external xtal */
74-
if (SetSysClock_PLL_HSE(0) == 0)
80+
if (SetSysClock_PLL_HSE(0, lowspeed) == 0)
7581
#endif
7682
{
7783
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
@@ -103,12 +109,22 @@ bool isBetaBoard() {
103109
/******************************************************************************/
104110
/* PLL (clocked by HSE) used as System clock source */
105111
/******************************************************************************/
106-
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
112+
uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed)
107113
{
108114
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
109115
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
110116
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
111117

118+
// If we are reconfiguring the clock, select CSI as system clock source to allow modification of the PLL configuration
119+
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) {
120+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
121+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_CSI;
122+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
123+
{
124+
return 0;
125+
}
126+
}
127+
112128
/* Enable oscillator pin */
113129
__HAL_RCC_GPIOH_CLK_ENABLE();
114130
GPIO_InitTypeDef gpio_osc_init_structure;
@@ -128,7 +144,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
128144
}
129145
/* Configure the main internal regulator output voltage */
130146

131-
if (isBootloader()) {
147+
if (lowspeed) {
132148
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
133149
} else {
134150
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
@@ -147,14 +163,15 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
147163
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
148164
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
149165
RCC_OscInitStruct.PLL.PLLM = 5;
150-
if (isBootloader()) {
166+
if (lowspeed) {
151167
RCC_OscInitStruct.PLL.PLLN = 40;
152168
} else {
153169
RCC_OscInitStruct.PLL.PLLN = 160;
154170
}
171+
155172
if (isBetaBoard()) {
156173
RCC_OscInitStruct.PLL.PLLM = 9;
157-
if (isBootloader()) {
174+
if (lowspeed) {
158175
RCC_OscInitStruct.PLL.PLLN = 80;
159176
} else {
160177
RCC_OscInitStruct.PLL.PLLN = 300;
@@ -182,7 +199,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
182199
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
183200
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
184201
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
185-
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
202+
if (lowspeed) {
203+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
204+
return 0; // FAIL
205+
} else {
206+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
186207
return 0; // FAIL
187208
}
188209

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