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Extend FPGA SPI test
Add test cases for: - async mode, - different frequencies, - block write
1 parent 1c91d03 commit 17d5e6d

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1 file changed

+97
-18
lines changed
  • TESTS/mbed_hal_fpga_ci_test_shield/spi

1 file changed

+97
-18
lines changed

‎TESTS/mbed_hal_fpga_ci_test_shield/spi/main.cpp

+97-18
Original file line numberDiff line numberDiff line change
@@ -34,23 +34,45 @@ using namespace utest::v1;
3434
#include "pinmap.h"
3535
#include "test_utils.h"
3636

37+
typedef enum {
38+
TRANSFER_SPI_MASTER_WRITE_SYNC,
39+
TRANSFER_SPI_MASTER_BLOCK_WRITE_SYNC,
40+
TRANSFER_SPI_MASTER_TRANSFER_ASYNC
41+
} transfer_type_t;
42+
43+
#define FREQ_500_KHZ 500000
44+
#define FREQ_1_MHZ 1000000
45+
#define FREQ_2_MHZ 2000000
3746

3847
const int TRANSFER_COUNT = 300;
3948
SPIMasterTester tester(DefaultFormFactor::pins(), DefaultFormFactor::restricted_pins());
4049

50+
spi_t spi;
51+
static volatile bool async_trasfer_done;
52+
53+
#if DEVICE_SPI_ASYNCH
54+
void spi_async_handler()
55+
{
56+
int event = spi_irq_handler_asynch(&spi);
57+
58+
if (event == SPI_EVENT_COMPLETE) {
59+
async_trasfer_done = true;
60+
}
61+
}
62+
#endif
4163

4264
void spi_test_init_free(PinName mosi, PinName miso, PinName sclk, PinName ssel)
4365
{
44-
spi_t spi;
4566
spi_init(&spi, mosi, miso, sclk, ssel);
4667
spi_format(&spi, 8, SPITester::Mode0, 0);
4768
spi_frequency(&spi, 1000000);
4869
spi_free(&spi);
4970
}
5071

51-
void spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel, SPITester::SpiMode spi_mode, uint32_t sym_size)
72+
void spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel, SPITester::SpiMode spi_mode, uint32_t sym_size, transfer_type_t transfer_type, uint32_t freqency)
5273
{
5374
uint32_t sym_mask = ((1 << sym_size) - 1);
75+
5476
// Remap pins for test
5577
tester.reset();
5678
tester.pin_map_set(mosi, MbedTester::LogicalPinSPIMosi);
@@ -59,10 +81,10 @@ void spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel, SPI
5981
tester.pin_map_set(ssel, MbedTester::LogicalPinSPISsel);
6082

6183
// Initialize mbed SPI pins
62-
spi_t spi;
84+
6385
spi_init(&spi, mosi, miso, sclk, ssel);
6486
spi_format(&spi, sym_size, spi_mode, 0);
65-
spi_frequency(&spi, 1000000);
87+
spi_frequency(&spi, freqency);
6688

6789
// Configure spi_slave module
6890
tester.set_mode(spi_mode);
@@ -73,13 +95,61 @@ void spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel, SPI
7395
tester.peripherals_reset();
7496
tester.select_peripheral(SPITester::PeripheralSPI);
7597

76-
// Send and receive test data
7798
uint32_t checksum = 0;
78-
for (int i = 0; i < TRANSFER_COUNT; i++) {
79-
uint32_t data = spi_master_write(&spi, (0 - i) & sym_mask);
80-
TEST_ASSERT_EQUAL(i & sym_mask, data);
99+
int result = 0;
100+
uint8_t tx_buf[TRANSFER_COUNT] = {0};
101+
uint8_t rx_buf[TRANSFER_COUNT] = {0};
102+
103+
// Send and receive test data
104+
switch (transfer_type) {
105+
case TRANSFER_SPI_MASTER_WRITE_SYNC:
106+
for (int i = 0; i < TRANSFER_COUNT; i++) {
107+
uint32_t data = spi_master_write(&spi, (0 - i) & sym_mask);
108+
TEST_ASSERT_EQUAL(i & sym_mask, data);
109+
110+
checksum += (0 - i) & sym_mask;
111+
}
112+
break;
113+
114+
case TRANSFER_SPI_MASTER_BLOCK_WRITE_SYNC:
115+
for (int i = 0; i < TRANSFER_COUNT; i++) {
116+
tx_buf[i] = (0 - i) & sym_mask;
117+
checksum += (0 - i) & sym_mask;
118+
rx_buf[i] = 0xAA;
119+
}
120+
121+
result = spi_master_block_write(&spi, (const char *)tx_buf, TRANSFER_COUNT, (char *)rx_buf, TRANSFER_COUNT, 0xF5);
122+
123+
for (int i = 0; i < TRANSFER_COUNT; i++) {
124+
TEST_ASSERT_EQUAL(i & sym_mask, rx_buf[i]);
125+
}
126+
TEST_ASSERT_EQUAL(TRANSFER_COUNT, result);
127+
break;
128+
129+
#if DEVICE_SPI_ASYNCH
130+
case TRANSFER_SPI_MASTER_TRANSFER_ASYNC:
131+
for (int i = 0; i < TRANSFER_COUNT; i++) {
132+
tx_buf[i] = (0 - i) & sym_mask;
133+
checksum += (0 - i) & sym_mask;
134+
rx_buf[i] = 0xAA;
135+
}
136+
137+
async_trasfer_done = false;
138+
139+
spi_master_transfer(&spi, tx_buf, TRANSFER_COUNT, rx_buf, TRANSFER_COUNT, 8, (uint32_t)spi_async_handler, 0, DMA_USAGE_NEVER);
140+
while (!async_trasfer_done);
141+
142+
for (int i = 0; i < TRANSFER_COUNT; i++) {
143+
TEST_ASSERT_EQUAL(i & sym_mask, rx_buf[i]);
144+
}
145+
146+
break;
147+
#endif
148+
149+
default:
150+
TEST_ASSERT_TRUE(false);
151+
break;
81152

82-
checksum += (0 - i) & sym_mask;
83153
}
84154

85155
// Verify that the transfer was successful
@@ -90,27 +160,36 @@ void spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel, SPI
90160
tester.reset();
91161
}
92162

93-
template<SPITester::SpiMode spi_mode, uint32_t sym_size>
163+
template<SPITester::SpiMode spi_mode, uint32_t sym_size, transfer_type_t transfer_type, uint32_t freqency>
94164
void spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel)
95165
{
96-
spi_test_common(mosi, miso, sclk, ssel, spi_mode, sym_size);
166+
spi_test_common(mosi, miso, sclk, ssel, spi_mode, sym_size, transfer_type, freqency);
97167
}
98168

99169
Case cases[] = {
100170
// This will be run for all pins
101171
Case("SPI - init/free test all pins", all_ports<SPIPort, DefaultFormFactor, spi_test_init_free>),
102172

103173
// This will be run for all peripherals
104-
Case("SPI - basic test", all_peripherals<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode0, 8> >),
174+
Case("SPI - basic test", all_peripherals<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
105175

106176
// This will be run for single pin configuration
107-
Case("SPI - mode testing (MODE_1)", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode1, 8> >),
108-
Case("SPI - mode testing (MODE_2)", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode2, 8> >),
109-
Case("SPI - mode testing (MODE_3)", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode3, 8> >),
177+
Case("SPI - mode testing (MODE_1)", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode1, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
178+
Case("SPI - mode testing (MODE_2)", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode2, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
179+
Case("SPI - mode testing (MODE_3)", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode3, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
180+
181+
Case("SPI - symbol size testing (4)", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode0, 4, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
182+
Case("SPI - symbol size testing (12)", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode0, 12, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
183+
Case("SPI - symbol size testing (16)", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode0, 16, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
184+
185+
Case("SPI - frequency testing (500 kHz)", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_500_KHZ> >),
186+
Case("SPI - frequency testing (2 MHz)", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_2_MHZ> >),
187+
188+
Case("SPI - block write", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_BLOCK_WRITE_SYNC, FREQ_1_MHZ> >),
110189

111-
Case("SPI - symbol size testing (4)", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode0, 4> >),
112-
Case("SPI - symbol size testing (12)", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode0, 12> >),
113-
Case("SPI - symbol size testing (16)", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode0, 16> >)
190+
#if DEVICE_SPI_ASYNCH
191+
Case("SPI - async mode", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_TRANSFER_ASYNC, FREQ_1_MHZ> >)
192+
#endif
114193
};
115194

116195
utest::v1::status_t greentea_test_setup(const size_t number_of_cases)

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