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| 1 | +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD |
| 2 | +// |
| 3 | +// Licensed under the Apache License, Version 2.0 (the "License"); |
| 4 | +// you may not use this file except in compliance with the License. |
| 5 | +// You may obtain a copy of the License at |
| 6 | + |
| 7 | +// http://www.apache.org/licenses/LICENSE-2.0 |
| 8 | +// |
| 9 | +// Unless required by applicable law or agreed to in writing, software |
| 10 | +// distributed under the License is distributed on an "AS IS" BASIS, |
| 11 | +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 12 | +// See the License for the specific language governing permissions and |
| 13 | +// limitations under the License. |
| 14 | + |
| 15 | +#include "esp32-hal.h" |
| 16 | +#include "freertos/FreeRTOS.h" |
| 17 | +#include "freertos/task.h" |
| 18 | +#include "freertos/semphr.h" |
| 19 | +#include "rom/ets_sys.h" |
| 20 | +#include "esp32-hal-matrix.h" |
| 21 | +#include "soc/dport_reg.h" |
| 22 | +#include "soc/ledc_reg.h" |
| 23 | +#include "soc/ledc_struct.h" |
| 24 | + |
| 25 | +xSemaphoreHandle _ledc_sys_lock; |
| 26 | + |
| 27 | + |
| 28 | +#define LEDC_MUTEX_LOCK() do {} while (xSemaphoreTake(_ledc_sys_lock, portMAX_DELAY) != pdPASS) |
| 29 | +#define LEDC_MUTEX_UNLOCK() xSemaphoreGive(_ledc_sys_lock) |
| 30 | + |
| 31 | +/* |
| 32 | + * LEDC Chan to Group/Channel/Timer Mapping |
| 33 | +** ledc: 0 => Group: 0, Channel: 0, Timer: 0 |
| 34 | +** ledc: 1 => Group: 0, Channel: 1, Timer: 0 |
| 35 | +** ledc: 2 => Group: 0, Channel: 2, Timer: 1 |
| 36 | +** ledc: 3 => Group: 0, Channel: 3, Timer: 1 |
| 37 | +** ledc: 4 => Group: 0, Channel: 4, Timer: 2 |
| 38 | +** ledc: 5 => Group: 0, Channel: 5, Timer: 2 |
| 39 | +** ledc: 6 => Group: 0, Channel: 6, Timer: 3 |
| 40 | +** ledc: 7 => Group: 0, Channel: 7, Timer: 3 |
| 41 | +** ledc: 8 => Group: 1, Channel: 0, Timer: 0 |
| 42 | +** ledc: 9 => Group: 1, Channel: 1, Timer: 0 |
| 43 | +** ledc: 10 => Group: 1, Channel: 2, Timer: 1 |
| 44 | +** ledc: 11 => Group: 1, Channel: 3, Timer: 1 |
| 45 | +** ledc: 12 => Group: 1, Channel: 4, Timer: 2 |
| 46 | +** ledc: 13 => Group: 1, Channel: 5, Timer: 2 |
| 47 | +** ledc: 14 => Group: 1, Channel: 6, Timer: 3 |
| 48 | +** ledc: 15 => Group: 1, Channel: 7, Timer: 3 |
| 49 | +*/ |
| 50 | + |
| 51 | +//uint32_t frequency = (80MHz or 1MHz)/((div_num / 256.0)*(1 << bit_num)); |
| 52 | +void ledcSetupTimer(uint8_t chan, uint32_t div_num, uint8_t bit_num, bool apb_clk) |
| 53 | +{ |
| 54 | + ledc_dev_t * ledc_dev = (volatile ledc_dev_t *)(DR_REG_LEDC_BASE); |
| 55 | + uint8_t group=(chan/8), timer=((chan/2)%4); |
| 56 | + static bool tHasStarted = false; |
| 57 | + if(!tHasStarted) { |
| 58 | + tHasStarted = true; |
| 59 | + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_LEDC_CLK_EN); |
| 60 | + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_LEDC_RST); |
| 61 | + ledc_dev->conf.apb_clk_sel = 1;//LS use apb clock |
| 62 | + _ledc_sys_lock = xSemaphoreCreateMutex(); |
| 63 | + } |
| 64 | + LEDC_MUTEX_LOCK(); |
| 65 | + ledc_dev->timer_group[group].timer[timer].conf.div_num = div_num;//18 bit (10.8) This register is used to configure parameter for divider in timer the least significant eight bits represent the decimal part. |
| 66 | + ledc_dev->timer_group[group].timer[timer].conf.bit_num = bit_num;//5 bit This register controls the range of the counter in timer. the counter range is [0 2**bit_num] the max bit width for counter is 20. |
| 67 | + ledc_dev->timer_group[group].timer[timer].conf.tick_sel = apb_clk;//apb clock |
| 68 | + if(group) { |
| 69 | + ledc_dev->timer_group[group].timer[timer].conf.low_speed_update = 1;//This bit is only useful for low speed timer channels, reserved for high speed timers |
| 70 | + } |
| 71 | + ledc_dev->timer_group[group].timer[timer].conf.pause = 0; |
| 72 | + ledc_dev->timer_group[group].timer[timer].conf.rst = 1;//This bit is used to reset timer the counter will be 0 after reset. |
| 73 | + ledc_dev->timer_group[group].timer[timer].conf.rst = 0; |
| 74 | + LEDC_MUTEX_UNLOCK(); |
| 75 | +} |
| 76 | + |
| 77 | +uint32_t ledcSetupTimerFreq(uint8_t chan, uint32_t freq, uint8_t bit_num) |
| 78 | +{ |
| 79 | + uint64_t clk_freq = APB_CLK_FREQ; |
| 80 | + clk_freq <<= 8;//div_num is 8 bit decimal |
| 81 | + uint32_t div_num = (clk_freq >> bit_num) / freq; |
| 82 | + bool apb_clk = true; |
| 83 | + if(div_num > LEDC_DIV_NUM_HSTIMER0_V) { |
| 84 | + clk_freq /= 80; |
| 85 | + div_num = (clk_freq >> bit_num) / freq; |
| 86 | + if(div_num > LEDC_DIV_NUM_HSTIMER0_V) { |
| 87 | + div_num = LEDC_DIV_NUM_HSTIMER0_V;//lowest clock possible |
| 88 | + } |
| 89 | + apb_clk = false; |
| 90 | + } else if(div_num < 256) { |
| 91 | + div_num = 256;//highest clock possible |
| 92 | + } |
| 93 | + ledcSetupTimer(chan, div_num, bit_num, apb_clk); |
| 94 | + return (clk_freq >> bit_num) / div_num; |
| 95 | +} |
| 96 | + |
| 97 | +void ledcSetupChannel(uint8_t chan, uint8_t idle_level) |
| 98 | +{ |
| 99 | + uint8_t group=(chan/8), channel=(chan%8), timer=((chan/2)%4); |
| 100 | + ledc_dev_t * ledc_dev = (volatile ledc_dev_t *)(DR_REG_LEDC_BASE); |
| 101 | + LEDC_MUTEX_LOCK(); |
| 102 | + ledc_dev->channel_group[group].channel[channel].conf0.timer_sel = timer;//2 bit Selects the timer to attach 0-3 |
| 103 | + ledc_dev->channel_group[group].channel[channel].conf0.idle_lv = idle_level;//1 bit This bit is used to control the output value when channel is off. |
| 104 | + ledc_dev->channel_group[group].channel[channel].hpoint.hpoint = 0;//20 bit The output value changes to high when timer selected by channel has reached hpoint |
| 105 | + ledc_dev->channel_group[group].channel[channel].conf1.duty_inc = 1;//1 bit This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel |
| 106 | + ledc_dev->channel_group[group].channel[channel].conf1.duty_num = 1;//10 bit This register is used to control the number of increased or decreased times for channel |
| 107 | + ledc_dev->channel_group[group].channel[channel].conf1.duty_cycle = 1;//10 bit This register is used to increase or decrease the duty every duty_cycle cycles for channel |
| 108 | + ledc_dev->channel_group[group].channel[channel].conf1.duty_scale = 0;//10 bit This register controls the increase or decrease step scale for channel. |
| 109 | + ledc_dev->channel_group[group].channel[channel].duty.duty = 0; |
| 110 | + ledc_dev->channel_group[group].channel[channel].conf0.sig_out_en = 0;//This is the output enable control bit for channel |
| 111 | + ledc_dev->channel_group[group].channel[channel].conf1.duty_start = 0;//When duty_num duty_cycle and duty_scale has been configured. these register won't take effect until set duty_start. this bit is automatically cleared by hardware. |
| 112 | + if(group) { |
| 113 | + ledc_dev->channel_group[group].channel[channel].conf0.val &= ~BIT(4); |
| 114 | + } else { |
| 115 | + ledc_dev->channel_group[group].channel[channel].conf0.clk_en = 0; |
| 116 | + } |
| 117 | + LEDC_MUTEX_UNLOCK(); |
| 118 | +} |
| 119 | + |
| 120 | +uint32_t ledcSetup(uint8_t chan, uint32_t freq, uint8_t bit_num) |
| 121 | +{ |
| 122 | + if(chan > 15) { |
| 123 | + return 0; |
| 124 | + } |
| 125 | + uint32_t res_freq = ledcSetupTimerFreq(chan, freq, bit_num); |
| 126 | + ledcSetupChannel(chan, LOW); |
| 127 | + return res_freq; |
| 128 | +} |
| 129 | + |
| 130 | +void ledcWrite(uint8_t chan, uint32_t duty) |
| 131 | +{ |
| 132 | + if(chan > 15) { |
| 133 | + return; |
| 134 | + } |
| 135 | + uint8_t group=(chan/8), channel=(chan%8); |
| 136 | + ledc_dev_t * ledc_dev = (volatile ledc_dev_t *)(DR_REG_LEDC_BASE); |
| 137 | + LEDC_MUTEX_LOCK(); |
| 138 | + ledc_dev->channel_group[group].channel[channel].duty.duty = duty << 4;//25 bit (21.4) |
| 139 | + if(duty) { |
| 140 | + ledc_dev->channel_group[group].channel[channel].conf0.sig_out_en = 1;//This is the output enable control bit for channel |
| 141 | + ledc_dev->channel_group[group].channel[channel].conf1.duty_start = 1;//When duty_num duty_cycle and duty_scale has been configured. these register won't take effect until set duty_start. this bit is automatically cleared by hardware. |
| 142 | + if(group) { |
| 143 | + ledc_dev->channel_group[group].channel[channel].conf0.val |= BIT(4); |
| 144 | + } else { |
| 145 | + ledc_dev->channel_group[group].channel[channel].conf0.clk_en = 1; |
| 146 | + } |
| 147 | + } else { |
| 148 | + ledc_dev->channel_group[group].channel[channel].conf0.sig_out_en = 0;//This is the output enable control bit for channel |
| 149 | + ledc_dev->channel_group[group].channel[channel].conf1.duty_start = 0;//When duty_num duty_cycle and duty_scale has been configured. these register won't take effect until set duty_start. this bit is automatically cleared by hardware. |
| 150 | + if(group) { |
| 151 | + ledc_dev->channel_group[group].channel[channel].conf0.val &= ~BIT(4); |
| 152 | + } else { |
| 153 | + ledc_dev->channel_group[group].channel[channel].conf0.clk_en = 0; |
| 154 | + } |
| 155 | + } |
| 156 | + LEDC_MUTEX_UNLOCK(); |
| 157 | +} |
| 158 | + |
| 159 | +uint32_t ledcRead(uint8_t chan) |
| 160 | +{ |
| 161 | + if(chan > 15) { |
| 162 | + return 0; |
| 163 | + } |
| 164 | + ledc_dev_t * ledc_dev = (volatile ledc_dev_t *)(DR_REG_LEDC_BASE); |
| 165 | + return ledc_dev->channel_group[chan/8].channel[chan%8].duty.duty >> 4; |
| 166 | +} |
| 167 | + |
| 168 | +void ledcAttachPin(uint8_t pin, uint8_t chan) |
| 169 | +{ |
| 170 | + if(chan > 15) { |
| 171 | + return; |
| 172 | + } |
| 173 | + pinMode(pin, OUTPUT); |
| 174 | + pinMatrixOutAttach(pin, ((chan/8)?LEDC_LS_SIG_OUT0_IDX:LEDC_HS_SIG_OUT0_IDX) + (chan%8), false, false); |
| 175 | +} |
| 176 | + |
| 177 | +void ledcDetachPin(uint8_t pin) |
| 178 | +{ |
| 179 | + pinMatrixOutDetach(pin, false, false); |
| 180 | +} |
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