forked from espressif/arduino-esp32
-
-
Notifications
You must be signed in to change notification settings - Fork 7
/
Copy pathxtml605.h
executable file
·338 lines (268 loc) · 11.9 KB
/
xtml605.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
/* Copyright (c) 2007-2013 by Tensilica Inc. ALL RIGHTS RESERVED.
/ These coded instructions, statements, and computer programs are the
/ copyrighted works and confidential proprietary information of Tensilica Inc.
/ They may not be modified, copied, reproduced, distributed, or disclosed to
/ third parties in any manner, medium, or form, in whole or in part, without
/ the prior written consent of Tensilica Inc.
*/
/* xtml605.h - Xtensa Xilinx ML605 (XT-ML605) board specific definitions */
/* xtkc705.h - Also includes this, for the Xilinx KC705 (XT-KC705). */
#ifndef _INC_ML605_H_
#define _INC_ML605_H_
#include <xtensa/config/core.h>
#include <xtensa/config/system.h>
#if XTBOARD_IS_KC705
#define XTBOARD_NAME "XT-KC705"
#else
#define XTBOARD_NAME "XT-ML605"
#endif
/*
* Default assignment of ML605 devices to external interrupts.
*/
/* Ethernet interrupt: */
#ifdef XCHAL_EXTINT1_NUM
#define ETHERNET_INTNUM XCHAL_EXTINT1_NUM
#define ETHERNET_INTLEVEL XCHAL_EXTINT1_LEVEL
#define ETHERNET_INTMASK XCHAL_EXTINT1_MASK
#else
#define ETHERNET_INTMASK 0
#endif
/* UART interrupt: */
#ifdef XCHAL_EXTINT0_NUM
#define UART16550_INTNUM XCHAL_EXTINT0_NUM
#define UART16550_INTLEVEL XCHAL_EXTINT0_LEVEL
#define UART16550_INTMASK XCHAL_EXTINT0_MASK
#else
#define UART16550_INTMASK 0
#endif
/* Audio output interrupt (I2S transmitter FIFO): */
#ifdef XCHAL_EXTINT2_NUM
#define AUDIO_I2S_OUT_INTNUM XCHAL_EXTINT2_NUM
#define AUDIO_I2S_OUT_INTLEVEL XCHAL_EXTINT2_LEVEL
#define AUDIO_I2S_OUT_INTMASK XCHAL_EXTINT2_MASK
#else
#define AUDIO_I2S_OUT_INTMASK 0
#endif
/* Audio input interrupt (I2S receiver FIFO): */
#ifdef XCHAL_EXTINT3_NUM
#define AUDIO_I2S_IN_INTNUM XCHAL_EXTINT3_NUM
#define AUDIO_I2S_IN_INTLEVEL XCHAL_EXTINT3_LEVEL
#define AUDIO_I2S_IN_INTMASK XCHAL_EXTINT3_MASK
#else
#define AUDIO_I2S_IN_INTMASK 0
#endif
/* I2C interrupt */
#ifdef XCHAL_EXTINT4_NUM
#define I2C_INTNUM XCHAL_EXTINT4_NUM
#define I2C_INTLEVEL XCHAL_EXTINT4_LEVEL
#define I2C_INTMASK XCHAL_EXTINT4_MASK
#else
#define I2C_INTMASK 0
#endif
/* USB interrupt */
#ifdef XCHAL_EXTINT5_NUM
#define USB_INTNUM XCHAL_EXTINT5_NUM
#define USB_INTLEVEL XCHAL_EXTINT5_LEVEL
#define USB_INTMASK XCHAL_EXTINT5_MASK
#else
#define USB_INTMASK 0
#endif
/*
* Device addresses.
*
* Note: for endianness-independence, use 32-bit loads and stores for all
* register accesses to Ethernet, UART and LED devices. Undefined bits
* may need to be masked out if needed when reading if the actual register
* size is smaller than 32 bits.
*
* Note: ML605 bus byte lanes are defined in terms of msbyte and lsbyte
* relative to the processor. So 32-bit registers are accessed consistently
* from both big and little endian processors. However, this means byte
* sequences are not consistent between big and little endian processors.
* This is fine for RAM, and for ROM if ROM is created for a specific
* processor (and thus has correct byte sequences). However this may be
* unexpected for Flash, which might contain a file-system that one wants
* to use for multiple processor configurations (eg. the Flash might contain
* the Ethernet card's address, endianness-independent application data, etc).
* That is, byte sequences written in Flash by a core of a given endianness
* will be byte-swapped when seen by a core of the other endianness.
* Someone implementing an endianness-independent Flash file system will
* likely handle this byte-swapping issue in the Flash driver software.
*/
#define ML605_FLASH_MAXSIZE 0x01000000 /* 16 MB */
#define ML605_FLASH_IOBLOCK_OFS 0x08000000
#define KC705_FLASH_MAXSIZE 0x08000000 /* 128 MB */
#define KC705_FLASH_IOBLOCK_OFS 0x00000000
#if XTBOARD_IS_KC705
#define XTBOARD_FLASH_MAXSIZE KC705_FLASH_MAXSIZE
#define XTBOARD_FLASH_IO_OFS KC705_FLASH_IOBLOCK_OFS
#else
#define XTBOARD_FLASH_MAXSIZE ML605_FLASH_MAXSIZE
#define XTBOARD_FLASH_IO_OFS ML605_FLASH_IOBLOCK_OFS
#endif
#ifdef XSHAL_IOBLOCK_BYPASS_PADDR
/* Flash Memory: */
# define XTBOARD_FLASH_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+XTBOARD_FLASH_IO_OFS)
/* FPGA registers: */
# define XTBOARD_FPGAREGS_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D020000)
/* Ethernet controller/transceiver SONIC SN83934: */
# define ETHERNET_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D030000)
/* UART National-Semi PC16550D: */
# define UART16550_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D050000)
/* I2S transmitter */
# define AUDIO_I2S_OUT_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D080000)
/* I2S receiver */
# define AUDIO_I2S_IN_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D088000)
/* I2C master */
# define I2C_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D090000)
/* SPI controller */
# define SPI_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D0A0000)
/* Display controller Sunplus SPLC780D, 4bit mode,
* LCD Display MYTech MOC-16216B-B: */
# define SPLC780D_4BIT_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D0C0000)
/* USB Controller */
# define USB_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D0D0000)
/* Ethernet buffer: */
# define ETHERNET_BUFFER_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D800000)
#endif /* XSHAL_IOBLOCK_BYPASS_PADDR */
/* These devices might be accessed cached: */
#ifdef XSHAL_IOBLOCK_CACHED_PADDR
# define XTBOARD_FLASH_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+XTBOARD_FLASH_IO_OFS)
# define ETHERNET_BUFFER_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x0D800000)
#endif /* XSHAL_IOBLOCK_CACHED_PADDR */
/*** Same thing over again, this time with virtual addresses: ***/
#ifdef XSHAL_IOBLOCK_BYPASS_VADDR
/* Flash Memory: */
# define XTBOARD_FLASH_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+XTBOARD_FLASH_IO_OFS)
/* FPGA registers: */
# define XTBOARD_FPGAREGS_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D020000)
/* Ethernet controller/transceiver SONIC SN83934: */
# define ETHERNET_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D030000)
/* UART National-Semi PC16550D: */
# define UART16550_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D050000)
/* I2S transmitter */
# define AUDIO_I2S_OUT_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D080000)
/* I2S receiver */
# define AUDIO_I2S_IN_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D088000)
/* I2C master */
# define I2C_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D090000)
/* SPI controller */
# define SPI_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D0A0000)
/* Display controller Sunplus SPLC780D, 4bit mode,
* LCD Display MYTech MOC-16216B-B: */
# define SPLC780D_4BIT_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D0C0000)
/* USB Controller */
# define USB_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D0D0000)
/* Ethernet buffer: */
# define ETHERNET_BUFFER_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D800000)
#endif /* XSHAL_IOBLOCK_BYPASS_VADDR */
/* These devices might be accessed cached: */
#ifdef XSHAL_IOBLOCK_CACHED_VADDR
# define XTBOARD_FLASH_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+XTBOARD_FLASH_IO_OFS)
# define ETHERNET_BUFFER_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D800000)
#endif /* XSHAL_IOBLOCK_CACHED_VADDR */
/* System ROM: */
#define XTBOARD_ROM_SIZE XSHAL_ROM_SIZE
#ifdef XSHAL_ROM_VADDR
#define XTBOARD_ROM_VADDR XSHAL_ROM_VADDR
#endif
#ifdef XSHAL_ROM_PADDR
#define XTBOARD_ROM_PADDR XSHAL_ROM_PADDR
#endif
/* System RAM: */
#define XTBOARD_RAM_SIZE XSHAL_RAM_SIZE
#ifdef XSHAL_RAM_VADDR
#define XTBOARD_RAM_VADDR XSHAL_RAM_VADDR
#endif
#ifdef XSHAL_RAM_PADDR
#define XTBOARD_RAM_PADDR XSHAL_RAM_PADDR
#endif
#define XTBOARD_RAM_BYPASS_VADDR XSHAL_RAM_BYPASS_VADDR
#define XTBOARD_RAM_BYPASS_PADDR XSHAL_RAM_BYPASS_PADDR
/*
* Things that depend on device addresses.
*/
#define XTBOARD_CACHEATTR_WRITEBACK XSHAL_XT2000_CACHEATTR_WRITEBACK
#define XTBOARD_CACHEATTR_WRITEALLOC XSHAL_XT2000_CACHEATTR_WRITEALLOC
#define XTBOARD_CACHEATTR_WRITETHRU XSHAL_XT2000_CACHEATTR_WRITETHRU
#define XTBOARD_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS
#define XTBOARD_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT
#define XTBOARD_BUSINT_PIPE_REGIONS XSHAL_XT2000_PIPE_REGIONS
#define XTBOARD_BUSINT_SDRAM_REGIONS XSHAL_XT2000_SDRAM_REGIONS
/*
* FPGA registers.
* All these registers are normally accessed using 32-bit loads/stores.
*/
/* Register offsets: */
#define XTBOARD_DATECD_OFS 0x00 /* date code (read-only) */
#define XTBOARD_CLKFRQ_OFS 0x04 /* clock frequency Hz (read-only) */
#define XTBOARD_SYSLED_OFS 0x08 /* LEDs */
#define XTBOARD_DIPSW_OFS 0x0C /* DIP switch bits (read-only) */
#define XTBOARD_SWRST_OFS 0x10 /* software reset */
/* Physical register addresses: */
#ifdef XTBOARD_FPGAREGS_PADDR
#define XTBOARD_DATECD_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DATECD_OFS)
#define XTBOARD_CLKFRQ_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_CLKFRQ_OFS)
#define XTBOARD_SYSLED_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_SYSLED_OFS)
#define XTBOARD_DIPSW_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DIPSW_OFS)
#define XTBOARD_SWRST_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_SWRST_OFS)
#endif
/* Virtual register addresses: */
#ifdef XTBOARD_FPGAREGS_VADDR
#define XTBOARD_DATECD_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DATECD_OFS)
#define XTBOARD_CLKFRQ_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_CLKFRQ_OFS)
#define XTBOARD_SYSLED_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_SYSLED_OFS)
#define XTBOARD_DIPSW_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DIPSW_OFS)
#define XTBOARD_SWRST_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_SWRST_OFS)
/* Register access (for C code): */
#define XTBOARD_DATECD_REG (*(volatile unsigned*) XTBOARD_DATECD_VADDR)
#define XTBOARD_CLKFRQ_REG (*(volatile unsigned*) XTBOARD_CLKFRQ_VADDR)
#define XTBOARD_SYSLED_REG (*(volatile unsigned*) XTBOARD_SYSLED_VADDR)
#define XTBOARD_DIPSW_REG (*(volatile unsigned*) XTBOARD_DIPSW_VADDR)
#define XTBOARD_SWRST_REG (*(volatile unsigned*) XTBOARD_SWRST_VADDR)
#endif
/* DATECD (date code; when core was built) bit fields: */
/* BCD-coded month (01..12): */
#define XTBOARD_DATECD_MONTH_SHIFT 24
#define XTBOARD_DATECD_MONTH_BITS 8
#define XTBOARD_DATECD_MONTH_MASK 0xFF000000
/* BCD-coded day (01..31): */
#define XTBOARD_DATECD_DAY_SHIFT 16
#define XTBOARD_DATECD_DAY_BITS 8
#define XTBOARD_DATECD_DAY_MASK 0x00FF0000
/* BCD-coded year (2001..9999): */
#define XTBOARD_DATECD_YEAR_SHIFT 0
#define XTBOARD_DATECD_YEAR_BITS 16
#define XTBOARD_DATECD_YEAR_MASK 0x0000FFFF
/* SYSLED (system LED) bit fields: */
/* LED control bits (off=0, on=1): */
#define XTBOARD_SYSLED_USER_SHIFT 0
#define XTBOARD_SYSLED_USER_BITS 2
#define XTBOARD_SYSLED_USER_MASK 0x00000003
/* DIP Switch SW? (left=sw1=lsb=bit0, right=sw4=msb=bit3; off=0, on=1): */
/* DIP switch bit fields (bit2/sw3 is reserved and presently unused): */
#if XTBOARD_IS_KC705
#define XTBOARD_DIPSW_USER_SHIFT 0
#define XTBOARD_DIPSW_USER_BITS 2
#define XTBOARD_DIPSW_USER_MASK 0x00000003
#define XTBOARD_DIPSW_BOOT_SHIFT 3
#define XTBOARD_DIPSW_BOOT_BITS 1
#define XTBOARD_DIPSW_BOOT_MASK 0x00000008
#else /* ML605: */
#define XTBOARD_DIPSW_USER_SHIFT 0
#define XTBOARD_DIPSW_USER_BITS 6
#define XTBOARD_DIPSW_USER_MASK 0x0000003F
#define XTBOARD_DIPSW_BOOT_SHIFT 7
#define XTBOARD_DIPSW_BOOT_BITS 1
#define XTBOARD_DIPSW_BOOT_MASK 0x00000080
#endif /*ML605*/
#define XTBOARD_DIPSW_BOOT_RAM (0<<XTBOARD_DIPSW_BOOT_SHIFT) /* off */
#define XTBOARD_DIPSW_BOOT_FLASH (1<<XTBOARD_DIPSW_BOOT_SHIFT) /* on */
/* SWRST (software reset; allows s/w to generate power-on equivalent reset): */
/* Software reset bits: */
#define XTBOARD_SWRST_SWR_SHIFT 0
#define XTBOARD_SWRST_SWR_BITS 16
#define XTBOARD_SWRST_SWR_MASK 0x0000FFFF
/* Software reset value -- writing this value resets the board: */
#define XTBOARD_SWRST_RESETVALUE 0x0000DEAD
#endif /*_INC_ML605_H_*/