diff --git a/.github/workflows/compile-examples.yml b/.github/workflows/compile-examples.yml index 1a3eff1d0..31598c04c 100644 --- a/.github/workflows/compile-examples.yml +++ b/.github/workflows/compile-examples.yml @@ -97,6 +97,7 @@ jobs: additional-libraries: | - name: Arduino_BHY2 - name: ArduinoBLE + - name: PacketSerial - board: fqbn: arduino:mbed:nicla_vision additional-sketch-paths: | diff --git a/boards.txt b/boards.txt index 5cd6b1258..0508a02b0 100644 --- a/boards.txt +++ b/boards.txt @@ -13,7 +13,6 @@ edge_control.build.fpu=-mfpu=fpv4-sp-d16 edge_control.build.float-abi=-mfloat-abi=softfp edge_control.build.board=EDGE_CONTROL edge_control.build.ldscript=linker_script.ld -edge_control.build.postbuild.cmd="{tools.imgtool.path}/{tools.imgtool.cmd}" exit edge_control.compiler.mbed.arch.define=-DARDUINO_ARCH_NRF52840 edge_control.compiler.mbed.defines={build.variant.path}/defines.txt edge_control.compiler.mbed.ldflags={build.variant.path}/ldflags.txt @@ -80,11 +79,10 @@ envie_m7.build.slot_size=0x1E0000 envie_m7.build.header_size=0x20000 envie_m7.build.alignment=32 envie_m7.build.version=1.2.3+4 -envie_m7.menu.security.sien.build.postbuild.cmd="{tools.imgtool.path}/{tools.imgtool.cmd}" {tools.imgtool.flags} +envie_m7.menu.security.sien.recipe.hooks.objcopy.postobjcopy.1.pattern="{tools.imgtool.path}/{tools.imgtool.cmd}" {tools.imgtool.flags} envie_m7.menu.security.sien.build.keys.keychain={runtime.platform.path}/libraries/MCUboot/default_keys envie_m7.menu.security.sien.build.keys.sign_key=ecdsa-p256-signing-priv-key.pem envie_m7.menu.security.sien.build.keys.encrypt_key=ecdsa-p256-encrypt-pub-key.pem -envie_m7.menu.security.none.build.postbuild.cmd="{tools.imgtool.path}/{tools.imgtool.cmd}" exit envie_m7.compiler.mbed.arch.define= envie_m7.compiler.mbed.defines={build.variant.path}/defines.txt envie_m7.compiler.mbed.ldflags={build.variant.path}/ldflags.txt @@ -167,7 +165,6 @@ envie_m4.menu.split.100_0.build.extra_ldflags=-DCM4_BINARY_START=0x60000000 -DCM envie_m4.build.architecture=cortex-m4 envie_m4.build.board=PORTENTA_H7_M4 envie_m4.build.ldscript=linker_script.ld -envie_m4.build.postbuild.cmd="{tools.imgtool.path}/{tools.imgtool.cmd}" exit envie_m4.compiler.mbed.arch.define= envie_m4.compiler.mbed.defines={build.variant.path}/defines.txt envie_m4.compiler.mbed.ldflags={build.variant.path}/ldflags.txt @@ -262,8 +259,6 @@ portenta_x8.bootloader.programmer=-f interface/stlink.cfg portenta_x8.bootloader.extra_action.preflash=stm32h7x option_write 0 0x01c 0xb86aaf0 portenta_x8.bootloader.file=PORTENTA_X7/STM32H747AII6_CM7.elf -portenta_x8.build.postbuild.cmd="{tools.imgtool.path}/{tools.imgtool.cmd}" exit - ############################################################## nano33ble.name=Arduino Nano 33 BLE @@ -279,7 +274,6 @@ nano33ble.build.fpu=-mfpu=fpv4-sp-d16 nano33ble.build.float-abi=-mfloat-abi=softfp nano33ble.build.board=ARDUINO_NANO33BLE nano33ble.build.ldscript=linker_script.ld -nano33ble.build.postbuild.cmd="{tools.imgtool.path}/{tools.imgtool.cmd}" exit nano33ble.compiler.mbed.arch.define=-DARDUINO_ARCH_NRF52840 nano33ble.compiler.mbed.defines={build.variant.path}/defines.txt nano33ble.compiler.mbed.ldflags={build.variant.path}/ldflags.txt @@ -337,7 +331,6 @@ nanorp2040connect.build.float-abi= nanorp2040connect.build.architecture=cortex-m0plus nanorp2040connect.build.board=NANO_RP2040_CONNECT nanorp2040connect.build.ldscript=linker_script.ld -nanorp2040connect.build.postbuild.cmd="{tools.imgtool.path}/{tools.imgtool.cmd}" exit nanorp2040connect.compiler.mbed.arch.define=-DARDUINO_ARCH_RP2040 nanorp2040connect.compiler.mbed.defines={build.variant.path}/defines.txt nanorp2040connect.compiler.mbed.ldflags={build.variant.path}/ldflags.txt @@ -346,6 +339,7 @@ nanorp2040connect.compiler.mbed.cxxflags={build.variant.path}/cxxflags.txt nanorp2040connect.compiler.mbed.includes={build.variant.path}/includes.txt nanorp2040connect.compiler.mbed.extra_ldflags=-lstdc++ -lsupc++ -lm -lc -lgcc -lnosys nanorp2040connect.compiler.mbed="{build.variant.path}/libs/libmbed.a" +nanorp2040connect.recipe.hooks.objcopy.postobjcopy.1.pattern="{runtime.tools.rp2040tools.path}/elf2uf2" "{build.path}/{build.project_name}.elf" "{build.path}/{build.project_name}.uf2" nanorp2040connect.vid.0=0x2341 nanorp2040connect.pid.0=0x005e nanorp2040connect.vid.1=0x2341 @@ -393,7 +387,6 @@ pico.build.float-abi= pico.build.architecture=cortex-m0plus pico.build.board=RASPBERRY_PI_PICO pico.build.ldscript=linker_script.ld -pico.build.postbuild.cmd="{tools.imgtool.path}/{tools.imgtool.cmd}" exit pico.compiler.mbed.arch.define=-DARDUINO_ARCH_RP2040 pico.compiler.mbed.defines={build.variant.path}/defines.txt pico.compiler.mbed.ldflags={build.variant.path}/ldflags.txt @@ -402,6 +395,7 @@ pico.compiler.mbed.cxxflags={build.variant.path}/cxxflags.txt pico.compiler.mbed.includes={build.variant.path}/includes.txt pico.compiler.mbed.extra_ldflags=-lstdc++ -lsupc++ -lm -lc -lgcc -lnosys pico.compiler.mbed="{build.variant.path}/libs/libmbed.a" +pico.recipe.hooks.objcopy.postobjcopy.1.pattern="{runtime.tools.rp2040tools.path}/elf2uf2" "{build.path}/{build.project_name}.elf" "{build.path}/{build.project_name}.uf2" pico.vid.0=0x2e8a pico.pid.0=0x00C0 pico.upload_port.0.vid=0x2e8a @@ -437,7 +431,6 @@ nicla_sense.build.fpu=-mfpu=fpv4-sp-d16 nicla_sense.build.float-abi=-mfloat-abi=softfp nicla_sense.build.board=NICLA nicla_sense.build.ldscript=linker_script.ld -nicla_sense.build.postbuild.cmd="{tools.imgtool.path}/{tools.imgtool.cmd}" exit nicla_sense.compiler.mbed.arch.define=-DARDUINO_ARCH_NRF52832 nicla_sense.compiler.mbed.defines={build.variant.path}/defines.txt nicla_sense.compiler.mbed.ldflags={build.variant.path}/ldflags.txt @@ -485,7 +478,6 @@ nicla_vision.build.extra_flags= nicla_vision.build.architecture=cortex-m7 nicla_vision.build.board=NICLA_VISION nicla_vision.build.ldscript=linker_script.ld -nicla_vision.build.postbuild.cmd="{tools.imgtool.path}/{tools.imgtool.cmd}" exit nicla_vision.compiler.mbed.arch.define= nicla_vision.compiler.mbed.defines={build.variant.path}/defines.txt nicla_vision.compiler.mbed.ldflags={build.variant.path}/ldflags.txt diff --git a/cores/arduino/mbed/connectivity/cellular/include/cellular/framework/AT/AT_CellularDevice.h b/cores/arduino/mbed/connectivity/cellular/include/cellular/framework/AT/AT_CellularDevice.h index 60ae735e7..fa011a096 100755 --- a/cores/arduino/mbed/connectivity/cellular/include/cellular/framework/AT/AT_CellularDevice.h +++ b/cores/arduino/mbed/connectivity/cellular/include/cellular/framework/AT/AT_CellularDevice.h @@ -67,7 +67,7 @@ class AT_CellularDevice : public CellularDevice { }; public: - AT_CellularDevice(FileHandle *fh); + AT_CellularDevice(FileHandle *fh, char *delim = "\r"); virtual ~AT_CellularDevice(); virtual nsapi_error_t clear(); diff --git a/cores/arduino/mbed/connectivity/drivers/emac/TARGET_ARM_SSG/COMPONENT_SMSC9220/smsc9220_emac_config.h b/cores/arduino/mbed/connectivity/drivers/emac/TARGET_ARM_SSG/COMPONENT_SMSC9220/smsc9220_emac_config.h index a96a00835..5f618308c 100644 --- a/cores/arduino/mbed/connectivity/drivers/emac/TARGET_ARM_SSG/COMPONENT_SMSC9220/smsc9220_emac_config.h +++ b/cores/arduino/mbed/connectivity/drivers/emac/TARGET_ARM_SSG/COMPONENT_SMSC9220/smsc9220_emac_config.h @@ -36,7 +36,7 @@ #define FLAG_RX 1U #define LINK_STATUS_THREAD_PRIORITY (osPriorityNormal) #define LINK_STATUS_THREAD_STACKSIZE 512U -#define LINK_STATUS_TASK_PERIOD_MS 200U +#define LINK_STATUS_TASK_PERIOD_MS 200ms #define PHY_STATE_LINK_DOWN false #define PHY_STATE_LINK_UP true #define CRC_LENGTH_BYTES 4U diff --git a/cores/arduino/mbed/connectivity/drivers/wifi/esp8266-driver/ESP8266/ESP8266.h b/cores/arduino/mbed/connectivity/drivers/wifi/esp8266-driver/ESP8266/ESP8266.h index 4b5b18943..963e8619b 100644 --- a/cores/arduino/mbed/connectivity/drivers/wifi/esp8266-driver/ESP8266/ESP8266.h +++ b/cores/arduino/mbed/connectivity/drivers/wifi/esp8266-driver/ESP8266/ESP8266.h @@ -455,9 +455,10 @@ class ESP8266 { /** * Stop board's and ESP8266's UART flow control * + * @param board_only true to apply to board only, false to apply both * @return true if started */ - bool stop_uart_hw_flow_ctrl(); + bool stop_uart_hw_flow_ctrl(bool board_only = false); /* * From AT firmware v1.7.0.0 onwards enables TCP passive mode diff --git a/cores/arduino/mbed/connectivity/lorawan/include/lorawan/LoRaRadio.h b/cores/arduino/mbed/connectivity/lorawan/include/lorawan/LoRaRadio.h index 601c6b9e5..f6673399a 100644 --- a/cores/arduino/mbed/connectivity/lorawan/include/lorawan/LoRaRadio.h +++ b/cores/arduino/mbed/connectivity/lorawan/include/lorawan/LoRaRadio.h @@ -200,7 +200,7 @@ typedef struct radio_fsk_packet_handler { /** * Storage for RSSI value of the received signal. */ - int8_t rssi_value; + int16_t rssi_value; /** * Automated frequency correction value. @@ -333,7 +333,7 @@ typedef struct radio_lora_packet_handler { /** * RSSI value in dBm for the received packet. */ - int8_t rssi_value; + int16_t rssi_value; /** * Size of the transmitted or received packet. diff --git a/cores/arduino/mbed/connectivity/lorawan/system/lorawan_data_structures.h b/cores/arduino/mbed/connectivity/lorawan/system/lorawan_data_structures.h index 7ce8cb33c..724bc87e7 100644 --- a/cores/arduino/mbed/connectivity/lorawan/system/lorawan_data_structures.h +++ b/cores/arduino/mbed/connectivity/lorawan/system/lorawan_data_structures.h @@ -908,7 +908,7 @@ typedef struct { * * Provides a certain QOS level set by network server in LinkADRReq MAC * command. The device will transmit the given UNCONFIRMED message nb_trials - * time with same frame counter until a downlink is received. Standard defined + * time with the same frame counter OR until a downlink is received. Standard defined * range is 1:15. Data rates will NOT be adapted according to chapter 18.4. */ uint8_t nb_trials; diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/eventOS_callback_timer.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/eventOS_callback_timer.h index 6b7d70581..9ec9344e0 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/eventOS_callback_timer.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/eventOS_callback_timer.h @@ -1,15 +1,16 @@ /* - * Copyright (c) 2014-2015 ARM Limited. All rights reserved. + * Copyright (c) 2014-2015, Pelion and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/eventOS_event.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/eventOS_event.h index ac4a6d082..5cdddf7b0 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/eventOS_event.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/eventOS_event.h @@ -1,15 +1,16 @@ /* - * Copyright (c) 2014-2015 ARM Limited. All rights reserved. + * Copyright (c) 2014-2015, 2017, 2019-2020, Pelion and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/eventOS_event_timer.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/eventOS_event_timer.h index 776dd0e9f..8b19d3bb2 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/eventOS_event_timer.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/eventOS_event_timer.h @@ -1,15 +1,16 @@ /* - * Copyright (c) 2014-2015 ARM Limited. All rights reserved. + * Copyright (c) 2014-2015, 2017, 2020, Pelion and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/eventOS_scheduler.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/eventOS_scheduler.h index 5059eaa01..691f4160d 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/eventOS_scheduler.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/eventOS_scheduler.h @@ -1,15 +1,16 @@ /* - * Copyright (c) 2014-2015 ARM Limited. All rights reserved. + * Copyright (c) 2014-2016, 2020, Pelion and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/platform/arm_hal_timer.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/platform/arm_hal_timer.h index 0a661abfa..e2b93e00e 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/platform/arm_hal_timer.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/platform/arm_hal_timer.h @@ -1,15 +1,16 @@ /* - * Copyright (c) 2014-2015 ARM Limited. All rights reserved. + * Copyright (c) 2014-2017, Pelion and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/platform/eventloop_config.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/platform/eventloop_config.h index 81e7e0393..4c7f6b26d 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/platform/eventloop_config.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/nanostack-event-loop/platform/eventloop_config.h @@ -1,15 +1,16 @@ /* - * Copyright (c) 2014-2015 ARM Limited. All rights reserved. + * Copyright (c) 2014-2017, 2019, Pelion and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/source/event.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/source/event.h index 9efb68585..92020d700 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/source/event.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/source/event.h @@ -1,15 +1,16 @@ /* - * Copyright (c) 2017 ARM Limited. All rights reserved. + * Copyright (c) 2017, Pelion and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/source/ns_timer.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/source/ns_timer.h index eac2f9d48..3286e31a1 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/source/ns_timer.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/source/ns_timer.h @@ -1,15 +1,16 @@ /* - * Copyright (c) 2014-2015 ARM Limited. All rights reserved. + * Copyright (c) 2014-2017, Pelion and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/source/timer_sys.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/source/timer_sys.h index a29aec937..54bc9c4dc 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/source/timer_sys.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack-eventloop/source/timer_sys.h @@ -1,15 +1,16 @@ /* - * Copyright (c) 2014-2015 ARM Limited. All rights reserved. + * Copyright (c) 2014-2015, 2017, Pelion and affiliates. * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/nanostack/net_interface.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/nanostack/net_interface.h index eb87675af..6be75ae8f 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/nanostack/net_interface.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/nanostack/net_interface.h @@ -99,6 +99,8 @@ typedef enum arm_library_event_type_e { #define SOCKET_NO_RAM (10 << 4) /** TCP connection problem indication (RFC 1122 R1) */ #define SOCKET_CONNECTION_PROBLEM (11 << 4) +/** Socket is busy or Radio is returning CCA failure */ +#define SOCKET_BUSY (12 << 4) #define SOCKET_BIND_DONE SOCKET_CONNECT_DONE /**< Backward compatibility */ #define SOCKET_BIND_FAIL SOCKET_CONNECT_FAIL /**< Backward compatibility */ diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/nanostack/socket_api.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/nanostack/socket_api.h index 7cf8b5774..fe19acd75 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/nanostack/socket_api.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/nanostack/socket_api.h @@ -115,6 +115,7 @@ extern "C" { * | | | TCP: some data acknowledged (d_len = data remaining in send queue) | * | SOCKET_NO_RAM | 0xA0 | No RAM available. | * | SOCKET_CONNECTION_PROBLEM | 0xB0 | TCP connection is retrying. | + * | SOCKET_BUSY | 0xC0 | Socket is busy or Radio channel is returning CCA failure. | * * * \section socket-tcp How to use TCP sockets: diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/nanostack/ws_bbr_api.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/nanostack/ws_bbr_api.h index 00e8623c6..2450de854 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/nanostack/ws_bbr_api.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/nanostack/ws_bbr_api.h @@ -88,6 +88,22 @@ typedef struct bbr_timezone_configuration { * "bit xxxxxxxxxxxxxxxS" 0 = false 1 = true Daylight saving time status*/ uint16_t status; } bbr_timezone_configuration_t; + + +/** + * \brief Border router configuration. + */ +typedef struct bbr_configuration_s { + uint32_t dhcp_address_lifetime; /**< DHCP address lifetime in seconds minimum 2 hours and maximum few days*/ + uint32_t rpl_default_lifetime; /**< RPL default lifetime value from 30 minutes to 16 hours*/ + uint16_t dag_max_rank_increase; /**< DIO Max rank increase. Range 0-2048 */ + uint16_t min_hop_rank_increase; /**< DIO Min hop rank increase. range 32-256 */ + uint16_t options; /**< Border router configuration options */ + uint8_t dio_interval_min; /**< DIO interval min. range 1-255 */ + uint8_t dio_interval_doublings; /**< DIO interval doublings. range 1-8 */ + uint8_t dio_redundancy_constant; /**< DIO redundancy constant. Range 0-10 */ +} bbr_configuration_t; + /** * Start backbone border router service. * @@ -270,7 +286,52 @@ int ws_bbr_eapol_node_limit_set(int8_t interface_id, uint16_t limit); int ws_bbr_ext_certificate_validation_set(int8_t interface_id, uint8_t validation); /** - * Sets RPL parameters + * Sets Border router configuration + * + * Sets the configuration to the border router. Use ws_configuration_get to get + * the settings and modify wanted parameters. + * + * Minor validation is done to parameters, but full validation must be done + * at application level + * + * \param interface_id Network interface ID. + * \param configuration_ptr Configuration structure. + * + * \return 0, Configuration parameters set. + * \return <0 Parameter set failed. + */ +int ws_bbr_configuration_set(int8_t interface_id, bbr_configuration_t *configuration_ptr); + +/** + * Get Border router configuration + * + * Gets the current configuration to the border router. + * + * \param interface_id Network interface ID. + * \param configuration_ptr Configuration structure. + * + * \return 0, Configuration parameters set. + * \return <0 Parameter set failed. + */ +int ws_bbr_configuration_get(int8_t interface_id, bbr_configuration_t *configuration_ptr); + +/** + * validate Border router configuration + * + * Minor validation is done to parameters. + * Full validation must be done at application level. + * + * \param interface_id Network interface ID. + * \param configuration_ptr Configuration structure. + * + * \return 0, Configuration parameters set. + * \return <0 Parameter set failed. + */ +int ws_bbr_configuration_validate(int8_t interface_id, bbr_configuration_t *configuration_ptr); + +/** + * Sets RPL parameters (DEPRECATED) + * Use ws_bbr_configuration_set instead. * * Sets RPL DIO trickle parameters. * @@ -285,7 +346,8 @@ int ws_bbr_ext_certificate_validation_set(int8_t interface_id, uint8_t validatio int ws_bbr_rpl_parameters_set(int8_t interface_id, uint8_t dio_interval_min, uint8_t dio_interval_doublings, uint8_t dio_redundancy_constant); /** - * Gets RPL parameters + * Gets RPL parameters (DEPRECATED) + * Use ws_bbr_configuration_get instead. * * Gets RPL DIO trickle parameters. * @@ -300,7 +362,8 @@ int ws_bbr_rpl_parameters_set(int8_t interface_id, uint8_t dio_interval_min, uin int ws_bbr_rpl_parameters_get(int8_t interface_id, uint8_t *dio_interval_min, uint8_t *dio_interval_doublings, uint8_t *dio_redundancy_constant); /** - * Validate RPL parameters + * Validate RPL parameters (DEPRECATED) + * Use ws_bbr_configuration_validate instead. * * Validates RPL DIO trickle parameters. * diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.h index 8c08a4397..b114ee914 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.h @@ -18,7 +18,6 @@ #ifndef WS_BOOTSTRAP_H_ #define WS_BOOTSTRAP_H_ - typedef enum { WS_INIT_EVENT = 0, /**< tasklet initializion event*/ WS_DISCOVERY_START, /**< discovery start*/ @@ -76,8 +75,6 @@ extern uint16_t test_pan_version; int ws_bootstrap_init(int8_t interface_id, net_6lowpan_mode_e bootstrap_mode); -void ws_bootstrap_state_machine(protocol_interface_info_entry_t *cur); - int ws_bootstrap_restart(int8_t interface_id); int ws_bootstrap_restart_delayed(int8_t interface_id); @@ -92,21 +89,19 @@ void ws_bootstrap_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t s void ws_bootstrap_trickle_timer(protocol_interface_info_entry_t *cur, uint16_t ticks); -void ws_bootstrap_primary_parent_update(protocol_interface_info_entry_t *interface, mac_neighbor_table_entry_t *neighbor); - -void ws_bootstrap_secondary_parent_update(protocol_interface_info_entry_t *interface); - void ws_nud_entry_remove_active(protocol_interface_info_entry_t *cur, void *neighbor); void ws_nud_active_timer(protocol_interface_info_entry_t *cur, uint16_t ticks); -void ws_dhcp_client_address_request(protocol_interface_info_entry_t *cur, uint8_t *prefix, uint8_t *parent_link_local); +void ws_bootstrap_eapol_parent_synch(struct protocol_interface_info_entry *cur, struct llc_neighbour_req *neighbor_info); -void ws_dhcp_client_address_delete(protocol_interface_info_entry_t *cur, uint8_t *prefix); +void ws_bootstrap_ll_address_validate(struct protocol_interface_info_entry *cur); -bool ws_eapol_relay_state_active(protocol_interface_info_entry_t *cur); +uint16_t ws_local_etx_read(protocol_interface_info_entry_t *interface, addrtype_t addr_type, const uint8_t *mac_adddress); -void ws_bootstrap_eapol_parent_synch(struct protocol_interface_info_entry *cur, struct llc_neighbour_req *neighbor_info); +bool ws_bootstrap_nd_ns_transmit(protocol_interface_info_entry_t *cur, ipv6_neighbour_t *entry, bool unicast, uint8_t seq); + +void ws_bootstrap_memory_configuration(); bool ws_bootstrap_validate_channel_plan(struct ws_us_ie *ws_us, struct protocol_interface_info_entry *cur); @@ -166,16 +161,15 @@ void ws_bootstrap_candidate_parent_sort(struct protocol_interface_info_entry *cu parent_info_t *ws_bootstrap_candidate_parent_get_best(protocol_interface_info_entry_t *cur); void ws_bootstrap_primary_parent_set(struct protocol_interface_info_entry *cur, struct llc_neighbour_req *neighbor_info, ws_parent_synch_e synch_req); -void ws_bootstrap_parent_confirm(protocol_interface_info_entry_t *cur, struct rpl_instance *instance); bool ws_bootstrap_neighbor_info_request(struct protocol_interface_info_entry *interface, const uint8_t *mac_64, struct llc_neighbour_req *neighbor_buffer, bool request_new); void ws_bootstrap_neighbor_list_clean(struct protocol_interface_info_entry *interface); int8_t ws_bootstrap_neighbor_set(protocol_interface_info_entry_t *cur, parent_info_t *parent_ptr, bool clear_list); +void ws_address_reregister_trig(struct protocol_interface_info_entry *interface); void ws_nud_table_reset(protocol_interface_info_entry_t *cur); -void ws_address_registration_update(protocol_interface_info_entry_t *interface, const uint8_t addr[16]); - void ws_bootstrap_configure_csma_ca_backoffs(protocol_interface_info_entry_t *cur, uint8_t max_backoffs, uint8_t min_be, uint8_t max_be); void ws_bootstrap_fhss_configure_channel_masks(protocol_interface_info_entry_t *cur, fhss_ws_configuration_t *fhss_configuration); +int8_t ws_bootstrap_fhss_initialize(protocol_interface_info_entry_t *cur); int8_t ws_bootstrap_fhss_set_defaults(protocol_interface_info_entry_t *cur, fhss_ws_configuration_t *fhss_configuration); void ws_bootstrap_fhss_activate(protocol_interface_info_entry_t *cur); uint16_t ws_bootstrap_randomize_fixed_channel(uint16_t configured_fixed_channel, uint8_t number_of_channels, uint32_t *channel_mask); @@ -186,9 +180,6 @@ void ws_bootstrap_configure_data_request_restart(protocol_interface_info_entry_t void ws_bootstrap_llc_hopping_update(struct protocol_interface_info_entry *cur, const fhss_ws_configuration_t *fhss_configuration); -void ws_bootstrap_rpl_activate(protocol_interface_info_entry_t *cur); -void ws_bootstrap_rpl_scan_start(protocol_interface_info_entry_t *cur); - void ws_bootstrap_ip_stack_reset(protocol_interface_info_entry_t *cur); void ws_bootstrap_ip_stack_activate(protocol_interface_info_entry_t *cur); @@ -201,13 +192,10 @@ void ws_bootstrap_network_start(protocol_interface_info_entry_t *cur); #else #define ws_bootstrap_init(interface_id, bootstrap_mode) (-1) -#define ws_bootstrap_state_machine(cur) #define ws_bootstrap_restart(cur) #define ws_bootstrap_neighbor_remove(cur, ll_address) #define ws_bootstrap_aro_failure(cur, ll_address) #define ws_bootstrap_neighbor_set_stable(interface, src64) -#define ws_bootstrap_primary_parent_update(interface, neighbor) -#define ws_bootstrap_secondary_parent_update(interface) #define ws_bootstrap_stack_info_get(cur, info_ptr) #define ws_bootstrap_neighbor_info_get(cur, neighbor_ptr, count) #define ws_bootstrap_test_procedure_trigger(cur, procedure); diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6lbr.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6lbr.h index 5517793fb..716454484 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6lbr.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6lbr.h @@ -22,6 +22,7 @@ void ws_bootstrap_6lbr_asynch_ind(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, const struct mcps_data_ie_list *ie_ext, uint8_t message_type); void ws_bootstrap_6lbr_asynch_confirm(struct protocol_interface_info_entry *interface, uint8_t asynch_message); +bool ws_bootstrap_6lbr_eapol_relay_state_active(protocol_interface_info_entry_t *cur); void ws_bootstrap_6lbr_event_handler(protocol_interface_info_entry_t *cur, arm_event_s *event); void ws_bootstrap_6lbr_state_machine(protocol_interface_info_entry_t *cur); void ws_bootstrap_6lbr_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds); @@ -32,6 +33,7 @@ void ws_bootstrap_6lbr_seconds_timer(protocol_interface_info_entry_t *cur, uint3 #define ws_bootstrap_6lbr_asynch_ind(cur, data, ie_ext, message_type) ((void) 0) #define ws_bootstrap_6lbr_asynch_confirm(interface, asynch_message) ((void) 0) +#define ws_bootstrap_6lbr_eapol_relay_state_active(cur) false #define ws_bootstrap_6lbr_event_handler(cur, event) ((void) 0) #define ws_bootstrap_6lbr_state_machine(cur) ((void) 0) #define ws_bootstrap_6lbr_seconds_timer(cur, seconds) ((void) 0) diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6ln.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6ln.h new file mode 100644 index 000000000..0b9edeffd --- /dev/null +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6ln.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2021, Pelion and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef WS_BOOTSTRAP_6LN_H_ +#define WS_BOOTSTRAP_6LN_H_ + +#if defined(HAVE_WS) && defined(HAVE_WS_HOST) + +void ws_bootstrap_6ln_asynch_ind(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, const struct mcps_data_ie_list *ie_ext, uint8_t message_type); +void ws_bootstrap_6ln_asynch_confirm(struct protocol_interface_info_entry *interface, uint8_t asynch_message); +bool ws_bootstrap_6ln_eapol_relay_state_active(protocol_interface_info_entry_t *cur); +void ws_bootstrap_6ln_event_handler(protocol_interface_info_entry_t *cur, arm_event_s *event); +void ws_bootstrap_6ln_state_machine(protocol_interface_info_entry_t *cur); +void ws_bootstrap_6ln_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds); + +int8_t ws_bootstrap_6ln_up(protocol_interface_info_entry_t *cur); +int8_t ws_bootstrap_6ln_down(protocol_interface_info_entry_t *cur); + +#define wisun_mode_host(cur) (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_HOST) + +#else + +#define ws_bootstrap_6lr_asynch_ind(cur, data, ie_ext, message_type) ((void) 0) +#define ws_bootstrap_6lr_asynch_confirm(interface, asynch_message) ((void) 0) +#define ws_bootstrap_6ln_eapol_relay_state_active(false) false +#define ws_bootstrap_6lr_event_handler(cur, event) ((void) 0) +#define ws_bootstrap_6ln_state_machine(cur) ((void) 0) +#define ws_bootstrap_6ln_seconds_timer(cur, seconds) ((void) 0) + +#define ws_bootstrap_6ln_up(cur) +#define ws_bootstrap_6ln_down(cur) + +#define wisun_mode_host(cur) (false) + +#endif //HAVE_WS + +#endif /* WS_BOOTSTRAP_6LN_H_ */ diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6lr.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6lr.h new file mode 100644 index 000000000..0facfa3d3 --- /dev/null +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6lr.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2021, Pelion and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef WS_BOOTSTRAP_6LR_H_ +#define WS_BOOTSTRAP_6LR_H_ + +#if defined(HAVE_WS) && defined(HAVE_WS_ROUTER) + +void ws_bootstrap_6lr_asynch_ind(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, const struct mcps_data_ie_list *ie_ext, uint8_t message_type); +void ws_bootstrap_6lr_asynch_confirm(struct protocol_interface_info_entry *interface, uint8_t asynch_message); +bool ws_bootstrap_6lr_eapol_relay_state_active(protocol_interface_info_entry_t *cur); +void ws_bootstrap_6lr_event_handler(protocol_interface_info_entry_t *cur, arm_event_s *event); +void ws_bootstrap_6lr_state_machine(protocol_interface_info_entry_t *cur); +void ws_bootstrap_6lr_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds); + +void ws_bootstrap_6lr_primary_parent_update(protocol_interface_info_entry_t *interface, mac_neighbor_table_entry_t *neighbor); +void ws_bootstrap_6lr_secondary_parent_update(protocol_interface_info_entry_t *interface); +void ws_bootstrap_6lr_address_registration_update(protocol_interface_info_entry_t *interface, const uint8_t addr[16]); + +#define wisun_mode_router(cur) (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_ROUTER) + +#else + +#define ws_bootstrap_6lr_asynch_ind(cur, data, ie_ext, message_type) ((void) 0) +#define ws_bootstrap_6lr_asynch_confirm(interface, asynch_message) ((void) 0) +#define ws_bootstrap_6lr_eapol_relay_state_active false +#define ws_bootstrap_6lr_event_handler(cur, event) ((void) 0) +#define ws_bootstrap_6lr_state_machine(cur) ((void) 0) +#define ws_bootstrap_6lr_seconds_timer(cur, seconds) ((void) 0) +#define ws_bootstrap_6lr_primary_parent_update(interface, neighbor) ((void) 0) +#define ws_bootstrap_6lr_secondary_parent_update(interface) ((void) 0) +#define ws_bootstrap_6lr_address_registration_update(interface, addr) ((void) 0) + +#define wisun_mode_router(cur) (false) + +#endif //HAVE_WS + +#endif /* WS_BOOTSTRAP_6LR_H_ */ diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_ffn.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_ffn.h index fcc9dd25d..b598b8147 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_ffn.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_ffn.h @@ -18,26 +18,15 @@ #ifndef WS_BOOTSTRAP_FFN_H_ #define WS_BOOTSTRAP_FFN_H_ -#if defined(HAVE_WS) && defined(HAVE_WS_ROUTER) +#ifdef HAVE_WS -void ws_bootstrap_ffn_asynch_ind(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, const struct mcps_data_ie_list *ie_ext, uint8_t message_type); -void ws_bootstrap_ffn_asynch_confirm(struct protocol_interface_info_entry *interface, uint8_t asynch_message); -void ws_bootstrap_ffn_event_handler(protocol_interface_info_entry_t *cur, arm_event_s *event); -void ws_bootstrap_ffn_state_machine(protocol_interface_info_entry_t *cur); -void ws_bootstrap_ffn_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds); +int8_t ws_bootstrap_ffn_up(protocol_interface_info_entry_t *cur); +int8_t ws_bootstrap_ffn_down(protocol_interface_info_entry_t *cur); -#define wisun_mode_router(cur) (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_ROUTER) +void ws_dhcp_client_address_request(protocol_interface_info_entry_t *cur, uint8_t *prefix, uint8_t *parent_link_local); -#else +void ws_bootstrap_ffn_rpl_configure(protocol_interface_info_entry_t *cur); -#define ws_bootstrap_ffn_asynch_ind(cur, data, ie_ext, message_type) ((void) 0) -#define ws_bootstrap_ffn_asynch_confirm(interface, asynch_message) ((void) 0) -#define ws_bootstrap_ffn_event_handler(cur, event) ((void) 0) -#define ws_bootstrap_ffn_state_machine(cur) ((void) 0) -#define ws_bootstrap_ffn_seconds_timer(cur, seconds) ((void) 0) +#endif -#define wisun_mode_router(cur) (false) - -#endif //HAVE_WS - -#endif /* WS_BOOTSTRAP_H_ */ +#endif /* WS_BOOTSTRAP_FFN_H_ */ diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_lfn.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_lfn.h deleted file mode 100644 index 84a0cf810..000000000 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_lfn.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2021, Pelion and affiliates. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef WS_BOOTSTRAP_LFN_H_ -#define WS_BOOTSTRAP_LFN_H_ - -#if defined(HAVE_WS) && defined(HAVE_WS_HOST) - -void ws_bootstrap_lfn_asynch_ind(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, const struct mcps_data_ie_list *ie_ext, uint8_t message_type); -void ws_bootstrap_lfn_asynch_confirm(struct protocol_interface_info_entry *interface, uint8_t asynch_message); -void ws_bootstrap_lfn_event_handler(protocol_interface_info_entry_t *cur, arm_event_s *event); -void ws_bootstrap_lfn_state_machine(protocol_interface_info_entry_t *cur); -void ws_bootstrap_lfn_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds); - -#define wisun_mode_host(cur) (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_HOST) - -#else - -#define ws_bootstrap_ffn_asynch_ind(cur, data, ie_ext, message_type) ((void) 0) -#define ws_bootstrap_ffn_asynch_confirm(interface, asynch_message) ((void) 0) -#define ws_bootstrap_ffn_event_handler(cur, event) ((void) 0) -#define ws_bootstrap_lfn_state_machine(cur) ((void) 0) -#define ws_bootstrap_lfn_seconds_timer(cur, seconds) ((void) 0) - -#define wisun_mode_host(cur) (false) - -#endif //HAVE_WS - -#endif /* WS_BOOTSTRAP_H_ */ diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_config.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_config.h index 9af23615d..d2715783a 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_config.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_config.h @@ -246,15 +246,21 @@ extern uint8_t DEVICE_MIN_SENS; * * Trickle is reset on start (inconsistent heard is set) */ +#define SEC_PROT_TIMER_EXPIRATIONS 4 // Number of retries +#define SEC_PROT_END_DELAY 30 // 30 seconds delay + #define SEC_PROT_SMALL_IMIN 60 // Retries done in 60 seconds #define SEC_PROT_SMALL_IMAX 120 // Largest value 120 seconds -#define SEC_PROT_RETRY_TIMEOUT_SMALL 450 // Retry timeout for small network additional 30 seconds for authenticator delay +// Retry timeout for small network; additional 30 seconds for authenticator delay +#define SEC_PROT_RETRY_TIMEOUT_SMALL (SEC_PROT_SMALL_IMAX * SEC_PROT_TIMER_EXPIRATIONS + SEC_PROT_END_DELAY) #define SEC_PROT_LARGE_IMIN 60 // Retries done in 60 seconds #define SEC_PROT_LARGE_IMAX 240 // Largest value 240 seconds -#define SEC_PROT_RETRY_TIMEOUT_LARGE 750 // Retry timeout for large network additional 30 seconds for authenticator delay +// Retry timeout for large network; additional 30 seconds for authenticator delay +#define SEC_PROT_RETRY_TIMEOUT_LARGE (SEC_PROT_LARGE_IMAX * SEC_PROT_TIMER_EXPIRATIONS + SEC_PROT_END_DELAY) -#define SEC_PROT_TIMER_EXPIRATIONS 4 // Number of retries +// Timeout for retrying side of the protocol (runs when trickle not running) +#define SEC_PROT_RETRYING_PROTOCOL_TIMEOUT (5 * 60 * 10) // 5 minutes in ticks // Maximum number of simultaneous security negotiations #define MAX_SIMULTANEOUS_SECURITY_NEGOTIATIONS_TX_QUEUE_MIN 64 diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_llc.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_llc.h index da89a3495..9b8e55f38 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_llc.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_llc.h @@ -117,7 +117,7 @@ typedef void ws_asynch_ind(struct protocol_interface_info_entry *interface, cons typedef void ws_asynch_confirm(struct protocol_interface_info_entry *interface, uint8_t asynch_message); /** - * @brief ws_asynch_confirm ws asynch data confirmation to asynch message request + * @brief ws_neighbor_info_request neighbor info request * @param interface The interface pointer * @param mac_64 Neighbor 64-bit address * @param neighbor_buffer Buffer where neighbor infor is buffered @@ -128,15 +128,31 @@ typedef void ws_asynch_confirm(struct protocol_interface_info_entry *interface, */ typedef bool ws_neighbor_info_request(struct protocol_interface_info_entry *interface, const uint8_t *mac_64, struct llc_neighbour_req *neighbor_buffer, bool request_new); +/** + * @brief ws_eapol_relay_active_check check if eapol relay is active + * @param interface The interface pointer + * + * @return true eapol relay is active + * @return false eapol relay is not active + */ +typedef bool ws_eapol_relay_active_check(struct protocol_interface_info_entry *cur); + /** * @brief ws_llc_create ws LLC module create * @param interface Interface pointer * @param asynch_ind_cb Asynch indication + * @param asynch_cnf_cb Asynch confirm + * @param ws_neighbor_info_request_cb neighbor info request + * @param eapol_relay_active_cb check if eapol relay is active + * * @param ie_ext Information element list * * Function allocate and init LLC class and init it 2 supported 2 API: ws asynch and MPX user are internally registered. + * + * @return 0 on success + * @return < 0 on failure */ -int8_t ws_llc_create(struct protocol_interface_info_entry *interface, ws_asynch_ind *asynch_ind_cb, ws_asynch_confirm *asynch_cnf_cb, ws_neighbor_info_request *ws_neighbor_info_request_cb); +int8_t ws_llc_create(struct protocol_interface_info_entry *interface, ws_asynch_ind *asynch_ind_cb, ws_asynch_confirm *asynch_cnf_cb, ws_neighbor_info_request *ws_neighbor_info_request_cb, ws_eapol_relay_active_check *eapol_relay_active_cb); /** * @brief ws_llc_reset Reset ws LLC parametrs and clean messages diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.h index 8abfe1e97..79df03158 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.h @@ -295,7 +295,7 @@ void ws_pae_auth_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_ #define ws_pae_auth_timing_adjust(timing) #define ws_pae_auth_addresses_set(interface_ptr, local_port, remote_addr, remote_port) 1 #define ws_pae_auth_delete NULL -#define ws_pae_auth_cb_register(interface_ptr, hash_set, nw_key_insert, nw_key_index_set, nw_info_updated, ip_addr_get, congestion_get, nw_frame_cnt_read) {(void) hash_set;} +#define ws_pae_auth_cb_register(interface_ptr, hash_set, nw_key_insert, nw_key_index_set, nw_info_updated, ip_addr_get, congestion_get, nw_frame_cnt_read) #define ws_pae_auth_start(interface_ptr) #define ws_pae_auth_gtks_updated NULL #define ws_pae_auth_nw_key_index_update NULL diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.h index 40cd01fb0..ab31a7c75 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.h @@ -573,6 +573,22 @@ typedef void ws_pae_controller_nw_frame_counter_set(protocol_interface_info_entr */ typedef void ws_pae_controller_nw_frame_counter_read(protocol_interface_info_entry_t *interface_ptr, uint32_t *counter, uint8_t slot); +/** + * ws_pae_controller_nw_key_cb_register register network key control callbacks + * + * \param interface_ptr interface + * \param nw_key_set network key set callback + * \param nw_key_clear network key clear callback + * \param nw_send_key_index_set network send key index set callback + * \param nw_frame_counter_set network frame counter set callback + * \param nw_frame_counter_read network frame counter read callback + * + * \return < 0 failure + * \return >= 0 success + * + */ +int8_t ws_pae_controller_nw_key_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_nw_key_set *nw_key_set, ws_pae_controller_nw_key_clear *nw_key_clear, ws_pae_controller_nw_send_key_index_set *nw_send_key_index_set, ws_pae_controller_nw_frame_counter_set *nw_frame_counter_set, ws_pae_controller_nw_frame_counter_read *nw_frame_counter_read); + /** * ws_pae_controller_auth_completed authentication completed callback * @@ -596,12 +612,29 @@ typedef void ws_pae_controller_auth_completed(protocol_interface_info_entry_t *i typedef const uint8_t *ws_pae_controller_auth_next_target(protocol_interface_info_entry_t *interface_ptr, const uint8_t *previous_eui_64, uint16_t *pan_id); /** - * ws_pae_controller_pan_ver_increment PAN version increment callback + * ws_pae_controller_authentication_cb_register register supplicant authentication control callbacks * * \param interface_ptr interface + * \param completed authentication completed callback + * \param next_target authentication next target callback + * + * \return < 0 failure + * \return >= 0 success * */ -typedef void ws_pae_controller_pan_ver_increment(protocol_interface_info_entry_t *interface_ptr); +int8_t ws_pae_controller_authentication_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_auth_completed *completed, ws_pae_controller_auth_next_target *auth_next_target); + +/** + * ws_pae_controller_ip_addr_get gets IP addressing information + * + * \param interface_ptr interface + * \param address IP address + * + * \return < 0 failure + * \return >= 0 success + * + */ +typedef int8_t ws_pae_controller_ip_addr_get(protocol_interface_info_entry_t *interface_ptr, uint8_t *address); /** * ws_pae_controller_nw_info_updated network information is updated (read from memory) @@ -626,17 +659,10 @@ typedef void ws_pae_controller_nw_info_updated(protocol_interface_info_entry_t * typedef bool ws_pae_controller_congestion_get(protocol_interface_info_entry_t *interface_ptr, uint16_t active_supp); /** - * ws_pae_controller_cb_register register controller callbacks + * ws_pae_controller_information_cb_register register information callbacks * * \param interface_ptr interface - * \param completed authentication completed callback - * \param next_target authentication next target callback - * \param nw_key_set network key set callback - * \param nw_key_clear network key clear callback - * \param nw_send_key_index_set network send key index set callback - * \param nw_frame_counter_set network frame counter set callback - * \param nw_frame_counter_read network frame counter read callback - * \param pan_ver_increment PAN version increment callback + * \param ip_addr_get IP address get callback * \param nw_info_updated network information updated callback * \param congestion_get congestion get callback * @@ -644,31 +670,27 @@ typedef bool ws_pae_controller_congestion_get(protocol_interface_info_entry_t *i * \return >= 0 success * */ -int8_t ws_pae_controller_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_auth_completed *completed, ws_pae_controller_auth_next_target *auth_next_target, ws_pae_controller_nw_key_set *nw_key_set, ws_pae_controller_nw_key_clear *nw_key_clear, ws_pae_controller_nw_send_key_index_set *nw_send_key_index_set, ws_pae_controller_nw_frame_counter_set *nw_frame_counter_set, ws_pae_controller_nw_frame_counter_read *nw_frame_counter_read, ws_pae_controller_pan_ver_increment *pan_ver_increment, ws_pae_controller_nw_info_updated *nw_info_updated, ws_pae_controller_congestion_get *congestion_get); +int8_t ws_pae_controller_information_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_ip_addr_get *ip_addr_get, ws_pae_controller_nw_info_updated *nw_info_updated, ws_pae_controller_congestion_get *congestion_get); /** - * ws_pae_controller_ip_addr_get gets IP addressing information + * ws_pae_controller_pan_ver_increment PAN version increment callback * * \param interface_ptr interface - * \param address IP address - * - * \return < 0 failure - * \return >= 0 success * */ -typedef int8_t ws_pae_controller_ip_addr_get(protocol_interface_info_entry_t *interface_ptr, uint8_t *address); +typedef void ws_pae_controller_pan_ver_increment(protocol_interface_info_entry_t *interface_ptr); /** - * ws_pae_controller_auth_cb_register register authenticator callbacks + * ws_pae_controller_bbr_control_cb_register register PAN version control callbacks * * \param interface_ptr interface - * \param ip_addr_get IP address get callback + * \param pan_ver_increment PAN version increment callback * * \return < 0 failure * \return >= 0 success * */ -int8_t ws_pae_controller_auth_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_ip_addr_get *ip_addr_get); +int8_t ws_pae_controller_pan_version_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_pan_ver_increment *pan_ver_increment); /** * ws_pae_controller_fast_timer PAE controller fast timer call diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_key_storage.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_key_storage.h index 39e6df60e..7c170b633 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_key_storage.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_key_storage.h @@ -18,6 +18,8 @@ #ifndef WS_PAE_KEY_STORAGE_H_ #define WS_PAE_KEY_STORAGE_H_ +#ifdef HAVE_PAE_AUTH + /* * Port access entity key storage functions. * @@ -169,4 +171,22 @@ void ws_pae_key_storage_fast_timer(uint16_t ticks); */ uint16_t ws_pae_key_storage_storing_interval_get(void); +#else + +#define ws_pae_key_storage_memory_set(key_storages_number, key_storage_size, key_storages) +#define ws_pae_key_storage_settings_set(alloc_max_number, alloc_size, storing_interval) +#define ws_pae_key_storage_init() +#define ws_pae_key_storage_delete() +#define ws_pae_key_storage_store() +#define ws_pae_key_storage_read(restart_cnt) +#define ws_pae_key_storage_remove() +#define ws_pae_key_storage_supp_write(instance, pae_supp) +#define ws_pae_key_storage_supp_read(instance, eui_64, gtks, certs) +#define ws_pae_key_storage_supp_delete(instance, eui64) +#define ws_pae_key_storage_timer(seconds) +#define ws_pae_key_storage_fast_timer(ticks) +#define ws_pae_key_storage_storing_interval_get() 0 + +#endif + #endif /* WS_PAE_KEY_STORAGE_H_ */ diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_supp.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_supp.h index c991d6506..377c78ec7 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_supp.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_supp.h @@ -265,8 +265,8 @@ void ws_pae_supp_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_ #define ws_pae_supp_init(interface_ptr, certs, sec_timer_cfg, sec_prot_cfg) 1 #define ws_pae_supp_delete NULL #define ws_pae_supp_timing_adjust(timing) 1 -#define ws_pae_supp_cb_register(interface_ptr, completed, nw_key_insert, nw_key_index_set) -#define ws_pae_supp_nw_key_valid(interface_ptr) -1 +#define ws_pae_supp_cb_register(interface_ptr, completed, auth_next_target,nw_key_insert, nw_key_index_set, gtk_hash_ptr_get, nw_info_updated) +#define ws_pae_supp_nw_key_valid(interface_ptr, br_iid) -1 #define ws_pae_supp_fast_timer NULL #define ws_pae_supp_slow_timer NULL #define ws_pae_supp_authenticate(interface_ptr, dest_pan_id, dest_eui_64) PAE_SUPP_NOT_ENABLED @@ -276,6 +276,7 @@ void ws_pae_supp_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_ #define ws_pae_supp_nw_key_index_update NULL #define ws_pae_supp_gtks_set(interface_ptr, gtks) #define ws_pae_supp_eapol_target_remove(interface_ptr) +#define ws_pae_supp_nw_info_set NULL #endif diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/Include/protocol.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/Include/protocol.h index a3a845ffb..e2a71fee2 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/Include/protocol.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/Include/protocol.h @@ -91,12 +91,10 @@ typedef enum icmp_state { ER_SCAN = 2, ER_ADDRESS_REQ = 3, ER_BIND_COMP = 4, -#ifdef HAVE_RPL ER_RPL_MC = 5, ER_RPL_SCAN = 6, ER_RPL_UNICAST = 7, ER_DAO_TX = 8, -#endif ER_PANA_AUTH = 9, ER_PANA_AUTH_DONE = 10, ER_PANA_AUTH_ERROR = 11, @@ -104,9 +102,7 @@ typedef enum icmp_state { ER_MLE_LINK_REQ = 13, ER_MLE_LINK_SHORT_SYNCH = 14, ER_MLE_LINK_ADDRESS_SYNCH = 15, -#ifdef HAVE_RPL ER_ROUTER_SYNCH = 17, -#endif ER_PANA_PING = 18, ER_PARENT_SYNCH_LOST = 19, ER_MLE_SCAN = 20, diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_control.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_control.h index c1cd57882..ce8a1d166 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_control.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_control.h @@ -18,8 +18,6 @@ #ifndef RPL_CONTROL_H_ #define RPL_CONTROL_H_ -#ifdef HAVE_RPL - #include "ns_list.h" #include "ipv6_stack/ipv6_routing_table.h" @@ -85,6 +83,29 @@ typedef struct rpl_dodag_conf { uint16_t lifetime_unit; /* seconds */ } rpl_dodag_conf_t; +/* Internally used configuration parameters for a DODAG, obtained through DIO DODAG Configuration options + * + * This structure has all the fields that are in the configuration + * to allow forwarding new bits that are added in future specifications. + */ +typedef struct rpl_dodag_conf_int { + uint8_t options; /* Flags|A|PCS */ + uint8_t reserved; /* Reserved fields in options (byte 12)*/ + uint8_t dio_interval_min; /* log2 milliseconds */ + uint8_t dio_interval_doublings; + uint8_t dio_redundancy_constant; + uint8_t default_lifetime; /* lifetime units */ + uint16_t dag_max_rank_increase; + uint16_t min_hop_rank_increase; + uint16_t objective_code_point; + uint16_t lifetime_unit; /* seconds */ +} rpl_dodag_conf_int_t; + +/* Helpers to handle configuration option bits*/ +#define rpl_conf_options(security, path_control_size) ((security ? 1:0) << 4) | (path_control_size & 0x07) +#define rpl_conf_option_security(conf) (bool)((conf)->options & 0x08) +#define rpl_conf_option_path_control_size(conf) ((conf)->options & 0x07) + /* Descriptor for a route from a DIO Route Information option. * Used to hold the "master copy" in the DODAG structure - the table for the * current DODAG is used to populate routes in our system routing table, and to @@ -104,6 +125,8 @@ typedef struct rpl_dio_route { uint8_t prefix[]; /* Variable-length prefix */ } rpl_dio_route_t; +#ifdef HAVE_RPL + typedef NS_LIST_HEAD(rpl_dio_route_t, link) rpl_dio_route_list_t; /******************************* RPL internal API ****************************/ @@ -112,7 +135,7 @@ void *rpl_realloc(void *p, uint16_t old_size, uint16_t new_size); void rpl_free(void *p, uint16_t size); void rpl_control_transmit(struct rpl_domain *domain, struct protocol_interface_info_entry *cur, uint8_t code, struct buffer *buf, const uint8_t *dst); void rpl_control_transmit_multicast_dio(struct rpl_domain *domain, struct rpl_instance *instance, uint8_t instance_id, uint8_t dodag_version, uint16_t rank, uint8_t g_mop_prf, uint8_t dtsn, const uint8_t dodagid[16], const struct rpl_dodag_conf *conf); -void rpl_control_transmit_dio(struct rpl_domain *domain, struct protocol_interface_info_entry *cur, uint8_t instance_id, uint8_t dodag_version, uint16_t rank, uint8_t g_mop_prf, uint8_t dtsn, struct rpl_dodag *dodag, const uint8_t dodagid[16], const struct rpl_dodag_conf *conf, const uint8_t *dst); +void rpl_control_transmit_dio(struct rpl_domain *domain, struct protocol_interface_info_entry *cur, uint8_t instance_id, uint8_t dodag_version, uint16_t rank, uint8_t g_mop_prf, uint8_t dtsn, struct rpl_dodag *dodag, const uint8_t dodagid[16], const struct rpl_dodag_conf_int *conf, const uint8_t *dst); bool rpl_control_transmit_dao(struct rpl_domain *domain, struct protocol_interface_info_entry *cur, struct rpl_instance *instance, uint8_t instance_id, uint8_t dao_sequence, const uint8_t dodagid[16], const uint8_t *opts, uint16_t opts_size, const uint8_t *dst); void rpl_control_disable_ra_routes(struct rpl_domain *domain); void rpl_control_event(struct rpl_domain *domain, rpl_event_t event); @@ -207,7 +230,7 @@ struct rpl_instance *rpl_control_enumerate_instances(rpl_domain_t *domain, struc struct rpl_instance *rpl_control_lookup_instance(rpl_domain_t *domain, uint8_t instance_id, const uint8_t *dodagid); bool rpl_control_get_instance_dao_target_count(rpl_domain_t *domain, uint8_t instance_id, const uint8_t *dodagid, const uint8_t *prefix, uint16_t *target_count); bool rpl_control_read_dodag_info(const struct rpl_instance *instance, struct rpl_dodag_info_t *dodag_info); -const rpl_dodag_conf_t *rpl_control_get_dodag_config(const struct rpl_instance *instance); +const rpl_dodag_conf_int_t *rpl_control_get_dodag_config(const struct rpl_instance *instance); const uint8_t *rpl_control_preferred_parent_addr(const struct rpl_instance *instance, bool global); uint16_t rpl_control_current_rank(const struct rpl_instance *instance); uint8_t rpl_policy_mrhof_parent_set_size_get(const rpl_domain_t *domain); @@ -215,15 +238,39 @@ void rpl_control_instant_poison(struct protocol_interface_info_entry *cur, rpl_d #else /* HAVE_RPL */ +#define rpl_control_set_memory_limits(soft_limit, hard_limit) #define rpl_control_fast_timer(ticks) ((void) 0) #define rpl_control_slow_timer(seconds) ((void) 0) +#define rpl_control_transmit_dis(domain, cur, pred, instance_id, dodagid, version, dst) ((void) 0) +#define rpl_control_transmit_dio_trigger(cur, domain) ((void) 0) +#define rpl_control_parent_selection_trigger(domain) ((void) 0) +#define rpl_control_force_leaf(domain, leaf) ((void) 0) +#define rpl_control_poison(domain, poison_count) ((void) 0) +#define rpl_control_dao_timeout(domain, seconds) ((void) 0) +#define rpl_control_set_domain_on_interface(cur, domain, downstream) ((void) 0) #define rpl_control_remove_domain_from_interface(cur) ((void) 0) #define rpl_control_free_domain_instances_from_interface(cur) ((void) 0) +#define rpl_control_set_callback(domain, callback, prefix_learn_cb, new_parent_add, parent_dis, cb_handle) ((void) 0) +#define rpl_control_is_dodag_parent(interface, ll_addr) (false) +#define rpl_control_is_dodag_parent_candidate(interface, ll_addr, candidate_cmp_limiter) (false) +#define rpl_control_probe_parent_candidate(interface, ll_addr) (false) +#define rpl_control_neighbor_info_get(interface, ll_addr, global_address) (0xffff) +#define rpl_possible_better_candidate(interface, rpl_instance, ll_addr, candidate_rank, etx) (false) +#define rpl_control_parent_candidate_list_size(interface, parent_list) (0) +#define rpl_control_candidate_list_size(interface, rpl_instance) (0) +#define rpl_control_selected_parent_count(interface, rpl_instance) (0) +#define rpl_control_neighbor_delete(interface, ll_addr) ((void) 0) +#define rpl_control_find_worst_neighbor(interface, rpl_instance, ll_addr) (false) #define rpl_control_register_address(interface, addr) ((void) 0) #define rpl_control_address_register_done(interface, ll_addr, status) (false) +#define rpl_control_enumerate_instances(domain, instance) (NULL) +#define rpl_control_read_dodag_info(instance, dodag_info) (false) +#define rpl_control_get_dodag_config(instance) (NULL) +#define rpl_control_preferred_parent_addr(instance, global) (NULL) +#define rpl_control_current_rank(instance) (RPL_RANK_INFINITE) #define rpl_policy_mrhof_parent_set_size_get(domain) (0) -#define rpl_control_set_mrhof_parent_set_size(parent_set_size) #define rpl_control_instant_poison(cur, domain) ((void) 0) + #endif /* HAVE_RPL */ #endif /* RPL_CONTROL_H_ */ diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.h index b80e0e9f2..4b5943259 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.h @@ -26,7 +26,7 @@ void rpl_policy_force_tunnel_set(bool enable); bool rpl_policy_join_instance(rpl_domain_t *domain, uint8_t instance_id, const uint8_t *dodagid); bool rpl_policy_join_dodag(rpl_domain_t *domain, uint8_t g_mop_prf, uint8_t instance_id, const uint8_t *dodagid); -bool rpl_policy_join_config(rpl_domain_t *domain, const rpl_dodag_conf_t *conf, bool *leaf_only); +bool rpl_policy_join_config(rpl_domain_t *domain, const rpl_dodag_conf_int_t *conf, bool *leaf_only); bool rpl_policy_request_dao_acks(const rpl_domain_t *domain, uint8_t mop); uint16_t rpl_policy_initial_dao_ack_wait(const rpl_domain_t *domain, uint8_t mop); diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_structures.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_structures.h index 0adeaacbf..d43dea4a2 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_structures.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_structures.h @@ -81,7 +81,7 @@ struct rpl_dodag { uint32_t timestamp; /* How long since we heard a DIO */ uint8_t id[16]; /* Root identifier */ uint8_t g_mop_prf; /* Grounded, Mode, Preference */ - rpl_dodag_conf_t config; /* Configuration from DIO */ + rpl_dodag_conf_int_t config; /* Configuration from DIO */ uint8_t info_version; /* Version for g_mop_prf and config */ bool root: 1; /* We are the root of this DODAG */ bool was_root: 1; /* If we have ever been a root in this DODAG */ diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.h index 3a3cb183c..b15e65f43 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.h @@ -108,7 +108,7 @@ uint8_t rpl_dodag_get_version_number_as_root(const rpl_dodag_t *dodag); void rpl_dodag_set_version_number_as_root(rpl_dodag_t *dodag, uint8_t number); void rpl_dodag_set_leaf(rpl_dodag_t *dodag, bool leaf); bool rpl_dodag_am_leaf(const rpl_dodag_t *dodag); -const rpl_dodag_conf_t *rpl_dodag_get_config(const rpl_dodag_t *dodag); +const rpl_dodag_conf_int_t *rpl_dodag_get_config(const rpl_dodag_t *dodag); void rpl_dodag_inconsistency(rpl_dodag_t *dodag); void rpl_dodag_increment_dtsn(rpl_dodag_t *dodag); rpl_cmp_t rpl_dodag_pref_compare(const rpl_dodag_t *a, const rpl_dodag_t *b); @@ -138,7 +138,7 @@ rpl_neighbour_t *rpl_lookup_neighbour_by_ll_address(const rpl_instance_t *instan rpl_neighbour_t *rpl_lookup_last_candidate_from_list(const rpl_instance_t *instance); rpl_neighbour_t *rpl_create_neighbour(rpl_dodag_version_t *instance, const uint8_t *ll_addr, int8_t if_id, uint8_t g_mop_prf, uint8_t dtsn); void rpl_delete_neighbour(rpl_instance_t *instance, rpl_neighbour_t *neighbour); -bool rpl_dodag_update_config(rpl_dodag_t *dodag, const rpl_dodag_conf_t *conf, const uint8_t *src, bool *become_leaf); +bool rpl_dodag_update_config(rpl_dodag_t *dodag, const rpl_dodag_conf_int_t *conf, const uint8_t *src, bool *become_leaf); const uint8_t *rpl_neighbour_ll_address(const rpl_neighbour_t *neighbour); const uint8_t *rpl_neighbour_global_address(const rpl_neighbour_t *neighbour); void rpl_neighbour_update_global_address(rpl_neighbour_t *neighbour, const uint8_t *addr); diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.h index 83a01879c..cc04b141a 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.h @@ -26,7 +26,6 @@ */ #define EUI64_LEN 8 -#define SEC_TOTAL_TIMEOUT 30 * 60 * 10 // 30 minutes #define SEC_FINISHED_TIMEOUT 5 * 10 // 5 seconds #define FWH_NONCE_LENGTH 32 @@ -299,11 +298,12 @@ bool sec_prot_result_timeout_check(sec_prot_common_t *data); bool sec_prot_result_ok_check(sec_prot_common_t *data); /** - * sec_prot_default_timeout_set sets default timeout for protocol + * sec_prot_timeout_set sets timeout for protocol * * \param data common data + * \param ticks ticks * */ -void sec_prot_default_timeout_set(sec_prot_common_t *data); +void sec_prot_timeout_set(sec_prot_common_t *data, uint16_t ticks); #endif /* SEC_PROT_LIB_H_ */ diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/base/cfg_ws_full.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/base/cfg_ws_full.h new file mode 100644 index 000000000..798f3c88a --- /dev/null +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/base/cfg_ws_full.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2021, Pelion and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "cfg_ws_border_router.h" + +#define HAVE_PAE_SUPP diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/base/cfg_ws_host.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/base/cfg_ws_host.h index 49122b9da..aec86edcd 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/base/cfg_ws_host.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/base/cfg_ws_host.h @@ -18,9 +18,7 @@ #define HAVE_WS #define HAVE_WS_HOST #define HAVE_WS_VERSION_1_1 -#define HAVE_RPL #define HAVE_MPL #define HAVE_6LOWPAN_ND #define HAVE_IPV6_ND -#define HAVE_PAE_SUPP -#define HAVE_6LOWPAN_ROUTER \ No newline at end of file +#define HAVE_6LOWPAN_ROUTER diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/base/cfg_ws_router.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/base/cfg_ws_router.h index 78f353794..5e3656203 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/base/cfg_ws_router.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/base/cfg_ws_router.h @@ -17,5 +17,6 @@ #include "cfg_ws_host.h" +#define HAVE_RPL #define HAVE_WS_ROUTER #define HAVE_EAPOL_RELAY diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_generic.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_generic.h index c7a27d4c2..49ccb5ee9 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_generic.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_generic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, 2016-2019, Pelion and affiliates. + * Copyright (c) 2014, 2016-2021, Pelion and affiliates. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -20,7 +20,7 @@ #include "base/cfg_lowpan_border_router.h" #include "base/cfg_local_socket.h" #include "base/cfg_rf_tunnel.h" -#include "base/cfg_ws_border_router.h" +#include "base/cfg_ws_full.h" #define FEA_TRACE_SUPPORT #define EXTRA_CONSISTENCY_CHECKS diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_ws_full.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_ws_full.h new file mode 100644 index 000000000..798f3c88a --- /dev/null +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_ws_full.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2021, Pelion and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "cfg_ws_border_router.h" + +#define HAVE_PAE_SUPP diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_ws_host.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_ws_host.h index 74b3113c4..debfeb2c8 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_ws_host.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_ws_host.h @@ -20,4 +20,5 @@ #define FEA_TRACE_SUPPORT #define EXTRA_CONSISTENCY_CHECKS +#define HAVE_PAE_SUPP diff --git a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_ws_router.h b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_ws_router.h index a4cf95250..da740e5c6 100644 --- a/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_ws_router.h +++ b/cores/arduino/mbed/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_ws_router.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Pelion and affiliates. + * Copyright (c) 2019-2021, Pelion and affiliates. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -20,4 +20,5 @@ #define FEA_TRACE_SUPPORT #define EXTRA_CONSISTENCY_CHECKS +#define HAVE_PAE_SUPP diff --git a/cores/arduino/mbed/drivers/include/drivers/InterruptIn.h b/cores/arduino/mbed/drivers/include/drivers/InterruptIn.h index ff8b14675..1b3a9eadd 100644 --- a/cores/arduino/mbed/drivers/include/drivers/InterruptIn.h +++ b/cores/arduino/mbed/drivers/include/drivers/InterruptIn.h @@ -129,7 +129,7 @@ class InterruptIn : private NonCopyable { */ void disable_irq(); - static void _irq_handler(uint32_t id, gpio_irq_event event); + static void _irq_handler(uintptr_t context, gpio_irq_event event); #if !defined(DOXYGEN_ONLY) protected: gpio_t gpio; diff --git a/cores/arduino/mbed/hal/include/hal/gpio_irq_api.h b/cores/arduino/mbed/hal/include/hal/gpio_irq_api.h index e08b049c5..cb9a40d5c 100644 --- a/cores/arduino/mbed/hal/include/hal/gpio_irq_api.h +++ b/cores/arduino/mbed/hal/include/hal/gpio_irq_api.h @@ -41,7 +41,7 @@ typedef enum { */ typedef struct gpio_irq_s gpio_irq_t; -typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event); +typedef void (*gpio_irq_handler)(uintptr_t context, gpio_irq_event event); /** * \defgroup hal_gpioirq GPIO IRQ HAL functions @@ -75,10 +75,10 @@ typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event); * @param obj The GPIO object to initialize * @param pin The GPIO pin name * @param handler The handler to be attached to GPIO IRQ - * @param id The object ID (id != 0, 0 is reserved) + * @param context The context to be passed back to the handler (context != 0, 0 is reserved) * @return -1 if pin is NC, 0 otherwise */ -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id); +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context); /** Release the GPIO IRQ PIN * diff --git a/cores/arduino/mbed/platform/cxxsupport/mstd_span b/cores/arduino/mbed/platform/cxxsupport/mstd_span index 184f14ee3..ef0873dd2 100644 --- a/cores/arduino/mbed/platform/cxxsupport/mstd_span +++ b/cores/arduino/mbed/platform/cxxsupport/mstd_span @@ -139,7 +139,9 @@ class span { public: using element_type = ElementType; using value_type = typename mstd::remove_cv_t; - using index_type = size_t; + using size_type = size_t; + // Typedef because IAR does not allow [[deprecated]] with using + [[deprecated("Use size_type instead.")]] typedef size_t index_type; using difference_type = ptrdiff_t; using pointer = element_type *; using const_pointer = const element_type *; @@ -148,7 +150,7 @@ public: using iterator = pointer; using reverse_iterator = std::reverse_iterator; - static constexpr index_type extent = Extent; + static constexpr size_type extent = Extent; // Constructors, copy and assignment template>(*)[], ElementType(*)[]>::value, int> = 0> - constexpr span(It ptr, index_type count) : + constexpr span(It ptr, size_type count) : _storage(ptr, count) { MBED_ASSERT(extent == dynamic_extent || extent == count); @@ -251,32 +253,32 @@ public: return {data() + Offset, Count != dynamic_extent ? Count : size() - Offset}; } - constexpr span first(index_type count) const + constexpr span first(size_type count) const { MBED_ASSERT(count <= size()); return {data(), count}; } - constexpr span last(index_type count) const + constexpr span last(size_type count) const { MBED_ASSERT(count <= size()); return {data() + (size() - count), count}; } constexpr span - subspan(index_type offset, index_type count = dynamic_extent) const + subspan(size_type offset, size_type count = dynamic_extent) const { MBED_ASSERT(offset <= size() && (count == dynamic_extent || count <= size() - offset)); return {data() + offset, count == dynamic_extent ? size() - offset : count }; } // Observers - constexpr index_type size() const noexcept + constexpr size_type size() const noexcept { return _storage._size; } - constexpr index_type size_bytes() const noexcept + constexpr size_type size_bytes() const noexcept { return size() * sizeof(element_type); } @@ -287,7 +289,7 @@ public: } // Element access - constexpr reference operator[](index_type idx) const + constexpr reference operator[](size_type idx) const { MBED_ASSERT(idx < size()); return *(data() + idx); @@ -336,7 +338,7 @@ private: }; template -constexpr span::index_type span::extent; +constexpr span::size_type span::extent; #if __cplusplus >= 201703L || __cpp_deduction_guides >= 201703L // Deduction guides diff --git a/cores/arduino/mbed/platform/include/platform/mbed_assert.h b/cores/arduino/mbed/platform/include/platform/mbed_assert.h index c5ec5702b..34ee1587d 100644 --- a/cores/arduino/mbed/platform/include/platform/mbed_assert.h +++ b/cores/arduino/mbed/platform/include/platform/mbed_assert.h @@ -66,7 +66,7 @@ MBED_NORETURN void mbed_assert_internal(const char *expr, const char *file, int #define MBED_ASSERT(expr) \ do { \ if (!(expr)) { \ - mbed_assert_internal(#expr, __FILE__, __LINE__); \ + mbed_assert_internal(#expr, MBED_FILENAME, __LINE__); \ } \ } while (0) #endif diff --git a/cores/arduino/mbed/platform/include/platform/mbed_toolchain.h b/cores/arduino/mbed/platform/include/platform/mbed_toolchain.h index 2fa91d69e..f9c016ab8 100644 --- a/cores/arduino/mbed/platform/include/platform/mbed_toolchain.h +++ b/cores/arduino/mbed/platform/include/platform/mbed_toolchain.h @@ -33,6 +33,11 @@ #endif #endif +/* Fix strrchr() not declared for IAR, used in MBED_FILENAME */ +#if defined(__ICCARM__) +#include +#endif + // Warning for unsupported compilers #if !defined(__GNUC__) /* GCC */ \ && !defined(__clang__) /* LLVM/Clang */ \ diff --git a/cores/arduino/mbed/platform/include/platform/mbed_version.h b/cores/arduino/mbed/platform/include/platform/mbed_version.h index acb21d367..55e0c9494 100644 --- a/cores/arduino/mbed/platform/include/platform/mbed_version.h +++ b/cores/arduino/mbed/platform/include/platform/mbed_version.h @@ -38,14 +38,14 @@ * * @note 99 is default value for development version (master branch) */ -#define MBED_MINOR_VERSION 15 +#define MBED_MINOR_VERSION 16 /** MBED_PATCH_VERSION * Mbed OS patch version * * @note 99 is default value for development version (master branch) */ -#define MBED_PATCH_VERSION 1 +#define MBED_PATCH_VERSION 0 #define MBED_ENCODE_VERSION(major, minor, patch) ((major)*10000 + (minor)*100 + (patch)) diff --git a/cores/arduino/mbed/storage/filesystem/littlefs/include/littlefs/LittleFileSystem.h b/cores/arduino/mbed/storage/filesystem/littlefs/include/littlefs/LittleFileSystem.h index c1e3a3c29..0051f18da 100644 --- a/cores/arduino/mbed/storage/filesystem/littlefs/include/littlefs/LittleFileSystem.h +++ b/cores/arduino/mbed/storage/filesystem/littlefs/include/littlefs/LittleFileSystem.h @@ -65,6 +65,7 @@ class LittleFileSystem : public mbed::FileSystem { virtual ~LittleFileSystem(); +#if !defined(TARGET_PORTENTA_H7_M7) || !defined(MCUBOOT_BOOTLOADER_BUILD) /** Format a block device with the LittleFileSystem. * * The block device to format should be mounted when this function is called. @@ -94,6 +95,7 @@ class LittleFileSystem : public mbed::FileSystem { lfs_size_t block_size = MBED_LFS_BLOCK_SIZE, lfs_size_t lookahead = MBED_LFS_LOOKAHEAD); +#endif /** Mount a file system to a block device. * * @param bd Block device to mount to. @@ -107,6 +109,7 @@ class LittleFileSystem : public mbed::FileSystem { */ virtual int unmount(); +#if !defined(TARGET_PORTENTA_H7_M7) || !defined(MCUBOOT_BOOTLOADER_BUILD) /** Reformat a file system. Results in an empty and mounted file system. * * @param bd @@ -118,6 +121,7 @@ class LittleFileSystem : public mbed::FileSystem { * @return 0 on success, negative error code on failure */ virtual int reformat(mbed::BlockDevice *bd); +#endif /** Remove a file from the file system. * @@ -126,6 +130,7 @@ class LittleFileSystem : public mbed::FileSystem { */ virtual int remove(const char *path); +#if !defined(TARGET_PORTENTA_H7_M7) || !defined(MCUBOOT_BOOTLOADER_BUILD) /** Rename a file in the file system. * * @param path The name of the file to rename. @@ -133,6 +138,7 @@ class LittleFileSystem : public mbed::FileSystem { * @return 0 on success, negative error code on failure */ virtual int rename(const char *path, const char *newpath); +#endif /** Store information about the file in a stat structure * diff --git a/cores/arduino/mbed/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/config/sdk_config.h b/cores/arduino/mbed/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/config/sdk_config.h index b1112d715..dea0276dd 100644 --- a/cores/arduino/mbed/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/config/sdk_config.h +++ b/cores/arduino/mbed/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/config/sdk_config.h @@ -4487,6 +4487,18 @@ #define NRFX_WDT_CONFIG_LOG_LEVEL 3 #endif + +// NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver. +//========================================================== + +// <0=> Include WDT IRQ handling +// <1=> Remove WDT IRQ handling + +#ifndef NRFX_WDT_CONFIG_NO_IRQ +#define NRFX_WDT_CONFIG_NO_IRQ 1 +#endif + + // NRFX_WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. // <0=> Default diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_feather_rp2040.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_feather_rp2040.h new file mode 100644 index 000000000..2da8e7009 --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_feather_rp2040.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_ADAFRUIT_FEATHER_RP2040_H +#define _BOARDS_ADAFRUIT_FEATHER_RP2040_H + +// For board detection +#define ADAFRUIT_FEATHER_RP2040 + +// On some samples, the xosc can take longer to stabilize than is usual +#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER +#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 64 +#endif + +//------------- UART -------------// +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +//------------- LED -------------// +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 13 +#endif + +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 16 +#endif + +//------------- I2C -------------// +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 1 +#endif + +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 2 +#endif + +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 3 +#endif + +//------------- SPI -------------// +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif + +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif + +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 20 +#endif + +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif + +//------------- FLASH -------------// + +// Use slower generic flash access +#define PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 4 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_itsybitsy_rp2040.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_itsybitsy_rp2040.h new file mode 100644 index 000000000..f9d27e919 --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_itsybitsy_rp2040.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_ADAFRUIT_ITSYBITSY_RP2040_H +#define _BOARDS_ADAFRUIT_ITSYBITSY_RP2040_H + +// For board detection +#define ADAFRUIT_ITSYBITSY_RP2040 + +// On some samples, the xosc can take longer to stabilize than is usual +#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER +#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 64 +#endif + +//------------- UART -------------// +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +//------------- LED -------------// +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 11 +#endif + +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 17 +#endif + +#ifndef PICO_DEFAULT_WS2812_POWER_PIN +#define PICO_DEFAULT_WS2812_POWER_PIN 16 +#endif + +//------------- I2C -------------// +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif + +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 2 +#endif + +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 3 +#endif + +//------------- SPI -------------// +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif + +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif + +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 20 +#endif + +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif + +//------------- FLASH -------------// + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_qtpy_rp2040.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_qtpy_rp2040.h new file mode 100644 index 000000000..24184c27f --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_qtpy_rp2040.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_ADAFRUIT_QTPY_RP2040_H +#define _BOARDS_ADAFRUIT_QTPY_RP2040_H + +// For board detection +#define ADAFRUIT_QTPY_RP2040 + +// On some samples, the xosc can take longer to stabilize than is usual +#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER +#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 64 +#endif + +//------------- UART -------------// +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 1 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 20 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 5 +#endif + +//------------- LED -------------// +// No normal LED +// #define PICO_DEFAULT_LED_PIN 13 + +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 12 +#endif + +#ifndef PICO_DEFAULT_WS2812_POWER_PIN +#define PICO_DEFAULT_WS2812_POWER_PIN 11 +#endif + +//------------- I2C -------------// +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif + +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 24 +#endif + +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 25 +#endif + +//------------- SPI -------------// +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif + +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 3 +#endif + +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 4 +#endif + +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 6 +#endif + +//------------- FLASH -------------// + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_trinkey_qt2040.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_trinkey_qt2040.h new file mode 100644 index 000000000..f9b49df74 --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/adafruit_trinkey_qt2040.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_ADAFRUIT_TRINKEY_QT2040_H +#define _BOARDS_ADAFRUIT_TRINKEY_QT2040_H + +// For board detection +#define ADAFRUIT_TRINKEY_QT2040 + +// On some samples, the xosc can take longer to stabilize than is usual +#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER +#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 64 +#endif + +//------------- UART -------------// +// no PICO_DEFAULT_UART +// no PICO_DEFAULT_UART_TX_PIN +// no PICO_DEFAULT_UART_RX_PIN + +//------------- LED -------------// +// No normal LED +// #define PICO_DEFAULT_LED_PIN 13 + +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 27 +#endif + +//------------- I2C -------------// +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif + +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 16 +#endif + +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 17 +#endif + +//------------- SPI -------------// +// no PICO_DEFAULT_SPI +// no PICO_DEFAULT_SPI_SCK_PIN +// no PICO_DEFAULT_SPI_TX_PIN +// no PICO_DEFAULT_SPI_RX_PIN +// no PICO_DEFAULT_SPI_CSN_PIN + +//------------- FLASH -------------// + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/arduino_nano_rp2040_connect.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/arduino_nano_rp2040_connect.h new file mode 100644 index 000000000..39c6564fb --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/arduino_nano_rp2040_connect.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_ARDUINO_NANO_RP2040_CONNECT_H +#define _BOARDS_ARDUINO_NANO_RP2040_CONNECT_H + +// For board detection +#define ARDUINO_NANO_RP2040_CONNECT + +//------------- UART -------------// +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +//------------- LED -------------// +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 6 +#endif +// no PICO_DEFAULT_WS2812_PIN + +//------------- I2C -------------// +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif + +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 12 +#endif + +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 13 +#endif + +//------------- SPI -------------// +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif + +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 7 +#endif + +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 4 +#endif + +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 6 +#endif + +//------------- FLASH -------------// + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/melopero_shake_rp2040.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/melopero_shake_rp2040.h new file mode 100644 index 000000000..d07ca6123 --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/melopero_shake_rp2040.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_MELOPERO_SHAKE_RP2040_H +#define _BOARDS_MELOPERO_SHAKE_RP2040_H + +// For board detection +#define MELOPERO_SHAKE_RP2040 + +//------------- UART -------------// +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 1 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 8 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 9 +#endif + +//------------- LED -------------// +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 13 +#endif + +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 16 +#endif + +//------------- I2C -------------// +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 1 +#endif + +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 2 +#endif + +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 3 +#endif + +//------------- SPI -------------// +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif + +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif + +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 20 +#endif + +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif + +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 1 +#endif + +//------------- FLASH -------------// + + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pico.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pico.h index c1ab7819a..9e7f53752 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pico.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pico.h @@ -14,21 +14,57 @@ #ifndef _BOARDS_PICO_H #define _BOARDS_PICO_H +// For board detection +#define RASPBERRYPI_PICO + +// --- UART --- #ifndef PICO_DEFAULT_UART #define PICO_DEFAULT_UART 0 #endif - #ifndef PICO_DEFAULT_UART_TX_PIN #define PICO_DEFAULT_UART_TX_PIN 0 #endif - #ifndef PICO_DEFAULT_UART_RX_PIN #define PICO_DEFAULT_UART_RX_PIN 1 #endif +// --- LED --- #ifndef PICO_DEFAULT_LED_PIN #define PICO_DEFAULT_LED_PIN 25 #endif +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 #ifndef PICO_FLASH_SPI_CLKDIV #define PICO_FLASH_SPI_CLKDIV 2 @@ -41,12 +77,8 @@ // Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) #define PICO_SMPS_MODE_PIN 23 -#ifndef PICO_FLOAT_SUPPORT_ROM_V1 -#define PICO_FLOAT_SUPPORT_ROM_V1 1 -#endif - -#ifndef PICO_DOUBLE_SUPPORT_ROM_V1 -#define PICO_DOUBLE_SUPPORT_ROM_V1 1 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 1 #endif #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_interstate75.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_interstate75.h new file mode 100644 index 000000000..e2621b0bf --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_interstate75.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_PIMORONI_INTERSTATE75_H +#define _BOARDS_PIMORONI_INTERSTATE75_H + +// For board detection +#define PIMORONI_INTERSTATE75 + +// --- BOARD SPECIFIC --- +#ifndef INTERSTATE75_R0_PIN +#define INTERSTATE75_R0_PIN 0 +#endif + +#ifndef INTERSTATE75_G0_PIN +#define INTERSTATE75_G0_PIN 1 +#endif + +#ifndef INTERSTATE75_B0_PIN +#define INTERSTATE75_B0_PIN 2 +#endif + +#ifndef INTERSTATE75_R1_PIN +#define INTERSTATE75_R1_PIN 3 +#endif + +#ifndef INTERSTATE75_G1_PIN +#define INTERSTATE75_G1_PIN 4 +#endif + +#ifndef INTERSTATE75_B1_PIN +#define INTERSTATE75_B1_PIN 5 +#endif + +#ifndef INTERSTATE75_ROW_A_PIN +#define INTERSTATE75_ROW_A_PIN 6 +#endif + +#ifndef INTERSTATE75_ROW_B_PIN +#define INTERSTATE75_ROW_B_PIN 7 +#endif + +#ifndef INTERSTATE75_ROW_C_PIN +#define INTERSTATE75_ROW_C_PIN 8 +#endif + +#ifndef INTERSTATE75_ROW_D_PIN +#define INTERSTATE75_ROW_D_PIN 9 +#endif + +#ifndef INTERSTATE75_ROW_E_PIN +#define INTERSTATE75_ROW_E_PIN 10 +#endif + +#ifndef INTERSTATE75_CLK_PIN +#define INTERSTATE75_CLK_PIN 11 +#endif + +#ifndef INTERSTATE75_LAT_PIN +#define INTERSTATE75_LAT_PIN 12 +#endif + +#ifndef INTERSTATE75_OE_PIN +#define INTERSTATE75_OE_PIN 13 +#endif + +#ifndef INTERSTATE75_SW_A_PIN +#define INTERSTATE75_SW_A_PIN 14 +#endif + +#ifndef INTERSTATE75_LED_R_PIN +#define INTERSTATE75_LED_R_PIN 16 +#endif + +#ifndef INTERSTATE75_LED_G_PIN +#define INTERSTATE75_LED_G_PIN 17 +#endif + +#ifndef INTERSTATE75_LED_B_PIN +#define INTERSTATE75_LED_B_PIN 18 +#endif + +#ifndef INTERSTATE75_I2C +#define INTERSTATE75_I2C 0 +#endif + +#ifndef INTERSTATE75_INT_PIN +#define INTERSTATE75_INT_PIN 19 +#endif + +#ifndef INTERSTATE75_SDA_PIN +#define INTERSTATE75_SDA_PIN 20 +#endif + +#ifndef INTERSTATE75_SCL_PIN +#define INTERSTATE75_SCL_PIN 21 +#endif + +#ifndef INTERSTATE75_USER_SW_PIN +#define INTERSTATE75_USER_SW_PIN 23 +#endif + +#ifndef INTERSTATE75_A0_PIN +#define INTERSTATE75_A0_PIN 26 +#endif + +#ifndef INTERSTATE75_A1_PIN +#define INTERSTATE75_A1_PIN 27 +#endif + +#ifndef INTERSTATE75_A2_PIN +#define INTERSTATE75_A2_PIN 28 +#endif + +#ifndef INTERSTATE75_NUM_ADC_PINS +#define INTERSTATE75_NUM_ADC_PINS 3 +#endif + +#ifndef INTERSTATE75_CURRENT_SENSE_PIN +#define INTERSTATE75_CURRENT_SENSE_PIN 29 +#endif + +// --- UART --- +// no PICO_DEFAULT_UART +// no PICO_DEFAULT_UART_TX_PIN +// no PICO_DEFAULT_UART_RX_PIN + +// --- LED --- +// Included so basic examples will work, and set it to the green LED +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN INTERSTATE75_LED_G_PIN +#endif +// no PICO_DEFAULT_WS2812_PIN + +#ifndef PICO_DEFAULT_LED_PIN_INVERTED +#define PICO_DEFAULT_LED_PIN_INVERTED 1 +#endif + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C INTERSTATE75_I2C +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN INTERSTATE75_SDA_PIN +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN INTERSTATE75_SCL_PIN +#endif + +// --- SPI --- +// no PICO_DEFAULT_SPI +// no PICO_DEFAULT_SPI_SCK_PIN +// no PICO_DEFAULT_SPI_TX_PIN +// no PICO_DEFAULT_SPI_RX_PIN +// no PICO_DEFAULT_SPI_CSN_PIN + +// --- FLASH --- +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_keybow2040.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_keybow2040.h new file mode 100644 index 000000000..43772e840 --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_keybow2040.h @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_PIMORONI_KEYBOW2040_H +#define _BOARDS_PIMORONI_KEYBOW2040_H + +// For board detection +#define PIMORONI_KEYBOW2040 + +// --- BOARD SPECIFIC --- +#ifndef KEYBOW2040_I2C_SDA_PIN +#define KEYBOW2040_I2C_SDA_PIN 4 +#endif + +#ifndef KEYBOW2040_I2C_SCL_PIN +#define KEYBOW2040_I2C_SCL_PIN 5 +#endif + +#ifndef KEYBOW2040_I2C_INT_PIN +#define KEYBOW2040_I2C_INT_PIN 3 +#endif + +#ifndef KEYBOW2040_USER_SW_PIN +#define KEYBOW2040_USER_SW_PIN 23 +#endif + +#ifndef KEYBOW2040_SW0_PIN +#define KEYBOW2040_SW0_PIN 21 +#endif + +#ifndef KEYBOW2040_SW1_PIN +#define KEYBOW2040_SW1_PIN 20 +#endif + +#ifndef KEYBOW2040_SW2_PIN +#define KEYBOW2040_SW2_PIN 19 +#endif + +#ifndef KEYBOW2040_SW3_PIN +#define KEYBOW2040_SW3_PIN 18 +#endif + +#ifndef KEYBOW2040_SW4_PIN +#define KEYBOW2040_SW4_PIN 17 +#endif + +#ifndef KEYBOW2040_SW5_PIN +#define KEYBOW2040_SW5_PIN 16 +#endif + +#ifndef KEYBOW2040_SW6_PIN +#define KEYBOW2040_SW6_PIN 15 +#endif + +#ifndef KEYBOW2040_SW7_PIN +#define KEYBOW2040_SW7_PIN 14 +#endif + +#ifndef KEYBOW2040_SW8_PIN +#define KEYBOW2040_SW8_PIN 13 +#endif + +#ifndef KEYBOW2040_SW9_PIN +#define KEYBOW2040_SW9_PIN 12 +#endif + +#ifndef KEYBOW2040_SW10_PIN +#define KEYBOW2040_SW10_PIN 11 +#endif + +#ifndef KEYBOW2040_SW11_PIN +#define KEYBOW2040_SW11_PIN 10 +#endif + +#ifndef KEYBOW2040_SW12_PIN +#define KEYBOW2040_SW12_PIN 9 +#endif + +#ifndef KEYBOW2040_SW13_PIN +#define KEYBOW2040_SW13_PIN 8 +#endif + +#ifndef KEYBOW2040_SW14_PIN +#define KEYBOW2040_SW14_PIN 7 +#endif + +#ifndef KEYBOW2040_SW15_PIN +#define KEYBOW2040_SW15_PIN 6 +#endif + +#ifndef KEYBOW2040_NUM_SWITCHES_PINS +#define KEYBOW2040_NUM_SWITCHES_PINS 16 +#endif + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +// no PICO_DEFAULT_LED_PIN +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN KEYBOW2040_I2C_SDA_PIN +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN KEYBOW2040_I2C_SCL_PIN +#endif + +// --- SPI --- +// no PICO_DEFAULT_SPI +// no PICO_DEFAULT_SPI_SCK_PIN +// no PICO_DEFAULT_SPI_TX_PIN +// no PICO_DEFAULT_SPI_RX_PIN +// no PICO_DEFAULT_SPI_CSN_PIN + +// --- FLASH --- +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_pga2040.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_pga2040.h new file mode 100644 index 000000000..980f16800 --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_pga2040.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_PIMORONI_PGA2040_H +#define _BOARDS_PIMORONI_PGA2040_H + +// For board detection +#define PIMORONI_PGA2040 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +// no PICO_DEFAULT_LED_PIN +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- FLASH --- +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_picolipo_16mb.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_picolipo_16mb.h new file mode 100644 index 000000000..338977b44 --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_picolipo_16mb.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_PIMORONI_PICOLIPO_16MB_H +#define _BOARDS_PIMORONI_PICOLIPO_16MB_H + +// For board detection +#define PIMORONI_PICOLIPO_16MB + +// --- BOARD SPECIFIC --- +#ifndef PICOLIPO_USER_SW_PIN +#define PICOLIPO_USER_SW_PIN 23 +#endif + +#ifndef PICOLIPO_VBUS_DETECT_PIN +#define PICOLIPO_VBUS_DETECT_PIN 24 +#endif + +#ifndef PICOLIPO_BAT_SENSE_PIN +#define PICOLIPO_BAT_SENSE_PIN 29 +#endif + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- FLASH --- +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_picolipo_4mb.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_picolipo_4mb.h new file mode 100644 index 000000000..871ed8368 --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_picolipo_4mb.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_PIMORONI_PICOLIPO_4MB_H +#define _BOARDS_PIMORONI_PICOLIPO_4MB_H + +// For board detection +#define PIMORONI_PICOLIPO_4MB + +// --- BOARD SPECIFIC --- +#ifndef PICOLIPO_USER_SW_PIN +#define PICOLIPO_USER_SW_PIN 23 +#endif + +#ifndef PICOLIPO_VBUS_DETECT_PIN +#define PICOLIPO_VBUS_DETECT_PIN 24 +#endif + +#ifndef PICOLIPO_BAT_SENSE_PIN +#define PICOLIPO_BAT_SENSE_PIN 29 +#endif + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- FLASH --- +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_picosystem.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_picosystem.h new file mode 100644 index 000000000..1e7c80e82 --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_picosystem.h @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_PIMORONI_PICOSYSTEM_H +#define _BOARDS_PIMORONI_PICOSYSTEM_H + +// For board detection +#define PIMORONI_PICOSYSTEM + +// --- BOARD SPECIFIC --- +#ifndef PICOSYSTEM_VBUS_DETECT_PIN +#define PICOSYSTEM_VBUS_DETECT_PIN 2 +#endif + +#ifndef PICOSYSTEM_LCD_SPI +#define PICOSYSTEM_LCD_SPI 0 +#endif + +#ifndef PICOSYSTEM_LCD_RESET_PIN +#define PICOSYSTEM_LCD_RESET_PIN 4 +#endif + +#ifndef PICOSYSTEM_LCD_CSN_PIN +#define PICOSYSTEM_LCD_CSN_PIN 5 +#endif + +#ifndef PICOSYSTEM_LCD_SCLK_PIN +#define PICOSYSTEM_LCD_SCLK_PIN 6 +#endif + +#ifndef PICOSYSTEM_LCD_MOSI_PIN +#define PICOSYSTEM_LCD_MOSI_PIN 7 +#endif + +#ifndef PICOSYSTEM_LCD_VSYNC_PIN +#define PICOSYSTEM_LCD_VSYNC_PIN 8 +#endif + +#ifndef PICOSYSTEM_LCD_DC_PIN +#define PICOSYSTEM_LCD_DC_PIN 9 +#endif + +#ifndef PICOSYSTEM_AUDIO_PIN +#define PICOSYSTEM_AUDIO_PIN 11 +#endif + +#ifndef PICOSYSTEM_BACKLIGHT_PIN +#define PICOSYSTEM_BACKLIGHT_PIN 12 +#endif + +#ifndef PICOSYSTEM_LED_G_PIN +#define PICOSYSTEM_LED_G_PIN 13 +#endif + +#ifndef PICOSYSTEM_LED_R_PIN +#define PICOSYSTEM_LED_R_PIN 14 +#endif + +#ifndef PICOSYSTEM_LED_B_PIN +#define PICOSYSTEM_LED_B_PIN 15 +#endif + +#ifndef PICOSYSTEM_SW_Y_PIN +#define PICOSYSTEM_SW_Y_PIN 16 +#endif + +#ifndef PICOSYSTEM_SW_X_PIN +#define PICOSYSTEM_SW_X_PIN 17 +#endif + +#ifndef PICOSYSTEM_SW_A_PIN +#define PICOSYSTEM_SW_A_PIN 18 +#endif + +#ifndef PICOSYSTEM_SW_B_PIN +#define PICOSYSTEM_SW_B_PIN 19 +#endif + +#ifndef PICOSYSTEM_SW_DOWN_PIN +#define PICOSYSTEM_SW_DOWN_PIN 20 +#endif + +#ifndef PICOSYSTEM_SW_RIGHT_PIN +#define PICOSYSTEM_SW_RIGHT_PIN 21 +#endif + +#ifndef PICOSYSTEM_SW_LEFT_PIN +#define PICOSYSTEM_SW_LEFT_PIN 22 +#endif + +#ifndef PICOSYSTEM_SW_UP_PIN +#define PICOSYSTEM_SW_UP_PIN 23 +#endif + +#ifndef PICOSYSTEM_CHARGE_STAT_PIN +#define PICOSYSTEM_CHARGE_STAT_PIN 24 +#endif + +#ifndef PICOSYSTEM_BAT_SENSE_PIN +#define PICOSYSTEM_BAT_SENSE_PIN 26 +#endif + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +// Included so basic examples will work, and set it to the green LED +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN PICOSYSTEM_LED_G_PIN +#endif +// no PICO_DEFAULT_WS2812_PIN + +#ifndef PICO_DEFAULT_LED_PIN_INVERTED +#define PICO_DEFAULT_LED_PIN_INVERTED 1 +#endif + +// --- I2C --- +//no PICO_DEFAULT_I2C +//no PICO_DEFAULT_I2C_SDA_PIN +//no PICO_DEFAULT_I2C_SCL_PIN + +// --- SPI --- +// no PICO_DEFAULT_SPI +// no PICO_DEFAULT_SPI_SCK_PIN +// no PICO_DEFAULT_SPI_TX_PIN +// no PICO_DEFAULT_SPI_RX_PIN +// no PICO_DEFAULT_SPI_CSN_PIN + +// --- FLASH --- +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_plasma2040.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_plasma2040.h new file mode 100644 index 000000000..226aaf538 --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_plasma2040.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_PIMORONI_PLASMA2040_H +#define _BOARDS_PIMORONI_PLASMA2040_H + +// For board detection +#define PIMORONI_PLASMA2040 + +// --- BOARD SPECIFIC --- +#ifndef PLASMA2040_SW_A_PIN +#define PLASMA2040_SW_A_PIN 12 +#endif + +#ifndef PLASMA2040_SW_B_PIN +#define PLASMA2040_SW_B_PIN 13 +#endif + +#ifndef PLASMA2040_CLK_PIN +#define PLASMA2040_CLK_PIN 14 +#endif + +#ifndef PLASMA2040_DATA_PIN +#define PLASMA2040_DATA_PIN 15 +#endif + +#ifndef PLASMA2040_LED_R_PIN +#define PLASMA2040_LED_R_PIN 16 +#endif + +#ifndef PLASMA2040_LED_G_PIN +#define PLASMA2040_LED_G_PIN 17 +#endif + +#ifndef PLASMA2040_LED_B_PIN +#define PLASMA2040_LED_B_PIN 18 +#endif + +#ifndef PLASMA2040_I2C +#define PLASMA2040_I2C 0 +#endif + +#ifndef PLASMA2040_INT_PIN +#define PLASMA2040_INT_PIN 19 +#endif + +#ifndef PLASMA2040_SDA_PIN +#define PLASMA2040_SDA_PIN 20 +#endif + +#ifndef PLASMA2040_SCL_PIN +#define PLASMA2040_SCL_PIN 21 +#endif + +#ifndef PLASMA2040_USER_SW_PIN +#define PLASMA2040_USER_SW_PIN 23 +#endif + +#ifndef PLASMA2040_A0_PIN +#define PLASMA2040_A0_PIN 26 +#endif + +#ifndef PLASMA2040_A1_PIN +#define PLASMA2040_A1_PIN 27 +#endif + +#ifndef PLASMA2040_A2_PIN +#define PLASMA2040_A2_PIN 28 +#endif + +#ifndef PLASMA2040_NUM_ADC_PINS +#define PLASMA2040_NUM_ADC_PINS 3 +#endif + +#ifndef PLASMA2040_CURRENT_SENSE_PIN +#define PLASMA2040_CURRENT_SENSE_PIN 29 +#endif + +// --- UART --- +// no PICO_DEFAULT_UART +// no PICO_DEFAULT_UART_TX_PIN +// no PICO_DEFAULT_UART_RX_PIN + +// --- LED --- +// Included so basic examples will work, and set it to the green LED +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN PLASMA2040_LED_G_PIN +#endif +// no PICO_DEFAULT_WS2812_PIN + +#ifndef PICO_DEFAULT_LED_PIN_INVERTED +#define PICO_DEFAULT_LED_PIN_INVERTED 1 +#endif + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C PLASMA2040_I2C +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN PLASMA2040_SDA_PIN +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN PLASMA2040_SCL_PIN +#endif + +// --- SPI --- +// no PICO_DEFAULT_SPI +// no PICO_DEFAULT_SPI_SCK_PIN +// no PICO_DEFAULT_SPI_TX_PIN +// no PICO_DEFAULT_SPI_RX_PIN +// no PICO_DEFAULT_SPI_CSN_PIN + +// --- FLASH --- +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_tiny2040.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_tiny2040.h new file mode 100644 index 000000000..51d17f66a --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pimoroni_tiny2040.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_PIMORONI_TINY2040_H +#define _BOARDS_PIMORONI_TINY2040_H + +// For board detection +#define PIMORONI_TINY2040 + +// --- BOARD SPECIFIC --- +#ifndef TINY2040_LED_R_PIN +#define TINY2040_LED_R_PIN 18 +#endif + +#ifndef TINY2040_LED_G_PIN +#define TINY2040_LED_G_PIN 19 +#endif + +#ifndef TINY2040_LED_B_PIN +#define TINY2040_LED_B_PIN 20 +#endif + +#ifndef TINY2040_USER_SW_PIN +#define TINY2040_USER_SW_PIN 23 +#endif + +#ifndef TINY2040_A0_PIN +#define TINY2040_A0_PIN 26 +#endif + +#ifndef TINY2040_A1_PIN +#define TINY2040_A1_PIN 27 +#endif + +#ifndef TINY2040_A2_PIN +#define TINY2040_A2_PIN 28 +#endif + +#ifndef TINY2040_A3_PIN +#define TINY2040_A3_PIN 29 +#endif + +#ifndef TINY2040_NUM_IO_PINS +#define TINY2040_NUM_IO_PINS 8 +#endif + +#ifndef TINY2040_NUM_ADC_PINS +#define TINY2040_NUM_ADC_PINS 4 +#endif + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +// Included so basic examples will work, and set it to the green LED +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN TINY2040_LED_G_PIN +#endif +// no PICO_DEFAULT_WS2812_PIN + +#ifndef PICO_DEFAULT_LED_PIN_INVERTED +#define PICO_DEFAULT_LED_PIN_INVERTED 1 +#endif + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 1 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 2 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 3 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 6 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 7 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 4 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 5 +#endif + +// --- FLASH --- +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pybstick26_rp2040.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pybstick26_rp2040.h new file mode 100644 index 000000000..8a9ca4156 --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/pybstick26_rp2040.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_PYBSTICK26_RP2040_H +#define _BOARDS_PYBSTICK26_RP2040_H + +// For board detection +#define PYBSTICK26_RP2040 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 23 +#endif +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 1 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 6 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 7 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 1 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 10 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 11 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 8 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 9 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (1 * 1024 * 1024) +#endif + +// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) +// Linear regulator on Pybstick26 +//#define PICO_SMPS_MODE_PIN 23 + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif +// of #define _BOARDS_PYBSTICK26_RP2040_H diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/sparkfun_micromod.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/sparkfun_micromod.h new file mode 100644 index 000000000..0c6e5687c --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/sparkfun_micromod.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- +// +//------------------------------------------------------------------------------------------ +// Board definition for the SparkFun RP2040 MicroMod processor board +// +// This header may be included by other board headers as "boards/sparkfun_micromod.h" + +#ifndef _BOARDS_SPARKFUN_MICROMOD_H +#define _BOARDS_SPARKFUN_MICROMOD_H + +// For board detection +#define SPARKFUN_MICROMOD + +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif + +// Default I2C - for qwiic connector +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif + +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif + +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 22 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 23 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 20 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 21 +#endif + +// spi flash +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 + +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/sparkfun_promicro.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/sparkfun_promicro.h new file mode 100644 index 000000000..45bb4a244 --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/sparkfun_promicro.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- +// +//------------------------------------------------------------------------------------------ +// Board definition for the SparkFun RP2040 ProMicro +// +// This header may be included by other board headers as "boards/sparkfun_promicro.h" + +#ifndef _BOARDS_SPARKFUN_PROMICRO_H +#define _BOARDS_SPARKFUN_PROMICRO_H + +// For board detection +#define SPARKFUN_PROMICRO + +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// The PRO Micro doesnt have a plain LED, but a WS2812 +//#ifndef PICO_DEFAULT_LED_PIN +//#define PICO_DEFAULT_LED_PIN 25 +//#endif +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 25 +#endif + +// Default I2C - for the onboard qwiic connector +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 16 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 17 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 22 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 23 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 20 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 21 +#endif + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// board has 16M onboard flash +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 + +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/sparkfun_thingplus.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/sparkfun_thingplus.h new file mode 100644 index 000000000..d1e69d566 --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/sparkfun_thingplus.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- +// +//------------------------------------------------------------------------------------------ +// Board definition for the SparkFun RP2040 Thing Plus +// +// This header may be included by other board headers as "boards/sparkfun_thingplus.h" + +#ifndef _BOARDS_SPARKFUN_THINGPLUS_H +#define _BOARDS_SPARKFUN_THINGPLUS_H + +// For board detection +#define SPARKFUN_THINGPLUS + +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif + +// Default I2C - for qwiic connector +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 1 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 6 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 7 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 2 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 3 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 4 +#endif + + +// spi flash + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +// The thing plus has a SD Card. +#define PICO_SD_CLK_PIN 14 +#define PICO_SD_CMD_PIN 15 +#define PICO_SD_DAT0_PIN 12 +// DAT pins count down +#define PICO_SD_DAT_PIN_INCREMENT -1 + +#ifndef PICO_SD_DAT_PIN_COUNT +#define PICO_SD_DAT_PIN_COUNT 4 +#endif + +// All boards have B1 RP2040 + +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/vgaboard.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/vgaboard.h index e2c3674c2..f0b6f0e10 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/vgaboard.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/vgaboard.h @@ -12,21 +12,8 @@ #ifndef _BOARDS_VGABOARD_H #define _BOARDS_VGABOARD_H -#ifndef PICO_DEFAULT_UART -#define PICO_DEFAULT_UART 1 -#endif - -#ifndef PICO_DEFAULT_UART_TX_PIN -#define PICO_DEFAULT_UART_TX_PIN 20 -#endif - -#ifndef PICO_DEFAULT_UART_RX_PIN -#define PICO_DEFAULT_UART_RX_PIN 21 -#endif - -#ifndef PICO_DEFAULT_LED_PIN -#define PICO_DEFAULT_LED_PIN 25 // same as Pico -#endif +// For board detection +#define RASPBERRYPI_VGABOARD // Audio pins. I2S BCK, LRCK are on the same pins as PWM L/R. // - When outputting I2S, PWM sees BCK and LRCK, which should sound silent as @@ -42,8 +29,8 @@ #define VGABOARD_VGA_COLOR_PIN_BASE 0 #define VGABOARD_VGA_SYNC_PIN_BASE 16 -// Note DAT2/3 are shared with UART TX/RX (pull jumpers off header to access -// UART pins and disconnect SD DAT2/3) +// Note DAT1/2 are shared with UART TX/RX (pull jumpers off header to access +// UART pins and disconnect SD DAT1/2) #define VGABOARD_SD_CLK_PIN 5 #define VGABOARD_SD_CMD_PIN 18 #define VGABOARD_SD_DAT0_PIN 19 @@ -54,51 +41,42 @@ #define VGABOARD_BUTTON_B_PIN 6 #define VGABOARD_BUTTON_C_PIN 11 -#ifndef PICO_SCANVIDEO_COLOR_PIN_BASE -#define PICO_SCANVIDEO_COLOR_PIN_BASE VGABOARD_VGA_COLOR_PIN_BASE +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 1 #endif -#ifndef PICO_SCANVIDEO_SYMC_PIN_BASE -#define PICO_SCANVIDEO_SYNC_PIN_BASE VGABOARD_VGA_SYNC_PIN_BASE +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 20 #endif -#ifndef PICO_SD_CLK_PIN -#define PICO_SD_CLK_PIN VGABOARD_SD_CLK_PIN +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 21 #endif -#ifndef PICO_SD_CMD_PIN -#define PICO_SD_CMD_PIN VGABOARD_SD_CMD_PIN -#endif +#define PICO_SCANVIDEO_COLOR_PIN_BASE VGABOARD_VGA_COLOR_PIN_BASE +#define PICO_SCANVIDEO_SYNC_PIN_BASE VGABOARD_VGA_SYNC_PIN_BASE -#ifndef PICO_SD_DAT0_PIN +#define PICO_SD_CLK_PIN VGABOARD_SD_CLK_PIN +#define PICO_SD_CMD_PIN VGABOARD_SD_CMD_PIN #define PICO_SD_DAT0_PIN VGABOARD_SD_DAT0_PIN + +// 1 or 4 +#ifndef PICO_SD_DAT_PIN_COUNT +#define PICO_SD_DAT_PIN_COUNT 4 #endif +// 1 or -1 +#define PICO_SD_DAT_PIN_INCREMENT 1 + #define PICO_AUDIO_I2S_DATA_PIN VGABOARD_I2S_DIN_PIN #define PICO_AUDIO_I2S_CLOCK_PIN_BASE VGABOARD_I2S_BCK_PIN #define PICO_AUDIO_PWM_L_PIN VGABOARD_PWM_L_PIN #define PICO_AUDIO_PWM_R_PIN VGABOARD_PWM_R_PIN -#ifndef PICO_FLASH_SPI_CLKDIV -#define PICO_FLASH_SPI_CLKDIV 2 -#endif - -#ifndef PICO_FLASH_SIZE_BYTES -#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) -#endif - -// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) -#define PICO_SMPS_MODE_PIN 23 - -#ifndef PICO_FLOAT_SUPPORT_ROM_V1 -#define PICO_FLOAT_SUPPORT_ROM_V1 1 -#endif - -#ifndef PICO_DOUBLE_SUPPORT_ROM_V1 -#define PICO_DOUBLE_SUPPORT_ROM_V1 1 -#endif - #define PICO_VGA_BOARD +// vgaboard has a Pico on it, so default anything we haven't set above +#include "boards/pico.h" + #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_lcd_0.96.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_lcd_0.96.h new file mode 100644 index 000000000..8c59c5c49 --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_lcd_0.96.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + + +#ifndef _BOARDS_WAVESHARE_RP2040_LCD_0_96_H +#define _BOARDS_WAVESHARE_RP2040_LCD_0_96_H + +// For board detection +#define WAVESHARE_RP2040_LCD_0_96 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- LCD --- +#ifndef WAVESHARE_RP2040_LCD_SPI +#define WAVESHARE_RP2040_LCD_SPI 1 +#endif +#ifndef WAVESHARE_RP2040_LCD_DC_PIN +#define WAVESHARE_RP2040_LCD_DC_PIN 8 +#endif +#ifndef WAVESHARE_RP2040_LCD_CS_PIN +#define WAVESHARE_RP2040_LCD_CS_PIN 9 +#endif +#ifndef WAVESHARE_RP2040_LCD_SCLK_PIN +#define WAVESHARE_RP2040_LCD_SCLK_PIN 10 +#endif +#ifndef WAVESHARE_RP2040_LCD_TX_PIN +#define WAVESHARE_RP2040_LCD_TX_PIN 11 +#endif +#ifndef WAVESHARE_RP2040_LCD_RST_PIN +#define WAVESHARE_RP2040_LCD_RST_PIN 12 +#endif +#ifndef WAVESHARE_RP2040_LCD_BL_PIN +#define WAVESHARE_RP2040_LCD_BL_PIN 25 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) +#endif + +// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) +#define PICO_SMPS_MODE_PIN 23 + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif + diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_plus_16mb.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_plus_16mb.h new file mode 100644 index 000000000..6f5e1441c --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_plus_16mb.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + + +#ifndef _BOARDS_WAVESHARE_RP2040_PLUS_16MB_H +#define _BOARDS_WAVESHARE_RP2040_PLUS_16MB_H + +// For board detection +#define WAVESHARE_RP2040_PLUS_16MB + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 1 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 6 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 7 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) +#define PICO_SMPS_MODE_PIN 23 + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_plus_4mb.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_plus_4mb.h new file mode 100644 index 000000000..d8dd8f6b3 --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_plus_4mb.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + + +#ifndef _BOARDS_WAVESHARE_RP2040_PLUS_4MB_H +#define _BOARDS_WAVESHARE_RP2040_PLUS_4MB_H + +// For board detection +#define WAVESHARE_RP2040_PLUS_4MB + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 1 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 6 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 7 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024) +#endif + +// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) +#define PICO_SMPS_MODE_PIN 23 + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_zero.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_zero.h new file mode 100644 index 000000000..281b4dc8b --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/boards/include/boards/waveshare_rp2040_zero.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + + +#ifndef _BOARDS_WAVESHARE_RP2040_ZERO_H +#define _BOARDS_WAVESHARE_RP2040_ZERO_H + +// For board detection +#define WAVESHARE_RP2040_ZERO + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- WS2812 --- +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 16 +#endif + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 1 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 6 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 7 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 1 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 10 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 11 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 12 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 13 +#endif + +// --- FLASH --- +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) +#endif + +// All boards have B1 RP2040 +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 0 +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico.h index cdd5c2373..1b7365120 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico.h @@ -8,16 +8,18 @@ #define PICO_H_ /** \file pico.h -* \defgroup pico_base pico_base -* -* Core types and macros for the Raspberry Pi Pico SDK. This header is intended to be included by all source code + * \defgroup pico_base pico_base + * + * Core types and macros for the Raspberry Pi Pico SDK. This header is intended to be included by all source code + * as it includes configuration headers and overrides in the correct order + * + * This header may be included by assembly code */ #include "pico/types.h" #include "pico/version.h" #include "pico/config.h" #include "pico/platform.h" -#include "pico/assert.h" #include "pico/error.h" #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/assert.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/assert.h index 7d2beff95..8910ebdb8 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/assert.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/assert.h @@ -7,7 +7,7 @@ #ifndef _PICO_ASSERT_H #define _PICO_ASSERT_H -#include "pico/types.h" +#include #ifdef __cplusplus @@ -36,7 +36,7 @@ extern "C" { #define hard_assert_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) hard_assert(!(test));}) #ifdef NDEBUG -extern void hard_assertion_failure(); +extern void hard_assertion_failure(void); static inline void hard_assert(bool condition, ...) { if (!condition) hard_assertion_failure(); diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/config.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/config.h index a0d5c0b40..8d6926941 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/config.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/config.h @@ -8,7 +8,7 @@ #define PICO_CONFIG_H_ // ----------------------------------------------------- -// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLY CODE SO // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // OR USE #ifndef __ASSEMBLER__ guards // ------------- @@ -16,4 +16,6 @@ // PICO_CONFIG_HEADER_FILES and then PICO_SDK__CONFIG_INCLUDE_FILES // entries are dumped in order at build time into this generated header +#include "pico/config_autogen.h" + #endif \ No newline at end of file diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/error.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/error.h index 722a696f5..fadb45ec0 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/error.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/error.h @@ -7,6 +7,8 @@ #ifndef _PICO_ERROR_H #define _PICO_ERROR_H +#ifndef __ASSEMBLER__ + /*! * Common return codes from pico_sdk methods that return a status */ @@ -18,4 +20,6 @@ enum { PICO_ERROR_NO_DATA = -3, }; +#endif // !__ASSEMBLER__ + #endif \ No newline at end of file diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/types.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/types.h index 37a4c303c..8e1627ca8 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/types.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_base/include/pico/types.h @@ -7,55 +7,67 @@ #ifndef _PICO_TYPES_H #define _PICO_TYPES_H +#ifndef __ASSEMBLER__ + +#include "pico/assert.h" + #include #include #include typedef unsigned int uint; -#ifdef NDEBUG /*! \typedef absolute_time_t \brief An opaque 64 bit timestamp in microseconds The type is used instead of a raw uint64_t to prevent accidentally passing relative times or times in the wrong time units where an absolute time is required. It is equivalent to uint64_t in release builds. - \see to_us_since_boot - \see update_us_since_boot + \see to_us_since_boot() + \see update_us_since_boot() + \ingroup timestamp */ +#ifdef NDEBUG typedef uint64_t absolute_time_t; +#else +typedef struct { + uint64_t _private_us_since_boot; +} absolute_time_t; +#endif /*! fn to_us_since_boot * \brief convert an absolute_time_t into a number of microseconds since boot. - * \param t the number of microseconds since boot - * \return an absolute_time_t value equivalent to t + * \param t the absolute time to convert + * \return a number of microseconds since boot, equivalent to t + * \ingroup timestamp */ static inline uint64_t to_us_since_boot(absolute_time_t t) { +#ifdef NDEBUG return t; +#else + return t._private_us_since_boot; +#endif } /*! fn update_us_since_boot * \brief update an absolute_time_t value to represent a given number of microseconds since boot * \param t the absolute time value to update - * \param us_since_boot the number of microseconds since boot to represent + * \param us_since_boot the number of microseconds since boot to represent. Note this should be representable + * as a signed 64 bit integer + * \ingroup timestamp */ static inline void update_us_since_boot(absolute_time_t *t, uint64_t us_since_boot) { +#ifdef NDEBUG *t = us_since_boot; +#else + assert(us_since_boot <= INT64_MAX); + t->_private_us_since_boot = us_since_boot; +#endif } +#ifdef NDEBUG #define ABSOLUTE_TIME_INITIALIZED_VAR(name, value) name = value #else -typedef struct { - uint64_t _private_us_since_boot; -} absolute_time_t; - -static inline uint64_t to_us_since_boot(absolute_time_t t) { - return t._private_us_since_boot; -} - -static inline void update_us_since_boot(absolute_time_t *t, uint64_t us_since_boot) { - t->_private_us_since_boot = us_since_boot; -} #define ABSOLUTE_TIME_INITIALIZED_VAR(name, value) name = {value} #endif @@ -76,4 +88,7 @@ typedef struct { int8_t sec; ///< 0..59 } datetime_t; +#define bool_to_bit(x) ((uint)!!(x)) + +#endif #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info.h index 2a641abda..77b1c08a6 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info.h @@ -7,7 +7,9 @@ #ifndef _PICO_BINARY_INFO_H #define _PICO_BINARY_INFO_H -/** +/** \file binary_info.h + * \defgroup pico_binary_info pico_binary_info + * * Binary info is intended for embedding machine readable information with the binary in FLASH. * * Example uses include: @@ -20,9 +22,10 @@ #include "pico/binary_info/defs.h" #include "pico/binary_info/structure.h" -#if PICO_ON_DEVICE +#if !PICO_ON_DEVICE && !defined(PICO_NO_BINARY_INFO) +#define PICO_NO_BINARY_INFO 1 +#endif +#if !PICO_NO_BINARY_INFO #include "pico/binary_info/code.h" #endif - - -#endif \ No newline at end of file +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/code.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/code.h index af3ce554e..e87a2cd14 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/code.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/code.h @@ -25,12 +25,14 @@ #endif /** * Declare some binary information that will be included if the contain source file/line is compiled into the binary + * \ingroup pico_binary_info */ #define bi_decl(_decl) __bi_mark_enclosure _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.keep.", __used); /** * Declare some binary information that will be included if the function containing the decl is linked into the binary. * The SDK uses --gc-sections, so functions that are never called will be removed by the linker, and any associated * binary information declared this way will also be stripped + * \ingroup pico_binary_info */ #define bi_decl_if_func_used(_decl) ({__bi_mark_enclosure _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.", ); *(volatile uint8_t *)&__bi_ptr_lineno_var_name;}); @@ -136,4 +138,4 @@ static const struct _binary_info_named_group __bi_lineno_var_name = { \ #define bi_3pins_with_names(p0, name0, p1, name1, p2, name2) bi_pin_mask_with_names((1u << (p0)) | (1u << (p1)) | (1u << (p2)), name0 "|" name1 "|" name2) #define bi_4pins_with_names(p0, name0, p1, name1, p2, name2, p3, name3) bi_pin_mask_with_names((1u << (p0)) | (1u << (p1)) | (1u << (p2)) | (1u << (p3)), name0 "|" name1 "|" name2 "|" name3) -#endif \ No newline at end of file +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/structure.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/structure.h index 2e261b252..49d2fd690 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/structure.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_binary_info/include/pico/binary_info/structure.h @@ -54,6 +54,7 @@ typedef struct _binary_info_core binary_info_t; #define BINARY_INFO_ID_RP_PROGRAM_BUILD_ATTRIBUTE 0x4275f0d3 #define BINARY_INFO_ID_RP_SDK_VERSION 0x5360b3ab #define BINARY_INFO_ID_RP_PICO_BOARD 0xb63cffbb +#define BINARY_INFO_ID_RP_BOOT2_NAME 0x7f8882e1 #if PICO_ON_DEVICE #define bi_ptr_of(x) x * diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/include/pico/stdlib.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/include/pico/stdlib.h index 04e62750d..da0eef53c 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/include/pico/stdlib.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_stdlib/include/pico/stdlib.h @@ -44,18 +44,28 @@ extern "C" { // respective INTERFACE libraries, so these defines are set if the library // is included for the target executable -#if PICO_STDIO_UART +#if LIB_PICO_STDIO_UART #include "pico/stdio_uart.h" #endif -#if PICO_STDIO_USB +#if LIB_PICO_STDIO_USB #include "pico/stdio_usb.h" #endif -#if PICO_STDIO_SEMIHOSTING +#if LIB_PICO_STDIO_SEMIHOSTING #include "pico/stdio_semihosting.h" #endif +// PICO_CONFIG: PICO_DEFAULT_LED_PIN, Optionally define a pin that drives a regular LED on the board, group=pico_stdlib + +// PICO_CONFIG: PICO_DEFAULT_LED_PIN_INVERTED, 1 if LED is inverted or 0 if not, type=int, default=0, group=pico_stdlib +#ifndef PICO_DEFAULT_LED_PIN_INVERTED +#define PICO_DEFAULT_LED_PIN_INVERTED 0 +#endif + +// PICO_CONFIG: PICO_DEFAULT_WS2812_PIN, Optionally define a pin that controls data to a WS2812 compatible LED on the board, group=pico_stdlib +// PICO_CONFIG: PICO_DEFAULT_WS2812_POWER_PIN, Optionally define a pin that controls power to a WS2812 compatible LED on the board, group=pico_stdlib + /*! \brief Set up the default UART and assign it to the default GPIO's * \ingroup pico_stdlib * @@ -71,14 +81,14 @@ extern "C" { * PICO_DEFAULT_UART_TX_PIN * PICO_DEFAULT_UART_RX_PIN */ -void setup_default_uart(); +void setup_default_uart(void); /*! \brief Initialise the system clock to 48MHz * \ingroup pico_stdlib * * Set the system clock to 48MHz, and set the peripheral clock to match. */ -void set_sys_clock_48mhz(); +void set_sys_clock_48mhz(void); /*! \brief Initialise the system clock * \ingroup pico_stdlib diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/critical_section.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/critical_section.h index 17a8b3f47..2f9449475 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/critical_section.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/critical_section.h @@ -22,11 +22,12 @@ extern "C" { * from the other core, and from (higher priority) interrupts on the same core. It does the former * using a spin lock and the latter by disabling interrupts on the calling core. * - * Because interrupts are disabled by this function, uses of the critical_section should be as short as possible. + * Because interrupts are disabled when a critical_section is owned, uses of the critical_section + * should be as short as possible. */ typedef struct __packed_aligned critical_section { - lock_core_t core; + spin_lock_t *spin_lock; uint32_t save; } critical_section_t; @@ -38,16 +39,16 @@ typedef struct __packed_aligned critical_section { * critical sections, however if you do so you *must* use \ref critical_section_init_with_lock_num * to ensure that the spin lock's used are different. * - * \param critsec Pointer to critical_section structure + * \param crit_sec Pointer to critical_section structure */ -void critical_section_init(critical_section_t *critsec); +void critical_section_init(critical_section_t *crit_sec); /*! \brief Initialise a critical_section structure assigning a specific spin lock number * \ingroup critical_section - * \param critsec Pointer to critical_section structure + * \param crit_sec Pointer to critical_section structure * \param lock_num the specific spin lock number to use */ -void critical_section_init_with_lock_num(critical_section_t *critsec, uint lock_num); +void critical_section_init_with_lock_num(critical_section_t *crit_sec, uint lock_num); /*! \brief Enter a critical_section * \ingroup critical_section @@ -55,20 +56,32 @@ void critical_section_init_with_lock_num(critical_section_t *critsec, uint lock_ * If the spin lock associated with this critical section is in use, then this * method will block until it is released. * - * \param critsec Pointer to critical_section structure + * \param crit_sec Pointer to critical_section structure */ -static inline void critical_section_enter_blocking(critical_section_t *critsec) { - critsec->save = spin_lock_blocking(critsec->core.spin_lock); +static inline void critical_section_enter_blocking(critical_section_t *crit_sec) { + crit_sec->save = spin_lock_blocking(crit_sec->spin_lock); } /*! \brief Release a critical_section * \ingroup critical_section * - * \param critsec Pointer to critical_section structure + * \param crit_sec Pointer to critical_section structure */ -static inline void critical_section_exit(critical_section_t *critsec) { - spin_unlock(critsec->core.spin_lock, critsec->save); +static inline void critical_section_exit(critical_section_t *crit_sec) { + spin_unlock(crit_sec->spin_lock, crit_sec->save); } + +/*! \brief De-Initialise a critical_section created by the critical_section_init method + * \ingroup critical_section + * + * This method is only used to free the associated spin lock allocated via + * the critical_section_init method (it should not be used to de-initialize a spin lock + * created via critical_section_init_with_lock_num). After this call, the critical section is invalid + * + * \param crit_sec Pointer to critical_section structure + */ +void critical_section_deinit(critical_section_t *crit_sec); + #ifdef __cplusplus } #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/lock_core.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/lock_core.h index 758eb94fb..bf8bee793 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/lock_core.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/lock_core.h @@ -8,21 +8,190 @@ #define _PICO_LOCK_CORE_H #include "pico.h" +#include "pico/time.h" #include "hardware/sync.h" /** \file lock_core.h + * \defgroup lock_core lock_core * \ingroup pico_sync + * \brief base synchronization/lock primitive support * - * Base implementation for locking primitives protected by a spin lock + * Most of the pico_sync locking primitives contain a lock_core_t structure member. This currently just holds a spin + * lock which is used only to protect the contents of the rest of the structure as part of implementing the synchronization + * primitive. As such, the spin_lock member of lock core is never still held on return from any function for the primitive. + * + * \ref critical_section is an exceptional case in that it does not have a lock_core_t and simply wraps a spin lock, providing + * methods to lock and unlock said spin lock. + * + * lock_core based structures work by locking the spin lock, checking state, and then deciding whether they additionally need to block + * or notify when the spin lock is released. In the blocking case, they will wake up again in the future, and try the process again. + * + * By default the SDK just uses the processors' events via SEV and WEV for notification and blocking as these are sufficient for + * cross core, and notification from interrupt handlers. However macros are defined in this file that abstract the wait + * and notify mechanisms to allow the SDK locking functions to effectively be used within an RTOS or other environment. + * + * When implementing an RTOS, it is desirable for the SDK synchronization primitives that wait, to block the calling task (and immediately yield), + * and those that notify, to wake a blocked task which isn't on processor. At least the wait macro implementation needs to be atomic with the protecting + * spin_lock unlock from the callers point of view; i.e. the task should unlock the spin lock when it starts its wait. Such implementation is + * up to the RTOS integration, however the macros are defined such that such operations are always combined into a single call + * (so they can be perfomed atomically) even though the default implementation does not need this, as a WFE which starts + * following the corresponding SEV is not missed. */ -typedef struct lock_core { + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_LOCK_CORE, Enable/disable assertions in the lock core, type=bool, default=0, group=pico_sync +#ifndef PARAM_ASSERTIONS_ENABLED_LOCK_CORE +#define PARAM_ASSERTIONS_ENABLED_LOCK_CORE 0 +#endif + +/** \file lock_core.h + * \ingroup lock_core + * + * Base implementation for locking primitives protected by a spin lock. The spin lock is only used to protect + * access to the remaining lock state (in primitives using lock_core); it is never left locked outside + * of the function implementations + */ +struct lock_core { // spin lock protecting this lock's state spin_lock_t *spin_lock; // note any lock members in containing structures need not be volatile; // they are protected by memory/compiler barriers when gaining and release spin locks -} lock_core_t; +}; +typedef struct lock_core lock_core_t; + +/*! \brief Initialise a lock structure + * \ingroup lock_core + * + * Inititalize a lock structure, providing the spin lock number to use for protecting internal state. + * + * \param core Pointer to the lock_core to initialize + * \param lock_num Spin lock number to use for the lock. As the spin lock is only used internally to the locking primitive + * method implementations, this does not need to be globally unique, however could suffer contention + */ void lock_init(lock_core_t *core, uint lock_num); -#endif \ No newline at end of file +#ifndef lock_owner_id_t +/*! \brief type to use to store the 'owner' of a lock. + * \ingroup lock_core + * By default this is int8_t as it only needs to store the core number or -1, however it may be + * overridden if a larger type is required (e.g. for an RTOS task id) + */ +#define lock_owner_id_t int8_t +#endif + +#ifndef LOCK_INVALID_OWNER_ID +/*! \brief marker value to use for a lock_owner_id_t which does not refer to any valid owner + * \ingroup lock_core + */ +#define LOCK_INVALID_OWNER_ID ((lock_owner_id_t)-1) +#endif + +#ifndef lock_get_caller_owner_id +/*! \brief return the owner id for the caller + * \ingroup lock_core + * By default this returns the calling core number, but may be overridden (e.g. to return an RTOS task id) + */ +#define lock_get_caller_owner_id() ((lock_owner_id_t)get_core_num()) +#ifndef lock_is_owner_id_valid +#define lock_is_owner_id_valid(id) ((id)>=0) +#endif +#endif + +#ifndef lock_is_owner_id_valid +#define lock_is_owner_id_valid(id) ((id) != LOCK_INVALID_OWNER_ID) +#endif + +#ifndef lock_internal_spin_unlock_with_wait +/*! \brief Atomically unlock the lock's spin lock, and wait for a notification. + * \ingroup lock_core + * + * _Atomic_ here refers to the fact that it should not be possible for a concurrent lock_internal_spin_unlock_with_notify + * to insert itself between the spin unlock and this wait in a way that the wait does not see the notification (i.e. causing + * a missed notification). In other words this method should always wake up in response to a lock_internal_spin_unlock_with_notify + * for the same lock, which completes after this call starts. + * + * In an ideal implementation, this method would return exactly after the corresponding lock_internal_spin_unlock_with_notify + * has subsequently been called on the same lock instance, however this method is free to return at _any_ point before that; + * this macro is _always_ used in a loop which locks the spin lock, checks the internal locking primitive state and then + * waits again if the calling thread should not proceed. + * + * By default this macro simply unlocks the spin lock, and then performs a WFE, but may be overridden + * (e.g. to actually block the RTOS task). + * + * \param lock the lock_core for the primitive which needs to block + * \param save the uint32_t value that should be passed to spin_unlock when the spin lock is unlocked. (i.e. the `PRIMASK` + * state when the spin lock was acquire + */ +#define lock_internal_spin_unlock_with_wait(lock, save) spin_unlock((lock)->spin_lock, save), __wfe() +#endif + +#ifndef lock_internal_spin_unlock_with_notify +/*! \brief Atomically unlock the lock's spin lock, and send a notification + * \ingroup lock_core + * + * _Atomic_ here refers to the fact that it should not be possible for this notification to happen during a + * lock_internal_spin_unlock_with_wait in a way that that wait does not see the notification (i.e. causing + * a missed notification). In other words this method should always wake up any lock_internal_spin_unlock_with_wait + * which started before this call completes. + * + * In an ideal implementation, this method would wake up only the corresponding lock_internal_spin_unlock_with_wait + * that has been called on the same lock instance, however it is free to wake up any of them, as they will check + * their condition and then re-wait if necessary/ + * + * By default this macro simply unlocks the spin lock, and then performs a SEV, but may be overridden + * (e.g. to actually un-block RTOS task(s)). + * + * \param lock the lock_core for the primitive which needs to block + * \param save the uint32_t value that should be passed to spin_unlock when the spin lock is unlocked. (i.e. the PRIMASK + * state when the spin lock was acquire) + */ +#define lock_internal_spin_unlock_with_notify(lock, save) spin_unlock((lock)->spin_lock, save), __sev() +#endif + +#ifndef lock_internal_spin_unlock_with_best_effort_wait_or_timeout +/*! \brief Atomically unlock the lock's spin lock, and wait for a notification or a timeout + * \ingroup lock_core + * + * _Atomic_ here refers to the fact that it should not be possible for a concurrent lock_internal_spin_unlock_with_notify + * to insert itself between the spin unlock and this wait in a way that the wait does not see the notification (i.e. causing + * a missed notification). In other words this method should always wake up in response to a lock_internal_spin_unlock_with_notify + * for the same lock, which completes after this call starts. + * + * In an ideal implementation, this method would return exactly after the corresponding lock_internal_spin_unlock_with_notify + * has subsequently been called on the same lock instance or the timeout has been reached, however this method is free to return + * at _any_ point before that; this macro is _always_ used in a loop which locks the spin lock, checks the internal locking + * primitive state and then waits again if the calling thread should not proceed. + * + * By default this simply unlocks the spin lock, and then calls \ref best_effort_wfe_or_timeout + * but may be overridden (e.g. to actually block the RTOS task with a timeout). + * + * \param lock the lock_core for the primitive which needs to block + * \param save the uint32_t value that should be passed to spin_unlock when the spin lock is unlocked. (i.e. the PRIMASK + * state when the spin lock was acquire) + * \param until the \ref absolute_time_t value + * \return true if the timeout has been reached + */ +#define lock_internal_spin_unlock_with_best_effort_wait_or_timeout(lock, save, until) ({ \ + spin_unlock((lock)->spin_lock, save); \ + best_effort_wfe_or_timeout(until); \ +}) +#endif + +#ifndef sync_internal_yield_until_before +/*! \brief yield to other processing until some time before the requested time + * \ingroup lock_core + * + * This method is provided for cases where the caller has no useful work to do + * until the specified time. + * + * By default this method does nothing, however it can be overridden (for example by an + * RTOS which is able to block the current task until the scheduler tick before + * the given time) + * + * \param until the \ref absolute_time_t value + */ +#define sync_internal_yield_until_before(until) ((void)0) +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/mutex.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/mutex.h index 4b5d1759c..e834dc513 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/mutex.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/mutex.h @@ -19,20 +19,51 @@ extern "C" { * \brief Mutex API for non IRQ mutual exclusion between cores * * Mutexes are application level locks usually used protecting data structures that might be used by - * multiple cores. Unlike critical sections, the mutex protected code is not necessarily - * required/expected to complete quickly, as no other sytemwide locks are held on account of a locked mutex. + * multiple threads of execution. Unlike critical sections, the mutex protected code is not necessarily + * required/expected to complete quickly, as no other sytem wide locks are held on account of an acquired mutex. * - * Because they are not re-entrant on the same core, blocking on a mutex should never be done in an IRQ - * handler. It is valid to call \ref mutex_try_enter from within an IRQ handler, if the operation - * that would be conducted under lock can be skipped if the mutex is locked (at least by the same core). + * When acquired, the mutex has an owner (see \ref lock_get_caller_owner_id) which with the plain SDK is just + * the acquiring core, but in an RTOS it could be a task, or an IRQ handler context. + * + * Two variants of mutex are provided; \ref mutex_t (and associated mutex_ functions) is a regular mutex that cannot + * be acquired recursively by the same owner (a deadlock will occur if you try). \ref recursive_mutex_t + * (and associated recursive_mutex_ functions) is a recursive mutex that can be recursively obtained by + * the same caller, at the expense of some more overhead when acquiring and releasing. + * + * It is generally a bad idea to call blocking mutex_ or recursive_mutex_ functions from within an IRQ handler. + * It is valid to call \ref mutex_try_enter or \ref recursive_mutex_try_enter from within an IRQ handler, if the operation + * that would be conducted under lock can be skipped if the mutex is locked (at least by the same owner). + * + * NOTE: For backwards compatibility with version 1.2.0 of the SDK, if the define + * PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY is set to 1, then the the regular mutex_ functions + * may also be used for recursive mutexes. This flag will be removed in a future version of the SDK. * * See \ref critical_section.h for protecting access between multiple cores AND IRQ handlers */ +/*! \brief recursive mutex instance + * \ingroup mutex + */ +typedef struct __packed_aligned { + lock_core_t core; + lock_owner_id_t owner; //! owner id LOCK_INVALID_OWNER_ID for unowned + uint8_t enter_count; //! ownership count +#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY + bool recursive; +#endif +} recursive_mutex_t; + +/*! \brief regular (non recursive) mutex instance + * \ingroup mutex + */ +#if !PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY typedef struct __packed_aligned mutex { lock_core_t core; - int8_t owner; //! core number or -1 for unowned + lock_owner_id_t owner; //! owner id LOCK_INVALID_OWNER_ID for unowned } mutex_t; +#else +typedef recursive_mutex_t mutex_t; // they are one and the same when backwards compatible with SDK1.2.0 +#endif /*! \brief Initialise a mutex structure * \ingroup mutex @@ -41,54 +72,145 @@ typedef struct __packed_aligned mutex { */ void mutex_init(mutex_t *mtx); +/*! \brief Initialise a recursive mutex structure + * \ingroup mutex + * + * A recursive mutex may be entered in a nested fashion by the same owner + * + * \param mtx Pointer to recursive mutex structure + */ +void recursive_mutex_init(recursive_mutex_t *mtx); + /*! \brief Take ownership of a mutex * \ingroup mutex * - * This function will block until the calling core can claim ownership of the mutex. - * On return the caller core owns the mutex + * This function will block until the caller can be granted ownership of the mutex. + * On return the caller owns the mutex * * \param mtx Pointer to mutex structure */ void mutex_enter_blocking(mutex_t *mtx); -/*! \brief Check to see if a mutex is available +/*! \brief Take ownership of a recursive mutex + * \ingroup mutex + * + * This function will block until the caller can be granted ownership of the mutex. + * On return the caller owns the mutex + * + * \param mtx Pointer to recursive mutex structure + */ +void recursive_mutex_enter_blocking(recursive_mutex_t *mtx); + +/*! \brief Attempt to take ownership of a mutex * \ingroup mutex * - * Will return true if the mutex is unowned, false otherwise + * If the mutex wasn't owned, this will claim the mutex for the caller and return true. + * Otherwise (if the mutex was already owned) this will return false and the + * caller will NOT own the mutex. * * \param mtx Pointer to mutex structure - * \param owner_out If mutex is owned, and this pointer is non-zero, it will be filled in with the core number of the current owner of the mutex + * \param owner_out If mutex was already owned, and this pointer is non-zero, it will be filled in with the owner id of the current owner of the mutex + * \return true if mutex now owned, false otherwise */ bool mutex_try_enter(mutex_t *mtx, uint32_t *owner_out); +/*! \brief Attempt to take ownership of a recursive mutex + * \ingroup mutex + * + * If the mutex wasn't owned or was owned by the caller, this will claim the mutex and return true. + * Otherwise (if the mutex was already owned by another owner) this will return false and the + * caller will NOT own the mutex. + * + * \param mtx Pointer to recursive mutex structure + * \param owner_out If mutex was already owned by another owner, and this pointer is non-zero, + * it will be filled in with the owner id of the current owner of the mutex + * \return true if the recursive mutex (now) owned, false otherwise + */ +bool recursive_mutex_try_enter(recursive_mutex_t *mtx, uint32_t *owner_out); + /*! \brief Wait for mutex with timeout * \ingroup mutex * - * Wait for up to the specific time to take ownership of the mutex. If the calling - * core can take ownership of the mutex before the timeout expires, then true will be returned - * and the calling core will own the mutex, otherwise false will be returned and the calling - * core will *NOT* own the mutex. + * Wait for up to the specific time to take ownership of the mutex. If the caller + * can be granted ownership of the mutex before the timeout expires, then true will be returned + * and the caller will own the mutex, otherwise false will be returned and the caller will NOT own the mutex. * * \param mtx Pointer to mutex structure * \param timeout_ms The timeout in milliseconds. - * \return true if mutex now owned, false if timeout occurred before mutex became available + * \return true if mutex now owned, false if timeout occurred before ownership could be granted */ bool mutex_enter_timeout_ms(mutex_t *mtx, uint32_t timeout_ms); +/*! \brief Wait for recursive mutex with timeout + * \ingroup mutex + * + * Wait for up to the specific time to take ownership of the recursive mutex. If the caller + * already has ownership of the mutex or can be granted ownership of the mutex before the timeout expires, + * then true will be returned and the caller will own the mutex, otherwise false will be returned and the caller + * will NOT own the mutex. + * + * \param mtx Pointer to recursive mutex structure + * \param timeout_ms The timeout in milliseconds. + * \return true if the recursive mutex (now) owned, false if timeout occurred before ownership could be granted + */ +bool recursive_mutex_enter_timeout_ms(recursive_mutex_t *mtx, uint32_t timeout_ms); + +/*! \brief Wait for mutex with timeout + * \ingroup mutex + * + * Wait for up to the specific time to take ownership of the mutex. If the caller + * can be granted ownership of the mutex before the timeout expires, then true will be returned + * and the caller will own the mutex, otherwise false will be returned and the caller + * will NOT own the mutex. + * + * \param mtx Pointer to mutex structure + * \param timeout_us The timeout in microseconds. + * \return true if mutex now owned, false if timeout occurred before ownership could be granted + */ +bool mutex_enter_timeout_us(mutex_t *mtx, uint32_t timeout_us); + +/*! \brief Wait for recursive mutex with timeout + * \ingroup mutex + * + * Wait for up to the specific time to take ownership of the recursive mutex. If the caller + * already has ownership of the mutex or can be granted ownership of the mutex before the timeout expires, + * then true will be returned and the caller will own the mutex, otherwise false will be returned and the caller + * will NOT own the mutex. + * + * \param mtx Pointer to mutex structure + * \param timeout_us The timeout in microseconds. + * \return true if the recursive mutex (now) owned, false if timeout occurred before ownership could be granted + */ +bool recursive_mutex_enter_timeout_us(recursive_mutex_t *mtx, uint32_t timeout_us); + /*! \brief Wait for mutex until a specific time * \ingroup mutex * - * Wait until the specific time to take ownership of the mutex. If the calling - * core can take ownership of the mutex before the timeout expires, then true will be returned - * and the calling core will own the mutex, otherwise false will be returned and the calling - * core will *NOT* own the mutex. + * Wait until the specific time to take ownership of the mutex. If the caller + * can be granted ownership of the mutex before the timeout expires, then true will be returned + * and the caller will own the mutex, otherwise false will be returned and the caller + * will NOT own the mutex. * * \param mtx Pointer to mutex structure - * \param until The time after which to return if the core cannot take owner ship of the mutex - * \return true if mutex now owned, false if timeout occurred before mutex became available + * \param until The time after which to return if the caller cannot be granted ownership of the mutex + * \return true if mutex now owned, false if timeout occurred before ownership could be granted */ bool mutex_enter_block_until(mutex_t *mtx, absolute_time_t until); +/*! \brief Wait for mutex until a specific time + * \ingroup mutex + * + * Wait until the specific time to take ownership of the mutex. If the caller + * already has ownership of the mutex or can be granted ownership of the mutex before the timeout expires, + * then true will be returned and the caller will own the mutex, otherwise false will be returned and the caller + * will NOT own the mutex. + * + * \param mtx Pointer to recursive mutex structure + * \param until The time after which to return if the caller cannot be granted ownership of the mutex + * \return true if the recursive mutex (now) owned, false if timeout occurred before ownership could be granted + */ +bool recursive_mutex_enter_block_until(recursive_mutex_t *mtx, absolute_time_t until); + /*! \brief Release ownership of a mutex * \ingroup mutex * @@ -96,13 +218,30 @@ bool mutex_enter_block_until(mutex_t *mtx, absolute_time_t until); */ void mutex_exit(mutex_t *mtx); -/*! \brief Test for mutex initialised state +/*! \brief Release ownership of a recursive mutex + * \ingroup mutex + * + * \param mtx Pointer to recursive mutex structure + */ +void recursive_mutex_exit(recursive_mutex_t *mtx); + +/*! \brief Test for mutex initialized state * \ingroup mutex * * \param mtx Pointer to mutex structure - * \return true if the mutex is initialised, false otherwise + * \return true if the mutex is initialized, false otherwise + */ +static inline bool mutex_is_initialized(mutex_t *mtx) { + return mtx->core.spin_lock != 0; +} + +/*! \brief Test for recursive mutex initialized state + * \ingroup mutex + * + * \param mtx Pointer to recursive mutex structure + * \return true if the recursive mutex is initialized, false otherwise */ -static inline bool mutex_is_initialzed(mutex_t *mtx) { +static inline bool recursive_mutex_is_initialized(recursive_mutex_t *mtx) { return mtx->core.spin_lock != 0; } @@ -129,6 +268,29 @@ static inline bool mutex_is_initialzed(mutex_t *mtx) { */ #define auto_init_mutex(name) static __attribute__((section(".mutex_array"))) mutex_t name +/*! \brief Helper macro for static definition of recursive mutexes + * \ingroup mutex + * + * A recursive mutex defined as follows: + * + * ```c + * auto_init_recursive_mutex(my_recursive_mutex); + * ``` + * + * Is equivalent to doing + * + * ```c + * static recursive_mutex_t my_recursive_mutex; + * + * void my_init_function() { + * recursive_mutex_init(&my_recursive_mutex); + * } + * ``` + * + * But the initialization of the mutex is performed automatically during runtime initialization + */ +#define auto_init_recursive_mutex(name) static __attribute__((section(".mutex_array"))) recursive_mutex_t name = { .core.spin_lock = (spin_lock_t *)1 /* marker for runtime_init */ } + #ifdef __cplusplus } #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/sem.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/sem.h index 19ac2925a..6244e3246 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/sem.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico/sem.h @@ -90,11 +90,38 @@ void sem_acquire_blocking(semaphore_t *sem); * return false, otherwise it will return true. * * \param sem Pointer to semaphore structure - * \param timeout_ms Time to wait to acquire the semaphore, in ms. + * \param timeout_ms Time to wait to acquire the semaphore, in milliseconds. * \return false if timeout reached, true if permit was acquired. */ bool sem_acquire_timeout_ms(semaphore_t *sem, uint32_t timeout_ms); +/*! \brief Acquire a permit from a semaphore, with timeout + * \ingroup sem + * + * This function will block and wait if no permits are available, until the + * defined timeout has been reached. If the timeout is reached the function will + * return false, otherwise it will return true. + * + * \param sem Pointer to semaphore structure + * \param timeout_us Time to wait to acquire the semaphore, in microseconds. + * \return false if timeout reached, true if permit was acquired. + */ +bool sem_acquire_timeout_us(semaphore_t *sem, uint32_t timeout_us); + +/*! \brief Wait to acquire a permit from a semaphore until a specific time + * \ingroup sem + * + * This function will block and wait if no permits are available, until the + * specified timeout time. If the timeout is reached the function will + * return false, otherwise it will return true. + * + * \param sem Pointer to semaphore structure + * \param until The time after which to return if the sem is not available. + * \return true if permit was acquired, false if the until time was reached before + * acquiring. + */ +bool sem_acquire_block_until(semaphore_t *sem, absolute_time_t until); + #ifdef __cplusplus } #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/pico/time.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/pico/time.h index ae0a84f7c..c00b7a82c 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/pico/time.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include/pico/time.h @@ -58,7 +58,7 @@ extern "C" { * \sa sleep_until() * \sa time_us_64() */ -static inline absolute_time_t get_absolute_time() { +static inline absolute_time_t get_absolute_time(void) { absolute_time_t t; update_us_since_boot(&t, time_us_64()); return t; @@ -77,7 +77,7 @@ static inline uint32_t us_to_ms(uint64_t us) { * \brief Convert a timestamp into a number of milliseconds since boot. * \param t an absolute_time_t value to convert * \return the number of microseconds since boot represented by t - * \sa to_us_since_boot + * \sa to_us_since_boot() */ static inline uint32_t to_ms_since_boot(absolute_time_t t) { uint64_t us = to_us_since_boot(t); @@ -152,10 +152,12 @@ static inline absolute_time_t make_timeout_time_ms(uint32_t ms) { * in case of overflow) */ static inline int64_t absolute_time_diff_us(absolute_time_t from, absolute_time_t to) { - return to_us_since_boot(to) - to_us_since_boot(from); + return (int64_t)(to_us_since_boot(to) - to_us_since_boot(from)); } -/*! \brief The timestamp representing the end of time; no timestamp is after this +/*! \brief The timestamp representing the end of time; this is actually not the maximum possible + * timestamp, but is set to 0x7fffffff_ffffffff microseconds to avoid sign overflows with time + * arithmetic. This is still over 7 million years, so should be sufficient. * \ingroup timestamp */ extern const absolute_time_t at_the_end_of_time; @@ -169,7 +171,7 @@ extern const absolute_time_t nil_time; * \ingroup timestamp * \param t the timestamp * \return true if the timestamp is nil - * \sa nil_time() + * \sa nil_time */ static inline bool is_nil_time(absolute_time_t t) { return !to_us_since_boot(t); @@ -228,7 +230,7 @@ void sleep_ms(uint32_t ms); /*! \brief Helper method for blocking on a timeout * \ingroup sleep * - * This method will return in response to a an event (as per __wfe) or + * This method will return in response to an event (as per __wfe) or * when the target time is reached, or at any point before. * * This method can be used to implement a lower power polling loop waiting on @@ -350,7 +352,7 @@ typedef struct alarm_pool alarm_pool_t; * \brief Create the default alarm pool (if not already created or disabled) * \ingroup alarm */ -void alarm_pool_init_default(); +void alarm_pool_init_default(void); #if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED /*! @@ -360,7 +362,7 @@ void alarm_pool_init_default(); * \ingroup alarm * \sa #PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM */ -alarm_pool_t *alarm_pool_get_default(); +alarm_pool_t *alarm_pool_get_default(void); #endif /** @@ -414,9 +416,12 @@ void alarm_pool_destroy(alarm_pool_t *pool); * @param time the timestamp when (after which) the callback should fire * @param callback the callback function * @param user_data user data to pass to the callback function - * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call - * @return >0 the alarm id - * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past) + * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set, + * then the callback should be called during (by) this function instead + * @return >0 the alarm id for an active (at the time of return) alarm + * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of. + * The latter can either happen because fire_if_past was false (i.e. no timer was ever created), + * or if the callback was called during this method but the callback cancelled itself by returning 0 * @return -1 if there were no alarm slots available */ alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback, void *user_data, bool fire_if_past); @@ -436,9 +441,12 @@ alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, ala * @param us the delay (from now) in microseconds when (after which) the callback should fire * @param callback the callback function * @param user_data user data to pass to the callback function - * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call + * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set, + * then the callback should be called during (by) this function instead * @return >0 the alarm id - * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past) + * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of. + * The latter can either happen because fire_if_past was false (i.e. no timer was ever created), + * or if the callback was called during this method but the callback cancelled itself by returning 0 * @return -1 if there were no alarm slots available */ static inline alarm_id_t alarm_pool_add_alarm_in_us(alarm_pool_t *pool, uint64_t us, alarm_callback_t callback, void *user_data, bool fire_if_past) { @@ -460,9 +468,12 @@ static inline alarm_id_t alarm_pool_add_alarm_in_us(alarm_pool_t *pool, uint64_t * @param ms the delay (from now) in milliseconds when (after which) the callback should fire * @param callback the callback function * @param user_data user data to pass to the callback function - * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call + * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set, + * then the callback should be called during (by) this function instead * @return >0 the alarm id - * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past) + * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of. + * The latter can either happen because fire_if_past was false (i.e. no timer was ever created), + * or if the callback was called during this method but the callback cancelled itself by returning 0 * @return -1 if there were no alarm slots available */ static inline alarm_id_t alarm_pool_add_alarm_in_ms(alarm_pool_t *pool, uint32_t ms, alarm_callback_t callback, void *user_data, bool fire_if_past) { @@ -494,9 +505,12 @@ bool alarm_pool_cancel_alarm(alarm_pool_t *pool, alarm_id_t alarm_id); * @param time the timestamp when (after which) the callback should fire * @param callback the callback function * @param user_data user data to pass to the callback function - * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call + * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set, + * then the callback should be called during (by) this function instead * @return >0 the alarm id - * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past) + * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of. + * The latter can either happen because fire_if_past was false (i.e. no timer was ever created), + * or if the callback was called during this method but the callback cancelled itself by returning 0 * @return -1 if there were no alarm slots available */ static inline alarm_id_t add_alarm_at(absolute_time_t time, alarm_callback_t callback, void *user_data, bool fire_if_past) { @@ -517,9 +531,12 @@ static inline alarm_id_t add_alarm_at(absolute_time_t time, alarm_callback_t cal * @param us the delay (from now) in microseconds when (after which) the callback should fire * @param callback the callback function * @param user_data user data to pass to the callback function - * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call + * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set, + * then the callback should be called during (by) this function instead * @return >0 the alarm id - * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past) + * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of. + * The latter can either happen because fire_if_past was false (i.e. no timer was ever created), + * or if the callback was called during this method but the callback cancelled itself by returning 0 * @return -1 if there were no alarm slots available */ static inline alarm_id_t add_alarm_in_us(uint64_t us, alarm_callback_t callback, void *user_data, bool fire_if_past) { @@ -540,9 +557,12 @@ static inline alarm_id_t add_alarm_in_us(uint64_t us, alarm_callback_t callback, * @param ms the delay (from now) in milliseconds when (after which) the callback should fire * @param callback the callback function * @param user_data user data to pass to the callback function - * @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call + * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set, + * then the callback should be called during (by) this function instead * @return >0 the alarm id - * @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past) + * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of. + * The latter can either happen because fire_if_past was false (i.e. no timer was ever created), + * or if the callback was called during this method but the callback cancelled itself by returning 0 * @return -1 if there were no alarm slots available */ static inline alarm_id_t add_alarm_in_ms(uint32_t ms, alarm_callback_t callback, void *user_data, bool fire_if_past) { diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_usb_reset_interface/include/pico/usb_reset_interface.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_usb_reset_interface/include/pico/usb_reset_interface.h new file mode 100644 index 000000000..153acf810 --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_usb_reset_interface/include/pico/usb_reset_interface.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_USB_RESET_INTERFACE_H +#define _PICO_USB_RESET_INTERFACE_H + +/** \file usb_reset_interface.h + * \defgroup pico_usb_reset_interface pico_usb_reset_interface + * + * Definition for the reset interface that may be exposed by the pico_stdio_usb library + */ + +// VENDOR sub-class for the reset interface +#define RESET_INTERFACE_SUBCLASS 0x00 +// VENDOR protocol for the reset interface +#define RESET_INTERFACE_PROTOCOL 0x01 + +// CONTROL requests: + +// reset to BOOTSEL +#define RESET_REQUEST_BOOTSEL 0x01 +// regular flash boot +#define RESET_REQUEST_FLASH 0x02 + +#endif \ No newline at end of file diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/datetime.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/datetime.h index 61b5c7e92..bb328351a 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/datetime.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/datetime.h @@ -9,6 +9,10 @@ #include "pico.h" +#ifdef __cplusplus +extern "C" { +#endif + /** \file datetime.h * \defgroup util_datetime datetime * \brief Date/Time formatting @@ -24,4 +28,7 @@ */ void datetime_to_str(char *buf, uint buf_size, const datetime_t *t); +#ifdef __cplusplus +} +#endif #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/pheap.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/pheap.h index 59617e7de..25351b44f 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/pheap.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/pheap.h @@ -29,7 +29,7 @@ extern "C" { * * NOTE: this class is not safe for concurrent usage. It should be externally protected. Furthermore * if used concurrently, the caller needs to protect around their use of the returned id. - * for example, ph_remove_head returns the id of an element that is no longer in the heap. + * for example, ph_remove_and_free_head returns the id of an element that is no longer in the heap. * * The user can still use this to look at the data in their companion array, however obviously further operations * on the heap may cause them to overwrite that data as the id may be reused on subsequent operations @@ -53,7 +53,11 @@ typedef struct pheap_node { pheap_node_id_t child, sibling, parent; } pheap_node_t; -// return true if a < b in natural order +/** + * A user comparator function for nodes in a pairing heap. + * + * \return true if a < b in natural order. Note this relative ordering must be stable from call to call. + */ typedef bool (*pheap_comparator)(void *user_data, pheap_node_id_t a, pheap_node_id_t b); typedef struct pheap { @@ -67,17 +71,42 @@ typedef struct pheap { pheap_node_id_t free_tail_id; } pheap_t; +/** + * Create a pairing heap, which effectively maintains an efficient sorted ordering + * of nodes. The heap itself stores no user per-node state, it is expected + * that the user maintains a companion array. A comparator function must + * be provided so that the heap implementation can determine the relative ordering of nodes + * + * \param max_nodes the maximum number of nodes that may be in the heap (this is bounded by + * PICO_PHEAP_MAX_ENTRIES which defaults to 255 to be able to store indexes + * in a single byte). + * \param comparator the node comparison function + * \param user_data a user data pointer associated with the heap that is provided in callbacks + * \return a newly allocated and initialized heap + */ pheap_t *ph_create(uint max_nodes, pheap_comparator comparator, void *user_data); +/** + * Removes all nodes from the pairing heap + * \param heap the heap + */ void ph_clear(pheap_t *heap); +/** + * De-allocates a pairing heap + * + * Note this method must *ONLY* be called on heaps created by ph_create() + * \param heap the heap + */ void ph_destroy(pheap_t *heap); +// internal method static inline pheap_node_t *ph_get_node(pheap_t *heap, pheap_node_id_t id) { assert(id && id <= heap->max_nodes); return heap->nodes + id - 1; } +// internal method static void ph_add_child_node(pheap_t *heap, pheap_node_id_t parent_id, pheap_node_id_t child_id) { pheap_node_t *n = ph_get_node(heap, parent_id); assert(parent_id); @@ -93,6 +122,7 @@ static void ph_add_child_node(pheap_t *heap, pheap_node_id_t parent_id, pheap_no } } +// internal method static pheap_node_id_t ph_merge_nodes(pheap_t *heap, pheap_node_id_t a, pheap_node_id_t b) { if (!a) return b; if (!b) return a; @@ -105,17 +135,34 @@ static pheap_node_id_t ph_merge_nodes(pheap_t *heap, pheap_node_id_t a, pheap_no } } +/** + * Allocate a new node from the unused space in the heap + * + * \param heap the heap + * \return an identifier for the node, or 0 if the heap is full + */ static inline pheap_node_id_t ph_new_node(pheap_t *heap) { if (!heap->free_head_id) return 0; pheap_node_id_t id = heap->free_head_id; - heap->free_head_id = ph_get_node(heap, id)->sibling; + pheap_node_t *hn = ph_get_node(heap, id); + heap->free_head_id = hn->sibling; if (!heap->free_head_id) heap->free_tail_id = 0; + hn->child = hn->sibling = hn->parent = 0; return id; } -// note this will callback the comparator for the node -// returns the (new) root of the heap -static inline pheap_node_id_t ph_insert(pheap_t *heap, pheap_node_id_t id) { +/** + * Inserts a node into the heap. + * + * This method inserts a node (previously allocated by ph_new_node()) + * into the heap, determining the correct order by calling + * the heap's comparator + * + * \param heap the heap + * \param id the id of the node to insert + * \return the id of the new head of the pairing heap (i.e. node that compares first) + */ +static inline pheap_node_id_t ph_insert_node(pheap_t *heap, pheap_node_id_t id) { assert(id); pheap_node_t *hn = ph_get_node(heap, id); hn->child = hn->sibling = hn->parent = 0; @@ -123,31 +170,120 @@ static inline pheap_node_id_t ph_insert(pheap_t *heap, pheap_node_id_t id) { return heap->root_id; } +/** + * Returns the head node in the heap, i.e. the node + * which compares first, but without removing it from the heap. + * + * \param heap the heap + * \return the current head node id + */ static inline pheap_node_id_t ph_peek_head(pheap_t *heap) { return heap->root_id; } -pheap_node_id_t ph_remove_head_reserve(pheap_t *heap, bool reserve); +/** + * Remove the head node from the pairing heap. This head node is + * the node which compares first in the logical ordering provided + * by the comparator. + * + * Note that in the case of free == true, the returned id is no longer + * allocated and may be re-used by future node allocations, so the caller + * should retrieve any per node state from the companion array before modifying + * the heap further. + * + * @param heap the heap + * @param free true if the id is also to be freed; false if not - useful if the caller + * may wish to re-insert an item with the same id) + * @return the old head node id. + */ +pheap_node_id_t ph_remove_head(pheap_t *heap, bool free); -static inline pheap_node_id_t ph_remove_head(pheap_t *heap) { - return ph_remove_head_reserve(heap, false); +/** + * Remove the head node from the pairing heap. This head node is + * the node which compares first in the logical ordering provided + * by the comparator. + * + * Note that the returned id will be freed, and thus may be re-used by future node allocations, + * so the caller should retrieve any per node state from the companion array before modifying + * the heap further. + * + * @param heap the heap + * @return the old head node id. + */ +static inline pheap_node_id_t ph_remove_and_free_head(pheap_t *heap) { + return ph_remove_head(heap, true); } -static inline bool ph_contains(pheap_t *heap, pheap_node_id_t id) { +/** + * Remove and free an arbitrary node from the pairing heap. This is a more + * costly operation than removing the head via ph_remove_and_free_head() + * + * @param heap the heap + * @param id the id of the node to free + * @return true if the the node was in the heap, false otherwise + */ +bool ph_remove_and_free_node(pheap_t *heap, pheap_node_id_t id); + +/** + * Determine if the heap contains a given node. Note containment refers + * to whether the node is inserted (ph_insert_node()) vs allocated (ph_new_node()) + * + * @param heap the heap + * @param id the id of the node + * @return true if the heap contains a node with the given id, false otherwise. + */ +static inline bool ph_contains_node(pheap_t *heap, pheap_node_id_t id) { return id == heap->root_id || ph_get_node(heap, id)->parent; } -bool ph_delete(pheap_t *heap, pheap_node_id_t id); -static inline void ph_add_to_free_list(pheap_t *heap, pheap_node_id_t id) { - assert(id && !ph_contains(heap, id)); +/** + * Free a node that is not currently in the heap, but has been allocated + * + * @param heap the heap + * @param id the id of the node + */ +static inline void ph_free_node(pheap_t *heap, pheap_node_id_t id) { + assert(id && !ph_contains_node(heap, id)); if (heap->free_tail_id) { ph_get_node(heap, heap->free_tail_id)->sibling = id; } heap->free_tail_id = id; } -void ph_dump(pheap_t *heap, void (*dump_key)(pheap_node_id_t, void *), void *user_data); +/** + * Print a representation of the heap for debugging + * + * @param heap the heap + * @param dump_key a method to print a node value + * @param user_data the user data to pass to the dump_key method + */ +void ph_dump(pheap_t *heap, void (*dump_key)(pheap_node_id_t id, void *user_data), void *user_data); + +/** + * Initialize a statically allocated heap (ph_create() using the C heap). + * The heap member `nodes` must be allocated of size max_nodes. + * + * @param heap the heap + * @param max_nodes the max number of nodes in the heap (matching the size of the heap's nodes array) + * @param comparator the comparator for the heap + * @param user_data the user data for the heap. + */ +void ph_post_alloc_init(pheap_t *heap, uint max_nodes, pheap_comparator comparator, void *user_data); + +/** + * Define a statically allocated pairing heap. This must be initialized + * by ph_post_alloc_init + */ +#define PHEAP_DEFINE_STATIC(name, _max_nodes) \ + static_assert(_max_nodes && _max_nodes < (1u << (8 * sizeof(pheap_node_id_t))), ""); \ + static pheap_node_t name ## _nodes[_max_nodes]; \ + static pheap_t name = { \ + .nodes = name ## _nodes, \ + .max_nodes = _max_nodes \ + }; + + #ifdef __cplusplus } #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/queue.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/queue.h index d65548eaa..097578a61 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/queue.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico/util/queue.h @@ -10,6 +10,11 @@ #include "pico.h" #include "hardware/sync.h" +// PICO_CONFIG: PICO_QUEUE_MAX_LEVEL, Maintain a field for the highest level that has been reached by a queue, type=bool, default=0, advanced=true, group=queue +#ifndef PICO_QUEUE_MAX_LEVEL +#define PICO_QUEUE_MAX_LEVEL 0 +#endif + /** \file queue.h * \defgroup queue queue * Multi-core and IRQ safe queue implementation. @@ -18,13 +23,22 @@ * \ingroup pico_util */ +#ifdef __cplusplus +extern "C" { +#endif + +#include "pico/lock_core.h" + typedef struct { - spin_lock_t *lock; + lock_core_t core; uint8_t *data; uint16_t wptr; uint16_t rptr; uint16_t element_size; uint16_t element_count; +#if PICO_QUEUE_MAX_LEVEL + uint16_t max_level; +#endif } queue_t; /*! \brief Initialise a queue with a specific spinlock for concurrency protection @@ -69,9 +83,9 @@ void queue_free(queue_t *q); static inline uint queue_get_level_unsafe(queue_t *q) { int32_t rc = (int32_t)q->wptr - (int32_t)q->rptr; if (rc < 0) { - rc += + q->element_count + 1; + rc += q->element_count + 1; } - return rc; + return (uint)rc; } /*! \brief Check of level of the specified queue. @@ -81,12 +95,38 @@ static inline uint queue_get_level_unsafe(queue_t *q) { * \return Number of entries in the queue */ static inline uint queue_get_level(queue_t *q) { - uint32_t save = spin_lock_blocking(q->lock); + uint32_t save = spin_lock_blocking(q->core.spin_lock); uint level = queue_get_level_unsafe(q); - spin_unlock(q->lock, save); + spin_unlock(q->core.spin_lock, save); return level; } +/*! \brief Returns the highest level reached by the specified queue since it was created + * or since the max level was reset + * \ingroup queue + * + * \param q Pointer to a queue_t structure, used as a handle + * \return Maximum level of the queue + */ +#if PICO_QUEUE_MAX_LEVEL +static inline uint queue_get_max_level(queue_t *q) { + return q->max_level; +} +#endif + +/*! \brief Reset the highest level reached of the specified queue. + * \ingroup queue + * + * \param q Pointer to a queue_t structure, used as a handle + */ +#if PICO_QUEUE_MAX_LEVEL +static inline void queue_reset_max_level(queue_t *q) { + uint32_t save = spin_lock_blocking(q->core.spin_lock); + q->max_level = queue_get_level_unsafe(q); + spin_unlock(q->core.spin_lock, save); +} +#endif + /*! \brief Check if queue is empty * \ingroup queue * @@ -123,7 +163,7 @@ static inline bool queue_is_full(queue_t *q) { * If the queue is full this function will return immediately with false, otherwise * the data is copied into a new value added to the queue, and this function will return true. */ -bool queue_try_add(queue_t *q, void *data); +bool queue_try_add(queue_t *q, const void *data); /*! \brief Non-blocking removal of entry from the queue if non empty * \ingroup queue @@ -159,7 +199,7 @@ bool queue_try_peek(queue_t *q, void *data); * * If the queue is full this function will block, until a removal happens on the queue */ -void queue_add_blocking(queue_t *q, void *data); +void queue_add_blocking(queue_t *q, const void *data); /*! \brief Blocking remove entry from queue * \ingroup queue @@ -181,4 +221,7 @@ void queue_remove_blocking(queue_t *q, void *data); */ void queue_peek_blocking(queue_t *q, void *data); +#ifdef __cplusplus +} +#endif #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/generated/pico/config_autogen.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/generated/pico/config_autogen.h new file mode 100644 index 000000000..e1e1e33f6 --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/generated/pico/config_autogen.h @@ -0,0 +1,7 @@ +// AUTOGENERATED FROM PICO_CONFIG_HEADER_FILES and then PICO__CONFIG_HEADER_FILES +// DO NOT EDIT! + + +// based on PICO_CONFIG_HEADER_FILES: + +#include "boards/pico.h" \ No newline at end of file diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/generated/pico/version.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/generated/pico/version.h index 7b537522f..96e417bdd 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/generated/pico/version.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/generated/pico/version.h @@ -12,8 +12,8 @@ #define _PICO_VERSION_H #define PICO_SDK_VERSION_MAJOR 1 -#define PICO_SDK_VERSION_MINOR 0 -#define PICO_SDK_VERSION_REVISION 1 -#define PICO_SDK_VERSION_STRING "1.0.1" +#define PICO_SDK_VERSION_MINOR 3 +#define PICO_SDK_VERSION_REVISION 0 +#define PICO_SDK_VERSION_STRING "1.3.0" #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/platform_defs.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/platform_defs.h index 51c027222..08c715944 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/platform_defs.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/platform_defs.h @@ -7,41 +7,38 @@ #ifndef _HARDWARE_PLATFORM_DEFS_H #define _HARDWARE_PLATFORM_DEFS_H -// This header is included from C and assembler - only define macros +// This header is included from C and assembler - intended mostly for #defines; guard other stuff with #ifdef __ASSEMBLER__ -#include "hardware/regs/addressmap.h" - -#define NUM_CORES 2u -#define NUM_DMA_CHANNELS 12u -#define NUM_IRQS 32u -#define NUM_PIOS 2u -#define NUM_PIO_STATE_MACHINES 4u -#define NUM_PWM_SLICES 8u -#define NUM_SPIN_LOCKS 32u -#define NUM_UARTS 2u -#define NUM_BANK0_GPIOS 30u - -#define PIO_INSTRUCTION_COUNT 32u - -#define XOSC_MHZ 12u - -// PICO_CONFIG: PICO_STACK_SIZE, Stack Size, min=0x100, default=0x800, advanced=true, group=pico_standard_link -#ifndef PICO_STACK_SIZE -#define PICO_STACK_SIZE 0x800u +#ifndef _u +#ifdef __ASSEMBLER__ +#define _u(x) x +#else +#define _u(x) x ## u #endif - -// PICO_CONFIG: PICO_HEAP_SIZE, Heap size to reserve, min=0x100, default=0x800, advanced=true, group=pico_standard_link -#ifndef PICO_HEAP_SIZE -#define PICO_HEAP_SIZE 0x800 -#endif - -// PICO_CONFIG: PICO_NO_RAM_VECTOR_TABLE, Enable/disable the RAM vector table, type=bool, default=0, advanced=true, group=pico_runtime -#ifndef PICO_NO_RAM_VECTOR_TABLE -#define PICO_NO_RAM_VECTOR_TABLE 0 #endif -#ifndef PICO_FLASH_SIZE_BYTES -#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) +#define NUM_CORES _u(2) +#define NUM_DMA_CHANNELS _u(12) +#define NUM_DMA_TIMERS _u(4) +#define NUM_IRQS _u(32) +#define NUM_PIOS _u(2) +#define NUM_PIO_STATE_MACHINES _u(4) +#define NUM_PWM_SLICES _u(8) +#define NUM_SPIN_LOCKS _u(32) +#define NUM_UARTS _u(2) +#define NUM_I2CS _u(2) +#define NUM_SPIS _u(2) +#define NUM_TIMERS _u(4) +#define NUM_ADC_CHANNELS _u(5) + +#define NUM_BANK0_GPIOS _u(30) +#define NUM_QSPI_GPIOS _u(6) + +#define PIO_INSTRUCTION_COUNT _u(32) + +// PICO_CONFIG: XOSC_MHZ, The crystal oscillator frequency in Mhz, type=int, default=12, advanced=true, group=hardware_base +#ifndef XOSC_MHZ +#define XOSC_MHZ _u(12) #endif #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/adc.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/adc.h index 82bb0f8fb..47510be51 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/adc.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/adc.h @@ -14,9 +14,9 @@ // ============================================================================= // Register : ADC_CS // Description : ADC Control and Status -#define ADC_CS_OFFSET 0x00000000 -#define ADC_CS_BITS 0x001f770f -#define ADC_CS_RESET 0x00000000 +#define ADC_CS_OFFSET _u(0x00000000) +#define ADC_CS_BITS _u(0x001f770f) +#define ADC_CS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ADC_CS_RROBIN // Description : Round-robin sampling. 1 bit per channel. Set all bits to 0 to @@ -27,202 +27,202 @@ // indicated by AINSEL. // AINSEL will be updated after each conversion with the // newly-selected channel. -#define ADC_CS_RROBIN_RESET 0x00 -#define ADC_CS_RROBIN_BITS 0x001f0000 -#define ADC_CS_RROBIN_MSB 20 -#define ADC_CS_RROBIN_LSB 16 +#define ADC_CS_RROBIN_RESET _u(0x00) +#define ADC_CS_RROBIN_BITS _u(0x001f0000) +#define ADC_CS_RROBIN_MSB _u(20) +#define ADC_CS_RROBIN_LSB _u(16) #define ADC_CS_RROBIN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ADC_CS_AINSEL // Description : Select analog mux input. Updated automatically in round-robin // mode. -#define ADC_CS_AINSEL_RESET 0x0 -#define ADC_CS_AINSEL_BITS 0x00007000 -#define ADC_CS_AINSEL_MSB 14 -#define ADC_CS_AINSEL_LSB 12 +#define ADC_CS_AINSEL_RESET _u(0x0) +#define ADC_CS_AINSEL_BITS _u(0x00007000) +#define ADC_CS_AINSEL_MSB _u(14) +#define ADC_CS_AINSEL_LSB _u(12) #define ADC_CS_AINSEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ADC_CS_ERR_STICKY // Description : Some past ADC conversion encountered an error. Write 1 to // clear. -#define ADC_CS_ERR_STICKY_RESET 0x0 -#define ADC_CS_ERR_STICKY_BITS 0x00000400 -#define ADC_CS_ERR_STICKY_MSB 10 -#define ADC_CS_ERR_STICKY_LSB 10 +#define ADC_CS_ERR_STICKY_RESET _u(0x0) +#define ADC_CS_ERR_STICKY_BITS _u(0x00000400) +#define ADC_CS_ERR_STICKY_MSB _u(10) +#define ADC_CS_ERR_STICKY_LSB _u(10) #define ADC_CS_ERR_STICKY_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : ADC_CS_ERR // Description : The most recent ADC conversion encountered an error; result is // undefined or noisy. -#define ADC_CS_ERR_RESET 0x0 -#define ADC_CS_ERR_BITS 0x00000200 -#define ADC_CS_ERR_MSB 9 -#define ADC_CS_ERR_LSB 9 +#define ADC_CS_ERR_RESET _u(0x0) +#define ADC_CS_ERR_BITS _u(0x00000200) +#define ADC_CS_ERR_MSB _u(9) +#define ADC_CS_ERR_LSB _u(9) #define ADC_CS_ERR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : ADC_CS_READY // Description : 1 if the ADC is ready to start a new conversion. Implies any // previous conversion has completed. // 0 whilst conversion in progress. -#define ADC_CS_READY_RESET 0x0 -#define ADC_CS_READY_BITS 0x00000100 -#define ADC_CS_READY_MSB 8 -#define ADC_CS_READY_LSB 8 +#define ADC_CS_READY_RESET _u(0x0) +#define ADC_CS_READY_BITS _u(0x00000100) +#define ADC_CS_READY_MSB _u(8) +#define ADC_CS_READY_LSB _u(8) #define ADC_CS_READY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : ADC_CS_START_MANY // Description : Continuously perform conversions whilst this bit is 1. A new // conversion will start immediately after the previous finishes. -#define ADC_CS_START_MANY_RESET 0x0 -#define ADC_CS_START_MANY_BITS 0x00000008 -#define ADC_CS_START_MANY_MSB 3 -#define ADC_CS_START_MANY_LSB 3 +#define ADC_CS_START_MANY_RESET _u(0x0) +#define ADC_CS_START_MANY_BITS _u(0x00000008) +#define ADC_CS_START_MANY_MSB _u(3) +#define ADC_CS_START_MANY_LSB _u(3) #define ADC_CS_START_MANY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ADC_CS_START_ONCE // Description : Start a single conversion. Self-clearing. Ignored if start_many // is asserted. -#define ADC_CS_START_ONCE_RESET 0x0 -#define ADC_CS_START_ONCE_BITS 0x00000004 -#define ADC_CS_START_ONCE_MSB 2 -#define ADC_CS_START_ONCE_LSB 2 +#define ADC_CS_START_ONCE_RESET _u(0x0) +#define ADC_CS_START_ONCE_BITS _u(0x00000004) +#define ADC_CS_START_ONCE_MSB _u(2) +#define ADC_CS_START_ONCE_LSB _u(2) #define ADC_CS_START_ONCE_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : ADC_CS_TS_EN // Description : Power on temperature sensor. 1 - enabled. 0 - disabled. -#define ADC_CS_TS_EN_RESET 0x0 -#define ADC_CS_TS_EN_BITS 0x00000002 -#define ADC_CS_TS_EN_MSB 1 -#define ADC_CS_TS_EN_LSB 1 +#define ADC_CS_TS_EN_RESET _u(0x0) +#define ADC_CS_TS_EN_BITS _u(0x00000002) +#define ADC_CS_TS_EN_MSB _u(1) +#define ADC_CS_TS_EN_LSB _u(1) #define ADC_CS_TS_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ADC_CS_EN // Description : Power on ADC and enable its clock. // 1 - enabled. 0 - disabled. -#define ADC_CS_EN_RESET 0x0 -#define ADC_CS_EN_BITS 0x00000001 -#define ADC_CS_EN_MSB 0 -#define ADC_CS_EN_LSB 0 +#define ADC_CS_EN_RESET _u(0x0) +#define ADC_CS_EN_BITS _u(0x00000001) +#define ADC_CS_EN_MSB _u(0) +#define ADC_CS_EN_LSB _u(0) #define ADC_CS_EN_ACCESS "RW" // ============================================================================= // Register : ADC_RESULT // Description : Result of most recent ADC conversion -#define ADC_RESULT_OFFSET 0x00000004 -#define ADC_RESULT_BITS 0x00000fff -#define ADC_RESULT_RESET 0x00000000 -#define ADC_RESULT_MSB 11 -#define ADC_RESULT_LSB 0 +#define ADC_RESULT_OFFSET _u(0x00000004) +#define ADC_RESULT_BITS _u(0x00000fff) +#define ADC_RESULT_RESET _u(0x00000000) +#define ADC_RESULT_MSB _u(11) +#define ADC_RESULT_LSB _u(0) #define ADC_RESULT_ACCESS "RO" // ============================================================================= // Register : ADC_FCS // Description : FIFO control and status -#define ADC_FCS_OFFSET 0x00000008 -#define ADC_FCS_BITS 0x0f0f0f0f -#define ADC_FCS_RESET 0x00000000 +#define ADC_FCS_OFFSET _u(0x00000008) +#define ADC_FCS_BITS _u(0x0f0f0f0f) +#define ADC_FCS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ADC_FCS_THRESH // Description : DREQ/IRQ asserted when level >= threshold -#define ADC_FCS_THRESH_RESET 0x0 -#define ADC_FCS_THRESH_BITS 0x0f000000 -#define ADC_FCS_THRESH_MSB 27 -#define ADC_FCS_THRESH_LSB 24 +#define ADC_FCS_THRESH_RESET _u(0x0) +#define ADC_FCS_THRESH_BITS _u(0x0f000000) +#define ADC_FCS_THRESH_MSB _u(27) +#define ADC_FCS_THRESH_LSB _u(24) #define ADC_FCS_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ADC_FCS_LEVEL // Description : The number of conversion results currently waiting in the FIFO -#define ADC_FCS_LEVEL_RESET 0x0 -#define ADC_FCS_LEVEL_BITS 0x000f0000 -#define ADC_FCS_LEVEL_MSB 19 -#define ADC_FCS_LEVEL_LSB 16 +#define ADC_FCS_LEVEL_RESET _u(0x0) +#define ADC_FCS_LEVEL_BITS _u(0x000f0000) +#define ADC_FCS_LEVEL_MSB _u(19) +#define ADC_FCS_LEVEL_LSB _u(16) #define ADC_FCS_LEVEL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : ADC_FCS_OVER // Description : 1 if the FIFO has been overflowed. Write 1 to clear. -#define ADC_FCS_OVER_RESET 0x0 -#define ADC_FCS_OVER_BITS 0x00000800 -#define ADC_FCS_OVER_MSB 11 -#define ADC_FCS_OVER_LSB 11 +#define ADC_FCS_OVER_RESET _u(0x0) +#define ADC_FCS_OVER_BITS _u(0x00000800) +#define ADC_FCS_OVER_MSB _u(11) +#define ADC_FCS_OVER_LSB _u(11) #define ADC_FCS_OVER_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : ADC_FCS_UNDER // Description : 1 if the FIFO has been underflowed. Write 1 to clear. -#define ADC_FCS_UNDER_RESET 0x0 -#define ADC_FCS_UNDER_BITS 0x00000400 -#define ADC_FCS_UNDER_MSB 10 -#define ADC_FCS_UNDER_LSB 10 +#define ADC_FCS_UNDER_RESET _u(0x0) +#define ADC_FCS_UNDER_BITS _u(0x00000400) +#define ADC_FCS_UNDER_MSB _u(10) +#define ADC_FCS_UNDER_LSB _u(10) #define ADC_FCS_UNDER_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : ADC_FCS_FULL // Description : None -#define ADC_FCS_FULL_RESET 0x0 -#define ADC_FCS_FULL_BITS 0x00000200 -#define ADC_FCS_FULL_MSB 9 -#define ADC_FCS_FULL_LSB 9 +#define ADC_FCS_FULL_RESET _u(0x0) +#define ADC_FCS_FULL_BITS _u(0x00000200) +#define ADC_FCS_FULL_MSB _u(9) +#define ADC_FCS_FULL_LSB _u(9) #define ADC_FCS_FULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : ADC_FCS_EMPTY // Description : None -#define ADC_FCS_EMPTY_RESET 0x0 -#define ADC_FCS_EMPTY_BITS 0x00000100 -#define ADC_FCS_EMPTY_MSB 8 -#define ADC_FCS_EMPTY_LSB 8 +#define ADC_FCS_EMPTY_RESET _u(0x0) +#define ADC_FCS_EMPTY_BITS _u(0x00000100) +#define ADC_FCS_EMPTY_MSB _u(8) +#define ADC_FCS_EMPTY_LSB _u(8) #define ADC_FCS_EMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : ADC_FCS_DREQ_EN // Description : If 1: assert DMA requests when FIFO contains data -#define ADC_FCS_DREQ_EN_RESET 0x0 -#define ADC_FCS_DREQ_EN_BITS 0x00000008 -#define ADC_FCS_DREQ_EN_MSB 3 -#define ADC_FCS_DREQ_EN_LSB 3 +#define ADC_FCS_DREQ_EN_RESET _u(0x0) +#define ADC_FCS_DREQ_EN_BITS _u(0x00000008) +#define ADC_FCS_DREQ_EN_MSB _u(3) +#define ADC_FCS_DREQ_EN_LSB _u(3) #define ADC_FCS_DREQ_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ADC_FCS_ERR // Description : If 1: conversion error bit appears in the FIFO alongside the // result -#define ADC_FCS_ERR_RESET 0x0 -#define ADC_FCS_ERR_BITS 0x00000004 -#define ADC_FCS_ERR_MSB 2 -#define ADC_FCS_ERR_LSB 2 +#define ADC_FCS_ERR_RESET _u(0x0) +#define ADC_FCS_ERR_BITS _u(0x00000004) +#define ADC_FCS_ERR_MSB _u(2) +#define ADC_FCS_ERR_LSB _u(2) #define ADC_FCS_ERR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ADC_FCS_SHIFT // Description : If 1: FIFO results are right-shifted to be one byte in size. // Enables DMA to byte buffers. -#define ADC_FCS_SHIFT_RESET 0x0 -#define ADC_FCS_SHIFT_BITS 0x00000002 -#define ADC_FCS_SHIFT_MSB 1 -#define ADC_FCS_SHIFT_LSB 1 +#define ADC_FCS_SHIFT_RESET _u(0x0) +#define ADC_FCS_SHIFT_BITS _u(0x00000002) +#define ADC_FCS_SHIFT_MSB _u(1) +#define ADC_FCS_SHIFT_LSB _u(1) #define ADC_FCS_SHIFT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ADC_FCS_EN // Description : If 1: write result to the FIFO after each conversion. -#define ADC_FCS_EN_RESET 0x0 -#define ADC_FCS_EN_BITS 0x00000001 -#define ADC_FCS_EN_MSB 0 -#define ADC_FCS_EN_LSB 0 +#define ADC_FCS_EN_RESET _u(0x0) +#define ADC_FCS_EN_BITS _u(0x00000001) +#define ADC_FCS_EN_MSB _u(0) +#define ADC_FCS_EN_LSB _u(0) #define ADC_FCS_EN_ACCESS "RW" // ============================================================================= // Register : ADC_FIFO // Description : Conversion result FIFO -#define ADC_FIFO_OFFSET 0x0000000c -#define ADC_FIFO_BITS 0x00008fff -#define ADC_FIFO_RESET 0x00000000 +#define ADC_FIFO_OFFSET _u(0x0000000c) +#define ADC_FIFO_BITS _u(0x00008fff) +#define ADC_FIFO_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ADC_FIFO_ERR // Description : 1 if this particular sample experienced a conversion error. // Remains in the same location if the sample is shifted. #define ADC_FIFO_ERR_RESET "-" -#define ADC_FIFO_ERR_BITS 0x00008000 -#define ADC_FIFO_ERR_MSB 15 -#define ADC_FIFO_ERR_LSB 15 +#define ADC_FIFO_ERR_BITS _u(0x00008000) +#define ADC_FIFO_ERR_MSB _u(15) +#define ADC_FIFO_ERR_LSB _u(15) #define ADC_FIFO_ERR_ACCESS "RF" // ----------------------------------------------------------------------------- // Field : ADC_FIFO_VAL // Description : None #define ADC_FIFO_VAL_RESET "-" -#define ADC_FIFO_VAL_BITS 0x00000fff -#define ADC_FIFO_VAL_MSB 11 -#define ADC_FIFO_VAL_LSB 0 +#define ADC_FIFO_VAL_BITS _u(0x00000fff) +#define ADC_FIFO_VAL_MSB _u(11) +#define ADC_FIFO_VAL_LSB _u(0) #define ADC_FIFO_VAL_ACCESS "RF" // ============================================================================= // Register : ADC_DIV @@ -231,84 +231,84 @@ // at regular intervals rather than back-to-back. // The divider is reset when either of these fields are written. // Total period is 1 + INT + FRAC / 256 -#define ADC_DIV_OFFSET 0x00000010 -#define ADC_DIV_BITS 0x00ffffff -#define ADC_DIV_RESET 0x00000000 +#define ADC_DIV_OFFSET _u(0x00000010) +#define ADC_DIV_BITS _u(0x00ffffff) +#define ADC_DIV_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ADC_DIV_INT // Description : Integer part of clock divisor. -#define ADC_DIV_INT_RESET 0x0000 -#define ADC_DIV_INT_BITS 0x00ffff00 -#define ADC_DIV_INT_MSB 23 -#define ADC_DIV_INT_LSB 8 +#define ADC_DIV_INT_RESET _u(0x0000) +#define ADC_DIV_INT_BITS _u(0x00ffff00) +#define ADC_DIV_INT_MSB _u(23) +#define ADC_DIV_INT_LSB _u(8) #define ADC_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ADC_DIV_FRAC // Description : Fractional part of clock divisor. First-order delta-sigma. -#define ADC_DIV_FRAC_RESET 0x00 -#define ADC_DIV_FRAC_BITS 0x000000ff -#define ADC_DIV_FRAC_MSB 7 -#define ADC_DIV_FRAC_LSB 0 +#define ADC_DIV_FRAC_RESET _u(0x00) +#define ADC_DIV_FRAC_BITS _u(0x000000ff) +#define ADC_DIV_FRAC_MSB _u(7) +#define ADC_DIV_FRAC_LSB _u(0) #define ADC_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : ADC_INTR // Description : Raw Interrupts -#define ADC_INTR_OFFSET 0x00000014 -#define ADC_INTR_BITS 0x00000001 -#define ADC_INTR_RESET 0x00000000 +#define ADC_INTR_OFFSET _u(0x00000014) +#define ADC_INTR_BITS _u(0x00000001) +#define ADC_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ADC_INTR_FIFO // Description : Triggered when the sample FIFO reaches a certain level. // This level can be programmed via the FCS_THRESH field. -#define ADC_INTR_FIFO_RESET 0x0 -#define ADC_INTR_FIFO_BITS 0x00000001 -#define ADC_INTR_FIFO_MSB 0 -#define ADC_INTR_FIFO_LSB 0 +#define ADC_INTR_FIFO_RESET _u(0x0) +#define ADC_INTR_FIFO_BITS _u(0x00000001) +#define ADC_INTR_FIFO_MSB _u(0) +#define ADC_INTR_FIFO_LSB _u(0) #define ADC_INTR_FIFO_ACCESS "RO" // ============================================================================= // Register : ADC_INTE // Description : Interrupt Enable -#define ADC_INTE_OFFSET 0x00000018 -#define ADC_INTE_BITS 0x00000001 -#define ADC_INTE_RESET 0x00000000 +#define ADC_INTE_OFFSET _u(0x00000018) +#define ADC_INTE_BITS _u(0x00000001) +#define ADC_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ADC_INTE_FIFO // Description : Triggered when the sample FIFO reaches a certain level. // This level can be programmed via the FCS_THRESH field. -#define ADC_INTE_FIFO_RESET 0x0 -#define ADC_INTE_FIFO_BITS 0x00000001 -#define ADC_INTE_FIFO_MSB 0 -#define ADC_INTE_FIFO_LSB 0 +#define ADC_INTE_FIFO_RESET _u(0x0) +#define ADC_INTE_FIFO_BITS _u(0x00000001) +#define ADC_INTE_FIFO_MSB _u(0) +#define ADC_INTE_FIFO_LSB _u(0) #define ADC_INTE_FIFO_ACCESS "RW" // ============================================================================= // Register : ADC_INTF // Description : Interrupt Force -#define ADC_INTF_OFFSET 0x0000001c -#define ADC_INTF_BITS 0x00000001 -#define ADC_INTF_RESET 0x00000000 +#define ADC_INTF_OFFSET _u(0x0000001c) +#define ADC_INTF_BITS _u(0x00000001) +#define ADC_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ADC_INTF_FIFO // Description : Triggered when the sample FIFO reaches a certain level. // This level can be programmed via the FCS_THRESH field. -#define ADC_INTF_FIFO_RESET 0x0 -#define ADC_INTF_FIFO_BITS 0x00000001 -#define ADC_INTF_FIFO_MSB 0 -#define ADC_INTF_FIFO_LSB 0 +#define ADC_INTF_FIFO_RESET _u(0x0) +#define ADC_INTF_FIFO_BITS _u(0x00000001) +#define ADC_INTF_FIFO_MSB _u(0) +#define ADC_INTF_FIFO_LSB _u(0) #define ADC_INTF_FIFO_ACCESS "RW" // ============================================================================= // Register : ADC_INTS // Description : Interrupt status after masking & forcing -#define ADC_INTS_OFFSET 0x00000020 -#define ADC_INTS_BITS 0x00000001 -#define ADC_INTS_RESET 0x00000000 +#define ADC_INTS_OFFSET _u(0x00000020) +#define ADC_INTS_BITS _u(0x00000001) +#define ADC_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ADC_INTS_FIFO // Description : Triggered when the sample FIFO reaches a certain level. // This level can be programmed via the FCS_THRESH field. -#define ADC_INTS_FIFO_RESET 0x0 -#define ADC_INTS_FIFO_BITS 0x00000001 -#define ADC_INTS_FIFO_MSB 0 -#define ADC_INTS_FIFO_LSB 0 +#define ADC_INTS_FIFO_RESET _u(0x0) +#define ADC_INTS_FIFO_BITS _u(0x00000001) +#define ADC_INTS_FIFO_MSB _u(0) +#define ADC_INTS_FIFO_LSB _u(0) #define ADC_INTS_FIFO_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_ADC_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/addressmap.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/addressmap.h index 39451ac22..b39ab45fd 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/addressmap.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/addressmap.h @@ -6,67 +6,69 @@ #ifndef _ADDRESSMAP_H_ #define _ADDRESSMAP_H_ +#include "hardware/platform_defs.h" + // Register address offsets for atomic RMW aliases #define REG_ALIAS_RW_BITS (0x0u << 12u) #define REG_ALIAS_XOR_BITS (0x1u << 12u) #define REG_ALIAS_SET_BITS (0x2u << 12u) #define REG_ALIAS_CLR_BITS (0x3u << 12u) -#define ROM_BASE 0x00000000 -#define XIP_BASE 0x10000000 -#define XIP_MAIN_BASE 0x10000000 -#define XIP_NOALLOC_BASE 0x11000000 -#define XIP_NOCACHE_BASE 0x12000000 -#define XIP_NOCACHE_NOALLOC_BASE 0x13000000 -#define XIP_CTRL_BASE 0x14000000 -#define XIP_SRAM_BASE 0x15000000 -#define XIP_SRAM_END 0x15004000 -#define XIP_SSI_BASE 0x18000000 -#define SRAM_BASE 0x20000000 -#define SRAM_STRIPED_BASE 0x20000000 -#define SRAM_STRIPED_END 0x20040000 -#define SRAM4_BASE 0x20040000 -#define SRAM5_BASE 0x20041000 -#define SRAM_END 0x20042000 -#define SRAM0_BASE 0x21000000 -#define SRAM1_BASE 0x21010000 -#define SRAM2_BASE 0x21020000 -#define SRAM3_BASE 0x21030000 -#define SYSINFO_BASE 0x40000000 -#define SYSCFG_BASE 0x40004000 -#define CLOCKS_BASE 0x40008000 -#define RESETS_BASE 0x4000c000 -#define PSM_BASE 0x40010000 -#define IO_BANK0_BASE 0x40014000 -#define IO_QSPI_BASE 0x40018000 -#define PADS_BANK0_BASE 0x4001c000 -#define PADS_QSPI_BASE 0x40020000 -#define XOSC_BASE 0x40024000 -#define PLL_SYS_BASE 0x40028000 -#define PLL_USB_BASE 0x4002c000 -#define BUSCTRL_BASE 0x40030000 -#define UART0_BASE 0x40034000 -#define UART1_BASE 0x40038000 -#define SPI0_BASE 0x4003c000 -#define SPI1_BASE 0x40040000 -#define I2C0_BASE 0x40044000 -#define I2C1_BASE 0x40048000 -#define ADC_BASE 0x4004c000 -#define PWM_BASE 0x40050000 -#define TIMER_BASE 0x40054000 -#define WATCHDOG_BASE 0x40058000 -#define RTC_BASE 0x4005c000 -#define ROSC_BASE 0x40060000 -#define VREG_AND_CHIP_RESET_BASE 0x40064000 -#define TBMAN_BASE 0x4006c000 -#define DMA_BASE 0x50000000 -#define USBCTRL_DPRAM_BASE 0x50100000 -#define USBCTRL_BASE 0x50100000 -#define USBCTRL_REGS_BASE 0x50110000 -#define PIO0_BASE 0x50200000 -#define PIO1_BASE 0x50300000 -#define XIP_AUX_BASE 0x50400000 -#define SIO_BASE 0xd0000000 -#define PPB_BASE 0xe0000000 +#define ROM_BASE _u(0x00000000) +#define XIP_BASE _u(0x10000000) +#define XIP_MAIN_BASE _u(0x10000000) +#define XIP_NOALLOC_BASE _u(0x11000000) +#define XIP_NOCACHE_BASE _u(0x12000000) +#define XIP_NOCACHE_NOALLOC_BASE _u(0x13000000) +#define XIP_CTRL_BASE _u(0x14000000) +#define XIP_SRAM_BASE _u(0x15000000) +#define XIP_SRAM_END _u(0x15004000) +#define XIP_SSI_BASE _u(0x18000000) +#define SRAM_BASE _u(0x20000000) +#define SRAM_STRIPED_BASE _u(0x20000000) +#define SRAM_STRIPED_END _u(0x20040000) +#define SRAM4_BASE _u(0x20040000) +#define SRAM5_BASE _u(0x20041000) +#define SRAM_END _u(0x20042000) +#define SRAM0_BASE _u(0x21000000) +#define SRAM1_BASE _u(0x21010000) +#define SRAM2_BASE _u(0x21020000) +#define SRAM3_BASE _u(0x21030000) +#define SYSINFO_BASE _u(0x40000000) +#define SYSCFG_BASE _u(0x40004000) +#define CLOCKS_BASE _u(0x40008000) +#define RESETS_BASE _u(0x4000c000) +#define PSM_BASE _u(0x40010000) +#define IO_BANK0_BASE _u(0x40014000) +#define IO_QSPI_BASE _u(0x40018000) +#define PADS_BANK0_BASE _u(0x4001c000) +#define PADS_QSPI_BASE _u(0x40020000) +#define XOSC_BASE _u(0x40024000) +#define PLL_SYS_BASE _u(0x40028000) +#define PLL_USB_BASE _u(0x4002c000) +#define BUSCTRL_BASE _u(0x40030000) +#define UART0_BASE _u(0x40034000) +#define UART1_BASE _u(0x40038000) +#define SPI0_BASE _u(0x4003c000) +#define SPI1_BASE _u(0x40040000) +#define I2C0_BASE _u(0x40044000) +#define I2C1_BASE _u(0x40048000) +#define ADC_BASE _u(0x4004c000) +#define PWM_BASE _u(0x40050000) +#define TIMER_BASE _u(0x40054000) +#define WATCHDOG_BASE _u(0x40058000) +#define RTC_BASE _u(0x4005c000) +#define ROSC_BASE _u(0x40060000) +#define VREG_AND_CHIP_RESET_BASE _u(0x40064000) +#define TBMAN_BASE _u(0x4006c000) +#define DMA_BASE _u(0x50000000) +#define USBCTRL_DPRAM_BASE _u(0x50100000) +#define USBCTRL_BASE _u(0x50100000) +#define USBCTRL_REGS_BASE _u(0x50110000) +#define PIO0_BASE _u(0x50200000) +#define PIO1_BASE _u(0x50300000) +#define XIP_AUX_BASE _u(0x50400000) +#define SIO_BASE _u(0xd0000000) +#define PPB_BASE _u(0xe0000000) #endif // _ADDRESSMAP_H_ diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/busctrl.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/busctrl.h index 6c02aee54..8be0d8666 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/busctrl.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/busctrl.h @@ -15,40 +15,40 @@ // ============================================================================= // Register : BUSCTRL_BUS_PRIORITY // Description : Set the priority of each master for bus arbitration. -#define BUSCTRL_BUS_PRIORITY_OFFSET 0x00000000 -#define BUSCTRL_BUS_PRIORITY_BITS 0x00001111 -#define BUSCTRL_BUS_PRIORITY_RESET 0x00000000 +#define BUSCTRL_BUS_PRIORITY_OFFSET _u(0x00000000) +#define BUSCTRL_BUS_PRIORITY_BITS _u(0x00001111) +#define BUSCTRL_BUS_PRIORITY_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : BUSCTRL_BUS_PRIORITY_DMA_W // Description : 0 - low priority, 1 - high priority -#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET 0x0 -#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS 0x00001000 -#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB 12 -#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB 12 +#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET _u(0x0) +#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS _u(0x00001000) +#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB _u(12) +#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB _u(12) #define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : BUSCTRL_BUS_PRIORITY_DMA_R // Description : 0 - low priority, 1 - high priority -#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET 0x0 -#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS 0x00000100 -#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB 8 -#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB 8 +#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET _u(0x0) +#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS _u(0x00000100) +#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB _u(8) +#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB _u(8) #define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : BUSCTRL_BUS_PRIORITY_PROC1 // Description : 0 - low priority, 1 - high priority -#define BUSCTRL_BUS_PRIORITY_PROC1_RESET 0x0 -#define BUSCTRL_BUS_PRIORITY_PROC1_BITS 0x00000010 -#define BUSCTRL_BUS_PRIORITY_PROC1_MSB 4 -#define BUSCTRL_BUS_PRIORITY_PROC1_LSB 4 +#define BUSCTRL_BUS_PRIORITY_PROC1_RESET _u(0x0) +#define BUSCTRL_BUS_PRIORITY_PROC1_BITS _u(0x00000010) +#define BUSCTRL_BUS_PRIORITY_PROC1_MSB _u(4) +#define BUSCTRL_BUS_PRIORITY_PROC1_LSB _u(4) #define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : BUSCTRL_BUS_PRIORITY_PROC0 // Description : 0 - low priority, 1 - high priority -#define BUSCTRL_BUS_PRIORITY_PROC0_RESET 0x0 -#define BUSCTRL_BUS_PRIORITY_PROC0_BITS 0x00000001 -#define BUSCTRL_BUS_PRIORITY_PROC0_MSB 0 -#define BUSCTRL_BUS_PRIORITY_PROC0_LSB 0 +#define BUSCTRL_BUS_PRIORITY_PROC0_RESET _u(0x0) +#define BUSCTRL_BUS_PRIORITY_PROC0_BITS _u(0x00000001) +#define BUSCTRL_BUS_PRIORITY_PROC0_MSB _u(0) +#define BUSCTRL_BUS_PRIORITY_PROC0_LSB _u(0) #define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW" // ============================================================================= // Register : BUSCTRL_BUS_PRIORITY_ACK @@ -58,11 +58,11 @@ // Arbiters update their local priority when servicing a new // nonsequential access. // In normal circumstances this will happen almost immediately. -#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET 0x00000004 -#define BUSCTRL_BUS_PRIORITY_ACK_BITS 0x00000001 -#define BUSCTRL_BUS_PRIORITY_ACK_RESET 0x00000000 -#define BUSCTRL_BUS_PRIORITY_ACK_MSB 0 -#define BUSCTRL_BUS_PRIORITY_ACK_LSB 0 +#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET _u(0x00000004) +#define BUSCTRL_BUS_PRIORITY_ACK_BITS _u(0x00000001) +#define BUSCTRL_BUS_PRIORITY_ACK_RESET _u(0x00000000) +#define BUSCTRL_BUS_PRIORITY_ACK_MSB _u(0) +#define BUSCTRL_BUS_PRIORITY_ACK_LSB _u(0) #define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO" // ============================================================================= // Register : BUSCTRL_PERFCTR0 @@ -71,22 +71,63 @@ // Count some event signal from the busfabric arbiters. // Write any value to clear. Select an event to count using // PERFSEL0 -#define BUSCTRL_PERFCTR0_OFFSET 0x00000008 -#define BUSCTRL_PERFCTR0_BITS 0x00ffffff -#define BUSCTRL_PERFCTR0_RESET 0x00000000 -#define BUSCTRL_PERFCTR0_MSB 23 -#define BUSCTRL_PERFCTR0_LSB 0 +#define BUSCTRL_PERFCTR0_OFFSET _u(0x00000008) +#define BUSCTRL_PERFCTR0_BITS _u(0x00ffffff) +#define BUSCTRL_PERFCTR0_RESET _u(0x00000000) +#define BUSCTRL_PERFCTR0_MSB _u(23) +#define BUSCTRL_PERFCTR0_LSB _u(0) #define BUSCTRL_PERFCTR0_ACCESS "WC" // ============================================================================= // Register : BUSCTRL_PERFSEL0 // Description : Bus fabric performance event select for PERFCTR0 -// Select a performance event for PERFCTR0 -#define BUSCTRL_PERFSEL0_OFFSET 0x0000000c -#define BUSCTRL_PERFSEL0_BITS 0x0000001f -#define BUSCTRL_PERFSEL0_RESET 0x0000001f -#define BUSCTRL_PERFSEL0_MSB 4 -#define BUSCTRL_PERFSEL0_LSB 0 -#define BUSCTRL_PERFSEL0_ACCESS "RW" +// Select an event for PERFCTR0. Count either contested accesses, +// or all accesses, on a downstream port of the main crossbar. +// 0x00 -> apb_contested +// 0x01 -> apb +// 0x02 -> fastperi_contested +// 0x03 -> fastperi +// 0x04 -> sram5_contested +// 0x05 -> sram5 +// 0x06 -> sram4_contested +// 0x07 -> sram4 +// 0x08 -> sram3_contested +// 0x09 -> sram3 +// 0x0a -> sram2_contested +// 0x0b -> sram2 +// 0x0c -> sram1_contested +// 0x0d -> sram1 +// 0x0e -> sram0_contested +// 0x0f -> sram0 +// 0x10 -> xip_main_contested +// 0x11 -> xip_main +// 0x12 -> rom_contested +// 0x13 -> rom +#define BUSCTRL_PERFSEL0_OFFSET _u(0x0000000c) +#define BUSCTRL_PERFSEL0_BITS _u(0x0000001f) +#define BUSCTRL_PERFSEL0_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL0_MSB _u(4) +#define BUSCTRL_PERFSEL0_LSB _u(0) +#define BUSCTRL_PERFSEL0_ACCESS "RW" +#define BUSCTRL_PERFSEL0_VALUE_APB_CONTESTED _u(0x00) +#define BUSCTRL_PERFSEL0_VALUE_APB _u(0x01) +#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_CONTESTED _u(0x02) +#define BUSCTRL_PERFSEL0_VALUE_FASTPERI _u(0x03) +#define BUSCTRL_PERFSEL0_VALUE_SRAM5_CONTESTED _u(0x04) +#define BUSCTRL_PERFSEL0_VALUE_SRAM5 _u(0x05) +#define BUSCTRL_PERFSEL0_VALUE_SRAM4_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL0_VALUE_SRAM4 _u(0x07) +#define BUSCTRL_PERFSEL0_VALUE_SRAM3_CONTESTED _u(0x08) +#define BUSCTRL_PERFSEL0_VALUE_SRAM3 _u(0x09) +#define BUSCTRL_PERFSEL0_VALUE_SRAM2_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL0_VALUE_SRAM2 _u(0x0b) +#define BUSCTRL_PERFSEL0_VALUE_SRAM1_CONTESTED _u(0x0c) +#define BUSCTRL_PERFSEL0_VALUE_SRAM1 _u(0x0d) +#define BUSCTRL_PERFSEL0_VALUE_SRAM0_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL0_VALUE_SRAM0 _u(0x0f) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN_CONTESTED _u(0x10) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN _u(0x11) +#define BUSCTRL_PERFSEL0_VALUE_ROM_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL0_VALUE_ROM _u(0x13) // ============================================================================= // Register : BUSCTRL_PERFCTR1 // Description : Bus fabric performance counter 1 @@ -94,22 +135,63 @@ // Count some event signal from the busfabric arbiters. // Write any value to clear. Select an event to count using // PERFSEL1 -#define BUSCTRL_PERFCTR1_OFFSET 0x00000010 -#define BUSCTRL_PERFCTR1_BITS 0x00ffffff -#define BUSCTRL_PERFCTR1_RESET 0x00000000 -#define BUSCTRL_PERFCTR1_MSB 23 -#define BUSCTRL_PERFCTR1_LSB 0 +#define BUSCTRL_PERFCTR1_OFFSET _u(0x00000010) +#define BUSCTRL_PERFCTR1_BITS _u(0x00ffffff) +#define BUSCTRL_PERFCTR1_RESET _u(0x00000000) +#define BUSCTRL_PERFCTR1_MSB _u(23) +#define BUSCTRL_PERFCTR1_LSB _u(0) #define BUSCTRL_PERFCTR1_ACCESS "WC" // ============================================================================= // Register : BUSCTRL_PERFSEL1 // Description : Bus fabric performance event select for PERFCTR1 -// Select a performance event for PERFCTR1 -#define BUSCTRL_PERFSEL1_OFFSET 0x00000014 -#define BUSCTRL_PERFSEL1_BITS 0x0000001f -#define BUSCTRL_PERFSEL1_RESET 0x0000001f -#define BUSCTRL_PERFSEL1_MSB 4 -#define BUSCTRL_PERFSEL1_LSB 0 -#define BUSCTRL_PERFSEL1_ACCESS "RW" +// Select an event for PERFCTR1. Count either contested accesses, +// or all accesses, on a downstream port of the main crossbar. +// 0x00 -> apb_contested +// 0x01 -> apb +// 0x02 -> fastperi_contested +// 0x03 -> fastperi +// 0x04 -> sram5_contested +// 0x05 -> sram5 +// 0x06 -> sram4_contested +// 0x07 -> sram4 +// 0x08 -> sram3_contested +// 0x09 -> sram3 +// 0x0a -> sram2_contested +// 0x0b -> sram2 +// 0x0c -> sram1_contested +// 0x0d -> sram1 +// 0x0e -> sram0_contested +// 0x0f -> sram0 +// 0x10 -> xip_main_contested +// 0x11 -> xip_main +// 0x12 -> rom_contested +// 0x13 -> rom +#define BUSCTRL_PERFSEL1_OFFSET _u(0x00000014) +#define BUSCTRL_PERFSEL1_BITS _u(0x0000001f) +#define BUSCTRL_PERFSEL1_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL1_MSB _u(4) +#define BUSCTRL_PERFSEL1_LSB _u(0) +#define BUSCTRL_PERFSEL1_ACCESS "RW" +#define BUSCTRL_PERFSEL1_VALUE_APB_CONTESTED _u(0x00) +#define BUSCTRL_PERFSEL1_VALUE_APB _u(0x01) +#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_CONTESTED _u(0x02) +#define BUSCTRL_PERFSEL1_VALUE_FASTPERI _u(0x03) +#define BUSCTRL_PERFSEL1_VALUE_SRAM5_CONTESTED _u(0x04) +#define BUSCTRL_PERFSEL1_VALUE_SRAM5 _u(0x05) +#define BUSCTRL_PERFSEL1_VALUE_SRAM4_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL1_VALUE_SRAM4 _u(0x07) +#define BUSCTRL_PERFSEL1_VALUE_SRAM3_CONTESTED _u(0x08) +#define BUSCTRL_PERFSEL1_VALUE_SRAM3 _u(0x09) +#define BUSCTRL_PERFSEL1_VALUE_SRAM2_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL1_VALUE_SRAM2 _u(0x0b) +#define BUSCTRL_PERFSEL1_VALUE_SRAM1_CONTESTED _u(0x0c) +#define BUSCTRL_PERFSEL1_VALUE_SRAM1 _u(0x0d) +#define BUSCTRL_PERFSEL1_VALUE_SRAM0_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL1_VALUE_SRAM0 _u(0x0f) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN_CONTESTED _u(0x10) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN _u(0x11) +#define BUSCTRL_PERFSEL1_VALUE_ROM_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL1_VALUE_ROM _u(0x13) // ============================================================================= // Register : BUSCTRL_PERFCTR2 // Description : Bus fabric performance counter 2 @@ -117,22 +199,63 @@ // Count some event signal from the busfabric arbiters. // Write any value to clear. Select an event to count using // PERFSEL2 -#define BUSCTRL_PERFCTR2_OFFSET 0x00000018 -#define BUSCTRL_PERFCTR2_BITS 0x00ffffff -#define BUSCTRL_PERFCTR2_RESET 0x00000000 -#define BUSCTRL_PERFCTR2_MSB 23 -#define BUSCTRL_PERFCTR2_LSB 0 +#define BUSCTRL_PERFCTR2_OFFSET _u(0x00000018) +#define BUSCTRL_PERFCTR2_BITS _u(0x00ffffff) +#define BUSCTRL_PERFCTR2_RESET _u(0x00000000) +#define BUSCTRL_PERFCTR2_MSB _u(23) +#define BUSCTRL_PERFCTR2_LSB _u(0) #define BUSCTRL_PERFCTR2_ACCESS "WC" // ============================================================================= // Register : BUSCTRL_PERFSEL2 // Description : Bus fabric performance event select for PERFCTR2 -// Select a performance event for PERFCTR2 -#define BUSCTRL_PERFSEL2_OFFSET 0x0000001c -#define BUSCTRL_PERFSEL2_BITS 0x0000001f -#define BUSCTRL_PERFSEL2_RESET 0x0000001f -#define BUSCTRL_PERFSEL2_MSB 4 -#define BUSCTRL_PERFSEL2_LSB 0 -#define BUSCTRL_PERFSEL2_ACCESS "RW" +// Select an event for PERFCTR2. Count either contested accesses, +// or all accesses, on a downstream port of the main crossbar. +// 0x00 -> apb_contested +// 0x01 -> apb +// 0x02 -> fastperi_contested +// 0x03 -> fastperi +// 0x04 -> sram5_contested +// 0x05 -> sram5 +// 0x06 -> sram4_contested +// 0x07 -> sram4 +// 0x08 -> sram3_contested +// 0x09 -> sram3 +// 0x0a -> sram2_contested +// 0x0b -> sram2 +// 0x0c -> sram1_contested +// 0x0d -> sram1 +// 0x0e -> sram0_contested +// 0x0f -> sram0 +// 0x10 -> xip_main_contested +// 0x11 -> xip_main +// 0x12 -> rom_contested +// 0x13 -> rom +#define BUSCTRL_PERFSEL2_OFFSET _u(0x0000001c) +#define BUSCTRL_PERFSEL2_BITS _u(0x0000001f) +#define BUSCTRL_PERFSEL2_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL2_MSB _u(4) +#define BUSCTRL_PERFSEL2_LSB _u(0) +#define BUSCTRL_PERFSEL2_ACCESS "RW" +#define BUSCTRL_PERFSEL2_VALUE_APB_CONTESTED _u(0x00) +#define BUSCTRL_PERFSEL2_VALUE_APB _u(0x01) +#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_CONTESTED _u(0x02) +#define BUSCTRL_PERFSEL2_VALUE_FASTPERI _u(0x03) +#define BUSCTRL_PERFSEL2_VALUE_SRAM5_CONTESTED _u(0x04) +#define BUSCTRL_PERFSEL2_VALUE_SRAM5 _u(0x05) +#define BUSCTRL_PERFSEL2_VALUE_SRAM4_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL2_VALUE_SRAM4 _u(0x07) +#define BUSCTRL_PERFSEL2_VALUE_SRAM3_CONTESTED _u(0x08) +#define BUSCTRL_PERFSEL2_VALUE_SRAM3 _u(0x09) +#define BUSCTRL_PERFSEL2_VALUE_SRAM2_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL2_VALUE_SRAM2 _u(0x0b) +#define BUSCTRL_PERFSEL2_VALUE_SRAM1_CONTESTED _u(0x0c) +#define BUSCTRL_PERFSEL2_VALUE_SRAM1 _u(0x0d) +#define BUSCTRL_PERFSEL2_VALUE_SRAM0_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL2_VALUE_SRAM0 _u(0x0f) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN_CONTESTED _u(0x10) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN _u(0x11) +#define BUSCTRL_PERFSEL2_VALUE_ROM_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL2_VALUE_ROM _u(0x13) // ============================================================================= // Register : BUSCTRL_PERFCTR3 // Description : Bus fabric performance counter 3 @@ -140,21 +263,62 @@ // Count some event signal from the busfabric arbiters. // Write any value to clear. Select an event to count using // PERFSEL3 -#define BUSCTRL_PERFCTR3_OFFSET 0x00000020 -#define BUSCTRL_PERFCTR3_BITS 0x00ffffff -#define BUSCTRL_PERFCTR3_RESET 0x00000000 -#define BUSCTRL_PERFCTR3_MSB 23 -#define BUSCTRL_PERFCTR3_LSB 0 +#define BUSCTRL_PERFCTR3_OFFSET _u(0x00000020) +#define BUSCTRL_PERFCTR3_BITS _u(0x00ffffff) +#define BUSCTRL_PERFCTR3_RESET _u(0x00000000) +#define BUSCTRL_PERFCTR3_MSB _u(23) +#define BUSCTRL_PERFCTR3_LSB _u(0) #define BUSCTRL_PERFCTR3_ACCESS "WC" // ============================================================================= // Register : BUSCTRL_PERFSEL3 // Description : Bus fabric performance event select for PERFCTR3 -// Select a performance event for PERFCTR3 -#define BUSCTRL_PERFSEL3_OFFSET 0x00000024 -#define BUSCTRL_PERFSEL3_BITS 0x0000001f -#define BUSCTRL_PERFSEL3_RESET 0x0000001f -#define BUSCTRL_PERFSEL3_MSB 4 -#define BUSCTRL_PERFSEL3_LSB 0 -#define BUSCTRL_PERFSEL3_ACCESS "RW" +// Select an event for PERFCTR3. Count either contested accesses, +// or all accesses, on a downstream port of the main crossbar. +// 0x00 -> apb_contested +// 0x01 -> apb +// 0x02 -> fastperi_contested +// 0x03 -> fastperi +// 0x04 -> sram5_contested +// 0x05 -> sram5 +// 0x06 -> sram4_contested +// 0x07 -> sram4 +// 0x08 -> sram3_contested +// 0x09 -> sram3 +// 0x0a -> sram2_contested +// 0x0b -> sram2 +// 0x0c -> sram1_contested +// 0x0d -> sram1 +// 0x0e -> sram0_contested +// 0x0f -> sram0 +// 0x10 -> xip_main_contested +// 0x11 -> xip_main +// 0x12 -> rom_contested +// 0x13 -> rom +#define BUSCTRL_PERFSEL3_OFFSET _u(0x00000024) +#define BUSCTRL_PERFSEL3_BITS _u(0x0000001f) +#define BUSCTRL_PERFSEL3_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL3_MSB _u(4) +#define BUSCTRL_PERFSEL3_LSB _u(0) +#define BUSCTRL_PERFSEL3_ACCESS "RW" +#define BUSCTRL_PERFSEL3_VALUE_APB_CONTESTED _u(0x00) +#define BUSCTRL_PERFSEL3_VALUE_APB _u(0x01) +#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_CONTESTED _u(0x02) +#define BUSCTRL_PERFSEL3_VALUE_FASTPERI _u(0x03) +#define BUSCTRL_PERFSEL3_VALUE_SRAM5_CONTESTED _u(0x04) +#define BUSCTRL_PERFSEL3_VALUE_SRAM5 _u(0x05) +#define BUSCTRL_PERFSEL3_VALUE_SRAM4_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL3_VALUE_SRAM4 _u(0x07) +#define BUSCTRL_PERFSEL3_VALUE_SRAM3_CONTESTED _u(0x08) +#define BUSCTRL_PERFSEL3_VALUE_SRAM3 _u(0x09) +#define BUSCTRL_PERFSEL3_VALUE_SRAM2_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL3_VALUE_SRAM2 _u(0x0b) +#define BUSCTRL_PERFSEL3_VALUE_SRAM1_CONTESTED _u(0x0c) +#define BUSCTRL_PERFSEL3_VALUE_SRAM1 _u(0x0d) +#define BUSCTRL_PERFSEL3_VALUE_SRAM0_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL3_VALUE_SRAM0 _u(0x0f) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN_CONTESTED _u(0x10) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN _u(0x11) +#define BUSCTRL_PERFSEL3_VALUE_ROM_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL3_VALUE_ROM _u(0x13) // ============================================================================= #endif // HARDWARE_REGS_BUSCTRL_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/clocks.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/clocks.h index 1b44490f7..c0d2eaba4 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/clocks.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/clocks.h @@ -14,52 +14,52 @@ // ============================================================================= // Register : CLOCKS_CLK_GPOUT0_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_GPOUT0_CTRL_OFFSET 0x00000000 -#define CLOCKS_CLK_GPOUT0_CTRL_BITS 0x00131de0 -#define CLOCKS_CLK_GPOUT0_CTRL_RESET 0x00000000 +#define CLOCKS_CLK_GPOUT0_CTRL_OFFSET _u(0x00000000) +#define CLOCKS_CLK_GPOUT0_CTRL_BITS _u(0x00131de0) +#define CLOCKS_CLK_GPOUT0_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT0_CTRL_NUDGE // Description : An edge on this signal shifts the phase of the output by 1 // cycle of the input clock // This can be done at any time -#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_RESET 0x0 -#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_BITS 0x00100000 -#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_MSB 20 -#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_LSB _u(20) #define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT0_CTRL_PHASE // Description : This delays the enable signal by up to 3 cycles of the input // clock // This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_RESET 0x0 -#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_BITS 0x00030000 -#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_MSB 17 -#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_LSB _u(16) #define CLOCKS_CLK_GPOUT0_CTRL_PHASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT0_CTRL_DC50 // Description : Enables duty cycle correction for odd divisors -#define CLOCKS_CLK_GPOUT0_CTRL_DC50_RESET 0x0 -#define CLOCKS_CLK_GPOUT0_CTRL_DC50_BITS 0x00001000 -#define CLOCKS_CLK_GPOUT0_CTRL_DC50_MSB 12 -#define CLOCKS_CLK_GPOUT0_CTRL_DC50_LSB 12 +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_BITS _u(0x00001000) +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_MSB _u(12) +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_LSB _u(12) #define CLOCKS_CLK_GPOUT0_CTRL_DC50_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT0_CTRL_ENABLE // Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_RESET 0x0 -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS 0x00000800 -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_MSB 11 -#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_LSB _u(11) #define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT0_CTRL_KILL // Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_GPOUT0_CTRL_KILL_RESET 0x0 -#define CLOCKS_CLK_GPOUT0_CTRL_KILL_BITS 0x00000400 -#define CLOCKS_CLK_GPOUT0_CTRL_KILL_MSB 10 -#define CLOCKS_CLK_GPOUT0_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_LSB _u(10) #define CLOCKS_CLK_GPOUT0_CTRL_KILL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT0_CTRL_AUXSRC @@ -75,102 +75,106 @@ // 0x8 -> clk_adc // 0x9 -> clk_rtc // 0xa -> clk_ref -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_RESET 0x0 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS 0x000001e0 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MSB 8 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB _u(5) #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x0 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x1 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x2 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x3 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_ROSC_CLKSRC 0x4 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x5 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_SYS 0x6 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_USB 0x7 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_ADC 0x8 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_RTC 0x9 -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_REF 0xa +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x4) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) // ============================================================================= // Register : CLOCKS_CLK_GPOUT0_DIV // Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_GPOUT0_DIV_OFFSET 0x00000004 -#define CLOCKS_CLK_GPOUT0_DIV_BITS 0xffffffff -#define CLOCKS_CLK_GPOUT0_DIV_RESET 0x00000100 +#define CLOCKS_CLK_GPOUT0_DIV_OFFSET _u(0x00000004) +#define CLOCKS_CLK_GPOUT0_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT0_DIV_RESET _u(0x00000100) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT0_DIV_INT // Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_GPOUT0_DIV_INT_RESET 0x000001 -#define CLOCKS_CLK_GPOUT0_DIV_INT_BITS 0xffffff00 -#define CLOCKS_CLK_GPOUT0_DIV_INT_MSB 31 -#define CLOCKS_CLK_GPOUT0_DIV_INT_LSB 8 +#define CLOCKS_CLK_GPOUT0_DIV_INT_RESET _u(0x000001) +#define CLOCKS_CLK_GPOUT0_DIV_INT_BITS _u(0xffffff00) +#define CLOCKS_CLK_GPOUT0_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_GPOUT0_DIV_INT_LSB _u(8) #define CLOCKS_CLK_GPOUT0_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT0_DIV_FRAC // Description : Fractional component of the divisor -#define CLOCKS_CLK_GPOUT0_DIV_FRAC_RESET 0x00 -#define CLOCKS_CLK_GPOUT0_DIV_FRAC_BITS 0x000000ff -#define CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB 7 -#define CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_RESET _u(0x00) +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_BITS _u(0x000000ff) +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB _u(7) +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB _u(0) #define CLOCKS_CLK_GPOUT0_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_GPOUT0_SELECTED -// Description : Indicates which src is currently selected (one-hot) -#define CLOCKS_CLK_GPOUT0_SELECTED_OFFSET 0x00000008 -#define CLOCKS_CLK_GPOUT0_SELECTED_BITS 0xffffffff -#define CLOCKS_CLK_GPOUT0_SELECTED_RESET 0x00000001 -#define CLOCKS_CLK_GPOUT0_SELECTED_MSB 31 -#define CLOCKS_CLK_GPOUT0_SELECTED_LSB 0 +// Description : Indicates which SRC is currently selected by the glitchless mux +// (one-hot). +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_GPOUT0_SELECTED_OFFSET _u(0x00000008) +#define CLOCKS_CLK_GPOUT0_SELECTED_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT0_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_GPOUT0_SELECTED_MSB _u(31) +#define CLOCKS_CLK_GPOUT0_SELECTED_LSB _u(0) #define CLOCKS_CLK_GPOUT0_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_GPOUT1_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_GPOUT1_CTRL_OFFSET 0x0000000c -#define CLOCKS_CLK_GPOUT1_CTRL_BITS 0x00131de0 -#define CLOCKS_CLK_GPOUT1_CTRL_RESET 0x00000000 +#define CLOCKS_CLK_GPOUT1_CTRL_OFFSET _u(0x0000000c) +#define CLOCKS_CLK_GPOUT1_CTRL_BITS _u(0x00131de0) +#define CLOCKS_CLK_GPOUT1_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT1_CTRL_NUDGE // Description : An edge on this signal shifts the phase of the output by 1 // cycle of the input clock // This can be done at any time -#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_RESET 0x0 -#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_BITS 0x00100000 -#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_MSB 20 -#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_LSB _u(20) #define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT1_CTRL_PHASE // Description : This delays the enable signal by up to 3 cycles of the input // clock // This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_RESET 0x0 -#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_BITS 0x00030000 -#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_MSB 17 -#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_LSB _u(16) #define CLOCKS_CLK_GPOUT1_CTRL_PHASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT1_CTRL_DC50 // Description : Enables duty cycle correction for odd divisors -#define CLOCKS_CLK_GPOUT1_CTRL_DC50_RESET 0x0 -#define CLOCKS_CLK_GPOUT1_CTRL_DC50_BITS 0x00001000 -#define CLOCKS_CLK_GPOUT1_CTRL_DC50_MSB 12 -#define CLOCKS_CLK_GPOUT1_CTRL_DC50_LSB 12 +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_BITS _u(0x00001000) +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_MSB _u(12) +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_LSB _u(12) #define CLOCKS_CLK_GPOUT1_CTRL_DC50_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT1_CTRL_ENABLE // Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_RESET 0x0 -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_BITS 0x00000800 -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_MSB 11 -#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_LSB _u(11) #define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT1_CTRL_KILL // Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_GPOUT1_CTRL_KILL_RESET 0x0 -#define CLOCKS_CLK_GPOUT1_CTRL_KILL_BITS 0x00000400 -#define CLOCKS_CLK_GPOUT1_CTRL_KILL_MSB 10 -#define CLOCKS_CLK_GPOUT1_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_LSB _u(10) #define CLOCKS_CLK_GPOUT1_CTRL_KILL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT1_CTRL_AUXSRC @@ -186,102 +190,106 @@ // 0x8 -> clk_adc // 0x9 -> clk_rtc // 0xa -> clk_ref -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_RESET 0x0 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_BITS 0x000001e0 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MSB 8 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_LSB _u(5) #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x0 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x1 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x2 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x3 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_ROSC_CLKSRC 0x4 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x5 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_SYS 0x6 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_USB 0x7 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_ADC 0x8 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_RTC 0x9 -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_REF 0xa +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x4) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) // ============================================================================= // Register : CLOCKS_CLK_GPOUT1_DIV // Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_GPOUT1_DIV_OFFSET 0x00000010 -#define CLOCKS_CLK_GPOUT1_DIV_BITS 0xffffffff -#define CLOCKS_CLK_GPOUT1_DIV_RESET 0x00000100 +#define CLOCKS_CLK_GPOUT1_DIV_OFFSET _u(0x00000010) +#define CLOCKS_CLK_GPOUT1_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT1_DIV_RESET _u(0x00000100) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT1_DIV_INT // Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_GPOUT1_DIV_INT_RESET 0x000001 -#define CLOCKS_CLK_GPOUT1_DIV_INT_BITS 0xffffff00 -#define CLOCKS_CLK_GPOUT1_DIV_INT_MSB 31 -#define CLOCKS_CLK_GPOUT1_DIV_INT_LSB 8 +#define CLOCKS_CLK_GPOUT1_DIV_INT_RESET _u(0x000001) +#define CLOCKS_CLK_GPOUT1_DIV_INT_BITS _u(0xffffff00) +#define CLOCKS_CLK_GPOUT1_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_GPOUT1_DIV_INT_LSB _u(8) #define CLOCKS_CLK_GPOUT1_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT1_DIV_FRAC // Description : Fractional component of the divisor -#define CLOCKS_CLK_GPOUT1_DIV_FRAC_RESET 0x00 -#define CLOCKS_CLK_GPOUT1_DIV_FRAC_BITS 0x000000ff -#define CLOCKS_CLK_GPOUT1_DIV_FRAC_MSB 7 -#define CLOCKS_CLK_GPOUT1_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_RESET _u(0x00) +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_BITS _u(0x000000ff) +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_MSB _u(7) +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_LSB _u(0) #define CLOCKS_CLK_GPOUT1_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_GPOUT1_SELECTED -// Description : Indicates which src is currently selected (one-hot) -#define CLOCKS_CLK_GPOUT1_SELECTED_OFFSET 0x00000014 -#define CLOCKS_CLK_GPOUT1_SELECTED_BITS 0xffffffff -#define CLOCKS_CLK_GPOUT1_SELECTED_RESET 0x00000001 -#define CLOCKS_CLK_GPOUT1_SELECTED_MSB 31 -#define CLOCKS_CLK_GPOUT1_SELECTED_LSB 0 +// Description : Indicates which SRC is currently selected by the glitchless mux +// (one-hot). +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_GPOUT1_SELECTED_OFFSET _u(0x00000014) +#define CLOCKS_CLK_GPOUT1_SELECTED_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT1_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_GPOUT1_SELECTED_MSB _u(31) +#define CLOCKS_CLK_GPOUT1_SELECTED_LSB _u(0) #define CLOCKS_CLK_GPOUT1_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_GPOUT2_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_GPOUT2_CTRL_OFFSET 0x00000018 -#define CLOCKS_CLK_GPOUT2_CTRL_BITS 0x00131de0 -#define CLOCKS_CLK_GPOUT2_CTRL_RESET 0x00000000 +#define CLOCKS_CLK_GPOUT2_CTRL_OFFSET _u(0x00000018) +#define CLOCKS_CLK_GPOUT2_CTRL_BITS _u(0x00131de0) +#define CLOCKS_CLK_GPOUT2_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT2_CTRL_NUDGE // Description : An edge on this signal shifts the phase of the output by 1 // cycle of the input clock // This can be done at any time -#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_RESET 0x0 -#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_BITS 0x00100000 -#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_MSB 20 -#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_LSB _u(20) #define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT2_CTRL_PHASE // Description : This delays the enable signal by up to 3 cycles of the input // clock // This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_RESET 0x0 -#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_BITS 0x00030000 -#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_MSB 17 -#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_LSB _u(16) #define CLOCKS_CLK_GPOUT2_CTRL_PHASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT2_CTRL_DC50 // Description : Enables duty cycle correction for odd divisors -#define CLOCKS_CLK_GPOUT2_CTRL_DC50_RESET 0x0 -#define CLOCKS_CLK_GPOUT2_CTRL_DC50_BITS 0x00001000 -#define CLOCKS_CLK_GPOUT2_CTRL_DC50_MSB 12 -#define CLOCKS_CLK_GPOUT2_CTRL_DC50_LSB 12 +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_BITS _u(0x00001000) +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_MSB _u(12) +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_LSB _u(12) #define CLOCKS_CLK_GPOUT2_CTRL_DC50_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT2_CTRL_ENABLE // Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_RESET 0x0 -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_BITS 0x00000800 -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_MSB 11 -#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_LSB _u(11) #define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT2_CTRL_KILL // Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_GPOUT2_CTRL_KILL_RESET 0x0 -#define CLOCKS_CLK_GPOUT2_CTRL_KILL_BITS 0x00000400 -#define CLOCKS_CLK_GPOUT2_CTRL_KILL_MSB 10 -#define CLOCKS_CLK_GPOUT2_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_LSB _u(10) #define CLOCKS_CLK_GPOUT2_CTRL_KILL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT2_CTRL_AUXSRC @@ -297,102 +305,106 @@ // 0x8 -> clk_adc // 0x9 -> clk_rtc // 0xa -> clk_ref -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_RESET 0x0 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_BITS 0x000001e0 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MSB 8 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_LSB _u(5) #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x0 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x1 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x2 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x3 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x4 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x5 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_SYS 0x6 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_USB 0x7 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_ADC 0x8 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_RTC 0x9 -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_REF 0xa +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x4) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) // ============================================================================= // Register : CLOCKS_CLK_GPOUT2_DIV // Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_GPOUT2_DIV_OFFSET 0x0000001c -#define CLOCKS_CLK_GPOUT2_DIV_BITS 0xffffffff -#define CLOCKS_CLK_GPOUT2_DIV_RESET 0x00000100 +#define CLOCKS_CLK_GPOUT2_DIV_OFFSET _u(0x0000001c) +#define CLOCKS_CLK_GPOUT2_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT2_DIV_RESET _u(0x00000100) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT2_DIV_INT // Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_GPOUT2_DIV_INT_RESET 0x000001 -#define CLOCKS_CLK_GPOUT2_DIV_INT_BITS 0xffffff00 -#define CLOCKS_CLK_GPOUT2_DIV_INT_MSB 31 -#define CLOCKS_CLK_GPOUT2_DIV_INT_LSB 8 +#define CLOCKS_CLK_GPOUT2_DIV_INT_RESET _u(0x000001) +#define CLOCKS_CLK_GPOUT2_DIV_INT_BITS _u(0xffffff00) +#define CLOCKS_CLK_GPOUT2_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_GPOUT2_DIV_INT_LSB _u(8) #define CLOCKS_CLK_GPOUT2_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT2_DIV_FRAC // Description : Fractional component of the divisor -#define CLOCKS_CLK_GPOUT2_DIV_FRAC_RESET 0x00 -#define CLOCKS_CLK_GPOUT2_DIV_FRAC_BITS 0x000000ff -#define CLOCKS_CLK_GPOUT2_DIV_FRAC_MSB 7 -#define CLOCKS_CLK_GPOUT2_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_RESET _u(0x00) +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_BITS _u(0x000000ff) +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_MSB _u(7) +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_LSB _u(0) #define CLOCKS_CLK_GPOUT2_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_GPOUT2_SELECTED -// Description : Indicates which src is currently selected (one-hot) -#define CLOCKS_CLK_GPOUT2_SELECTED_OFFSET 0x00000020 -#define CLOCKS_CLK_GPOUT2_SELECTED_BITS 0xffffffff -#define CLOCKS_CLK_GPOUT2_SELECTED_RESET 0x00000001 -#define CLOCKS_CLK_GPOUT2_SELECTED_MSB 31 -#define CLOCKS_CLK_GPOUT2_SELECTED_LSB 0 +// Description : Indicates which SRC is currently selected by the glitchless mux +// (one-hot). +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_GPOUT2_SELECTED_OFFSET _u(0x00000020) +#define CLOCKS_CLK_GPOUT2_SELECTED_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT2_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_GPOUT2_SELECTED_MSB _u(31) +#define CLOCKS_CLK_GPOUT2_SELECTED_LSB _u(0) #define CLOCKS_CLK_GPOUT2_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_GPOUT3_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_GPOUT3_CTRL_OFFSET 0x00000024 -#define CLOCKS_CLK_GPOUT3_CTRL_BITS 0x00131de0 -#define CLOCKS_CLK_GPOUT3_CTRL_RESET 0x00000000 +#define CLOCKS_CLK_GPOUT3_CTRL_OFFSET _u(0x00000024) +#define CLOCKS_CLK_GPOUT3_CTRL_BITS _u(0x00131de0) +#define CLOCKS_CLK_GPOUT3_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT3_CTRL_NUDGE // Description : An edge on this signal shifts the phase of the output by 1 // cycle of the input clock // This can be done at any time -#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_RESET 0x0 -#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_BITS 0x00100000 -#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_MSB 20 -#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_LSB _u(20) #define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT3_CTRL_PHASE // Description : This delays the enable signal by up to 3 cycles of the input // clock // This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_RESET 0x0 -#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_BITS 0x00030000 -#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_MSB 17 -#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_LSB _u(16) #define CLOCKS_CLK_GPOUT3_CTRL_PHASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT3_CTRL_DC50 // Description : Enables duty cycle correction for odd divisors -#define CLOCKS_CLK_GPOUT3_CTRL_DC50_RESET 0x0 -#define CLOCKS_CLK_GPOUT3_CTRL_DC50_BITS 0x00001000 -#define CLOCKS_CLK_GPOUT3_CTRL_DC50_MSB 12 -#define CLOCKS_CLK_GPOUT3_CTRL_DC50_LSB 12 +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_BITS _u(0x00001000) +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_MSB _u(12) +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_LSB _u(12) #define CLOCKS_CLK_GPOUT3_CTRL_DC50_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT3_CTRL_ENABLE // Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_RESET 0x0 -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_BITS 0x00000800 -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_MSB 11 -#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_LSB _u(11) #define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT3_CTRL_KILL // Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_GPOUT3_CTRL_KILL_RESET 0x0 -#define CLOCKS_CLK_GPOUT3_CTRL_KILL_BITS 0x00000400 -#define CLOCKS_CLK_GPOUT3_CTRL_KILL_MSB 10 -#define CLOCKS_CLK_GPOUT3_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_LSB _u(10) #define CLOCKS_CLK_GPOUT3_CTRL_KILL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT3_CTRL_AUXSRC @@ -408,73 +420,77 @@ // 0x8 -> clk_adc // 0x9 -> clk_rtc // 0xa -> clk_ref -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_RESET 0x0 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_BITS 0x000001e0 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MSB 8 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_LSB _u(5) #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x0 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x1 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x2 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x3 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x4 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x5 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_SYS 0x6 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_USB 0x7 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_ADC 0x8 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_RTC 0x9 -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_REF 0xa +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x4) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) // ============================================================================= // Register : CLOCKS_CLK_GPOUT3_DIV // Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_GPOUT3_DIV_OFFSET 0x00000028 -#define CLOCKS_CLK_GPOUT3_DIV_BITS 0xffffffff -#define CLOCKS_CLK_GPOUT3_DIV_RESET 0x00000100 +#define CLOCKS_CLK_GPOUT3_DIV_OFFSET _u(0x00000028) +#define CLOCKS_CLK_GPOUT3_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT3_DIV_RESET _u(0x00000100) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT3_DIV_INT // Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_GPOUT3_DIV_INT_RESET 0x000001 -#define CLOCKS_CLK_GPOUT3_DIV_INT_BITS 0xffffff00 -#define CLOCKS_CLK_GPOUT3_DIV_INT_MSB 31 -#define CLOCKS_CLK_GPOUT3_DIV_INT_LSB 8 +#define CLOCKS_CLK_GPOUT3_DIV_INT_RESET _u(0x000001) +#define CLOCKS_CLK_GPOUT3_DIV_INT_BITS _u(0xffffff00) +#define CLOCKS_CLK_GPOUT3_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_GPOUT3_DIV_INT_LSB _u(8) #define CLOCKS_CLK_GPOUT3_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_GPOUT3_DIV_FRAC // Description : Fractional component of the divisor -#define CLOCKS_CLK_GPOUT3_DIV_FRAC_RESET 0x00 -#define CLOCKS_CLK_GPOUT3_DIV_FRAC_BITS 0x000000ff -#define CLOCKS_CLK_GPOUT3_DIV_FRAC_MSB 7 -#define CLOCKS_CLK_GPOUT3_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_RESET _u(0x00) +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_BITS _u(0x000000ff) +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_MSB _u(7) +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_LSB _u(0) #define CLOCKS_CLK_GPOUT3_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_GPOUT3_SELECTED -// Description : Indicates which src is currently selected (one-hot) -#define CLOCKS_CLK_GPOUT3_SELECTED_OFFSET 0x0000002c -#define CLOCKS_CLK_GPOUT3_SELECTED_BITS 0xffffffff -#define CLOCKS_CLK_GPOUT3_SELECTED_RESET 0x00000001 -#define CLOCKS_CLK_GPOUT3_SELECTED_MSB 31 -#define CLOCKS_CLK_GPOUT3_SELECTED_LSB 0 +// Description : Indicates which SRC is currently selected by the glitchless mux +// (one-hot). +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_GPOUT3_SELECTED_OFFSET _u(0x0000002c) +#define CLOCKS_CLK_GPOUT3_SELECTED_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT3_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_GPOUT3_SELECTED_MSB _u(31) +#define CLOCKS_CLK_GPOUT3_SELECTED_LSB _u(0) #define CLOCKS_CLK_GPOUT3_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_REF_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_REF_CTRL_OFFSET 0x00000030 -#define CLOCKS_CLK_REF_CTRL_BITS 0x00000063 -#define CLOCKS_CLK_REF_CTRL_RESET 0x00000000 +#define CLOCKS_CLK_REF_CTRL_OFFSET _u(0x00000030) +#define CLOCKS_CLK_REF_CTRL_BITS _u(0x00000063) +#define CLOCKS_CLK_REF_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_REF_CTRL_AUXSRC // Description : Selects the auxiliary clock source, will glitch when switching // 0x0 -> clksrc_pll_usb // 0x1 -> clksrc_gpin0 // 0x2 -> clksrc_gpin1 -#define CLOCKS_CLK_REF_CTRL_AUXSRC_RESET 0x0 -#define CLOCKS_CLK_REF_CTRL_AUXSRC_BITS 0x00000060 -#define CLOCKS_CLK_REF_CTRL_AUXSRC_MSB 6 -#define CLOCKS_CLK_REF_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_REF_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_BITS _u(0x00000060) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_MSB _u(6) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_LSB _u(5) #define CLOCKS_CLK_REF_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x0 -#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x1 -#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x2 +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_REF_CTRL_SRC // Description : Selects the clock source glitchlessly, can be changed @@ -483,42 +499,51 @@ // 0x1 -> clksrc_clk_ref_aux // 0x2 -> xosc_clksrc #define CLOCKS_CLK_REF_CTRL_SRC_RESET "-" -#define CLOCKS_CLK_REF_CTRL_SRC_BITS 0x00000003 -#define CLOCKS_CLK_REF_CTRL_SRC_MSB 1 -#define CLOCKS_CLK_REF_CTRL_SRC_LSB 0 +#define CLOCKS_CLK_REF_CTRL_SRC_BITS _u(0x00000003) +#define CLOCKS_CLK_REF_CTRL_SRC_MSB _u(1) +#define CLOCKS_CLK_REF_CTRL_SRC_LSB _u(0) #define CLOCKS_CLK_REF_CTRL_SRC_ACCESS "RW" -#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH 0x0 -#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX 0x1 -#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC 0x2 +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH _u(0x0) +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX _u(0x1) +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC _u(0x2) // ============================================================================= // Register : CLOCKS_CLK_REF_DIV // Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_REF_DIV_OFFSET 0x00000034 -#define CLOCKS_CLK_REF_DIV_BITS 0x00000300 -#define CLOCKS_CLK_REF_DIV_RESET 0x00000100 +#define CLOCKS_CLK_REF_DIV_OFFSET _u(0x00000034) +#define CLOCKS_CLK_REF_DIV_BITS _u(0x00000300) +#define CLOCKS_CLK_REF_DIV_RESET _u(0x00000100) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_REF_DIV_INT // Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_REF_DIV_INT_RESET 0x1 -#define CLOCKS_CLK_REF_DIV_INT_BITS 0x00000300 -#define CLOCKS_CLK_REF_DIV_INT_MSB 9 -#define CLOCKS_CLK_REF_DIV_INT_LSB 8 +#define CLOCKS_CLK_REF_DIV_INT_RESET _u(0x1) +#define CLOCKS_CLK_REF_DIV_INT_BITS _u(0x00000300) +#define CLOCKS_CLK_REF_DIV_INT_MSB _u(9) +#define CLOCKS_CLK_REF_DIV_INT_LSB _u(8) #define CLOCKS_CLK_REF_DIV_INT_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_REF_SELECTED -// Description : Indicates which src is currently selected (one-hot) -#define CLOCKS_CLK_REF_SELECTED_OFFSET 0x00000038 -#define CLOCKS_CLK_REF_SELECTED_BITS 0xffffffff -#define CLOCKS_CLK_REF_SELECTED_RESET 0x00000001 -#define CLOCKS_CLK_REF_SELECTED_MSB 31 -#define CLOCKS_CLK_REF_SELECTED_LSB 0 +// Description : Indicates which SRC is currently selected by the glitchless mux +// (one-hot). +// The glitchless multiplexer does not switch instantaneously (to +// avoid glitches), so software should poll this register to wait +// for the switch to complete. This register contains one decoded +// bit for each of the clock sources enumerated in the CTRL SRC +// field. At most one of these bits will be set at any time, +// indicating that clock is currently present at the output of the +// glitchless mux. Whilst switching is in progress, this register +// may briefly show all-0s. +#define CLOCKS_CLK_REF_SELECTED_OFFSET _u(0x00000038) +#define CLOCKS_CLK_REF_SELECTED_BITS _u(0xffffffff) +#define CLOCKS_CLK_REF_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_REF_SELECTED_MSB _u(31) +#define CLOCKS_CLK_REF_SELECTED_LSB _u(0) #define CLOCKS_CLK_REF_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_SYS_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_SYS_CTRL_OFFSET 0x0000003c -#define CLOCKS_CLK_SYS_CTRL_BITS 0x000000e1 -#define CLOCKS_CLK_SYS_CTRL_RESET 0x00000000 +#define CLOCKS_CLK_SYS_CTRL_OFFSET _u(0x0000003c) +#define CLOCKS_CLK_SYS_CTRL_BITS _u(0x000000e1) +#define CLOCKS_CLK_SYS_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_SYS_CTRL_AUXSRC // Description : Selects the auxiliary clock source, will glitch when switching @@ -528,82 +553,91 @@ // 0x3 -> xosc_clksrc // 0x4 -> clksrc_gpin0 // 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET 0x0 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS 0x000000e0 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_MSB 7 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB _u(5) #define CLOCKS_CLK_SYS_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x0 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x1 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC 0x2 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x3 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x4 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x5 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x1) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x2) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_SYS_CTRL_SRC // Description : Selects the clock source glitchlessly, can be changed // on-the-fly // 0x0 -> clk_ref // 0x1 -> clksrc_clk_sys_aux -#define CLOCKS_CLK_SYS_CTRL_SRC_RESET 0x0 -#define CLOCKS_CLK_SYS_CTRL_SRC_BITS 0x00000001 -#define CLOCKS_CLK_SYS_CTRL_SRC_MSB 0 -#define CLOCKS_CLK_SYS_CTRL_SRC_LSB 0 +#define CLOCKS_CLK_SYS_CTRL_SRC_RESET _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_SRC_BITS _u(0x00000001) +#define CLOCKS_CLK_SYS_CTRL_SRC_MSB _u(0) +#define CLOCKS_CLK_SYS_CTRL_SRC_LSB _u(0) #define CLOCKS_CLK_SYS_CTRL_SRC_ACCESS "RW" -#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF 0x0 -#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX 0x1 +#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX _u(0x1) // ============================================================================= // Register : CLOCKS_CLK_SYS_DIV // Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_SYS_DIV_OFFSET 0x00000040 -#define CLOCKS_CLK_SYS_DIV_BITS 0xffffffff -#define CLOCKS_CLK_SYS_DIV_RESET 0x00000100 +#define CLOCKS_CLK_SYS_DIV_OFFSET _u(0x00000040) +#define CLOCKS_CLK_SYS_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_SYS_DIV_RESET _u(0x00000100) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_SYS_DIV_INT // Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_SYS_DIV_INT_RESET 0x000001 -#define CLOCKS_CLK_SYS_DIV_INT_BITS 0xffffff00 -#define CLOCKS_CLK_SYS_DIV_INT_MSB 31 -#define CLOCKS_CLK_SYS_DIV_INT_LSB 8 +#define CLOCKS_CLK_SYS_DIV_INT_RESET _u(0x000001) +#define CLOCKS_CLK_SYS_DIV_INT_BITS _u(0xffffff00) +#define CLOCKS_CLK_SYS_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_SYS_DIV_INT_LSB _u(8) #define CLOCKS_CLK_SYS_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_SYS_DIV_FRAC // Description : Fractional component of the divisor -#define CLOCKS_CLK_SYS_DIV_FRAC_RESET 0x00 -#define CLOCKS_CLK_SYS_DIV_FRAC_BITS 0x000000ff -#define CLOCKS_CLK_SYS_DIV_FRAC_MSB 7 -#define CLOCKS_CLK_SYS_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_SYS_DIV_FRAC_RESET _u(0x00) +#define CLOCKS_CLK_SYS_DIV_FRAC_BITS _u(0x000000ff) +#define CLOCKS_CLK_SYS_DIV_FRAC_MSB _u(7) +#define CLOCKS_CLK_SYS_DIV_FRAC_LSB _u(0) #define CLOCKS_CLK_SYS_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_SYS_SELECTED -// Description : Indicates which src is currently selected (one-hot) -#define CLOCKS_CLK_SYS_SELECTED_OFFSET 0x00000044 -#define CLOCKS_CLK_SYS_SELECTED_BITS 0xffffffff -#define CLOCKS_CLK_SYS_SELECTED_RESET 0x00000001 -#define CLOCKS_CLK_SYS_SELECTED_MSB 31 -#define CLOCKS_CLK_SYS_SELECTED_LSB 0 +// Description : Indicates which SRC is currently selected by the glitchless mux +// (one-hot). +// The glitchless multiplexer does not switch instantaneously (to +// avoid glitches), so software should poll this register to wait +// for the switch to complete. This register contains one decoded +// bit for each of the clock sources enumerated in the CTRL SRC +// field. At most one of these bits will be set at any time, +// indicating that clock is currently present at the output of the +// glitchless mux. Whilst switching is in progress, this register +// may briefly show all-0s. +#define CLOCKS_CLK_SYS_SELECTED_OFFSET _u(0x00000044) +#define CLOCKS_CLK_SYS_SELECTED_BITS _u(0xffffffff) +#define CLOCKS_CLK_SYS_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_SYS_SELECTED_MSB _u(31) +#define CLOCKS_CLK_SYS_SELECTED_LSB _u(0) #define CLOCKS_CLK_SYS_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_PERI_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_PERI_CTRL_OFFSET 0x00000048 -#define CLOCKS_CLK_PERI_CTRL_BITS 0x00000ce0 -#define CLOCKS_CLK_PERI_CTRL_RESET 0x00000000 +#define CLOCKS_CLK_PERI_CTRL_OFFSET _u(0x00000048) +#define CLOCKS_CLK_PERI_CTRL_BITS _u(0x00000ce0) +#define CLOCKS_CLK_PERI_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_PERI_CTRL_ENABLE // Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_PERI_CTRL_ENABLE_RESET 0x0 -#define CLOCKS_CLK_PERI_CTRL_ENABLE_BITS 0x00000800 -#define CLOCKS_CLK_PERI_CTRL_ENABLE_MSB 11 -#define CLOCKS_CLK_PERI_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_PERI_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_PERI_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_PERI_CTRL_ENABLE_LSB _u(11) #define CLOCKS_CLK_PERI_CTRL_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_PERI_CTRL_KILL // Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_PERI_CTRL_KILL_RESET 0x0 -#define CLOCKS_CLK_PERI_CTRL_KILL_BITS 0x00000400 -#define CLOCKS_CLK_PERI_CTRL_KILL_MSB 10 -#define CLOCKS_CLK_PERI_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_PERI_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_PERI_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_PERI_CTRL_KILL_LSB _u(10) #define CLOCKS_CLK_PERI_CTRL_KILL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_PERI_CTRL_AUXSRC @@ -615,68 +649,72 @@ // 0x4 -> xosc_clksrc // 0x5 -> clksrc_gpin0 // 0x6 -> clksrc_gpin1 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_RESET 0x0 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_BITS 0x000000e0 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_MSB 7 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_LSB _u(5) #define CLOCKS_CLK_PERI_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS 0x0 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x1 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x2 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x3 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x4 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x5 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x6 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x2) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x3) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x4) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x5) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x6) // ============================================================================= // Register : CLOCKS_CLK_PERI_SELECTED -// Description : Indicates which src is currently selected (one-hot) -#define CLOCKS_CLK_PERI_SELECTED_OFFSET 0x00000050 -#define CLOCKS_CLK_PERI_SELECTED_BITS 0xffffffff -#define CLOCKS_CLK_PERI_SELECTED_RESET 0x00000001 -#define CLOCKS_CLK_PERI_SELECTED_MSB 31 -#define CLOCKS_CLK_PERI_SELECTED_LSB 0 +// Description : Indicates which SRC is currently selected by the glitchless mux +// (one-hot). +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_PERI_SELECTED_OFFSET _u(0x00000050) +#define CLOCKS_CLK_PERI_SELECTED_BITS _u(0xffffffff) +#define CLOCKS_CLK_PERI_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_PERI_SELECTED_MSB _u(31) +#define CLOCKS_CLK_PERI_SELECTED_LSB _u(0) #define CLOCKS_CLK_PERI_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_USB_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_USB_CTRL_OFFSET 0x00000054 -#define CLOCKS_CLK_USB_CTRL_BITS 0x00130ce0 -#define CLOCKS_CLK_USB_CTRL_RESET 0x00000000 +#define CLOCKS_CLK_USB_CTRL_OFFSET _u(0x00000054) +#define CLOCKS_CLK_USB_CTRL_BITS _u(0x00130ce0) +#define CLOCKS_CLK_USB_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_USB_CTRL_NUDGE // Description : An edge on this signal shifts the phase of the output by 1 // cycle of the input clock // This can be done at any time -#define CLOCKS_CLK_USB_CTRL_NUDGE_RESET 0x0 -#define CLOCKS_CLK_USB_CTRL_NUDGE_BITS 0x00100000 -#define CLOCKS_CLK_USB_CTRL_NUDGE_MSB 20 -#define CLOCKS_CLK_USB_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_USB_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_USB_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_USB_CTRL_NUDGE_LSB _u(20) #define CLOCKS_CLK_USB_CTRL_NUDGE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_USB_CTRL_PHASE // Description : This delays the enable signal by up to 3 cycles of the input // clock // This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_USB_CTRL_PHASE_RESET 0x0 -#define CLOCKS_CLK_USB_CTRL_PHASE_BITS 0x00030000 -#define CLOCKS_CLK_USB_CTRL_PHASE_MSB 17 -#define CLOCKS_CLK_USB_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_USB_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_USB_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_USB_CTRL_PHASE_LSB _u(16) #define CLOCKS_CLK_USB_CTRL_PHASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_USB_CTRL_ENABLE // Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_USB_CTRL_ENABLE_RESET 0x0 -#define CLOCKS_CLK_USB_CTRL_ENABLE_BITS 0x00000800 -#define CLOCKS_CLK_USB_CTRL_ENABLE_MSB 11 -#define CLOCKS_CLK_USB_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_USB_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_USB_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_USB_CTRL_ENABLE_LSB _u(11) #define CLOCKS_CLK_USB_CTRL_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_USB_CTRL_KILL // Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_USB_CTRL_KILL_RESET 0x0 -#define CLOCKS_CLK_USB_CTRL_KILL_BITS 0x00000400 -#define CLOCKS_CLK_USB_CTRL_KILL_MSB 10 -#define CLOCKS_CLK_USB_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_USB_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_USB_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_USB_CTRL_KILL_LSB _u(10) #define CLOCKS_CLK_USB_CTRL_KILL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_USB_CTRL_AUXSRC @@ -687,81 +725,85 @@ // 0x3 -> xosc_clksrc // 0x4 -> clksrc_gpin0 // 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_RESET 0x0 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_BITS 0x000000e0 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_MSB 7 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_LSB _u(5) #define CLOCKS_CLK_USB_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x0 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x1 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x2 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x3 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x4 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x5 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) // ============================================================================= // Register : CLOCKS_CLK_USB_DIV // Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_USB_DIV_OFFSET 0x00000058 -#define CLOCKS_CLK_USB_DIV_BITS 0x00000300 -#define CLOCKS_CLK_USB_DIV_RESET 0x00000100 +#define CLOCKS_CLK_USB_DIV_OFFSET _u(0x00000058) +#define CLOCKS_CLK_USB_DIV_BITS _u(0x00000300) +#define CLOCKS_CLK_USB_DIV_RESET _u(0x00000100) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_USB_DIV_INT // Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_USB_DIV_INT_RESET 0x1 -#define CLOCKS_CLK_USB_DIV_INT_BITS 0x00000300 -#define CLOCKS_CLK_USB_DIV_INT_MSB 9 -#define CLOCKS_CLK_USB_DIV_INT_LSB 8 +#define CLOCKS_CLK_USB_DIV_INT_RESET _u(0x1) +#define CLOCKS_CLK_USB_DIV_INT_BITS _u(0x00000300) +#define CLOCKS_CLK_USB_DIV_INT_MSB _u(9) +#define CLOCKS_CLK_USB_DIV_INT_LSB _u(8) #define CLOCKS_CLK_USB_DIV_INT_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_USB_SELECTED -// Description : Indicates which src is currently selected (one-hot) -#define CLOCKS_CLK_USB_SELECTED_OFFSET 0x0000005c -#define CLOCKS_CLK_USB_SELECTED_BITS 0xffffffff -#define CLOCKS_CLK_USB_SELECTED_RESET 0x00000001 -#define CLOCKS_CLK_USB_SELECTED_MSB 31 -#define CLOCKS_CLK_USB_SELECTED_LSB 0 +// Description : Indicates which SRC is currently selected by the glitchless mux +// (one-hot). +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_USB_SELECTED_OFFSET _u(0x0000005c) +#define CLOCKS_CLK_USB_SELECTED_BITS _u(0xffffffff) +#define CLOCKS_CLK_USB_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_USB_SELECTED_MSB _u(31) +#define CLOCKS_CLK_USB_SELECTED_LSB _u(0) #define CLOCKS_CLK_USB_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_ADC_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_ADC_CTRL_OFFSET 0x00000060 -#define CLOCKS_CLK_ADC_CTRL_BITS 0x00130ce0 -#define CLOCKS_CLK_ADC_CTRL_RESET 0x00000000 +#define CLOCKS_CLK_ADC_CTRL_OFFSET _u(0x00000060) +#define CLOCKS_CLK_ADC_CTRL_BITS _u(0x00130ce0) +#define CLOCKS_CLK_ADC_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_ADC_CTRL_NUDGE // Description : An edge on this signal shifts the phase of the output by 1 // cycle of the input clock // This can be done at any time -#define CLOCKS_CLK_ADC_CTRL_NUDGE_RESET 0x0 -#define CLOCKS_CLK_ADC_CTRL_NUDGE_BITS 0x00100000 -#define CLOCKS_CLK_ADC_CTRL_NUDGE_MSB 20 -#define CLOCKS_CLK_ADC_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_ADC_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_ADC_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_ADC_CTRL_NUDGE_LSB _u(20) #define CLOCKS_CLK_ADC_CTRL_NUDGE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_ADC_CTRL_PHASE // Description : This delays the enable signal by up to 3 cycles of the input // clock // This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_ADC_CTRL_PHASE_RESET 0x0 -#define CLOCKS_CLK_ADC_CTRL_PHASE_BITS 0x00030000 -#define CLOCKS_CLK_ADC_CTRL_PHASE_MSB 17 -#define CLOCKS_CLK_ADC_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_ADC_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_ADC_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_ADC_CTRL_PHASE_LSB _u(16) #define CLOCKS_CLK_ADC_CTRL_PHASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_ADC_CTRL_ENABLE // Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_ADC_CTRL_ENABLE_RESET 0x0 -#define CLOCKS_CLK_ADC_CTRL_ENABLE_BITS 0x00000800 -#define CLOCKS_CLK_ADC_CTRL_ENABLE_MSB 11 -#define CLOCKS_CLK_ADC_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_ADC_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_ADC_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_ADC_CTRL_ENABLE_LSB _u(11) #define CLOCKS_CLK_ADC_CTRL_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_ADC_CTRL_KILL // Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_ADC_CTRL_KILL_RESET 0x0 -#define CLOCKS_CLK_ADC_CTRL_KILL_BITS 0x00000400 -#define CLOCKS_CLK_ADC_CTRL_KILL_MSB 10 -#define CLOCKS_CLK_ADC_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_ADC_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_ADC_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_ADC_CTRL_KILL_LSB _u(10) #define CLOCKS_CLK_ADC_CTRL_KILL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_ADC_CTRL_AUXSRC @@ -772,81 +814,85 @@ // 0x3 -> xosc_clksrc // 0x4 -> clksrc_gpin0 // 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_RESET 0x0 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_BITS 0x000000e0 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_MSB 7 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_LSB _u(5) #define CLOCKS_CLK_ADC_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x0 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x1 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x2 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x3 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x4 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x5 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) // ============================================================================= // Register : CLOCKS_CLK_ADC_DIV // Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_ADC_DIV_OFFSET 0x00000064 -#define CLOCKS_CLK_ADC_DIV_BITS 0x00000300 -#define CLOCKS_CLK_ADC_DIV_RESET 0x00000100 +#define CLOCKS_CLK_ADC_DIV_OFFSET _u(0x00000064) +#define CLOCKS_CLK_ADC_DIV_BITS _u(0x00000300) +#define CLOCKS_CLK_ADC_DIV_RESET _u(0x00000100) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_ADC_DIV_INT // Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_ADC_DIV_INT_RESET 0x1 -#define CLOCKS_CLK_ADC_DIV_INT_BITS 0x00000300 -#define CLOCKS_CLK_ADC_DIV_INT_MSB 9 -#define CLOCKS_CLK_ADC_DIV_INT_LSB 8 +#define CLOCKS_CLK_ADC_DIV_INT_RESET _u(0x1) +#define CLOCKS_CLK_ADC_DIV_INT_BITS _u(0x00000300) +#define CLOCKS_CLK_ADC_DIV_INT_MSB _u(9) +#define CLOCKS_CLK_ADC_DIV_INT_LSB _u(8) #define CLOCKS_CLK_ADC_DIV_INT_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_ADC_SELECTED -// Description : Indicates which src is currently selected (one-hot) -#define CLOCKS_CLK_ADC_SELECTED_OFFSET 0x00000068 -#define CLOCKS_CLK_ADC_SELECTED_BITS 0xffffffff -#define CLOCKS_CLK_ADC_SELECTED_RESET 0x00000001 -#define CLOCKS_CLK_ADC_SELECTED_MSB 31 -#define CLOCKS_CLK_ADC_SELECTED_LSB 0 +// Description : Indicates which SRC is currently selected by the glitchless mux +// (one-hot). +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_ADC_SELECTED_OFFSET _u(0x00000068) +#define CLOCKS_CLK_ADC_SELECTED_BITS _u(0xffffffff) +#define CLOCKS_CLK_ADC_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_ADC_SELECTED_MSB _u(31) +#define CLOCKS_CLK_ADC_SELECTED_LSB _u(0) #define CLOCKS_CLK_ADC_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_RTC_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) -#define CLOCKS_CLK_RTC_CTRL_OFFSET 0x0000006c -#define CLOCKS_CLK_RTC_CTRL_BITS 0x00130ce0 -#define CLOCKS_CLK_RTC_CTRL_RESET 0x00000000 +#define CLOCKS_CLK_RTC_CTRL_OFFSET _u(0x0000006c) +#define CLOCKS_CLK_RTC_CTRL_BITS _u(0x00130ce0) +#define CLOCKS_CLK_RTC_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_RTC_CTRL_NUDGE // Description : An edge on this signal shifts the phase of the output by 1 // cycle of the input clock // This can be done at any time -#define CLOCKS_CLK_RTC_CTRL_NUDGE_RESET 0x0 -#define CLOCKS_CLK_RTC_CTRL_NUDGE_BITS 0x00100000 -#define CLOCKS_CLK_RTC_CTRL_NUDGE_MSB 20 -#define CLOCKS_CLK_RTC_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_RTC_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_RTC_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_RTC_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_RTC_CTRL_NUDGE_LSB _u(20) #define CLOCKS_CLK_RTC_CTRL_NUDGE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_RTC_CTRL_PHASE // Description : This delays the enable signal by up to 3 cycles of the input // clock // This must be set before the clock is enabled to have any effect -#define CLOCKS_CLK_RTC_CTRL_PHASE_RESET 0x0 -#define CLOCKS_CLK_RTC_CTRL_PHASE_BITS 0x00030000 -#define CLOCKS_CLK_RTC_CTRL_PHASE_MSB 17 -#define CLOCKS_CLK_RTC_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_RTC_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_RTC_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_RTC_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_RTC_CTRL_PHASE_LSB _u(16) #define CLOCKS_CLK_RTC_CTRL_PHASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_RTC_CTRL_ENABLE // Description : Starts and stops the clock generator cleanly -#define CLOCKS_CLK_RTC_CTRL_ENABLE_RESET 0x0 -#define CLOCKS_CLK_RTC_CTRL_ENABLE_BITS 0x00000800 -#define CLOCKS_CLK_RTC_CTRL_ENABLE_MSB 11 -#define CLOCKS_CLK_RTC_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_RTC_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_RTC_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_RTC_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_RTC_CTRL_ENABLE_LSB _u(11) #define CLOCKS_CLK_RTC_CTRL_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_RTC_CTRL_KILL // Description : Asynchronously kills the clock generator -#define CLOCKS_CLK_RTC_CTRL_KILL_RESET 0x0 -#define CLOCKS_CLK_RTC_CTRL_KILL_BITS 0x00000400 -#define CLOCKS_CLK_RTC_CTRL_KILL_MSB 10 -#define CLOCKS_CLK_RTC_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_RTC_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_RTC_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_RTC_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_RTC_CTRL_KILL_LSB _u(10) #define CLOCKS_CLK_RTC_CTRL_KILL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_RTC_CTRL_AUXSRC @@ -857,153 +903,157 @@ // 0x3 -> xosc_clksrc // 0x4 -> clksrc_gpin0 // 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_RESET 0x0 -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_BITS 0x000000e0 -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_MSB 7 -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_LSB _u(5) #define CLOCKS_CLK_RTC_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x0 -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x1 -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x2 -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x3 -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x4 -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x5 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) // ============================================================================= // Register : CLOCKS_CLK_RTC_DIV // Description : Clock divisor, can be changed on-the-fly -#define CLOCKS_CLK_RTC_DIV_OFFSET 0x00000070 -#define CLOCKS_CLK_RTC_DIV_BITS 0xffffffff -#define CLOCKS_CLK_RTC_DIV_RESET 0x00000100 +#define CLOCKS_CLK_RTC_DIV_OFFSET _u(0x00000070) +#define CLOCKS_CLK_RTC_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_RTC_DIV_RESET _u(0x00000100) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_RTC_DIV_INT // Description : Integer component of the divisor, 0 -> divide by 2^16 -#define CLOCKS_CLK_RTC_DIV_INT_RESET 0x000001 -#define CLOCKS_CLK_RTC_DIV_INT_BITS 0xffffff00 -#define CLOCKS_CLK_RTC_DIV_INT_MSB 31 -#define CLOCKS_CLK_RTC_DIV_INT_LSB 8 +#define CLOCKS_CLK_RTC_DIV_INT_RESET _u(0x000001) +#define CLOCKS_CLK_RTC_DIV_INT_BITS _u(0xffffff00) +#define CLOCKS_CLK_RTC_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_RTC_DIV_INT_LSB _u(8) #define CLOCKS_CLK_RTC_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_RTC_DIV_FRAC // Description : Fractional component of the divisor -#define CLOCKS_CLK_RTC_DIV_FRAC_RESET 0x00 -#define CLOCKS_CLK_RTC_DIV_FRAC_BITS 0x000000ff -#define CLOCKS_CLK_RTC_DIV_FRAC_MSB 7 -#define CLOCKS_CLK_RTC_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_RTC_DIV_FRAC_RESET _u(0x00) +#define CLOCKS_CLK_RTC_DIV_FRAC_BITS _u(0x000000ff) +#define CLOCKS_CLK_RTC_DIV_FRAC_MSB _u(7) +#define CLOCKS_CLK_RTC_DIV_FRAC_LSB _u(0) #define CLOCKS_CLK_RTC_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_RTC_SELECTED -// Description : Indicates which src is currently selected (one-hot) -#define CLOCKS_CLK_RTC_SELECTED_OFFSET 0x00000074 -#define CLOCKS_CLK_RTC_SELECTED_BITS 0xffffffff -#define CLOCKS_CLK_RTC_SELECTED_RESET 0x00000001 -#define CLOCKS_CLK_RTC_SELECTED_MSB 31 -#define CLOCKS_CLK_RTC_SELECTED_LSB 0 +// Description : Indicates which SRC is currently selected by the glitchless mux +// (one-hot). +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_RTC_SELECTED_OFFSET _u(0x00000074) +#define CLOCKS_CLK_RTC_SELECTED_BITS _u(0xffffffff) +#define CLOCKS_CLK_RTC_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_RTC_SELECTED_MSB _u(31) +#define CLOCKS_CLK_RTC_SELECTED_LSB _u(0) #define CLOCKS_CLK_RTC_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_SYS_RESUS_CTRL // Description : None -#define CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET 0x00000078 -#define CLOCKS_CLK_SYS_RESUS_CTRL_BITS 0x000111ff -#define CLOCKS_CLK_SYS_RESUS_CTRL_RESET 0x000000ff +#define CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET _u(0x00000078) +#define CLOCKS_CLK_SYS_RESUS_CTRL_BITS _u(0x000111ff) +#define CLOCKS_CLK_SYS_RESUS_CTRL_RESET _u(0x000000ff) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR // Description : For clearing the resus after the fault that triggered it has // been corrected -#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_RESET 0x0 -#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS 0x00010000 -#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_MSB 16 -#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_LSB 16 +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_RESET _u(0x0) +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS _u(0x00010000) +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_MSB _u(16) +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_LSB _u(16) #define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_SYS_RESUS_CTRL_FRCE // Description : Force a resus, for test purposes only -#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_RESET 0x0 -#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_BITS 0x00001000 -#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_MSB 12 -#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_LSB 12 +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_RESET _u(0x0) +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_BITS _u(0x00001000) +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_MSB _u(12) +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_LSB _u(12) #define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE // Description : Enable resus -#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_RESET 0x0 -#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS 0x00000100 -#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_MSB 8 -#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_LSB 8 +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS _u(0x00000100) +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_MSB _u(8) +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_LSB _u(8) #define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT // Description : This is expressed as a number of clk_ref cycles // and must be >= 2x clk_ref_freq/min_clk_tst_freq -#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_RESET 0xff -#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_BITS 0x000000ff -#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_MSB 7 -#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_LSB 0 +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_RESET _u(0xff) +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_BITS _u(0x000000ff) +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_MSB _u(7) +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_LSB _u(0) #define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_SYS_RESUS_STATUS // Description : None -#define CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET 0x0000007c -#define CLOCKS_CLK_SYS_RESUS_STATUS_BITS 0x00000001 -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESET 0x00000000 +#define CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET _u(0x0000007c) +#define CLOCKS_CLK_SYS_RESUS_STATUS_BITS _u(0x00000001) +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED // Description : Clock has been resuscitated, correct the error then send // ctrl_clear=1 -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_RESET 0x0 -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS 0x00000001 -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_MSB 0 -#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_LSB 0 +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_RESET _u(0x0) +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS _u(0x00000001) +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_MSB _u(0) +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_LSB _u(0) #define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_FC0_REF_KHZ // Description : Reference clock frequency in kHz -#define CLOCKS_FC0_REF_KHZ_OFFSET 0x00000080 -#define CLOCKS_FC0_REF_KHZ_BITS 0x000fffff -#define CLOCKS_FC0_REF_KHZ_RESET 0x00000000 -#define CLOCKS_FC0_REF_KHZ_MSB 19 -#define CLOCKS_FC0_REF_KHZ_LSB 0 +#define CLOCKS_FC0_REF_KHZ_OFFSET _u(0x00000080) +#define CLOCKS_FC0_REF_KHZ_BITS _u(0x000fffff) +#define CLOCKS_FC0_REF_KHZ_RESET _u(0x00000000) +#define CLOCKS_FC0_REF_KHZ_MSB _u(19) +#define CLOCKS_FC0_REF_KHZ_LSB _u(0) #define CLOCKS_FC0_REF_KHZ_ACCESS "RW" // ============================================================================= // Register : CLOCKS_FC0_MIN_KHZ // Description : Minimum pass frequency in kHz. This is optional. Set to 0 if // you are not using the pass/fail flags -#define CLOCKS_FC0_MIN_KHZ_OFFSET 0x00000084 -#define CLOCKS_FC0_MIN_KHZ_BITS 0x01ffffff -#define CLOCKS_FC0_MIN_KHZ_RESET 0x00000000 -#define CLOCKS_FC0_MIN_KHZ_MSB 24 -#define CLOCKS_FC0_MIN_KHZ_LSB 0 +#define CLOCKS_FC0_MIN_KHZ_OFFSET _u(0x00000084) +#define CLOCKS_FC0_MIN_KHZ_BITS _u(0x01ffffff) +#define CLOCKS_FC0_MIN_KHZ_RESET _u(0x00000000) +#define CLOCKS_FC0_MIN_KHZ_MSB _u(24) +#define CLOCKS_FC0_MIN_KHZ_LSB _u(0) #define CLOCKS_FC0_MIN_KHZ_ACCESS "RW" // ============================================================================= // Register : CLOCKS_FC0_MAX_KHZ // Description : Maximum pass frequency in kHz. This is optional. Set to // 0x1ffffff if you are not using the pass/fail flags -#define CLOCKS_FC0_MAX_KHZ_OFFSET 0x00000088 -#define CLOCKS_FC0_MAX_KHZ_BITS 0x01ffffff -#define CLOCKS_FC0_MAX_KHZ_RESET 0x01ffffff -#define CLOCKS_FC0_MAX_KHZ_MSB 24 -#define CLOCKS_FC0_MAX_KHZ_LSB 0 +#define CLOCKS_FC0_MAX_KHZ_OFFSET _u(0x00000088) +#define CLOCKS_FC0_MAX_KHZ_BITS _u(0x01ffffff) +#define CLOCKS_FC0_MAX_KHZ_RESET _u(0x01ffffff) +#define CLOCKS_FC0_MAX_KHZ_MSB _u(24) +#define CLOCKS_FC0_MAX_KHZ_LSB _u(0) #define CLOCKS_FC0_MAX_KHZ_ACCESS "RW" // ============================================================================= // Register : CLOCKS_FC0_DELAY // Description : Delays the start of frequency counting to allow the mux to // settle // Delay is measured in multiples of the reference clock period -#define CLOCKS_FC0_DELAY_OFFSET 0x0000008c -#define CLOCKS_FC0_DELAY_BITS 0x00000007 -#define CLOCKS_FC0_DELAY_RESET 0x00000001 -#define CLOCKS_FC0_DELAY_MSB 2 -#define CLOCKS_FC0_DELAY_LSB 0 +#define CLOCKS_FC0_DELAY_OFFSET _u(0x0000008c) +#define CLOCKS_FC0_DELAY_BITS _u(0x00000007) +#define CLOCKS_FC0_DELAY_RESET _u(0x00000001) +#define CLOCKS_FC0_DELAY_MSB _u(2) +#define CLOCKS_FC0_DELAY_LSB _u(0) #define CLOCKS_FC0_DELAY_ACCESS "RW" // ============================================================================= // Register : CLOCKS_FC0_INTERVAL // Description : The test interval is 0.98us * 2**interval, but let's call it // 1us * 2**interval // The default gives a test interval of 250us -#define CLOCKS_FC0_INTERVAL_OFFSET 0x00000090 -#define CLOCKS_FC0_INTERVAL_BITS 0x0000000f -#define CLOCKS_FC0_INTERVAL_RESET 0x00000008 -#define CLOCKS_FC0_INTERVAL_MSB 3 -#define CLOCKS_FC0_INTERVAL_LSB 0 +#define CLOCKS_FC0_INTERVAL_OFFSET _u(0x00000090) +#define CLOCKS_FC0_INTERVAL_BITS _u(0x0000000f) +#define CLOCKS_FC0_INTERVAL_RESET _u(0x00000008) +#define CLOCKS_FC0_INTERVAL_MSB _u(3) +#define CLOCKS_FC0_INTERVAL_LSB _u(0) #define CLOCKS_FC0_INTERVAL_ACCESS "RW" // ============================================================================= // Register : CLOCKS_FC0_SRC @@ -1023,1337 +1073,1337 @@ // 0x0b -> clk_usb // 0x0c -> clk_adc // 0x0d -> clk_rtc -#define CLOCKS_FC0_SRC_OFFSET 0x00000094 -#define CLOCKS_FC0_SRC_BITS 0x000000ff -#define CLOCKS_FC0_SRC_RESET 0x00000000 -#define CLOCKS_FC0_SRC_MSB 7 -#define CLOCKS_FC0_SRC_LSB 0 +#define CLOCKS_FC0_SRC_OFFSET _u(0x00000094) +#define CLOCKS_FC0_SRC_BITS _u(0x000000ff) +#define CLOCKS_FC0_SRC_RESET _u(0x00000000) +#define CLOCKS_FC0_SRC_MSB _u(7) +#define CLOCKS_FC0_SRC_LSB _u(0) #define CLOCKS_FC0_SRC_ACCESS "RW" -#define CLOCKS_FC0_SRC_VALUE_NULL 0x00 -#define CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY 0x01 -#define CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY 0x02 -#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC 0x03 -#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH 0x04 -#define CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC 0x05 -#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0 0x06 -#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN1 0x07 -#define CLOCKS_FC0_SRC_VALUE_CLK_REF 0x08 -#define CLOCKS_FC0_SRC_VALUE_CLK_SYS 0x09 -#define CLOCKS_FC0_SRC_VALUE_CLK_PERI 0x0a -#define CLOCKS_FC0_SRC_VALUE_CLK_USB 0x0b -#define CLOCKS_FC0_SRC_VALUE_CLK_ADC 0x0c -#define CLOCKS_FC0_SRC_VALUE_CLK_RTC 0x0d +#define CLOCKS_FC0_SRC_VALUE_NULL _u(0x00) +#define CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY _u(0x01) +#define CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY _u(0x02) +#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC _u(0x03) +#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH _u(0x04) +#define CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC _u(0x05) +#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0 _u(0x06) +#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN1 _u(0x07) +#define CLOCKS_FC0_SRC_VALUE_CLK_REF _u(0x08) +#define CLOCKS_FC0_SRC_VALUE_CLK_SYS _u(0x09) +#define CLOCKS_FC0_SRC_VALUE_CLK_PERI _u(0x0a) +#define CLOCKS_FC0_SRC_VALUE_CLK_USB _u(0x0b) +#define CLOCKS_FC0_SRC_VALUE_CLK_ADC _u(0x0c) +#define CLOCKS_FC0_SRC_VALUE_CLK_RTC _u(0x0d) // ============================================================================= // Register : CLOCKS_FC0_STATUS // Description : Frequency counter status -#define CLOCKS_FC0_STATUS_OFFSET 0x00000098 -#define CLOCKS_FC0_STATUS_BITS 0x11111111 -#define CLOCKS_FC0_STATUS_RESET 0x00000000 +#define CLOCKS_FC0_STATUS_OFFSET _u(0x00000098) +#define CLOCKS_FC0_STATUS_BITS _u(0x11111111) +#define CLOCKS_FC0_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_STATUS_DIED // Description : Test clock stopped during test -#define CLOCKS_FC0_STATUS_DIED_RESET 0x0 -#define CLOCKS_FC0_STATUS_DIED_BITS 0x10000000 -#define CLOCKS_FC0_STATUS_DIED_MSB 28 -#define CLOCKS_FC0_STATUS_DIED_LSB 28 +#define CLOCKS_FC0_STATUS_DIED_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_DIED_BITS _u(0x10000000) +#define CLOCKS_FC0_STATUS_DIED_MSB _u(28) +#define CLOCKS_FC0_STATUS_DIED_LSB _u(28) #define CLOCKS_FC0_STATUS_DIED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_STATUS_FAST // Description : Test clock faster than expected, only valid when status_done=1 -#define CLOCKS_FC0_STATUS_FAST_RESET 0x0 -#define CLOCKS_FC0_STATUS_FAST_BITS 0x01000000 -#define CLOCKS_FC0_STATUS_FAST_MSB 24 -#define CLOCKS_FC0_STATUS_FAST_LSB 24 +#define CLOCKS_FC0_STATUS_FAST_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_FAST_BITS _u(0x01000000) +#define CLOCKS_FC0_STATUS_FAST_MSB _u(24) +#define CLOCKS_FC0_STATUS_FAST_LSB _u(24) #define CLOCKS_FC0_STATUS_FAST_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_STATUS_SLOW // Description : Test clock slower than expected, only valid when status_done=1 -#define CLOCKS_FC0_STATUS_SLOW_RESET 0x0 -#define CLOCKS_FC0_STATUS_SLOW_BITS 0x00100000 -#define CLOCKS_FC0_STATUS_SLOW_MSB 20 -#define CLOCKS_FC0_STATUS_SLOW_LSB 20 +#define CLOCKS_FC0_STATUS_SLOW_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_SLOW_BITS _u(0x00100000) +#define CLOCKS_FC0_STATUS_SLOW_MSB _u(20) +#define CLOCKS_FC0_STATUS_SLOW_LSB _u(20) #define CLOCKS_FC0_STATUS_SLOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_STATUS_FAIL // Description : Test failed -#define CLOCKS_FC0_STATUS_FAIL_RESET 0x0 -#define CLOCKS_FC0_STATUS_FAIL_BITS 0x00010000 -#define CLOCKS_FC0_STATUS_FAIL_MSB 16 -#define CLOCKS_FC0_STATUS_FAIL_LSB 16 +#define CLOCKS_FC0_STATUS_FAIL_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_FAIL_BITS _u(0x00010000) +#define CLOCKS_FC0_STATUS_FAIL_MSB _u(16) +#define CLOCKS_FC0_STATUS_FAIL_LSB _u(16) #define CLOCKS_FC0_STATUS_FAIL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_STATUS_WAITING // Description : Waiting for test clock to start -#define CLOCKS_FC0_STATUS_WAITING_RESET 0x0 -#define CLOCKS_FC0_STATUS_WAITING_BITS 0x00001000 -#define CLOCKS_FC0_STATUS_WAITING_MSB 12 -#define CLOCKS_FC0_STATUS_WAITING_LSB 12 +#define CLOCKS_FC0_STATUS_WAITING_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_WAITING_BITS _u(0x00001000) +#define CLOCKS_FC0_STATUS_WAITING_MSB _u(12) +#define CLOCKS_FC0_STATUS_WAITING_LSB _u(12) #define CLOCKS_FC0_STATUS_WAITING_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_STATUS_RUNNING // Description : Test running -#define CLOCKS_FC0_STATUS_RUNNING_RESET 0x0 -#define CLOCKS_FC0_STATUS_RUNNING_BITS 0x00000100 -#define CLOCKS_FC0_STATUS_RUNNING_MSB 8 -#define CLOCKS_FC0_STATUS_RUNNING_LSB 8 +#define CLOCKS_FC0_STATUS_RUNNING_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_RUNNING_BITS _u(0x00000100) +#define CLOCKS_FC0_STATUS_RUNNING_MSB _u(8) +#define CLOCKS_FC0_STATUS_RUNNING_LSB _u(8) #define CLOCKS_FC0_STATUS_RUNNING_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_STATUS_DONE // Description : Test complete -#define CLOCKS_FC0_STATUS_DONE_RESET 0x0 -#define CLOCKS_FC0_STATUS_DONE_BITS 0x00000010 -#define CLOCKS_FC0_STATUS_DONE_MSB 4 -#define CLOCKS_FC0_STATUS_DONE_LSB 4 +#define CLOCKS_FC0_STATUS_DONE_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_DONE_BITS _u(0x00000010) +#define CLOCKS_FC0_STATUS_DONE_MSB _u(4) +#define CLOCKS_FC0_STATUS_DONE_LSB _u(4) #define CLOCKS_FC0_STATUS_DONE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_STATUS_PASS // Description : Test passed -#define CLOCKS_FC0_STATUS_PASS_RESET 0x0 -#define CLOCKS_FC0_STATUS_PASS_BITS 0x00000001 -#define CLOCKS_FC0_STATUS_PASS_MSB 0 -#define CLOCKS_FC0_STATUS_PASS_LSB 0 +#define CLOCKS_FC0_STATUS_PASS_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_PASS_BITS _u(0x00000001) +#define CLOCKS_FC0_STATUS_PASS_MSB _u(0) +#define CLOCKS_FC0_STATUS_PASS_LSB _u(0) #define CLOCKS_FC0_STATUS_PASS_ACCESS "RO" // ============================================================================= // Register : CLOCKS_FC0_RESULT // Description : Result of frequency measurement, only valid when status_done=1 -#define CLOCKS_FC0_RESULT_OFFSET 0x0000009c -#define CLOCKS_FC0_RESULT_BITS 0x3fffffff -#define CLOCKS_FC0_RESULT_RESET 0x00000000 +#define CLOCKS_FC0_RESULT_OFFSET _u(0x0000009c) +#define CLOCKS_FC0_RESULT_BITS _u(0x3fffffff) +#define CLOCKS_FC0_RESULT_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_RESULT_KHZ // Description : None -#define CLOCKS_FC0_RESULT_KHZ_RESET 0x0000000 -#define CLOCKS_FC0_RESULT_KHZ_BITS 0x3fffffe0 -#define CLOCKS_FC0_RESULT_KHZ_MSB 29 -#define CLOCKS_FC0_RESULT_KHZ_LSB 5 +#define CLOCKS_FC0_RESULT_KHZ_RESET _u(0x0000000) +#define CLOCKS_FC0_RESULT_KHZ_BITS _u(0x3fffffe0) +#define CLOCKS_FC0_RESULT_KHZ_MSB _u(29) +#define CLOCKS_FC0_RESULT_KHZ_LSB _u(5) #define CLOCKS_FC0_RESULT_KHZ_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_RESULT_FRAC // Description : None -#define CLOCKS_FC0_RESULT_FRAC_RESET 0x00 -#define CLOCKS_FC0_RESULT_FRAC_BITS 0x0000001f -#define CLOCKS_FC0_RESULT_FRAC_MSB 4 -#define CLOCKS_FC0_RESULT_FRAC_LSB 0 +#define CLOCKS_FC0_RESULT_FRAC_RESET _u(0x00) +#define CLOCKS_FC0_RESULT_FRAC_BITS _u(0x0000001f) +#define CLOCKS_FC0_RESULT_FRAC_MSB _u(4) +#define CLOCKS_FC0_RESULT_FRAC_LSB _u(0) #define CLOCKS_FC0_RESULT_FRAC_ACCESS "RO" // ============================================================================= // Register : CLOCKS_WAKE_EN0 // Description : enable clock in wake mode -#define CLOCKS_WAKE_EN0_OFFSET 0x000000a0 -#define CLOCKS_WAKE_EN0_BITS 0xffffffff -#define CLOCKS_WAKE_EN0_RESET 0xffffffff +#define CLOCKS_WAKE_EN0_OFFSET _u(0x000000a0) +#define CLOCKS_WAKE_EN0_BITS _u(0xffffffff) +#define CLOCKS_WAKE_EN0_RESET _u(0xffffffff) // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM3 // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_BITS 0x80000000 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_MSB 31 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_LSB 31 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_BITS _u(0x80000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_MSB _u(31) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_LSB _u(31) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM2 // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_BITS 0x40000000 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_MSB 30 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_LSB 30 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_BITS _u(0x40000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_MSB _u(30) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_LSB _u(30) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM1 // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_BITS 0x20000000 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_MSB 29 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_LSB 29 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_BITS _u(0x20000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_MSB _u(29) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_LSB _u(29) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM0 // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_BITS 0x10000000 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_MSB 28 -#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_LSB 28 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_BITS _u(0x10000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_MSB _u(28) +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_LSB _u(28) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SPI1 // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_BITS 0x08000000 -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_MSB 27 -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_LSB 27 +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_BITS _u(0x08000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_MSB _u(27) +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_LSB _u(27) #define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_PERI_SPI1 // Description : None -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_BITS 0x04000000 -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_MSB 26 -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_LSB 26 +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_BITS _u(0x04000000) +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_MSB _u(26) +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_LSB _u(26) #define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SPI0 // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_BITS 0x02000000 -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_MSB 25 -#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_LSB 25 +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_BITS _u(0x02000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_MSB _u(25) +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_LSB _u(25) #define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_PERI_SPI0 // Description : None -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_BITS 0x01000000 -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_MSB 24 -#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_LSB 24 +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_BITS _u(0x01000000) +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_MSB _u(24) +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_LSB _u(24) #define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SIO // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_BITS 0x00800000 -#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_MSB 23 -#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_LSB 23 +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_BITS _u(0x00800000) +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_MSB _u(23) +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_LSB _u(23) #define CLOCKS_WAKE_EN0_CLK_SYS_SIO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_RTC // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_BITS 0x00400000 -#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_MSB 22 -#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_LSB 22 +#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_BITS _u(0x00400000) +#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_MSB _u(22) +#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_LSB _u(22) #define CLOCKS_WAKE_EN0_CLK_SYS_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_RTC_RTC // Description : None -#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_BITS 0x00200000 -#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_MSB 21 -#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_LSB 21 +#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_BITS _u(0x00200000) +#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_MSB _u(21) +#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_LSB _u(21) #define CLOCKS_WAKE_EN0_CLK_RTC_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_ROSC // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_BITS 0x00100000 -#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_MSB 20 -#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_LSB 20 +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_BITS _u(0x00100000) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_MSB _u(20) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_LSB _u(20) #define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_ROM // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_BITS 0x00080000 -#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_MSB 19 -#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_LSB 19 +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_BITS _u(0x00080000) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_MSB _u(19) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_LSB _u(19) #define CLOCKS_WAKE_EN0_CLK_SYS_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_RESETS // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_BITS 0x00040000 -#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_MSB 18 -#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_LSB 18 +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_BITS _u(0x00040000) +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_MSB _u(18) +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_LSB _u(18) #define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PWM // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_BITS 0x00020000 -#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_MSB 17 -#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_LSB 17 +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_BITS _u(0x00020000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_MSB _u(17) +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_LSB _u(17) #define CLOCKS_WAKE_EN0_CLK_SYS_PWM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PSM // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_BITS 0x00010000 -#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_MSB 16 -#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_LSB 16 +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_BITS _u(0x00010000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_MSB _u(16) +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_LSB _u(16) #define CLOCKS_WAKE_EN0_CLK_SYS_PSM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_BITS 0x00008000 -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_MSB 15 -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_LSB 15 +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_BITS _u(0x00008000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_MSB _u(15) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_LSB _u(15) #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_BITS 0x00004000 -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_MSB 14 -#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_LSB 14 +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_BITS _u(0x00004000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_MSB _u(14) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_LSB _u(14) #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO1 // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_BITS 0x00002000 -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_MSB 13 -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_LSB 13 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_BITS _u(0x00002000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_MSB _u(13) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_LSB _u(13) #define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO0 // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_BITS 0x00001000 -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_MSB 12 -#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_LSB 12 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_BITS _u(0x00001000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_MSB _u(12) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_LSB _u(12) #define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PADS // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_BITS 0x00000800 -#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_MSB 11 -#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_LSB 11 +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_BITS _u(0x00000800) +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_MSB _u(11) +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_LSB _u(11) #define CLOCKS_WAKE_EN0_CLK_SYS_PADS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS 0x00000400 -#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB 10 -#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB 10 +#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _u(0x00000400) +#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _u(10) +#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB _u(10) #define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_JTAG // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_BITS 0x00000200 -#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_MSB 9 -#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_LSB 9 +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_BITS _u(0x00000200) +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_MSB _u(9) +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_LSB _u(9) #define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_IO // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_IO_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_IO_BITS 0x00000100 -#define CLOCKS_WAKE_EN0_CLK_SYS_IO_MSB 8 -#define CLOCKS_WAKE_EN0_CLK_SYS_IO_LSB 8 +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_BITS _u(0x00000100) +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_MSB _u(8) +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_LSB _u(8) #define CLOCKS_WAKE_EN0_CLK_SYS_IO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C1 // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_BITS 0x00000080 -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_MSB 7 -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_LSB 7 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_BITS _u(0x00000080) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_MSB _u(7) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_LSB _u(7) #define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C0 // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_BITS 0x00000040 -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_MSB 6 -#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_LSB 6 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_BITS _u(0x00000040) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_MSB _u(6) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_LSB _u(6) #define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_DMA // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_BITS 0x00000020 -#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_MSB 5 -#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_LSB 5 +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_BITS _u(0x00000020) +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_MSB _u(5) +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_LSB _u(5) #define CLOCKS_WAKE_EN0_CLK_SYS_DMA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_BITS 0x00000010 -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_MSB 4 -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_LSB 4 +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_BITS _u(0x00000010) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_MSB _u(4) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_LSB _u(4) #define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_BITS 0x00000008 -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_MSB 3 -#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_LSB 3 +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_BITS _u(0x00000008) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_MSB _u(3) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_LSB _u(3) #define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_ADC // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_BITS 0x00000004 -#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_MSB 2 -#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_LSB 2 +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_BITS _u(0x00000004) +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_MSB _u(2) +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_LSB _u(2) #define CLOCKS_WAKE_EN0_CLK_SYS_ADC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_ADC_ADC // Description : None -#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_BITS 0x00000002 -#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_MSB 1 -#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_LSB 1 +#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_BITS _u(0x00000002) +#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_MSB _u(1) +#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_LSB _u(1) #define CLOCKS_WAKE_EN0_CLK_ADC_ADC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS // Description : None -#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_RESET 0x1 -#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_BITS 0x00000001 -#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_MSB 0 -#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_LSB 0 +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_BITS _u(0x00000001) +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_MSB _u(0) +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_LSB _u(0) #define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_ACCESS "RW" // ============================================================================= // Register : CLOCKS_WAKE_EN1 // Description : enable clock in wake mode -#define CLOCKS_WAKE_EN1_OFFSET 0x000000a4 -#define CLOCKS_WAKE_EN1_BITS 0x00007fff -#define CLOCKS_WAKE_EN1_RESET 0x00007fff +#define CLOCKS_WAKE_EN1_OFFSET _u(0x000000a4) +#define CLOCKS_WAKE_EN1_BITS _u(0x00007fff) +#define CLOCKS_WAKE_EN1_RESET _u(0x00007fff) // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_XOSC // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_BITS 0x00004000 -#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_MSB 14 -#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_LSB 14 +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_BITS _u(0x00004000) +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_MSB _u(14) +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_LSB _u(14) #define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_XIP // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_BITS 0x00002000 -#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_MSB 13 -#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_LSB 13 +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_BITS _u(0x00002000) +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_MSB _u(13) +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_LSB _u(13) #define CLOCKS_WAKE_EN1_CLK_SYS_XIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_BITS 0x00001000 -#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_MSB 12 -#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_LSB 12 +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_BITS _u(0x00001000) +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_MSB _u(12) +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_LSB _u(12) #define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_USB_USBCTRL // Description : None -#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_BITS 0x00000800 -#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_MSB 11 -#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_LSB 11 +#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_BITS _u(0x00000800) +#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_MSB _u(11) +#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_LSB _u(11) #define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_BITS 0x00000400 -#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_MSB 10 -#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_LSB 10 +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_BITS _u(0x00000400) +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_MSB _u(10) +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_LSB _u(10) #define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_UART1 // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_BITS 0x00000200 -#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_MSB 9 -#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_LSB 9 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_BITS _u(0x00000200) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_MSB _u(9) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_LSB _u(9) #define CLOCKS_WAKE_EN1_CLK_SYS_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_PERI_UART1 // Description : None -#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_BITS 0x00000100 -#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_MSB 8 -#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_LSB 8 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_BITS _u(0x00000100) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_MSB _u(8) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_LSB _u(8) #define CLOCKS_WAKE_EN1_CLK_PERI_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_UART0 // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_BITS 0x00000080 -#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_MSB 7 -#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_LSB 7 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_BITS _u(0x00000080) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_MSB _u(7) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_LSB _u(7) #define CLOCKS_WAKE_EN1_CLK_SYS_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_PERI_UART0 // Description : None -#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_BITS 0x00000040 -#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_MSB 6 -#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_LSB 6 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_BITS _u(0x00000040) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_MSB _u(6) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_LSB _u(6) #define CLOCKS_WAKE_EN1_CLK_PERI_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_TIMER // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_BITS 0x00000020 -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_MSB 5 -#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_LSB 5 +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_BITS _u(0x00000020) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_MSB _u(5) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_LSB _u(5) #define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_TBMAN // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_BITS 0x00000010 -#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_MSB 4 -#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_LSB 4 +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_BITS _u(0x00000010) +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_MSB _u(4) +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_LSB _u(4) #define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_BITS 0x00000008 -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_MSB 3 -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_LSB 3 +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_BITS _u(0x00000008) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_MSB _u(3) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_LSB _u(3) #define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_BITS 0x00000004 -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_MSB 2 -#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_LSB 2 +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_BITS _u(0x00000004) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_MSB _u(2) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_LSB _u(2) #define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM5 // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_BITS 0x00000002 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_MSB 1 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_LSB 1 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_BITS _u(0x00000002) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_MSB _u(1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_LSB _u(1) #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM4 // Description : None -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_RESET 0x1 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_BITS 0x00000001 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_MSB 0 -#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_LSB 0 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_BITS _u(0x00000001) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_MSB _u(0) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_LSB _u(0) #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_ACCESS "RW" // ============================================================================= // Register : CLOCKS_SLEEP_EN0 // Description : enable clock in sleep mode -#define CLOCKS_SLEEP_EN0_OFFSET 0x000000a8 -#define CLOCKS_SLEEP_EN0_BITS 0xffffffff -#define CLOCKS_SLEEP_EN0_RESET 0xffffffff +#define CLOCKS_SLEEP_EN0_OFFSET _u(0x000000a8) +#define CLOCKS_SLEEP_EN0_BITS _u(0xffffffff) +#define CLOCKS_SLEEP_EN0_RESET _u(0xffffffff) // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_BITS 0x80000000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_MSB 31 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_LSB 31 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_BITS _u(0x80000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_MSB _u(31) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_LSB _u(31) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_BITS 0x40000000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_MSB 30 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_LSB 30 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_BITS _u(0x40000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_MSB _u(30) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_LSB _u(30) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_BITS 0x20000000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_MSB 29 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_LSB 29 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_BITS _u(0x20000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_MSB _u(29) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_LSB _u(29) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_BITS 0x10000000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_MSB 28 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_LSB 28 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_BITS _u(0x10000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_MSB _u(28) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_LSB _u(28) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SPI1 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_BITS 0x08000000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_MSB 27 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_LSB 27 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_BITS _u(0x08000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_MSB _u(27) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_LSB _u(27) #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_PERI_SPI1 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_BITS 0x04000000 -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_MSB 26 -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_LSB 26 +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_BITS _u(0x04000000) +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_MSB _u(26) +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_LSB _u(26) #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SPI0 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_BITS 0x02000000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_MSB 25 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_LSB 25 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_BITS _u(0x02000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_MSB _u(25) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_LSB _u(25) #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_PERI_SPI0 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_BITS 0x01000000 -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_MSB 24 -#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_LSB 24 +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_BITS _u(0x01000000) +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_MSB _u(24) +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_LSB _u(24) #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SIO // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_BITS 0x00800000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_MSB 23 -#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_LSB 23 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_BITS _u(0x00800000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_MSB _u(23) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_LSB _u(23) #define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_RTC // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_BITS 0x00400000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_MSB 22 -#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_LSB 22 +#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_BITS _u(0x00400000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_MSB _u(22) +#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_LSB _u(22) #define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_RTC_RTC // Description : None -#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_BITS 0x00200000 -#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_MSB 21 -#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_LSB 21 +#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_BITS _u(0x00200000) +#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_MSB _u(21) +#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_LSB _u(21) #define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROSC // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_BITS 0x00100000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_MSB 20 -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_LSB 20 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_BITS _u(0x00100000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_MSB _u(20) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_LSB _u(20) #define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROM // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_BITS 0x00080000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_MSB 19 -#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_LSB 19 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_BITS _u(0x00080000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_MSB _u(19) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_LSB _u(19) #define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_RESETS // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_BITS 0x00040000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_MSB 18 -#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_LSB 18 +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_BITS _u(0x00040000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_MSB _u(18) +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_LSB _u(18) #define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PWM // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_BITS 0x00020000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_MSB 17 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_LSB 17 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_BITS _u(0x00020000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_MSB _u(17) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_LSB _u(17) #define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PSM // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_BITS 0x00010000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_MSB 16 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_LSB 16 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_BITS _u(0x00010000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_MSB _u(16) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_LSB _u(16) #define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_BITS 0x00008000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_MSB 15 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_LSB 15 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_BITS _u(0x00008000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_MSB _u(15) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_LSB _u(15) #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_BITS 0x00004000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_MSB 14 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_LSB 14 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_BITS _u(0x00004000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_MSB _u(14) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_LSB _u(14) #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO1 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_BITS 0x00002000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_MSB 13 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_LSB 13 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_BITS _u(0x00002000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_MSB _u(13) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_LSB _u(13) #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO0 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_BITS 0x00001000 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_MSB 12 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_LSB 12 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_BITS _u(0x00001000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_MSB _u(12) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_LSB _u(12) #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PADS // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_BITS 0x00000800 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_MSB 11 -#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_LSB 11 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_BITS _u(0x00000800) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_MSB _u(11) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_LSB _u(11) #define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS 0x00000400 -#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB 10 -#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB 10 +#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _u(0x00000400) +#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _u(10) +#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB _u(10) #define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_JTAG // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_BITS 0x00000200 -#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_MSB 9 -#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_LSB 9 +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_BITS _u(0x00000200) +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_MSB _u(9) +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_LSB _u(9) #define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_IO // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_BITS 0x00000100 -#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_MSB 8 -#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_LSB 8 +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_BITS _u(0x00000100) +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_MSB _u(8) +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_LSB _u(8) #define CLOCKS_SLEEP_EN0_CLK_SYS_IO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C1 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_BITS 0x00000080 -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_MSB 7 -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_LSB 7 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_BITS _u(0x00000080) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_MSB _u(7) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_LSB _u(7) #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C0 // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_BITS 0x00000040 -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_MSB 6 -#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_LSB 6 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_BITS _u(0x00000040) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_MSB _u(6) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_LSB _u(6) #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_DMA // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_BITS 0x00000020 -#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_MSB 5 -#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_LSB 5 +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_BITS _u(0x00000020) +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_MSB _u(5) +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_LSB _u(5) #define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_BITS 0x00000010 -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_MSB 4 -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_LSB 4 +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_BITS _u(0x00000010) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_MSB _u(4) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_LSB _u(4) #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_BITS 0x00000008 -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_MSB 3 -#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_LSB 3 +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_BITS _u(0x00000008) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_MSB _u(3) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_LSB _u(3) #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_ADC // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_BITS 0x00000004 -#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_MSB 2 -#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_LSB 2 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_BITS _u(0x00000004) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_MSB _u(2) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_LSB _u(2) #define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_ADC_ADC // Description : None -#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_BITS 0x00000002 -#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_MSB 1 -#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_LSB 1 +#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_BITS _u(0x00000002) +#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_MSB _u(1) +#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_LSB _u(1) #define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS // Description : None -#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_RESET 0x1 -#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_BITS 0x00000001 -#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_MSB 0 -#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_LSB 0 +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_BITS _u(0x00000001) +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_MSB _u(0) +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_LSB _u(0) #define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_ACCESS "RW" // ============================================================================= // Register : CLOCKS_SLEEP_EN1 // Description : enable clock in sleep mode -#define CLOCKS_SLEEP_EN1_OFFSET 0x000000ac -#define CLOCKS_SLEEP_EN1_BITS 0x00007fff -#define CLOCKS_SLEEP_EN1_RESET 0x00007fff +#define CLOCKS_SLEEP_EN1_OFFSET _u(0x000000ac) +#define CLOCKS_SLEEP_EN1_BITS _u(0x00007fff) +#define CLOCKS_SLEEP_EN1_RESET _u(0x00007fff) // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_XOSC // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_BITS 0x00004000 -#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_MSB 14 -#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_LSB 14 +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_BITS _u(0x00004000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_MSB _u(14) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_LSB _u(14) #define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_XIP // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_BITS 0x00002000 -#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_MSB 13 -#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_LSB 13 +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_BITS _u(0x00002000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_MSB _u(13) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_LSB _u(13) #define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_BITS 0x00001000 -#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_MSB 12 -#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_LSB 12 +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_BITS _u(0x00001000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_MSB _u(12) +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_LSB _u(12) #define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL // Description : None -#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_BITS 0x00000800 -#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_MSB 11 -#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_LSB 11 +#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_BITS _u(0x00000800) +#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_MSB _u(11) +#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_LSB _u(11) #define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_BITS 0x00000400 -#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_MSB 10 -#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_LSB 10 +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_BITS _u(0x00000400) +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_MSB _u(10) +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_LSB _u(10) #define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART1 // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_BITS 0x00000200 -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_MSB 9 -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_LSB 9 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_BITS _u(0x00000200) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_MSB _u(9) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_LSB _u(9) #define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART1 // Description : None -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_BITS 0x00000100 -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_MSB 8 -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_LSB 8 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_BITS _u(0x00000100) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_MSB _u(8) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_LSB _u(8) #define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART0 // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_BITS 0x00000080 -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_MSB 7 -#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_LSB 7 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_BITS _u(0x00000080) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_MSB _u(7) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_LSB _u(7) #define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART0 // Description : None -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_BITS 0x00000040 -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_MSB 6 -#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_LSB 6 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_BITS _u(0x00000040) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_MSB _u(6) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_LSB _u(6) #define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_TIMER // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_BITS 0x00000020 -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_MSB 5 -#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_LSB 5 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_BITS _u(0x00000020) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_MSB _u(5) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_LSB _u(5) #define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_BITS 0x00000010 -#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_MSB 4 -#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_LSB 4 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_BITS _u(0x00000010) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_MSB _u(4) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_LSB _u(4) #define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_BITS 0x00000008 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_MSB 3 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_LSB 3 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_BITS _u(0x00000008) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_MSB _u(3) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_LSB _u(3) #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_BITS 0x00000004 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_MSB 2 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_LSB 2 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_BITS _u(0x00000004) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_MSB _u(2) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_LSB _u(2) #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5 // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_BITS 0x00000002 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_MSB 1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_LSB 1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_BITS _u(0x00000002) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_MSB _u(1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_LSB _u(1) #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4 // Description : None -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_RESET 0x1 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_BITS 0x00000001 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_MSB 0 -#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_LSB 0 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_BITS _u(0x00000001) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_MSB _u(0) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_LSB _u(0) #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_ACCESS "RW" // ============================================================================= // Register : CLOCKS_ENABLED0 // Description : indicates the state of the clock enable -#define CLOCKS_ENABLED0_OFFSET 0x000000b0 -#define CLOCKS_ENABLED0_BITS 0xffffffff -#define CLOCKS_ENABLED0_RESET 0x00000000 +#define CLOCKS_ENABLED0_OFFSET _u(0x000000b0) +#define CLOCKS_ENABLED0_BITS _u(0xffffffff) +#define CLOCKS_ENABLED0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SRAM3 // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_BITS 0x80000000 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_MSB 31 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_LSB 31 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_BITS _u(0x80000000) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_MSB _u(31) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_LSB _u(31) #define CLOCKS_ENABLED0_CLK_SYS_SRAM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SRAM2 // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_BITS 0x40000000 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_MSB 30 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_LSB 30 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_BITS _u(0x40000000) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_MSB _u(30) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_LSB _u(30) #define CLOCKS_ENABLED0_CLK_SYS_SRAM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SRAM1 // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_BITS 0x20000000 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_MSB 29 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_LSB 29 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_BITS _u(0x20000000) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_MSB _u(29) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_LSB _u(29) #define CLOCKS_ENABLED0_CLK_SYS_SRAM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SRAM0 // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_BITS 0x10000000 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_MSB 28 -#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_LSB 28 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_BITS _u(0x10000000) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_MSB _u(28) +#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_LSB _u(28) #define CLOCKS_ENABLED0_CLK_SYS_SRAM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SPI1 // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_SPI1_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_SPI1_BITS 0x08000000 -#define CLOCKS_ENABLED0_CLK_SYS_SPI1_MSB 27 -#define CLOCKS_ENABLED0_CLK_SYS_SPI1_LSB 27 +#define CLOCKS_ENABLED0_CLK_SYS_SPI1_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_SPI1_BITS _u(0x08000000) +#define CLOCKS_ENABLED0_CLK_SYS_SPI1_MSB _u(27) +#define CLOCKS_ENABLED0_CLK_SYS_SPI1_LSB _u(27) #define CLOCKS_ENABLED0_CLK_SYS_SPI1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_PERI_SPI1 // Description : None -#define CLOCKS_ENABLED0_CLK_PERI_SPI1_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_PERI_SPI1_BITS 0x04000000 -#define CLOCKS_ENABLED0_CLK_PERI_SPI1_MSB 26 -#define CLOCKS_ENABLED0_CLK_PERI_SPI1_LSB 26 +#define CLOCKS_ENABLED0_CLK_PERI_SPI1_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_PERI_SPI1_BITS _u(0x04000000) +#define CLOCKS_ENABLED0_CLK_PERI_SPI1_MSB _u(26) +#define CLOCKS_ENABLED0_CLK_PERI_SPI1_LSB _u(26) #define CLOCKS_ENABLED0_CLK_PERI_SPI1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SPI0 // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_SPI0_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_SPI0_BITS 0x02000000 -#define CLOCKS_ENABLED0_CLK_SYS_SPI0_MSB 25 -#define CLOCKS_ENABLED0_CLK_SYS_SPI0_LSB 25 +#define CLOCKS_ENABLED0_CLK_SYS_SPI0_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_SPI0_BITS _u(0x02000000) +#define CLOCKS_ENABLED0_CLK_SYS_SPI0_MSB _u(25) +#define CLOCKS_ENABLED0_CLK_SYS_SPI0_LSB _u(25) #define CLOCKS_ENABLED0_CLK_SYS_SPI0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_PERI_SPI0 // Description : None -#define CLOCKS_ENABLED0_CLK_PERI_SPI0_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_PERI_SPI0_BITS 0x01000000 -#define CLOCKS_ENABLED0_CLK_PERI_SPI0_MSB 24 -#define CLOCKS_ENABLED0_CLK_PERI_SPI0_LSB 24 +#define CLOCKS_ENABLED0_CLK_PERI_SPI0_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_PERI_SPI0_BITS _u(0x01000000) +#define CLOCKS_ENABLED0_CLK_PERI_SPI0_MSB _u(24) +#define CLOCKS_ENABLED0_CLK_PERI_SPI0_LSB _u(24) #define CLOCKS_ENABLED0_CLK_PERI_SPI0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SIO // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_SIO_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_SIO_BITS 0x00800000 -#define CLOCKS_ENABLED0_CLK_SYS_SIO_MSB 23 -#define CLOCKS_ENABLED0_CLK_SYS_SIO_LSB 23 +#define CLOCKS_ENABLED0_CLK_SYS_SIO_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_SIO_BITS _u(0x00800000) +#define CLOCKS_ENABLED0_CLK_SYS_SIO_MSB _u(23) +#define CLOCKS_ENABLED0_CLK_SYS_SIO_LSB _u(23) #define CLOCKS_ENABLED0_CLK_SYS_SIO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_RTC // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_RTC_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_RTC_BITS 0x00400000 -#define CLOCKS_ENABLED0_CLK_SYS_RTC_MSB 22 -#define CLOCKS_ENABLED0_CLK_SYS_RTC_LSB 22 +#define CLOCKS_ENABLED0_CLK_SYS_RTC_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_RTC_BITS _u(0x00400000) +#define CLOCKS_ENABLED0_CLK_SYS_RTC_MSB _u(22) +#define CLOCKS_ENABLED0_CLK_SYS_RTC_LSB _u(22) #define CLOCKS_ENABLED0_CLK_SYS_RTC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_RTC_RTC // Description : None -#define CLOCKS_ENABLED0_CLK_RTC_RTC_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_RTC_RTC_BITS 0x00200000 -#define CLOCKS_ENABLED0_CLK_RTC_RTC_MSB 21 -#define CLOCKS_ENABLED0_CLK_RTC_RTC_LSB 21 +#define CLOCKS_ENABLED0_CLK_RTC_RTC_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_RTC_RTC_BITS _u(0x00200000) +#define CLOCKS_ENABLED0_CLK_RTC_RTC_MSB _u(21) +#define CLOCKS_ENABLED0_CLK_RTC_RTC_LSB _u(21) #define CLOCKS_ENABLED0_CLK_RTC_RTC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_ROSC // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_ROSC_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_ROSC_BITS 0x00100000 -#define CLOCKS_ENABLED0_CLK_SYS_ROSC_MSB 20 -#define CLOCKS_ENABLED0_CLK_SYS_ROSC_LSB 20 +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_BITS _u(0x00100000) +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_MSB _u(20) +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_LSB _u(20) #define CLOCKS_ENABLED0_CLK_SYS_ROSC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_ROM // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_ROM_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_ROM_BITS 0x00080000 -#define CLOCKS_ENABLED0_CLK_SYS_ROM_MSB 19 -#define CLOCKS_ENABLED0_CLK_SYS_ROM_LSB 19 +#define CLOCKS_ENABLED0_CLK_SYS_ROM_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_ROM_BITS _u(0x00080000) +#define CLOCKS_ENABLED0_CLK_SYS_ROM_MSB _u(19) +#define CLOCKS_ENABLED0_CLK_SYS_ROM_LSB _u(19) #define CLOCKS_ENABLED0_CLK_SYS_ROM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_RESETS // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_RESETS_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_RESETS_BITS 0x00040000 -#define CLOCKS_ENABLED0_CLK_SYS_RESETS_MSB 18 -#define CLOCKS_ENABLED0_CLK_SYS_RESETS_LSB 18 +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_BITS _u(0x00040000) +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_MSB _u(18) +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_LSB _u(18) #define CLOCKS_ENABLED0_CLK_SYS_RESETS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PWM // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_PWM_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_PWM_BITS 0x00020000 -#define CLOCKS_ENABLED0_CLK_SYS_PWM_MSB 17 -#define CLOCKS_ENABLED0_CLK_SYS_PWM_LSB 17 +#define CLOCKS_ENABLED0_CLK_SYS_PWM_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PWM_BITS _u(0x00020000) +#define CLOCKS_ENABLED0_CLK_SYS_PWM_MSB _u(17) +#define CLOCKS_ENABLED0_CLK_SYS_PWM_LSB _u(17) #define CLOCKS_ENABLED0_CLK_SYS_PWM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PSM // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_PSM_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_PSM_BITS 0x00010000 -#define CLOCKS_ENABLED0_CLK_SYS_PSM_MSB 16 -#define CLOCKS_ENABLED0_CLK_SYS_PSM_LSB 16 +#define CLOCKS_ENABLED0_CLK_SYS_PSM_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PSM_BITS _u(0x00010000) +#define CLOCKS_ENABLED0_CLK_SYS_PSM_MSB _u(16) +#define CLOCKS_ENABLED0_CLK_SYS_PSM_LSB _u(16) #define CLOCKS_ENABLED0_CLK_SYS_PSM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PLL_USB // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_BITS 0x00008000 -#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_MSB 15 -#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_LSB 15 +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_BITS _u(0x00008000) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_MSB _u(15) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_LSB _u(15) #define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PLL_SYS // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_BITS 0x00004000 -#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_MSB 14 -#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_LSB 14 +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_BITS _u(0x00004000) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_MSB _u(14) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_LSB _u(14) #define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PIO1 // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_PIO1_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_PIO1_BITS 0x00002000 -#define CLOCKS_ENABLED0_CLK_SYS_PIO1_MSB 13 -#define CLOCKS_ENABLED0_CLK_SYS_PIO1_LSB 13 +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_BITS _u(0x00002000) +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_MSB _u(13) +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_LSB _u(13) #define CLOCKS_ENABLED0_CLK_SYS_PIO1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PIO0 // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_PIO0_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_PIO0_BITS 0x00001000 -#define CLOCKS_ENABLED0_CLK_SYS_PIO0_MSB 12 -#define CLOCKS_ENABLED0_CLK_SYS_PIO0_LSB 12 +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_BITS _u(0x00001000) +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_MSB _u(12) +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_LSB _u(12) #define CLOCKS_ENABLED0_CLK_SYS_PIO0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PADS // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_PADS_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_PADS_BITS 0x00000800 -#define CLOCKS_ENABLED0_CLK_SYS_PADS_MSB 11 -#define CLOCKS_ENABLED0_CLK_SYS_PADS_LSB 11 +#define CLOCKS_ENABLED0_CLK_SYS_PADS_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PADS_BITS _u(0x00000800) +#define CLOCKS_ENABLED0_CLK_SYS_PADS_MSB _u(11) +#define CLOCKS_ENABLED0_CLK_SYS_PADS_LSB _u(11) #define CLOCKS_ENABLED0_CLK_SYS_PADS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_BITS 0x00000400 -#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_MSB 10 -#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_LSB 10 +#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _u(0x00000400) +#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _u(10) +#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_LSB _u(10) #define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_JTAG // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_JTAG_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_JTAG_BITS 0x00000200 -#define CLOCKS_ENABLED0_CLK_SYS_JTAG_MSB 9 -#define CLOCKS_ENABLED0_CLK_SYS_JTAG_LSB 9 +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_BITS _u(0x00000200) +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_MSB _u(9) +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_LSB _u(9) #define CLOCKS_ENABLED0_CLK_SYS_JTAG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_IO // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_IO_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_IO_BITS 0x00000100 -#define CLOCKS_ENABLED0_CLK_SYS_IO_MSB 8 -#define CLOCKS_ENABLED0_CLK_SYS_IO_LSB 8 +#define CLOCKS_ENABLED0_CLK_SYS_IO_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_IO_BITS _u(0x00000100) +#define CLOCKS_ENABLED0_CLK_SYS_IO_MSB _u(8) +#define CLOCKS_ENABLED0_CLK_SYS_IO_LSB _u(8) #define CLOCKS_ENABLED0_CLK_SYS_IO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_I2C1 // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_I2C1_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_I2C1_BITS 0x00000080 -#define CLOCKS_ENABLED0_CLK_SYS_I2C1_MSB 7 -#define CLOCKS_ENABLED0_CLK_SYS_I2C1_LSB 7 +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_BITS _u(0x00000080) +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_MSB _u(7) +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_LSB _u(7) #define CLOCKS_ENABLED0_CLK_SYS_I2C1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_I2C0 // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_I2C0_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_I2C0_BITS 0x00000040 -#define CLOCKS_ENABLED0_CLK_SYS_I2C0_MSB 6 -#define CLOCKS_ENABLED0_CLK_SYS_I2C0_LSB 6 +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_BITS _u(0x00000040) +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_MSB _u(6) +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_LSB _u(6) #define CLOCKS_ENABLED0_CLK_SYS_I2C0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_DMA // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_DMA_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_DMA_BITS 0x00000020 -#define CLOCKS_ENABLED0_CLK_SYS_DMA_MSB 5 -#define CLOCKS_ENABLED0_CLK_SYS_DMA_LSB 5 +#define CLOCKS_ENABLED0_CLK_SYS_DMA_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_DMA_BITS _u(0x00000020) +#define CLOCKS_ENABLED0_CLK_SYS_DMA_MSB _u(5) +#define CLOCKS_ENABLED0_CLK_SYS_DMA_LSB _u(5) #define CLOCKS_ENABLED0_CLK_SYS_DMA_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_BITS 0x00000010 -#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_MSB 4 -#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_LSB 4 +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_BITS _u(0x00000010) +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_MSB _u(4) +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_LSB _u(4) #define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_BUSCTRL // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_BITS 0x00000008 -#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_MSB 3 -#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_LSB 3 +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_BITS _u(0x00000008) +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_MSB _u(3) +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_LSB _u(3) #define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_ADC // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_ADC_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_ADC_BITS 0x00000004 -#define CLOCKS_ENABLED0_CLK_SYS_ADC_MSB 2 -#define CLOCKS_ENABLED0_CLK_SYS_ADC_LSB 2 +#define CLOCKS_ENABLED0_CLK_SYS_ADC_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_ADC_BITS _u(0x00000004) +#define CLOCKS_ENABLED0_CLK_SYS_ADC_MSB _u(2) +#define CLOCKS_ENABLED0_CLK_SYS_ADC_LSB _u(2) #define CLOCKS_ENABLED0_CLK_SYS_ADC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_ADC_ADC // Description : None -#define CLOCKS_ENABLED0_CLK_ADC_ADC_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_ADC_ADC_BITS 0x00000002 -#define CLOCKS_ENABLED0_CLK_ADC_ADC_MSB 1 -#define CLOCKS_ENABLED0_CLK_ADC_ADC_LSB 1 +#define CLOCKS_ENABLED0_CLK_ADC_ADC_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_ADC_ADC_BITS _u(0x00000002) +#define CLOCKS_ENABLED0_CLK_ADC_ADC_MSB _u(1) +#define CLOCKS_ENABLED0_CLK_ADC_ADC_LSB _u(1) #define CLOCKS_ENABLED0_CLK_ADC_ADC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_CLOCKS // Description : None -#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_RESET 0x0 -#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_BITS 0x00000001 -#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_MSB 0 -#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_LSB 0 +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_BITS _u(0x00000001) +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_MSB _u(0) +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_LSB _u(0) #define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_ACCESS "RO" // ============================================================================= // Register : CLOCKS_ENABLED1 // Description : indicates the state of the clock enable -#define CLOCKS_ENABLED1_OFFSET 0x000000b4 -#define CLOCKS_ENABLED1_BITS 0x00007fff -#define CLOCKS_ENABLED1_RESET 0x00000000 +#define CLOCKS_ENABLED1_OFFSET _u(0x000000b4) +#define CLOCKS_ENABLED1_BITS _u(0x00007fff) +#define CLOCKS_ENABLED1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_XOSC // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_XOSC_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_XOSC_BITS 0x00004000 -#define CLOCKS_ENABLED1_CLK_SYS_XOSC_MSB 14 -#define CLOCKS_ENABLED1_CLK_SYS_XOSC_LSB 14 +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_BITS _u(0x00004000) +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_MSB _u(14) +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_LSB _u(14) #define CLOCKS_ENABLED1_CLK_SYS_XOSC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_XIP // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_XIP_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_XIP_BITS 0x00002000 -#define CLOCKS_ENABLED1_CLK_SYS_XIP_MSB 13 -#define CLOCKS_ENABLED1_CLK_SYS_XIP_LSB 13 +#define CLOCKS_ENABLED1_CLK_SYS_XIP_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_XIP_BITS _u(0x00002000) +#define CLOCKS_ENABLED1_CLK_SYS_XIP_MSB _u(13) +#define CLOCKS_ENABLED1_CLK_SYS_XIP_LSB _u(13) #define CLOCKS_ENABLED1_CLK_SYS_XIP_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_WATCHDOG // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_BITS 0x00001000 -#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_MSB 12 -#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_LSB 12 +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_BITS _u(0x00001000) +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_MSB _u(12) +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_LSB _u(12) #define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_USB_USBCTRL // Description : None -#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_BITS 0x00000800 -#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_MSB 11 -#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_LSB 11 +#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_BITS _u(0x00000800) +#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_MSB _u(11) +#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_LSB _u(11) #define CLOCKS_ENABLED1_CLK_USB_USBCTRL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_USBCTRL // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_BITS 0x00000400 -#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_MSB 10 -#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_LSB 10 +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_BITS _u(0x00000400) +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_MSB _u(10) +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_LSB _u(10) #define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_UART1 // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_UART1_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_UART1_BITS 0x00000200 -#define CLOCKS_ENABLED1_CLK_SYS_UART1_MSB 9 -#define CLOCKS_ENABLED1_CLK_SYS_UART1_LSB 9 +#define CLOCKS_ENABLED1_CLK_SYS_UART1_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_UART1_BITS _u(0x00000200) +#define CLOCKS_ENABLED1_CLK_SYS_UART1_MSB _u(9) +#define CLOCKS_ENABLED1_CLK_SYS_UART1_LSB _u(9) #define CLOCKS_ENABLED1_CLK_SYS_UART1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_PERI_UART1 // Description : None -#define CLOCKS_ENABLED1_CLK_PERI_UART1_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_PERI_UART1_BITS 0x00000100 -#define CLOCKS_ENABLED1_CLK_PERI_UART1_MSB 8 -#define CLOCKS_ENABLED1_CLK_PERI_UART1_LSB 8 +#define CLOCKS_ENABLED1_CLK_PERI_UART1_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_PERI_UART1_BITS _u(0x00000100) +#define CLOCKS_ENABLED1_CLK_PERI_UART1_MSB _u(8) +#define CLOCKS_ENABLED1_CLK_PERI_UART1_LSB _u(8) #define CLOCKS_ENABLED1_CLK_PERI_UART1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_UART0 // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_UART0_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_UART0_BITS 0x00000080 -#define CLOCKS_ENABLED1_CLK_SYS_UART0_MSB 7 -#define CLOCKS_ENABLED1_CLK_SYS_UART0_LSB 7 +#define CLOCKS_ENABLED1_CLK_SYS_UART0_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_UART0_BITS _u(0x00000080) +#define CLOCKS_ENABLED1_CLK_SYS_UART0_MSB _u(7) +#define CLOCKS_ENABLED1_CLK_SYS_UART0_LSB _u(7) #define CLOCKS_ENABLED1_CLK_SYS_UART0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_PERI_UART0 // Description : None -#define CLOCKS_ENABLED1_CLK_PERI_UART0_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_PERI_UART0_BITS 0x00000040 -#define CLOCKS_ENABLED1_CLK_PERI_UART0_MSB 6 -#define CLOCKS_ENABLED1_CLK_PERI_UART0_LSB 6 +#define CLOCKS_ENABLED1_CLK_PERI_UART0_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_PERI_UART0_BITS _u(0x00000040) +#define CLOCKS_ENABLED1_CLK_PERI_UART0_MSB _u(6) +#define CLOCKS_ENABLED1_CLK_PERI_UART0_LSB _u(6) #define CLOCKS_ENABLED1_CLK_PERI_UART0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_TIMER // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_TIMER_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_TIMER_BITS 0x00000020 -#define CLOCKS_ENABLED1_CLK_SYS_TIMER_MSB 5 -#define CLOCKS_ENABLED1_CLK_SYS_TIMER_LSB 5 +#define CLOCKS_ENABLED1_CLK_SYS_TIMER_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER_BITS _u(0x00000020) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER_MSB _u(5) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER_LSB _u(5) #define CLOCKS_ENABLED1_CLK_SYS_TIMER_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_TBMAN // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_BITS 0x00000010 -#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_MSB 4 -#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_LSB 4 +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_BITS _u(0x00000010) +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_MSB _u(4) +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_LSB _u(4) #define CLOCKS_ENABLED1_CLK_SYS_TBMAN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_SYSINFO // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_BITS 0x00000008 -#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_MSB 3 -#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_LSB 3 +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_BITS _u(0x00000008) +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_MSB _u(3) +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_LSB _u(3) #define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_SYSCFG // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_BITS 0x00000004 -#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_MSB 2 -#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_LSB 2 +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_BITS _u(0x00000004) +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_MSB _u(2) +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_LSB _u(2) #define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_SRAM5 // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_BITS 0x00000002 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_MSB 1 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_LSB 1 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_BITS _u(0x00000002) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_MSB _u(1) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_LSB _u(1) #define CLOCKS_ENABLED1_CLK_SYS_SRAM5_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_SRAM4 // Description : None -#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_RESET 0x0 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_BITS 0x00000001 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_MSB 0 -#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_LSB 0 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_BITS _u(0x00000001) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_MSB _u(0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_LSB _u(0) #define CLOCKS_ENABLED1_CLK_SYS_SRAM4_ACCESS "RO" // ============================================================================= // Register : CLOCKS_INTR // Description : Raw Interrupts -#define CLOCKS_INTR_OFFSET 0x000000b8 -#define CLOCKS_INTR_BITS 0x00000001 -#define CLOCKS_INTR_RESET 0x00000000 +#define CLOCKS_INTR_OFFSET _u(0x000000b8) +#define CLOCKS_INTR_BITS _u(0x00000001) +#define CLOCKS_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_INTR_CLK_SYS_RESUS // Description : None -#define CLOCKS_INTR_CLK_SYS_RESUS_RESET 0x0 -#define CLOCKS_INTR_CLK_SYS_RESUS_BITS 0x00000001 -#define CLOCKS_INTR_CLK_SYS_RESUS_MSB 0 -#define CLOCKS_INTR_CLK_SYS_RESUS_LSB 0 +#define CLOCKS_INTR_CLK_SYS_RESUS_RESET _u(0x0) +#define CLOCKS_INTR_CLK_SYS_RESUS_BITS _u(0x00000001) +#define CLOCKS_INTR_CLK_SYS_RESUS_MSB _u(0) +#define CLOCKS_INTR_CLK_SYS_RESUS_LSB _u(0) #define CLOCKS_INTR_CLK_SYS_RESUS_ACCESS "RO" // ============================================================================= // Register : CLOCKS_INTE // Description : Interrupt Enable -#define CLOCKS_INTE_OFFSET 0x000000bc -#define CLOCKS_INTE_BITS 0x00000001 -#define CLOCKS_INTE_RESET 0x00000000 +#define CLOCKS_INTE_OFFSET _u(0x000000bc) +#define CLOCKS_INTE_BITS _u(0x00000001) +#define CLOCKS_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_INTE_CLK_SYS_RESUS // Description : None -#define CLOCKS_INTE_CLK_SYS_RESUS_RESET 0x0 -#define CLOCKS_INTE_CLK_SYS_RESUS_BITS 0x00000001 -#define CLOCKS_INTE_CLK_SYS_RESUS_MSB 0 -#define CLOCKS_INTE_CLK_SYS_RESUS_LSB 0 +#define CLOCKS_INTE_CLK_SYS_RESUS_RESET _u(0x0) +#define CLOCKS_INTE_CLK_SYS_RESUS_BITS _u(0x00000001) +#define CLOCKS_INTE_CLK_SYS_RESUS_MSB _u(0) +#define CLOCKS_INTE_CLK_SYS_RESUS_LSB _u(0) #define CLOCKS_INTE_CLK_SYS_RESUS_ACCESS "RW" // ============================================================================= // Register : CLOCKS_INTF // Description : Interrupt Force -#define CLOCKS_INTF_OFFSET 0x000000c0 -#define CLOCKS_INTF_BITS 0x00000001 -#define CLOCKS_INTF_RESET 0x00000000 +#define CLOCKS_INTF_OFFSET _u(0x000000c0) +#define CLOCKS_INTF_BITS _u(0x00000001) +#define CLOCKS_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_INTF_CLK_SYS_RESUS // Description : None -#define CLOCKS_INTF_CLK_SYS_RESUS_RESET 0x0 -#define CLOCKS_INTF_CLK_SYS_RESUS_BITS 0x00000001 -#define CLOCKS_INTF_CLK_SYS_RESUS_MSB 0 -#define CLOCKS_INTF_CLK_SYS_RESUS_LSB 0 +#define CLOCKS_INTF_CLK_SYS_RESUS_RESET _u(0x0) +#define CLOCKS_INTF_CLK_SYS_RESUS_BITS _u(0x00000001) +#define CLOCKS_INTF_CLK_SYS_RESUS_MSB _u(0) +#define CLOCKS_INTF_CLK_SYS_RESUS_LSB _u(0) #define CLOCKS_INTF_CLK_SYS_RESUS_ACCESS "RW" // ============================================================================= // Register : CLOCKS_INTS // Description : Interrupt status after masking & forcing -#define CLOCKS_INTS_OFFSET 0x000000c4 -#define CLOCKS_INTS_BITS 0x00000001 -#define CLOCKS_INTS_RESET 0x00000000 +#define CLOCKS_INTS_OFFSET _u(0x000000c4) +#define CLOCKS_INTS_BITS _u(0x00000001) +#define CLOCKS_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_INTS_CLK_SYS_RESUS // Description : None -#define CLOCKS_INTS_CLK_SYS_RESUS_RESET 0x0 -#define CLOCKS_INTS_CLK_SYS_RESUS_BITS 0x00000001 -#define CLOCKS_INTS_CLK_SYS_RESUS_MSB 0 -#define CLOCKS_INTS_CLK_SYS_RESUS_LSB 0 +#define CLOCKS_INTS_CLK_SYS_RESUS_RESET _u(0x0) +#define CLOCKS_INTS_CLK_SYS_RESUS_BITS _u(0x00000001) +#define CLOCKS_INTS_CLK_SYS_RESUS_MSB _u(0) +#define CLOCKS_INTS_CLK_SYS_RESUS_LSB _u(0) #define CLOCKS_INTS_CLK_SYS_RESUS_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_CLOCKS_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dma.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dma.h index 3a1fdbca1..042c3c17c 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dma.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/dma.h @@ -17,11 +17,11 @@ // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH0_READ_ADDR_OFFSET 0x00000000 -#define DMA_CH0_READ_ADDR_BITS 0xffffffff -#define DMA_CH0_READ_ADDR_RESET 0x00000000 -#define DMA_CH0_READ_ADDR_MSB 31 -#define DMA_CH0_READ_ADDR_LSB 0 +#define DMA_CH0_READ_ADDR_OFFSET _u(0x00000000) +#define DMA_CH0_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH0_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH0_READ_ADDR_MSB _u(31) +#define DMA_CH0_READ_ADDR_LSB _u(0) #define DMA_CH0_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_WRITE_ADDR @@ -29,11 +29,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH0_WRITE_ADDR_OFFSET 0x00000004 -#define DMA_CH0_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH0_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH0_WRITE_ADDR_MSB 31 -#define DMA_CH0_WRITE_ADDR_LSB 0 +#define DMA_CH0_WRITE_ADDR_OFFSET _u(0x00000004) +#define DMA_CH0_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH0_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH0_WRITE_ADDR_MSB _u(31) +#define DMA_CH0_WRITE_ADDR_LSB _u(0) #define DMA_CH0_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_TRANS_COUNT @@ -57,27 +57,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH0_TRANS_COUNT_OFFSET 0x00000008 -#define DMA_CH0_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH0_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH0_TRANS_COUNT_MSB 31 -#define DMA_CH0_TRANS_COUNT_LSB 0 +#define DMA_CH0_TRANS_COUNT_OFFSET _u(0x00000008) +#define DMA_CH0_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH0_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH0_TRANS_COUNT_MSB _u(31) +#define DMA_CH0_TRANS_COUNT_LSB _u(0) #define DMA_CH0_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_CTRL_TRIG // Description : DMA Channel 0 Control and Status -#define DMA_CH0_CTRL_TRIG_OFFSET 0x0000000c -#define DMA_CH0_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH0_CTRL_TRIG_RESET 0x00000000 +#define DMA_CH0_CTRL_TRIG_OFFSET _u(0x0000000c) +#define DMA_CH0_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH0_CTRL_TRIG_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH0_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH0_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH0_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH0_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_READ_ERROR @@ -86,10 +86,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH0_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH0_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH0_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH0_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH0_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH0_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH0_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_WRITE_ERROR @@ -98,10 +98,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH0_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_BUSY @@ -112,10 +112,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH0_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH0_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH0_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH0_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH0_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH0_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH0_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_SNIFF_EN @@ -126,10 +126,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH0_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH0_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH0_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH0_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_BSWAP @@ -137,10 +137,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH0_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH0_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH0_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH0_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH0_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH0_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH0_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_IRQ_QUIET @@ -151,10 +151,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH0_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_TREQ_SEL @@ -168,36 +168,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH0_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (0). -#define DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH0_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH0_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH0_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH0_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH0_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH0_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH0_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH0_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_RING_SIZE @@ -210,12 +210,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH0_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH0_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH0_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH0_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH0_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH0_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH0_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -223,10 +223,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH0_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH0_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_INCR_READ @@ -235,10 +235,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH0_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH0_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH0_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH0_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH0_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH0_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH0_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_DATA_SIZE @@ -248,14 +248,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH0_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -268,10 +268,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_EN @@ -281,136 +281,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH0_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH0_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH0_CTRL_TRIG_EN_MSB 0 -#define DMA_CH0_CTRL_TRIG_EN_LSB 0 +#define DMA_CH0_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH0_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH0_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH0_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL1_CTRL // Description : Alias for channel 0 CTRL register -#define DMA_CH0_AL1_CTRL_OFFSET 0x00000010 -#define DMA_CH0_AL1_CTRL_BITS 0xffffffff +#define DMA_CH0_AL1_CTRL_OFFSET _u(0x00000010) +#define DMA_CH0_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH0_AL1_CTRL_RESET "-" -#define DMA_CH0_AL1_CTRL_MSB 31 -#define DMA_CH0_AL1_CTRL_LSB 0 -#define DMA_CH0_AL1_CTRL_ACCESS "RO" +#define DMA_CH0_AL1_CTRL_MSB _u(31) +#define DMA_CH0_AL1_CTRL_LSB _u(0) +#define DMA_CH0_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL1_READ_ADDR // Description : Alias for channel 0 READ_ADDR register -#define DMA_CH0_AL1_READ_ADDR_OFFSET 0x00000014 -#define DMA_CH0_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH0_AL1_READ_ADDR_OFFSET _u(0x00000014) +#define DMA_CH0_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH0_AL1_READ_ADDR_RESET "-" -#define DMA_CH0_AL1_READ_ADDR_MSB 31 -#define DMA_CH0_AL1_READ_ADDR_LSB 0 -#define DMA_CH0_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH0_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH0_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH0_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL1_WRITE_ADDR // Description : Alias for channel 0 WRITE_ADDR register -#define DMA_CH0_AL1_WRITE_ADDR_OFFSET 0x00000018 -#define DMA_CH0_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH0_AL1_WRITE_ADDR_OFFSET _u(0x00000018) +#define DMA_CH0_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH0_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH0_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH0_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH0_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH0_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 0 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000001c -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000001c) +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH0_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL2_CTRL // Description : Alias for channel 0 CTRL register -#define DMA_CH0_AL2_CTRL_OFFSET 0x00000020 -#define DMA_CH0_AL2_CTRL_BITS 0xffffffff +#define DMA_CH0_AL2_CTRL_OFFSET _u(0x00000020) +#define DMA_CH0_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH0_AL2_CTRL_RESET "-" -#define DMA_CH0_AL2_CTRL_MSB 31 -#define DMA_CH0_AL2_CTRL_LSB 0 -#define DMA_CH0_AL2_CTRL_ACCESS "RO" +#define DMA_CH0_AL2_CTRL_MSB _u(31) +#define DMA_CH0_AL2_CTRL_LSB _u(0) +#define DMA_CH0_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL2_TRANS_COUNT // Description : Alias for channel 0 TRANS_COUNT register -#define DMA_CH0_AL2_TRANS_COUNT_OFFSET 0x00000024 -#define DMA_CH0_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH0_AL2_TRANS_COUNT_OFFSET _u(0x00000024) +#define DMA_CH0_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH0_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH0_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH0_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH0_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH0_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL2_READ_ADDR // Description : Alias for channel 0 READ_ADDR register -#define DMA_CH0_AL2_READ_ADDR_OFFSET 0x00000028 -#define DMA_CH0_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH0_AL2_READ_ADDR_OFFSET _u(0x00000028) +#define DMA_CH0_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH0_AL2_READ_ADDR_RESET "-" -#define DMA_CH0_AL2_READ_ADDR_MSB 31 -#define DMA_CH0_AL2_READ_ADDR_LSB 0 -#define DMA_CH0_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH0_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH0_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH0_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 0 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000002c -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000002c) +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH0_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL3_CTRL // Description : Alias for channel 0 CTRL register -#define DMA_CH0_AL3_CTRL_OFFSET 0x00000030 -#define DMA_CH0_AL3_CTRL_BITS 0xffffffff +#define DMA_CH0_AL3_CTRL_OFFSET _u(0x00000030) +#define DMA_CH0_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH0_AL3_CTRL_RESET "-" -#define DMA_CH0_AL3_CTRL_MSB 31 -#define DMA_CH0_AL3_CTRL_LSB 0 -#define DMA_CH0_AL3_CTRL_ACCESS "RO" +#define DMA_CH0_AL3_CTRL_MSB _u(31) +#define DMA_CH0_AL3_CTRL_LSB _u(0) +#define DMA_CH0_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL3_WRITE_ADDR // Description : Alias for channel 0 WRITE_ADDR register -#define DMA_CH0_AL3_WRITE_ADDR_OFFSET 0x00000034 -#define DMA_CH0_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH0_AL3_WRITE_ADDR_OFFSET _u(0x00000034) +#define DMA_CH0_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH0_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH0_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH0_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH0_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH0_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL3_TRANS_COUNT // Description : Alias for channel 0 TRANS_COUNT register -#define DMA_CH0_AL3_TRANS_COUNT_OFFSET 0x00000038 -#define DMA_CH0_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH0_AL3_TRANS_COUNT_OFFSET _u(0x00000038) +#define DMA_CH0_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH0_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH0_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH0_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH0_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH0_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL3_READ_ADDR_TRIG // Description : Alias for channel 0 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET 0x0000003c -#define DMA_CH0_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000003c) +#define DMA_CH0_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH0_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH0_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH0_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH0_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH0_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_READ_ADDR // Description : DMA Channel 1 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH1_READ_ADDR_OFFSET 0x00000040 -#define DMA_CH1_READ_ADDR_BITS 0xffffffff -#define DMA_CH1_READ_ADDR_RESET 0x00000000 -#define DMA_CH1_READ_ADDR_MSB 31 -#define DMA_CH1_READ_ADDR_LSB 0 +#define DMA_CH1_READ_ADDR_OFFSET _u(0x00000040) +#define DMA_CH1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH1_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH1_READ_ADDR_MSB _u(31) +#define DMA_CH1_READ_ADDR_LSB _u(0) #define DMA_CH1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_WRITE_ADDR @@ -418,11 +418,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH1_WRITE_ADDR_OFFSET 0x00000044 -#define DMA_CH1_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH1_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH1_WRITE_ADDR_MSB 31 -#define DMA_CH1_WRITE_ADDR_LSB 0 +#define DMA_CH1_WRITE_ADDR_OFFSET _u(0x00000044) +#define DMA_CH1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH1_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH1_WRITE_ADDR_MSB _u(31) +#define DMA_CH1_WRITE_ADDR_LSB _u(0) #define DMA_CH1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_TRANS_COUNT @@ -446,27 +446,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH1_TRANS_COUNT_OFFSET 0x00000048 -#define DMA_CH1_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH1_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH1_TRANS_COUNT_MSB 31 -#define DMA_CH1_TRANS_COUNT_LSB 0 +#define DMA_CH1_TRANS_COUNT_OFFSET _u(0x00000048) +#define DMA_CH1_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH1_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH1_TRANS_COUNT_MSB _u(31) +#define DMA_CH1_TRANS_COUNT_LSB _u(0) #define DMA_CH1_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_CTRL_TRIG // Description : DMA Channel 1 Control and Status -#define DMA_CH1_CTRL_TRIG_OFFSET 0x0000004c -#define DMA_CH1_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH1_CTRL_TRIG_RESET 0x00000800 +#define DMA_CH1_CTRL_TRIG_OFFSET _u(0x0000004c) +#define DMA_CH1_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH1_CTRL_TRIG_RESET _u(0x00000800) // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH1_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH1_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH1_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH1_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_READ_ERROR @@ -475,10 +475,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH1_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH1_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH1_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH1_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH1_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH1_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH1_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_WRITE_ERROR @@ -487,10 +487,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH1_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_BUSY @@ -501,10 +501,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH1_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH1_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH1_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH1_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH1_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH1_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH1_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_SNIFF_EN @@ -515,10 +515,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH1_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH1_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH1_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH1_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_BSWAP @@ -526,10 +526,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH1_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH1_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH1_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH1_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH1_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH1_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH1_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_IRQ_QUIET @@ -540,10 +540,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH1_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_TREQ_SEL @@ -557,36 +557,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH1_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (1). -#define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET 0x1 -#define DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET _u(0x1) +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH1_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH1_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH1_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH1_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH1_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH1_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH1_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH1_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_RING_SIZE @@ -599,12 +599,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH1_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH1_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH1_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH1_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH1_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH1_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH1_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -612,10 +612,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH1_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH1_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_INCR_READ @@ -624,10 +624,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH1_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH1_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH1_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH1_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH1_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH1_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH1_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_DATA_SIZE @@ -637,14 +637,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH1_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -657,10 +657,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_EN @@ -670,136 +670,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH1_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH1_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH1_CTRL_TRIG_EN_MSB 0 -#define DMA_CH1_CTRL_TRIG_EN_LSB 0 +#define DMA_CH1_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH1_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH1_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH1_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL1_CTRL // Description : Alias for channel 1 CTRL register -#define DMA_CH1_AL1_CTRL_OFFSET 0x00000050 -#define DMA_CH1_AL1_CTRL_BITS 0xffffffff +#define DMA_CH1_AL1_CTRL_OFFSET _u(0x00000050) +#define DMA_CH1_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH1_AL1_CTRL_RESET "-" -#define DMA_CH1_AL1_CTRL_MSB 31 -#define DMA_CH1_AL1_CTRL_LSB 0 -#define DMA_CH1_AL1_CTRL_ACCESS "RO" +#define DMA_CH1_AL1_CTRL_MSB _u(31) +#define DMA_CH1_AL1_CTRL_LSB _u(0) +#define DMA_CH1_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL1_READ_ADDR // Description : Alias for channel 1 READ_ADDR register -#define DMA_CH1_AL1_READ_ADDR_OFFSET 0x00000054 -#define DMA_CH1_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH1_AL1_READ_ADDR_OFFSET _u(0x00000054) +#define DMA_CH1_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH1_AL1_READ_ADDR_RESET "-" -#define DMA_CH1_AL1_READ_ADDR_MSB 31 -#define DMA_CH1_AL1_READ_ADDR_LSB 0 -#define DMA_CH1_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH1_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH1_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH1_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL1_WRITE_ADDR // Description : Alias for channel 1 WRITE_ADDR register -#define DMA_CH1_AL1_WRITE_ADDR_OFFSET 0x00000058 -#define DMA_CH1_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH1_AL1_WRITE_ADDR_OFFSET _u(0x00000058) +#define DMA_CH1_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH1_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH1_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH1_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH1_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH1_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 1 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000005c -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000005c) +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH1_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL2_CTRL // Description : Alias for channel 1 CTRL register -#define DMA_CH1_AL2_CTRL_OFFSET 0x00000060 -#define DMA_CH1_AL2_CTRL_BITS 0xffffffff +#define DMA_CH1_AL2_CTRL_OFFSET _u(0x00000060) +#define DMA_CH1_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH1_AL2_CTRL_RESET "-" -#define DMA_CH1_AL2_CTRL_MSB 31 -#define DMA_CH1_AL2_CTRL_LSB 0 -#define DMA_CH1_AL2_CTRL_ACCESS "RO" +#define DMA_CH1_AL2_CTRL_MSB _u(31) +#define DMA_CH1_AL2_CTRL_LSB _u(0) +#define DMA_CH1_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL2_TRANS_COUNT // Description : Alias for channel 1 TRANS_COUNT register -#define DMA_CH1_AL2_TRANS_COUNT_OFFSET 0x00000064 -#define DMA_CH1_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH1_AL2_TRANS_COUNT_OFFSET _u(0x00000064) +#define DMA_CH1_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH1_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH1_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH1_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH1_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH1_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL2_READ_ADDR // Description : Alias for channel 1 READ_ADDR register -#define DMA_CH1_AL2_READ_ADDR_OFFSET 0x00000068 -#define DMA_CH1_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH1_AL2_READ_ADDR_OFFSET _u(0x00000068) +#define DMA_CH1_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH1_AL2_READ_ADDR_RESET "-" -#define DMA_CH1_AL2_READ_ADDR_MSB 31 -#define DMA_CH1_AL2_READ_ADDR_LSB 0 -#define DMA_CH1_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH1_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH1_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH1_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 1 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000006c -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000006c) +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH1_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL3_CTRL // Description : Alias for channel 1 CTRL register -#define DMA_CH1_AL3_CTRL_OFFSET 0x00000070 -#define DMA_CH1_AL3_CTRL_BITS 0xffffffff +#define DMA_CH1_AL3_CTRL_OFFSET _u(0x00000070) +#define DMA_CH1_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH1_AL3_CTRL_RESET "-" -#define DMA_CH1_AL3_CTRL_MSB 31 -#define DMA_CH1_AL3_CTRL_LSB 0 -#define DMA_CH1_AL3_CTRL_ACCESS "RO" +#define DMA_CH1_AL3_CTRL_MSB _u(31) +#define DMA_CH1_AL3_CTRL_LSB _u(0) +#define DMA_CH1_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL3_WRITE_ADDR // Description : Alias for channel 1 WRITE_ADDR register -#define DMA_CH1_AL3_WRITE_ADDR_OFFSET 0x00000074 -#define DMA_CH1_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH1_AL3_WRITE_ADDR_OFFSET _u(0x00000074) +#define DMA_CH1_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH1_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH1_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH1_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH1_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH1_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL3_TRANS_COUNT // Description : Alias for channel 1 TRANS_COUNT register -#define DMA_CH1_AL3_TRANS_COUNT_OFFSET 0x00000078 -#define DMA_CH1_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH1_AL3_TRANS_COUNT_OFFSET _u(0x00000078) +#define DMA_CH1_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH1_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH1_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH1_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH1_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH1_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL3_READ_ADDR_TRIG // Description : Alias for channel 1 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH1_AL3_READ_ADDR_TRIG_OFFSET 0x0000007c -#define DMA_CH1_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH1_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000007c) +#define DMA_CH1_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH1_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH1_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH1_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH1_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH1_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_READ_ADDR // Description : DMA Channel 2 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH2_READ_ADDR_OFFSET 0x00000080 -#define DMA_CH2_READ_ADDR_BITS 0xffffffff -#define DMA_CH2_READ_ADDR_RESET 0x00000000 -#define DMA_CH2_READ_ADDR_MSB 31 -#define DMA_CH2_READ_ADDR_LSB 0 +#define DMA_CH2_READ_ADDR_OFFSET _u(0x00000080) +#define DMA_CH2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH2_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH2_READ_ADDR_MSB _u(31) +#define DMA_CH2_READ_ADDR_LSB _u(0) #define DMA_CH2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_WRITE_ADDR @@ -807,11 +807,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH2_WRITE_ADDR_OFFSET 0x00000084 -#define DMA_CH2_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH2_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH2_WRITE_ADDR_MSB 31 -#define DMA_CH2_WRITE_ADDR_LSB 0 +#define DMA_CH2_WRITE_ADDR_OFFSET _u(0x00000084) +#define DMA_CH2_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH2_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH2_WRITE_ADDR_MSB _u(31) +#define DMA_CH2_WRITE_ADDR_LSB _u(0) #define DMA_CH2_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_TRANS_COUNT @@ -835,27 +835,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH2_TRANS_COUNT_OFFSET 0x00000088 -#define DMA_CH2_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH2_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH2_TRANS_COUNT_MSB 31 -#define DMA_CH2_TRANS_COUNT_LSB 0 +#define DMA_CH2_TRANS_COUNT_OFFSET _u(0x00000088) +#define DMA_CH2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH2_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH2_TRANS_COUNT_MSB _u(31) +#define DMA_CH2_TRANS_COUNT_LSB _u(0) #define DMA_CH2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_CTRL_TRIG // Description : DMA Channel 2 Control and Status -#define DMA_CH2_CTRL_TRIG_OFFSET 0x0000008c -#define DMA_CH2_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH2_CTRL_TRIG_RESET 0x00001000 +#define DMA_CH2_CTRL_TRIG_OFFSET _u(0x0000008c) +#define DMA_CH2_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH2_CTRL_TRIG_RESET _u(0x00001000) // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH2_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH2_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH2_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH2_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_READ_ERROR @@ -864,10 +864,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH2_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH2_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH2_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH2_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH2_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH2_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH2_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_WRITE_ERROR @@ -876,10 +876,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH2_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_BUSY @@ -890,10 +890,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH2_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH2_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH2_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH2_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH2_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH2_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH2_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_SNIFF_EN @@ -904,10 +904,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH2_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH2_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH2_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH2_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_BSWAP @@ -915,10 +915,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH2_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH2_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH2_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH2_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH2_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH2_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH2_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_IRQ_QUIET @@ -929,10 +929,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH2_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_TREQ_SEL @@ -946,36 +946,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH2_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (2). -#define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET 0x2 -#define DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET _u(0x2) +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH2_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH2_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH2_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH2_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH2_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH2_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH2_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH2_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_RING_SIZE @@ -988,12 +988,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH2_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH2_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH2_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH2_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH2_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH2_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH2_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -1001,10 +1001,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH2_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH2_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_INCR_READ @@ -1013,10 +1013,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH2_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH2_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH2_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH2_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH2_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH2_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH2_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_DATA_SIZE @@ -1026,14 +1026,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH2_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -1046,10 +1046,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_EN @@ -1059,136 +1059,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH2_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH2_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH2_CTRL_TRIG_EN_MSB 0 -#define DMA_CH2_CTRL_TRIG_EN_LSB 0 +#define DMA_CH2_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH2_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH2_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH2_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL1_CTRL // Description : Alias for channel 2 CTRL register -#define DMA_CH2_AL1_CTRL_OFFSET 0x00000090 -#define DMA_CH2_AL1_CTRL_BITS 0xffffffff +#define DMA_CH2_AL1_CTRL_OFFSET _u(0x00000090) +#define DMA_CH2_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH2_AL1_CTRL_RESET "-" -#define DMA_CH2_AL1_CTRL_MSB 31 -#define DMA_CH2_AL1_CTRL_LSB 0 -#define DMA_CH2_AL1_CTRL_ACCESS "RO" +#define DMA_CH2_AL1_CTRL_MSB _u(31) +#define DMA_CH2_AL1_CTRL_LSB _u(0) +#define DMA_CH2_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL1_READ_ADDR // Description : Alias for channel 2 READ_ADDR register -#define DMA_CH2_AL1_READ_ADDR_OFFSET 0x00000094 -#define DMA_CH2_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH2_AL1_READ_ADDR_OFFSET _u(0x00000094) +#define DMA_CH2_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH2_AL1_READ_ADDR_RESET "-" -#define DMA_CH2_AL1_READ_ADDR_MSB 31 -#define DMA_CH2_AL1_READ_ADDR_LSB 0 -#define DMA_CH2_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH2_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH2_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH2_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL1_WRITE_ADDR // Description : Alias for channel 2 WRITE_ADDR register -#define DMA_CH2_AL1_WRITE_ADDR_OFFSET 0x00000098 -#define DMA_CH2_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH2_AL1_WRITE_ADDR_OFFSET _u(0x00000098) +#define DMA_CH2_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH2_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH2_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH2_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH2_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH2_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 2 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000009c -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000009c) +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH2_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL2_CTRL // Description : Alias for channel 2 CTRL register -#define DMA_CH2_AL2_CTRL_OFFSET 0x000000a0 -#define DMA_CH2_AL2_CTRL_BITS 0xffffffff +#define DMA_CH2_AL2_CTRL_OFFSET _u(0x000000a0) +#define DMA_CH2_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH2_AL2_CTRL_RESET "-" -#define DMA_CH2_AL2_CTRL_MSB 31 -#define DMA_CH2_AL2_CTRL_LSB 0 -#define DMA_CH2_AL2_CTRL_ACCESS "RO" +#define DMA_CH2_AL2_CTRL_MSB _u(31) +#define DMA_CH2_AL2_CTRL_LSB _u(0) +#define DMA_CH2_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL2_TRANS_COUNT // Description : Alias for channel 2 TRANS_COUNT register -#define DMA_CH2_AL2_TRANS_COUNT_OFFSET 0x000000a4 -#define DMA_CH2_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH2_AL2_TRANS_COUNT_OFFSET _u(0x000000a4) +#define DMA_CH2_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH2_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH2_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH2_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH2_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH2_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL2_READ_ADDR // Description : Alias for channel 2 READ_ADDR register -#define DMA_CH2_AL2_READ_ADDR_OFFSET 0x000000a8 -#define DMA_CH2_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH2_AL2_READ_ADDR_OFFSET _u(0x000000a8) +#define DMA_CH2_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH2_AL2_READ_ADDR_RESET "-" -#define DMA_CH2_AL2_READ_ADDR_MSB 31 -#define DMA_CH2_AL2_READ_ADDR_LSB 0 -#define DMA_CH2_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH2_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH2_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH2_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 2 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_OFFSET 0x000000ac -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ac) +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH2_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL3_CTRL // Description : Alias for channel 2 CTRL register -#define DMA_CH2_AL3_CTRL_OFFSET 0x000000b0 -#define DMA_CH2_AL3_CTRL_BITS 0xffffffff +#define DMA_CH2_AL3_CTRL_OFFSET _u(0x000000b0) +#define DMA_CH2_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH2_AL3_CTRL_RESET "-" -#define DMA_CH2_AL3_CTRL_MSB 31 -#define DMA_CH2_AL3_CTRL_LSB 0 -#define DMA_CH2_AL3_CTRL_ACCESS "RO" +#define DMA_CH2_AL3_CTRL_MSB _u(31) +#define DMA_CH2_AL3_CTRL_LSB _u(0) +#define DMA_CH2_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL3_WRITE_ADDR // Description : Alias for channel 2 WRITE_ADDR register -#define DMA_CH2_AL3_WRITE_ADDR_OFFSET 0x000000b4 -#define DMA_CH2_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH2_AL3_WRITE_ADDR_OFFSET _u(0x000000b4) +#define DMA_CH2_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH2_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH2_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH2_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH2_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH2_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL3_TRANS_COUNT // Description : Alias for channel 2 TRANS_COUNT register -#define DMA_CH2_AL3_TRANS_COUNT_OFFSET 0x000000b8 -#define DMA_CH2_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH2_AL3_TRANS_COUNT_OFFSET _u(0x000000b8) +#define DMA_CH2_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH2_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH2_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH2_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH2_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH2_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL3_READ_ADDR_TRIG // Description : Alias for channel 2 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH2_AL3_READ_ADDR_TRIG_OFFSET 0x000000bc -#define DMA_CH2_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH2_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000bc) +#define DMA_CH2_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH2_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH2_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH2_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH2_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH2_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_READ_ADDR // Description : DMA Channel 3 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH3_READ_ADDR_OFFSET 0x000000c0 -#define DMA_CH3_READ_ADDR_BITS 0xffffffff -#define DMA_CH3_READ_ADDR_RESET 0x00000000 -#define DMA_CH3_READ_ADDR_MSB 31 -#define DMA_CH3_READ_ADDR_LSB 0 +#define DMA_CH3_READ_ADDR_OFFSET _u(0x000000c0) +#define DMA_CH3_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH3_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH3_READ_ADDR_MSB _u(31) +#define DMA_CH3_READ_ADDR_LSB _u(0) #define DMA_CH3_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_WRITE_ADDR @@ -1196,11 +1196,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH3_WRITE_ADDR_OFFSET 0x000000c4 -#define DMA_CH3_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH3_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH3_WRITE_ADDR_MSB 31 -#define DMA_CH3_WRITE_ADDR_LSB 0 +#define DMA_CH3_WRITE_ADDR_OFFSET _u(0x000000c4) +#define DMA_CH3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH3_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH3_WRITE_ADDR_MSB _u(31) +#define DMA_CH3_WRITE_ADDR_LSB _u(0) #define DMA_CH3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_TRANS_COUNT @@ -1224,27 +1224,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH3_TRANS_COUNT_OFFSET 0x000000c8 -#define DMA_CH3_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH3_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH3_TRANS_COUNT_MSB 31 -#define DMA_CH3_TRANS_COUNT_LSB 0 +#define DMA_CH3_TRANS_COUNT_OFFSET _u(0x000000c8) +#define DMA_CH3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH3_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH3_TRANS_COUNT_MSB _u(31) +#define DMA_CH3_TRANS_COUNT_LSB _u(0) #define DMA_CH3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_CTRL_TRIG // Description : DMA Channel 3 Control and Status -#define DMA_CH3_CTRL_TRIG_OFFSET 0x000000cc -#define DMA_CH3_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH3_CTRL_TRIG_RESET 0x00001800 +#define DMA_CH3_CTRL_TRIG_OFFSET _u(0x000000cc) +#define DMA_CH3_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH3_CTRL_TRIG_RESET _u(0x00001800) // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH3_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH3_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH3_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH3_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_READ_ERROR @@ -1253,10 +1253,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH3_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH3_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH3_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH3_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH3_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH3_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH3_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_WRITE_ERROR @@ -1265,10 +1265,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH3_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_BUSY @@ -1279,10 +1279,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH3_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH3_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH3_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH3_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH3_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH3_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH3_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_SNIFF_EN @@ -1293,10 +1293,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH3_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH3_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH3_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH3_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_BSWAP @@ -1304,10 +1304,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH3_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH3_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH3_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH3_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH3_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH3_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH3_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_IRQ_QUIET @@ -1318,10 +1318,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH3_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_TREQ_SEL @@ -1335,36 +1335,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH3_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (3). -#define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET 0x3 -#define DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET _u(0x3) +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH3_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH3_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH3_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH3_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH3_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH3_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH3_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH3_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_RING_SIZE @@ -1377,12 +1377,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH3_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH3_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH3_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH3_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH3_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH3_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH3_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -1390,10 +1390,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH3_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH3_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_INCR_READ @@ -1402,10 +1402,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH3_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH3_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH3_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH3_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH3_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH3_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH3_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_DATA_SIZE @@ -1415,14 +1415,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH3_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -1435,10 +1435,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_EN @@ -1448,136 +1448,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH3_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH3_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH3_CTRL_TRIG_EN_MSB 0 -#define DMA_CH3_CTRL_TRIG_EN_LSB 0 +#define DMA_CH3_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH3_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH3_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH3_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL1_CTRL // Description : Alias for channel 3 CTRL register -#define DMA_CH3_AL1_CTRL_OFFSET 0x000000d0 -#define DMA_CH3_AL1_CTRL_BITS 0xffffffff +#define DMA_CH3_AL1_CTRL_OFFSET _u(0x000000d0) +#define DMA_CH3_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH3_AL1_CTRL_RESET "-" -#define DMA_CH3_AL1_CTRL_MSB 31 -#define DMA_CH3_AL1_CTRL_LSB 0 -#define DMA_CH3_AL1_CTRL_ACCESS "RO" +#define DMA_CH3_AL1_CTRL_MSB _u(31) +#define DMA_CH3_AL1_CTRL_LSB _u(0) +#define DMA_CH3_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL1_READ_ADDR // Description : Alias for channel 3 READ_ADDR register -#define DMA_CH3_AL1_READ_ADDR_OFFSET 0x000000d4 -#define DMA_CH3_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH3_AL1_READ_ADDR_OFFSET _u(0x000000d4) +#define DMA_CH3_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH3_AL1_READ_ADDR_RESET "-" -#define DMA_CH3_AL1_READ_ADDR_MSB 31 -#define DMA_CH3_AL1_READ_ADDR_LSB 0 -#define DMA_CH3_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH3_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH3_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH3_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL1_WRITE_ADDR // Description : Alias for channel 3 WRITE_ADDR register -#define DMA_CH3_AL1_WRITE_ADDR_OFFSET 0x000000d8 -#define DMA_CH3_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH3_AL1_WRITE_ADDR_OFFSET _u(0x000000d8) +#define DMA_CH3_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH3_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH3_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH3_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH3_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH3_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 3 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_OFFSET 0x000000dc -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000000dc) +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH3_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL2_CTRL // Description : Alias for channel 3 CTRL register -#define DMA_CH3_AL2_CTRL_OFFSET 0x000000e0 -#define DMA_CH3_AL2_CTRL_BITS 0xffffffff +#define DMA_CH3_AL2_CTRL_OFFSET _u(0x000000e0) +#define DMA_CH3_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH3_AL2_CTRL_RESET "-" -#define DMA_CH3_AL2_CTRL_MSB 31 -#define DMA_CH3_AL2_CTRL_LSB 0 -#define DMA_CH3_AL2_CTRL_ACCESS "RO" +#define DMA_CH3_AL2_CTRL_MSB _u(31) +#define DMA_CH3_AL2_CTRL_LSB _u(0) +#define DMA_CH3_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL2_TRANS_COUNT // Description : Alias for channel 3 TRANS_COUNT register -#define DMA_CH3_AL2_TRANS_COUNT_OFFSET 0x000000e4 -#define DMA_CH3_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH3_AL2_TRANS_COUNT_OFFSET _u(0x000000e4) +#define DMA_CH3_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH3_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH3_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH3_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH3_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH3_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL2_READ_ADDR // Description : Alias for channel 3 READ_ADDR register -#define DMA_CH3_AL2_READ_ADDR_OFFSET 0x000000e8 -#define DMA_CH3_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH3_AL2_READ_ADDR_OFFSET _u(0x000000e8) +#define DMA_CH3_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH3_AL2_READ_ADDR_RESET "-" -#define DMA_CH3_AL2_READ_ADDR_MSB 31 -#define DMA_CH3_AL2_READ_ADDR_LSB 0 -#define DMA_CH3_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH3_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH3_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH3_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 3 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_OFFSET 0x000000ec -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ec) +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH3_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL3_CTRL // Description : Alias for channel 3 CTRL register -#define DMA_CH3_AL3_CTRL_OFFSET 0x000000f0 -#define DMA_CH3_AL3_CTRL_BITS 0xffffffff +#define DMA_CH3_AL3_CTRL_OFFSET _u(0x000000f0) +#define DMA_CH3_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH3_AL3_CTRL_RESET "-" -#define DMA_CH3_AL3_CTRL_MSB 31 -#define DMA_CH3_AL3_CTRL_LSB 0 -#define DMA_CH3_AL3_CTRL_ACCESS "RO" +#define DMA_CH3_AL3_CTRL_MSB _u(31) +#define DMA_CH3_AL3_CTRL_LSB _u(0) +#define DMA_CH3_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL3_WRITE_ADDR // Description : Alias for channel 3 WRITE_ADDR register -#define DMA_CH3_AL3_WRITE_ADDR_OFFSET 0x000000f4 -#define DMA_CH3_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH3_AL3_WRITE_ADDR_OFFSET _u(0x000000f4) +#define DMA_CH3_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH3_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH3_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH3_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH3_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH3_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL3_TRANS_COUNT // Description : Alias for channel 3 TRANS_COUNT register -#define DMA_CH3_AL3_TRANS_COUNT_OFFSET 0x000000f8 -#define DMA_CH3_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH3_AL3_TRANS_COUNT_OFFSET _u(0x000000f8) +#define DMA_CH3_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH3_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH3_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH3_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH3_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH3_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL3_READ_ADDR_TRIG // Description : Alias for channel 3 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH3_AL3_READ_ADDR_TRIG_OFFSET 0x000000fc -#define DMA_CH3_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH3_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000fc) +#define DMA_CH3_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH3_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH3_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH3_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH3_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH3_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_READ_ADDR // Description : DMA Channel 4 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH4_READ_ADDR_OFFSET 0x00000100 -#define DMA_CH4_READ_ADDR_BITS 0xffffffff -#define DMA_CH4_READ_ADDR_RESET 0x00000000 -#define DMA_CH4_READ_ADDR_MSB 31 -#define DMA_CH4_READ_ADDR_LSB 0 +#define DMA_CH4_READ_ADDR_OFFSET _u(0x00000100) +#define DMA_CH4_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH4_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH4_READ_ADDR_MSB _u(31) +#define DMA_CH4_READ_ADDR_LSB _u(0) #define DMA_CH4_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_WRITE_ADDR @@ -1585,11 +1585,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH4_WRITE_ADDR_OFFSET 0x00000104 -#define DMA_CH4_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH4_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH4_WRITE_ADDR_MSB 31 -#define DMA_CH4_WRITE_ADDR_LSB 0 +#define DMA_CH4_WRITE_ADDR_OFFSET _u(0x00000104) +#define DMA_CH4_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH4_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH4_WRITE_ADDR_MSB _u(31) +#define DMA_CH4_WRITE_ADDR_LSB _u(0) #define DMA_CH4_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_TRANS_COUNT @@ -1613,27 +1613,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH4_TRANS_COUNT_OFFSET 0x00000108 -#define DMA_CH4_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH4_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH4_TRANS_COUNT_MSB 31 -#define DMA_CH4_TRANS_COUNT_LSB 0 +#define DMA_CH4_TRANS_COUNT_OFFSET _u(0x00000108) +#define DMA_CH4_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH4_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH4_TRANS_COUNT_MSB _u(31) +#define DMA_CH4_TRANS_COUNT_LSB _u(0) #define DMA_CH4_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_CTRL_TRIG // Description : DMA Channel 4 Control and Status -#define DMA_CH4_CTRL_TRIG_OFFSET 0x0000010c -#define DMA_CH4_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH4_CTRL_TRIG_RESET 0x00002000 +#define DMA_CH4_CTRL_TRIG_OFFSET _u(0x0000010c) +#define DMA_CH4_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH4_CTRL_TRIG_RESET _u(0x00002000) // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH4_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH4_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH4_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH4_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_READ_ERROR @@ -1642,10 +1642,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH4_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH4_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH4_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH4_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH4_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH4_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH4_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_WRITE_ERROR @@ -1654,10 +1654,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH4_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_BUSY @@ -1668,10 +1668,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH4_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH4_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH4_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH4_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH4_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH4_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH4_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_SNIFF_EN @@ -1682,10 +1682,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH4_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH4_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH4_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH4_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_BSWAP @@ -1693,10 +1693,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH4_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH4_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH4_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH4_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH4_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH4_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH4_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_IRQ_QUIET @@ -1707,10 +1707,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH4_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_TREQ_SEL @@ -1724,36 +1724,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH4_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (4). -#define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET 0x4 -#define DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET _u(0x4) +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH4_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH4_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH4_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH4_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH4_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH4_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH4_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH4_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_RING_SIZE @@ -1766,12 +1766,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH4_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH4_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH4_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH4_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH4_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH4_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH4_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -1779,10 +1779,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH4_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH4_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_INCR_READ @@ -1791,10 +1791,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH4_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH4_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH4_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH4_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH4_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH4_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH4_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_DATA_SIZE @@ -1804,14 +1804,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH4_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -1824,10 +1824,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_EN @@ -1837,136 +1837,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH4_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH4_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH4_CTRL_TRIG_EN_MSB 0 -#define DMA_CH4_CTRL_TRIG_EN_LSB 0 +#define DMA_CH4_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH4_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH4_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH4_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL1_CTRL // Description : Alias for channel 4 CTRL register -#define DMA_CH4_AL1_CTRL_OFFSET 0x00000110 -#define DMA_CH4_AL1_CTRL_BITS 0xffffffff +#define DMA_CH4_AL1_CTRL_OFFSET _u(0x00000110) +#define DMA_CH4_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH4_AL1_CTRL_RESET "-" -#define DMA_CH4_AL1_CTRL_MSB 31 -#define DMA_CH4_AL1_CTRL_LSB 0 -#define DMA_CH4_AL1_CTRL_ACCESS "RO" +#define DMA_CH4_AL1_CTRL_MSB _u(31) +#define DMA_CH4_AL1_CTRL_LSB _u(0) +#define DMA_CH4_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL1_READ_ADDR // Description : Alias for channel 4 READ_ADDR register -#define DMA_CH4_AL1_READ_ADDR_OFFSET 0x00000114 -#define DMA_CH4_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH4_AL1_READ_ADDR_OFFSET _u(0x00000114) +#define DMA_CH4_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH4_AL1_READ_ADDR_RESET "-" -#define DMA_CH4_AL1_READ_ADDR_MSB 31 -#define DMA_CH4_AL1_READ_ADDR_LSB 0 -#define DMA_CH4_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH4_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH4_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH4_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL1_WRITE_ADDR // Description : Alias for channel 4 WRITE_ADDR register -#define DMA_CH4_AL1_WRITE_ADDR_OFFSET 0x00000118 -#define DMA_CH4_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH4_AL1_WRITE_ADDR_OFFSET _u(0x00000118) +#define DMA_CH4_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH4_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH4_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH4_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH4_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH4_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 4 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000011c -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000011c) +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH4_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL2_CTRL // Description : Alias for channel 4 CTRL register -#define DMA_CH4_AL2_CTRL_OFFSET 0x00000120 -#define DMA_CH4_AL2_CTRL_BITS 0xffffffff +#define DMA_CH4_AL2_CTRL_OFFSET _u(0x00000120) +#define DMA_CH4_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH4_AL2_CTRL_RESET "-" -#define DMA_CH4_AL2_CTRL_MSB 31 -#define DMA_CH4_AL2_CTRL_LSB 0 -#define DMA_CH4_AL2_CTRL_ACCESS "RO" +#define DMA_CH4_AL2_CTRL_MSB _u(31) +#define DMA_CH4_AL2_CTRL_LSB _u(0) +#define DMA_CH4_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL2_TRANS_COUNT // Description : Alias for channel 4 TRANS_COUNT register -#define DMA_CH4_AL2_TRANS_COUNT_OFFSET 0x00000124 -#define DMA_CH4_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH4_AL2_TRANS_COUNT_OFFSET _u(0x00000124) +#define DMA_CH4_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH4_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH4_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH4_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH4_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH4_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL2_READ_ADDR // Description : Alias for channel 4 READ_ADDR register -#define DMA_CH4_AL2_READ_ADDR_OFFSET 0x00000128 -#define DMA_CH4_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH4_AL2_READ_ADDR_OFFSET _u(0x00000128) +#define DMA_CH4_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH4_AL2_READ_ADDR_RESET "-" -#define DMA_CH4_AL2_READ_ADDR_MSB 31 -#define DMA_CH4_AL2_READ_ADDR_LSB 0 -#define DMA_CH4_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH4_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH4_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH4_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 4 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000012c -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000012c) +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH4_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL3_CTRL // Description : Alias for channel 4 CTRL register -#define DMA_CH4_AL3_CTRL_OFFSET 0x00000130 -#define DMA_CH4_AL3_CTRL_BITS 0xffffffff +#define DMA_CH4_AL3_CTRL_OFFSET _u(0x00000130) +#define DMA_CH4_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH4_AL3_CTRL_RESET "-" -#define DMA_CH4_AL3_CTRL_MSB 31 -#define DMA_CH4_AL3_CTRL_LSB 0 -#define DMA_CH4_AL3_CTRL_ACCESS "RO" +#define DMA_CH4_AL3_CTRL_MSB _u(31) +#define DMA_CH4_AL3_CTRL_LSB _u(0) +#define DMA_CH4_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL3_WRITE_ADDR // Description : Alias for channel 4 WRITE_ADDR register -#define DMA_CH4_AL3_WRITE_ADDR_OFFSET 0x00000134 -#define DMA_CH4_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH4_AL3_WRITE_ADDR_OFFSET _u(0x00000134) +#define DMA_CH4_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH4_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH4_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH4_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH4_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH4_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL3_TRANS_COUNT // Description : Alias for channel 4 TRANS_COUNT register -#define DMA_CH4_AL3_TRANS_COUNT_OFFSET 0x00000138 -#define DMA_CH4_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH4_AL3_TRANS_COUNT_OFFSET _u(0x00000138) +#define DMA_CH4_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH4_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH4_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH4_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH4_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH4_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL3_READ_ADDR_TRIG // Description : Alias for channel 4 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH4_AL3_READ_ADDR_TRIG_OFFSET 0x0000013c -#define DMA_CH4_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH4_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000013c) +#define DMA_CH4_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH4_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH4_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH4_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH4_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH4_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_READ_ADDR // Description : DMA Channel 5 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH5_READ_ADDR_OFFSET 0x00000140 -#define DMA_CH5_READ_ADDR_BITS 0xffffffff -#define DMA_CH5_READ_ADDR_RESET 0x00000000 -#define DMA_CH5_READ_ADDR_MSB 31 -#define DMA_CH5_READ_ADDR_LSB 0 +#define DMA_CH5_READ_ADDR_OFFSET _u(0x00000140) +#define DMA_CH5_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH5_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH5_READ_ADDR_MSB _u(31) +#define DMA_CH5_READ_ADDR_LSB _u(0) #define DMA_CH5_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_WRITE_ADDR @@ -1974,11 +1974,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH5_WRITE_ADDR_OFFSET 0x00000144 -#define DMA_CH5_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH5_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH5_WRITE_ADDR_MSB 31 -#define DMA_CH5_WRITE_ADDR_LSB 0 +#define DMA_CH5_WRITE_ADDR_OFFSET _u(0x00000144) +#define DMA_CH5_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH5_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH5_WRITE_ADDR_MSB _u(31) +#define DMA_CH5_WRITE_ADDR_LSB _u(0) #define DMA_CH5_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_TRANS_COUNT @@ -2002,27 +2002,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH5_TRANS_COUNT_OFFSET 0x00000148 -#define DMA_CH5_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH5_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH5_TRANS_COUNT_MSB 31 -#define DMA_CH5_TRANS_COUNT_LSB 0 +#define DMA_CH5_TRANS_COUNT_OFFSET _u(0x00000148) +#define DMA_CH5_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH5_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH5_TRANS_COUNT_MSB _u(31) +#define DMA_CH5_TRANS_COUNT_LSB _u(0) #define DMA_CH5_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_CTRL_TRIG // Description : DMA Channel 5 Control and Status -#define DMA_CH5_CTRL_TRIG_OFFSET 0x0000014c -#define DMA_CH5_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH5_CTRL_TRIG_RESET 0x00002800 +#define DMA_CH5_CTRL_TRIG_OFFSET _u(0x0000014c) +#define DMA_CH5_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH5_CTRL_TRIG_RESET _u(0x00002800) // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH5_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH5_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH5_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH5_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_READ_ERROR @@ -2031,10 +2031,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH5_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH5_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH5_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH5_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH5_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH5_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH5_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_WRITE_ERROR @@ -2043,10 +2043,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH5_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_BUSY @@ -2057,10 +2057,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH5_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH5_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH5_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH5_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH5_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH5_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH5_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_SNIFF_EN @@ -2071,10 +2071,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH5_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH5_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH5_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH5_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_BSWAP @@ -2082,10 +2082,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH5_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH5_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH5_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH5_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH5_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH5_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH5_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_IRQ_QUIET @@ -2096,10 +2096,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH5_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_TREQ_SEL @@ -2113,36 +2113,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH5_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (5). -#define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET 0x5 -#define DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET _u(0x5) +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH5_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH5_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH5_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH5_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH5_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH5_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH5_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH5_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_RING_SIZE @@ -2155,12 +2155,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH5_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH5_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH5_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH5_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH5_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH5_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH5_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -2168,10 +2168,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH5_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH5_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_INCR_READ @@ -2180,10 +2180,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH5_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH5_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH5_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH5_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH5_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH5_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH5_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_DATA_SIZE @@ -2193,14 +2193,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH5_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -2213,10 +2213,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_EN @@ -2226,136 +2226,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH5_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH5_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH5_CTRL_TRIG_EN_MSB 0 -#define DMA_CH5_CTRL_TRIG_EN_LSB 0 +#define DMA_CH5_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH5_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH5_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH5_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL1_CTRL // Description : Alias for channel 5 CTRL register -#define DMA_CH5_AL1_CTRL_OFFSET 0x00000150 -#define DMA_CH5_AL1_CTRL_BITS 0xffffffff +#define DMA_CH5_AL1_CTRL_OFFSET _u(0x00000150) +#define DMA_CH5_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH5_AL1_CTRL_RESET "-" -#define DMA_CH5_AL1_CTRL_MSB 31 -#define DMA_CH5_AL1_CTRL_LSB 0 -#define DMA_CH5_AL1_CTRL_ACCESS "RO" +#define DMA_CH5_AL1_CTRL_MSB _u(31) +#define DMA_CH5_AL1_CTRL_LSB _u(0) +#define DMA_CH5_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL1_READ_ADDR // Description : Alias for channel 5 READ_ADDR register -#define DMA_CH5_AL1_READ_ADDR_OFFSET 0x00000154 -#define DMA_CH5_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH5_AL1_READ_ADDR_OFFSET _u(0x00000154) +#define DMA_CH5_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH5_AL1_READ_ADDR_RESET "-" -#define DMA_CH5_AL1_READ_ADDR_MSB 31 -#define DMA_CH5_AL1_READ_ADDR_LSB 0 -#define DMA_CH5_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH5_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH5_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH5_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL1_WRITE_ADDR // Description : Alias for channel 5 WRITE_ADDR register -#define DMA_CH5_AL1_WRITE_ADDR_OFFSET 0x00000158 -#define DMA_CH5_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH5_AL1_WRITE_ADDR_OFFSET _u(0x00000158) +#define DMA_CH5_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH5_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH5_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH5_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH5_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH5_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 5 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000015c -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000015c) +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH5_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL2_CTRL // Description : Alias for channel 5 CTRL register -#define DMA_CH5_AL2_CTRL_OFFSET 0x00000160 -#define DMA_CH5_AL2_CTRL_BITS 0xffffffff +#define DMA_CH5_AL2_CTRL_OFFSET _u(0x00000160) +#define DMA_CH5_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH5_AL2_CTRL_RESET "-" -#define DMA_CH5_AL2_CTRL_MSB 31 -#define DMA_CH5_AL2_CTRL_LSB 0 -#define DMA_CH5_AL2_CTRL_ACCESS "RO" +#define DMA_CH5_AL2_CTRL_MSB _u(31) +#define DMA_CH5_AL2_CTRL_LSB _u(0) +#define DMA_CH5_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL2_TRANS_COUNT // Description : Alias for channel 5 TRANS_COUNT register -#define DMA_CH5_AL2_TRANS_COUNT_OFFSET 0x00000164 -#define DMA_CH5_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH5_AL2_TRANS_COUNT_OFFSET _u(0x00000164) +#define DMA_CH5_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH5_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH5_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH5_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH5_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH5_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL2_READ_ADDR // Description : Alias for channel 5 READ_ADDR register -#define DMA_CH5_AL2_READ_ADDR_OFFSET 0x00000168 -#define DMA_CH5_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH5_AL2_READ_ADDR_OFFSET _u(0x00000168) +#define DMA_CH5_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH5_AL2_READ_ADDR_RESET "-" -#define DMA_CH5_AL2_READ_ADDR_MSB 31 -#define DMA_CH5_AL2_READ_ADDR_LSB 0 -#define DMA_CH5_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH5_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH5_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH5_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 5 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000016c -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000016c) +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH5_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL3_CTRL // Description : Alias for channel 5 CTRL register -#define DMA_CH5_AL3_CTRL_OFFSET 0x00000170 -#define DMA_CH5_AL3_CTRL_BITS 0xffffffff +#define DMA_CH5_AL3_CTRL_OFFSET _u(0x00000170) +#define DMA_CH5_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH5_AL3_CTRL_RESET "-" -#define DMA_CH5_AL3_CTRL_MSB 31 -#define DMA_CH5_AL3_CTRL_LSB 0 -#define DMA_CH5_AL3_CTRL_ACCESS "RO" +#define DMA_CH5_AL3_CTRL_MSB _u(31) +#define DMA_CH5_AL3_CTRL_LSB _u(0) +#define DMA_CH5_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL3_WRITE_ADDR // Description : Alias for channel 5 WRITE_ADDR register -#define DMA_CH5_AL3_WRITE_ADDR_OFFSET 0x00000174 -#define DMA_CH5_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH5_AL3_WRITE_ADDR_OFFSET _u(0x00000174) +#define DMA_CH5_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH5_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH5_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH5_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH5_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH5_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL3_TRANS_COUNT // Description : Alias for channel 5 TRANS_COUNT register -#define DMA_CH5_AL3_TRANS_COUNT_OFFSET 0x00000178 -#define DMA_CH5_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH5_AL3_TRANS_COUNT_OFFSET _u(0x00000178) +#define DMA_CH5_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH5_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH5_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH5_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH5_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH5_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL3_READ_ADDR_TRIG // Description : Alias for channel 5 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH5_AL3_READ_ADDR_TRIG_OFFSET 0x0000017c -#define DMA_CH5_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH5_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000017c) +#define DMA_CH5_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH5_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH5_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH5_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH5_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH5_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_READ_ADDR // Description : DMA Channel 6 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH6_READ_ADDR_OFFSET 0x00000180 -#define DMA_CH6_READ_ADDR_BITS 0xffffffff -#define DMA_CH6_READ_ADDR_RESET 0x00000000 -#define DMA_CH6_READ_ADDR_MSB 31 -#define DMA_CH6_READ_ADDR_LSB 0 +#define DMA_CH6_READ_ADDR_OFFSET _u(0x00000180) +#define DMA_CH6_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH6_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH6_READ_ADDR_MSB _u(31) +#define DMA_CH6_READ_ADDR_LSB _u(0) #define DMA_CH6_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_WRITE_ADDR @@ -2363,11 +2363,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH6_WRITE_ADDR_OFFSET 0x00000184 -#define DMA_CH6_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH6_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH6_WRITE_ADDR_MSB 31 -#define DMA_CH6_WRITE_ADDR_LSB 0 +#define DMA_CH6_WRITE_ADDR_OFFSET _u(0x00000184) +#define DMA_CH6_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH6_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH6_WRITE_ADDR_MSB _u(31) +#define DMA_CH6_WRITE_ADDR_LSB _u(0) #define DMA_CH6_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_TRANS_COUNT @@ -2391,27 +2391,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH6_TRANS_COUNT_OFFSET 0x00000188 -#define DMA_CH6_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH6_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH6_TRANS_COUNT_MSB 31 -#define DMA_CH6_TRANS_COUNT_LSB 0 +#define DMA_CH6_TRANS_COUNT_OFFSET _u(0x00000188) +#define DMA_CH6_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH6_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH6_TRANS_COUNT_MSB _u(31) +#define DMA_CH6_TRANS_COUNT_LSB _u(0) #define DMA_CH6_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_CTRL_TRIG // Description : DMA Channel 6 Control and Status -#define DMA_CH6_CTRL_TRIG_OFFSET 0x0000018c -#define DMA_CH6_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH6_CTRL_TRIG_RESET 0x00003000 +#define DMA_CH6_CTRL_TRIG_OFFSET _u(0x0000018c) +#define DMA_CH6_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH6_CTRL_TRIG_RESET _u(0x00003000) // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH6_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH6_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH6_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH6_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_READ_ERROR @@ -2420,10 +2420,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH6_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH6_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH6_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH6_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH6_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH6_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH6_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_WRITE_ERROR @@ -2432,10 +2432,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH6_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_BUSY @@ -2446,10 +2446,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH6_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH6_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH6_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH6_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH6_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH6_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH6_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_SNIFF_EN @@ -2460,10 +2460,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH6_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH6_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH6_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH6_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_BSWAP @@ -2471,10 +2471,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH6_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH6_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH6_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH6_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH6_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH6_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH6_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_IRQ_QUIET @@ -2485,10 +2485,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH6_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_TREQ_SEL @@ -2502,36 +2502,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH6_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (6). -#define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET 0x6 -#define DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET _u(0x6) +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH6_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH6_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH6_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH6_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH6_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH6_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH6_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH6_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_RING_SIZE @@ -2544,12 +2544,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH6_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH6_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH6_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH6_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH6_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH6_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH6_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -2557,10 +2557,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH6_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH6_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_INCR_READ @@ -2569,10 +2569,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH6_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH6_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH6_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH6_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH6_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH6_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH6_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_DATA_SIZE @@ -2582,14 +2582,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH6_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -2602,10 +2602,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_EN @@ -2615,136 +2615,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH6_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH6_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH6_CTRL_TRIG_EN_MSB 0 -#define DMA_CH6_CTRL_TRIG_EN_LSB 0 +#define DMA_CH6_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH6_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH6_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH6_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL1_CTRL // Description : Alias for channel 6 CTRL register -#define DMA_CH6_AL1_CTRL_OFFSET 0x00000190 -#define DMA_CH6_AL1_CTRL_BITS 0xffffffff +#define DMA_CH6_AL1_CTRL_OFFSET _u(0x00000190) +#define DMA_CH6_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH6_AL1_CTRL_RESET "-" -#define DMA_CH6_AL1_CTRL_MSB 31 -#define DMA_CH6_AL1_CTRL_LSB 0 -#define DMA_CH6_AL1_CTRL_ACCESS "RO" +#define DMA_CH6_AL1_CTRL_MSB _u(31) +#define DMA_CH6_AL1_CTRL_LSB _u(0) +#define DMA_CH6_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL1_READ_ADDR // Description : Alias for channel 6 READ_ADDR register -#define DMA_CH6_AL1_READ_ADDR_OFFSET 0x00000194 -#define DMA_CH6_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH6_AL1_READ_ADDR_OFFSET _u(0x00000194) +#define DMA_CH6_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH6_AL1_READ_ADDR_RESET "-" -#define DMA_CH6_AL1_READ_ADDR_MSB 31 -#define DMA_CH6_AL1_READ_ADDR_LSB 0 -#define DMA_CH6_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH6_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH6_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH6_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL1_WRITE_ADDR // Description : Alias for channel 6 WRITE_ADDR register -#define DMA_CH6_AL1_WRITE_ADDR_OFFSET 0x00000198 -#define DMA_CH6_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH6_AL1_WRITE_ADDR_OFFSET _u(0x00000198) +#define DMA_CH6_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH6_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH6_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH6_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH6_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH6_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 6 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000019c -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000019c) +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH6_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL2_CTRL // Description : Alias for channel 6 CTRL register -#define DMA_CH6_AL2_CTRL_OFFSET 0x000001a0 -#define DMA_CH6_AL2_CTRL_BITS 0xffffffff +#define DMA_CH6_AL2_CTRL_OFFSET _u(0x000001a0) +#define DMA_CH6_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH6_AL2_CTRL_RESET "-" -#define DMA_CH6_AL2_CTRL_MSB 31 -#define DMA_CH6_AL2_CTRL_LSB 0 -#define DMA_CH6_AL2_CTRL_ACCESS "RO" +#define DMA_CH6_AL2_CTRL_MSB _u(31) +#define DMA_CH6_AL2_CTRL_LSB _u(0) +#define DMA_CH6_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL2_TRANS_COUNT // Description : Alias for channel 6 TRANS_COUNT register -#define DMA_CH6_AL2_TRANS_COUNT_OFFSET 0x000001a4 -#define DMA_CH6_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH6_AL2_TRANS_COUNT_OFFSET _u(0x000001a4) +#define DMA_CH6_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH6_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH6_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH6_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH6_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH6_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL2_READ_ADDR // Description : Alias for channel 6 READ_ADDR register -#define DMA_CH6_AL2_READ_ADDR_OFFSET 0x000001a8 -#define DMA_CH6_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH6_AL2_READ_ADDR_OFFSET _u(0x000001a8) +#define DMA_CH6_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH6_AL2_READ_ADDR_RESET "-" -#define DMA_CH6_AL2_READ_ADDR_MSB 31 -#define DMA_CH6_AL2_READ_ADDR_LSB 0 -#define DMA_CH6_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH6_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH6_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH6_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 6 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_OFFSET 0x000001ac -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ac) +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH6_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL3_CTRL // Description : Alias for channel 6 CTRL register -#define DMA_CH6_AL3_CTRL_OFFSET 0x000001b0 -#define DMA_CH6_AL3_CTRL_BITS 0xffffffff +#define DMA_CH6_AL3_CTRL_OFFSET _u(0x000001b0) +#define DMA_CH6_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH6_AL3_CTRL_RESET "-" -#define DMA_CH6_AL3_CTRL_MSB 31 -#define DMA_CH6_AL3_CTRL_LSB 0 -#define DMA_CH6_AL3_CTRL_ACCESS "RO" +#define DMA_CH6_AL3_CTRL_MSB _u(31) +#define DMA_CH6_AL3_CTRL_LSB _u(0) +#define DMA_CH6_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL3_WRITE_ADDR // Description : Alias for channel 6 WRITE_ADDR register -#define DMA_CH6_AL3_WRITE_ADDR_OFFSET 0x000001b4 -#define DMA_CH6_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH6_AL3_WRITE_ADDR_OFFSET _u(0x000001b4) +#define DMA_CH6_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH6_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH6_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH6_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH6_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH6_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL3_TRANS_COUNT // Description : Alias for channel 6 TRANS_COUNT register -#define DMA_CH6_AL3_TRANS_COUNT_OFFSET 0x000001b8 -#define DMA_CH6_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH6_AL3_TRANS_COUNT_OFFSET _u(0x000001b8) +#define DMA_CH6_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH6_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH6_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH6_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH6_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH6_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL3_READ_ADDR_TRIG // Description : Alias for channel 6 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH6_AL3_READ_ADDR_TRIG_OFFSET 0x000001bc -#define DMA_CH6_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH6_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001bc) +#define DMA_CH6_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH6_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH6_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH6_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH6_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH6_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_READ_ADDR // Description : DMA Channel 7 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH7_READ_ADDR_OFFSET 0x000001c0 -#define DMA_CH7_READ_ADDR_BITS 0xffffffff -#define DMA_CH7_READ_ADDR_RESET 0x00000000 -#define DMA_CH7_READ_ADDR_MSB 31 -#define DMA_CH7_READ_ADDR_LSB 0 +#define DMA_CH7_READ_ADDR_OFFSET _u(0x000001c0) +#define DMA_CH7_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH7_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH7_READ_ADDR_MSB _u(31) +#define DMA_CH7_READ_ADDR_LSB _u(0) #define DMA_CH7_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_WRITE_ADDR @@ -2752,11 +2752,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH7_WRITE_ADDR_OFFSET 0x000001c4 -#define DMA_CH7_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH7_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH7_WRITE_ADDR_MSB 31 -#define DMA_CH7_WRITE_ADDR_LSB 0 +#define DMA_CH7_WRITE_ADDR_OFFSET _u(0x000001c4) +#define DMA_CH7_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH7_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH7_WRITE_ADDR_MSB _u(31) +#define DMA_CH7_WRITE_ADDR_LSB _u(0) #define DMA_CH7_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_TRANS_COUNT @@ -2780,27 +2780,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH7_TRANS_COUNT_OFFSET 0x000001c8 -#define DMA_CH7_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH7_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH7_TRANS_COUNT_MSB 31 -#define DMA_CH7_TRANS_COUNT_LSB 0 +#define DMA_CH7_TRANS_COUNT_OFFSET _u(0x000001c8) +#define DMA_CH7_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH7_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH7_TRANS_COUNT_MSB _u(31) +#define DMA_CH7_TRANS_COUNT_LSB _u(0) #define DMA_CH7_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_CTRL_TRIG // Description : DMA Channel 7 Control and Status -#define DMA_CH7_CTRL_TRIG_OFFSET 0x000001cc -#define DMA_CH7_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH7_CTRL_TRIG_RESET 0x00003800 +#define DMA_CH7_CTRL_TRIG_OFFSET _u(0x000001cc) +#define DMA_CH7_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH7_CTRL_TRIG_RESET _u(0x00003800) // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH7_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH7_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH7_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH7_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_READ_ERROR @@ -2809,10 +2809,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH7_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH7_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH7_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH7_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH7_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH7_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH7_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_WRITE_ERROR @@ -2821,10 +2821,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH7_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_BUSY @@ -2835,10 +2835,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH7_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH7_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH7_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH7_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH7_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH7_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH7_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_SNIFF_EN @@ -2849,10 +2849,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH7_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH7_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH7_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH7_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_BSWAP @@ -2860,10 +2860,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH7_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH7_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH7_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH7_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH7_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH7_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH7_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_IRQ_QUIET @@ -2874,10 +2874,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH7_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_TREQ_SEL @@ -2891,36 +2891,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH7_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (7). -#define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET 0x7 -#define DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET _u(0x7) +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH7_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH7_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH7_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH7_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH7_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH7_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH7_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH7_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_RING_SIZE @@ -2933,12 +2933,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH7_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH7_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH7_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH7_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH7_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH7_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH7_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -2946,10 +2946,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH7_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH7_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_INCR_READ @@ -2958,10 +2958,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH7_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH7_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH7_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH7_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH7_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH7_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH7_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_DATA_SIZE @@ -2971,14 +2971,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH7_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -2991,10 +2991,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_EN @@ -3004,136 +3004,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH7_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH7_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH7_CTRL_TRIG_EN_MSB 0 -#define DMA_CH7_CTRL_TRIG_EN_LSB 0 +#define DMA_CH7_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH7_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH7_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH7_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL1_CTRL // Description : Alias for channel 7 CTRL register -#define DMA_CH7_AL1_CTRL_OFFSET 0x000001d0 -#define DMA_CH7_AL1_CTRL_BITS 0xffffffff +#define DMA_CH7_AL1_CTRL_OFFSET _u(0x000001d0) +#define DMA_CH7_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH7_AL1_CTRL_RESET "-" -#define DMA_CH7_AL1_CTRL_MSB 31 -#define DMA_CH7_AL1_CTRL_LSB 0 -#define DMA_CH7_AL1_CTRL_ACCESS "RO" +#define DMA_CH7_AL1_CTRL_MSB _u(31) +#define DMA_CH7_AL1_CTRL_LSB _u(0) +#define DMA_CH7_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL1_READ_ADDR // Description : Alias for channel 7 READ_ADDR register -#define DMA_CH7_AL1_READ_ADDR_OFFSET 0x000001d4 -#define DMA_CH7_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH7_AL1_READ_ADDR_OFFSET _u(0x000001d4) +#define DMA_CH7_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH7_AL1_READ_ADDR_RESET "-" -#define DMA_CH7_AL1_READ_ADDR_MSB 31 -#define DMA_CH7_AL1_READ_ADDR_LSB 0 -#define DMA_CH7_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH7_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH7_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH7_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL1_WRITE_ADDR // Description : Alias for channel 7 WRITE_ADDR register -#define DMA_CH7_AL1_WRITE_ADDR_OFFSET 0x000001d8 -#define DMA_CH7_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH7_AL1_WRITE_ADDR_OFFSET _u(0x000001d8) +#define DMA_CH7_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH7_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH7_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH7_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH7_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH7_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH7_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH7_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 7 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_OFFSET 0x000001dc -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000001dc) +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH7_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL2_CTRL // Description : Alias for channel 7 CTRL register -#define DMA_CH7_AL2_CTRL_OFFSET 0x000001e0 -#define DMA_CH7_AL2_CTRL_BITS 0xffffffff +#define DMA_CH7_AL2_CTRL_OFFSET _u(0x000001e0) +#define DMA_CH7_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH7_AL2_CTRL_RESET "-" -#define DMA_CH7_AL2_CTRL_MSB 31 -#define DMA_CH7_AL2_CTRL_LSB 0 -#define DMA_CH7_AL2_CTRL_ACCESS "RO" +#define DMA_CH7_AL2_CTRL_MSB _u(31) +#define DMA_CH7_AL2_CTRL_LSB _u(0) +#define DMA_CH7_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL2_TRANS_COUNT // Description : Alias for channel 7 TRANS_COUNT register -#define DMA_CH7_AL2_TRANS_COUNT_OFFSET 0x000001e4 -#define DMA_CH7_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH7_AL2_TRANS_COUNT_OFFSET _u(0x000001e4) +#define DMA_CH7_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH7_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH7_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH7_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH7_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH7_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH7_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH7_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL2_READ_ADDR // Description : Alias for channel 7 READ_ADDR register -#define DMA_CH7_AL2_READ_ADDR_OFFSET 0x000001e8 -#define DMA_CH7_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH7_AL2_READ_ADDR_OFFSET _u(0x000001e8) +#define DMA_CH7_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH7_AL2_READ_ADDR_RESET "-" -#define DMA_CH7_AL2_READ_ADDR_MSB 31 -#define DMA_CH7_AL2_READ_ADDR_LSB 0 -#define DMA_CH7_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH7_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH7_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH7_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 7 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_OFFSET 0x000001ec -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ec) +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH7_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL3_CTRL // Description : Alias for channel 7 CTRL register -#define DMA_CH7_AL3_CTRL_OFFSET 0x000001f0 -#define DMA_CH7_AL3_CTRL_BITS 0xffffffff +#define DMA_CH7_AL3_CTRL_OFFSET _u(0x000001f0) +#define DMA_CH7_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH7_AL3_CTRL_RESET "-" -#define DMA_CH7_AL3_CTRL_MSB 31 -#define DMA_CH7_AL3_CTRL_LSB 0 -#define DMA_CH7_AL3_CTRL_ACCESS "RO" +#define DMA_CH7_AL3_CTRL_MSB _u(31) +#define DMA_CH7_AL3_CTRL_LSB _u(0) +#define DMA_CH7_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL3_WRITE_ADDR // Description : Alias for channel 7 WRITE_ADDR register -#define DMA_CH7_AL3_WRITE_ADDR_OFFSET 0x000001f4 -#define DMA_CH7_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH7_AL3_WRITE_ADDR_OFFSET _u(0x000001f4) +#define DMA_CH7_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH7_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH7_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH7_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH7_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH7_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH7_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH7_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL3_TRANS_COUNT // Description : Alias for channel 7 TRANS_COUNT register -#define DMA_CH7_AL3_TRANS_COUNT_OFFSET 0x000001f8 -#define DMA_CH7_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH7_AL3_TRANS_COUNT_OFFSET _u(0x000001f8) +#define DMA_CH7_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH7_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH7_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH7_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH7_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH7_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH7_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH7_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL3_READ_ADDR_TRIG // Description : Alias for channel 7 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH7_AL3_READ_ADDR_TRIG_OFFSET 0x000001fc -#define DMA_CH7_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH7_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001fc) +#define DMA_CH7_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH7_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH7_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH7_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH7_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH7_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_READ_ADDR // Description : DMA Channel 8 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH8_READ_ADDR_OFFSET 0x00000200 -#define DMA_CH8_READ_ADDR_BITS 0xffffffff -#define DMA_CH8_READ_ADDR_RESET 0x00000000 -#define DMA_CH8_READ_ADDR_MSB 31 -#define DMA_CH8_READ_ADDR_LSB 0 +#define DMA_CH8_READ_ADDR_OFFSET _u(0x00000200) +#define DMA_CH8_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH8_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH8_READ_ADDR_MSB _u(31) +#define DMA_CH8_READ_ADDR_LSB _u(0) #define DMA_CH8_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_WRITE_ADDR @@ -3141,11 +3141,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH8_WRITE_ADDR_OFFSET 0x00000204 -#define DMA_CH8_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH8_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH8_WRITE_ADDR_MSB 31 -#define DMA_CH8_WRITE_ADDR_LSB 0 +#define DMA_CH8_WRITE_ADDR_OFFSET _u(0x00000204) +#define DMA_CH8_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH8_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH8_WRITE_ADDR_MSB _u(31) +#define DMA_CH8_WRITE_ADDR_LSB _u(0) #define DMA_CH8_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_TRANS_COUNT @@ -3169,27 +3169,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH8_TRANS_COUNT_OFFSET 0x00000208 -#define DMA_CH8_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH8_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH8_TRANS_COUNT_MSB 31 -#define DMA_CH8_TRANS_COUNT_LSB 0 +#define DMA_CH8_TRANS_COUNT_OFFSET _u(0x00000208) +#define DMA_CH8_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH8_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH8_TRANS_COUNT_MSB _u(31) +#define DMA_CH8_TRANS_COUNT_LSB _u(0) #define DMA_CH8_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_CTRL_TRIG // Description : DMA Channel 8 Control and Status -#define DMA_CH8_CTRL_TRIG_OFFSET 0x0000020c -#define DMA_CH8_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH8_CTRL_TRIG_RESET 0x00004000 +#define DMA_CH8_CTRL_TRIG_OFFSET _u(0x0000020c) +#define DMA_CH8_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH8_CTRL_TRIG_RESET _u(0x00004000) // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH8_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH8_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH8_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH8_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_READ_ERROR @@ -3198,10 +3198,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH8_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH8_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH8_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH8_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH8_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH8_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH8_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_WRITE_ERROR @@ -3210,10 +3210,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH8_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_BUSY @@ -3224,10 +3224,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH8_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH8_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH8_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH8_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH8_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH8_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH8_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_SNIFF_EN @@ -3238,10 +3238,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH8_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH8_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH8_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH8_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_BSWAP @@ -3249,10 +3249,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH8_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH8_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH8_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH8_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH8_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH8_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH8_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_IRQ_QUIET @@ -3263,10 +3263,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH8_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_TREQ_SEL @@ -3280,36 +3280,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH8_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (8). -#define DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET 0x8 -#define DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET _u(0x8) +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH8_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH8_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH8_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH8_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH8_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH8_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH8_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH8_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_RING_SIZE @@ -3322,12 +3322,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH8_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH8_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH8_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH8_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH8_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH8_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH8_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -3335,10 +3335,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH8_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH8_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_INCR_READ @@ -3347,10 +3347,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH8_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH8_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH8_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH8_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH8_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH8_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH8_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_DATA_SIZE @@ -3360,14 +3360,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH8_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -3380,10 +3380,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_EN @@ -3393,136 +3393,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH8_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH8_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH8_CTRL_TRIG_EN_MSB 0 -#define DMA_CH8_CTRL_TRIG_EN_LSB 0 +#define DMA_CH8_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH8_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH8_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH8_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL1_CTRL // Description : Alias for channel 8 CTRL register -#define DMA_CH8_AL1_CTRL_OFFSET 0x00000210 -#define DMA_CH8_AL1_CTRL_BITS 0xffffffff +#define DMA_CH8_AL1_CTRL_OFFSET _u(0x00000210) +#define DMA_CH8_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH8_AL1_CTRL_RESET "-" -#define DMA_CH8_AL1_CTRL_MSB 31 -#define DMA_CH8_AL1_CTRL_LSB 0 -#define DMA_CH8_AL1_CTRL_ACCESS "RO" +#define DMA_CH8_AL1_CTRL_MSB _u(31) +#define DMA_CH8_AL1_CTRL_LSB _u(0) +#define DMA_CH8_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL1_READ_ADDR // Description : Alias for channel 8 READ_ADDR register -#define DMA_CH8_AL1_READ_ADDR_OFFSET 0x00000214 -#define DMA_CH8_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH8_AL1_READ_ADDR_OFFSET _u(0x00000214) +#define DMA_CH8_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH8_AL1_READ_ADDR_RESET "-" -#define DMA_CH8_AL1_READ_ADDR_MSB 31 -#define DMA_CH8_AL1_READ_ADDR_LSB 0 -#define DMA_CH8_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH8_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH8_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH8_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL1_WRITE_ADDR // Description : Alias for channel 8 WRITE_ADDR register -#define DMA_CH8_AL1_WRITE_ADDR_OFFSET 0x00000218 -#define DMA_CH8_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH8_AL1_WRITE_ADDR_OFFSET _u(0x00000218) +#define DMA_CH8_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH8_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH8_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH8_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH8_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH8_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH8_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH8_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 8 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000021c -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000021c) +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH8_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL2_CTRL // Description : Alias for channel 8 CTRL register -#define DMA_CH8_AL2_CTRL_OFFSET 0x00000220 -#define DMA_CH8_AL2_CTRL_BITS 0xffffffff +#define DMA_CH8_AL2_CTRL_OFFSET _u(0x00000220) +#define DMA_CH8_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH8_AL2_CTRL_RESET "-" -#define DMA_CH8_AL2_CTRL_MSB 31 -#define DMA_CH8_AL2_CTRL_LSB 0 -#define DMA_CH8_AL2_CTRL_ACCESS "RO" +#define DMA_CH8_AL2_CTRL_MSB _u(31) +#define DMA_CH8_AL2_CTRL_LSB _u(0) +#define DMA_CH8_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL2_TRANS_COUNT // Description : Alias for channel 8 TRANS_COUNT register -#define DMA_CH8_AL2_TRANS_COUNT_OFFSET 0x00000224 -#define DMA_CH8_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH8_AL2_TRANS_COUNT_OFFSET _u(0x00000224) +#define DMA_CH8_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH8_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH8_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH8_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH8_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH8_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH8_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH8_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL2_READ_ADDR // Description : Alias for channel 8 READ_ADDR register -#define DMA_CH8_AL2_READ_ADDR_OFFSET 0x00000228 -#define DMA_CH8_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH8_AL2_READ_ADDR_OFFSET _u(0x00000228) +#define DMA_CH8_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH8_AL2_READ_ADDR_RESET "-" -#define DMA_CH8_AL2_READ_ADDR_MSB 31 -#define DMA_CH8_AL2_READ_ADDR_LSB 0 -#define DMA_CH8_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH8_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH8_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH8_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 8 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000022c -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000022c) +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH8_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL3_CTRL // Description : Alias for channel 8 CTRL register -#define DMA_CH8_AL3_CTRL_OFFSET 0x00000230 -#define DMA_CH8_AL3_CTRL_BITS 0xffffffff +#define DMA_CH8_AL3_CTRL_OFFSET _u(0x00000230) +#define DMA_CH8_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH8_AL3_CTRL_RESET "-" -#define DMA_CH8_AL3_CTRL_MSB 31 -#define DMA_CH8_AL3_CTRL_LSB 0 -#define DMA_CH8_AL3_CTRL_ACCESS "RO" +#define DMA_CH8_AL3_CTRL_MSB _u(31) +#define DMA_CH8_AL3_CTRL_LSB _u(0) +#define DMA_CH8_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL3_WRITE_ADDR // Description : Alias for channel 8 WRITE_ADDR register -#define DMA_CH8_AL3_WRITE_ADDR_OFFSET 0x00000234 -#define DMA_CH8_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH8_AL3_WRITE_ADDR_OFFSET _u(0x00000234) +#define DMA_CH8_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH8_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH8_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH8_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH8_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH8_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH8_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH8_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL3_TRANS_COUNT // Description : Alias for channel 8 TRANS_COUNT register -#define DMA_CH8_AL3_TRANS_COUNT_OFFSET 0x00000238 -#define DMA_CH8_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH8_AL3_TRANS_COUNT_OFFSET _u(0x00000238) +#define DMA_CH8_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH8_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH8_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH8_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH8_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH8_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH8_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH8_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL3_READ_ADDR_TRIG // Description : Alias for channel 8 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH8_AL3_READ_ADDR_TRIG_OFFSET 0x0000023c -#define DMA_CH8_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH8_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000023c) +#define DMA_CH8_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH8_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH8_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH8_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH8_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH8_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_READ_ADDR // Description : DMA Channel 9 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH9_READ_ADDR_OFFSET 0x00000240 -#define DMA_CH9_READ_ADDR_BITS 0xffffffff -#define DMA_CH9_READ_ADDR_RESET 0x00000000 -#define DMA_CH9_READ_ADDR_MSB 31 -#define DMA_CH9_READ_ADDR_LSB 0 +#define DMA_CH9_READ_ADDR_OFFSET _u(0x00000240) +#define DMA_CH9_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH9_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH9_READ_ADDR_MSB _u(31) +#define DMA_CH9_READ_ADDR_LSB _u(0) #define DMA_CH9_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_WRITE_ADDR @@ -3530,11 +3530,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH9_WRITE_ADDR_OFFSET 0x00000244 -#define DMA_CH9_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH9_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH9_WRITE_ADDR_MSB 31 -#define DMA_CH9_WRITE_ADDR_LSB 0 +#define DMA_CH9_WRITE_ADDR_OFFSET _u(0x00000244) +#define DMA_CH9_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH9_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH9_WRITE_ADDR_MSB _u(31) +#define DMA_CH9_WRITE_ADDR_LSB _u(0) #define DMA_CH9_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_TRANS_COUNT @@ -3558,27 +3558,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH9_TRANS_COUNT_OFFSET 0x00000248 -#define DMA_CH9_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH9_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH9_TRANS_COUNT_MSB 31 -#define DMA_CH9_TRANS_COUNT_LSB 0 +#define DMA_CH9_TRANS_COUNT_OFFSET _u(0x00000248) +#define DMA_CH9_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH9_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH9_TRANS_COUNT_MSB _u(31) +#define DMA_CH9_TRANS_COUNT_LSB _u(0) #define DMA_CH9_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_CTRL_TRIG // Description : DMA Channel 9 Control and Status -#define DMA_CH9_CTRL_TRIG_OFFSET 0x0000024c -#define DMA_CH9_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH9_CTRL_TRIG_RESET 0x00004800 +#define DMA_CH9_CTRL_TRIG_OFFSET _u(0x0000024c) +#define DMA_CH9_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH9_CTRL_TRIG_RESET _u(0x00004800) // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH9_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH9_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH9_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH9_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_READ_ERROR @@ -3587,10 +3587,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH9_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH9_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH9_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH9_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH9_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH9_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH9_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_WRITE_ERROR @@ -3599,10 +3599,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH9_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_BUSY @@ -3613,10 +3613,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH9_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH9_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH9_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH9_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH9_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH9_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH9_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_SNIFF_EN @@ -3627,10 +3627,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH9_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH9_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH9_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH9_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_BSWAP @@ -3638,10 +3638,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH9_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH9_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH9_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH9_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH9_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH9_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH9_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_IRQ_QUIET @@ -3652,10 +3652,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH9_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_TREQ_SEL @@ -3669,36 +3669,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH9_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (9). -#define DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET 0x9 -#define DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET _u(0x9) +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH9_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH9_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH9_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH9_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH9_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH9_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH9_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH9_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_RING_SIZE @@ -3711,12 +3711,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH9_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH9_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH9_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH9_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH9_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH9_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH9_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -3724,10 +3724,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH9_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH9_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_INCR_READ @@ -3736,10 +3736,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH9_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH9_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH9_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH9_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH9_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH9_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH9_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_DATA_SIZE @@ -3749,14 +3749,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH9_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -3769,10 +3769,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_EN @@ -3782,136 +3782,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH9_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH9_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH9_CTRL_TRIG_EN_MSB 0 -#define DMA_CH9_CTRL_TRIG_EN_LSB 0 +#define DMA_CH9_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH9_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH9_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH9_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL1_CTRL // Description : Alias for channel 9 CTRL register -#define DMA_CH9_AL1_CTRL_OFFSET 0x00000250 -#define DMA_CH9_AL1_CTRL_BITS 0xffffffff +#define DMA_CH9_AL1_CTRL_OFFSET _u(0x00000250) +#define DMA_CH9_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH9_AL1_CTRL_RESET "-" -#define DMA_CH9_AL1_CTRL_MSB 31 -#define DMA_CH9_AL1_CTRL_LSB 0 -#define DMA_CH9_AL1_CTRL_ACCESS "RO" +#define DMA_CH9_AL1_CTRL_MSB _u(31) +#define DMA_CH9_AL1_CTRL_LSB _u(0) +#define DMA_CH9_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL1_READ_ADDR // Description : Alias for channel 9 READ_ADDR register -#define DMA_CH9_AL1_READ_ADDR_OFFSET 0x00000254 -#define DMA_CH9_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH9_AL1_READ_ADDR_OFFSET _u(0x00000254) +#define DMA_CH9_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH9_AL1_READ_ADDR_RESET "-" -#define DMA_CH9_AL1_READ_ADDR_MSB 31 -#define DMA_CH9_AL1_READ_ADDR_LSB 0 -#define DMA_CH9_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH9_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH9_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH9_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL1_WRITE_ADDR // Description : Alias for channel 9 WRITE_ADDR register -#define DMA_CH9_AL1_WRITE_ADDR_OFFSET 0x00000258 -#define DMA_CH9_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH9_AL1_WRITE_ADDR_OFFSET _u(0x00000258) +#define DMA_CH9_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH9_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH9_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH9_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH9_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH9_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH9_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH9_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 9 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000025c -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000025c) +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH9_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL2_CTRL // Description : Alias for channel 9 CTRL register -#define DMA_CH9_AL2_CTRL_OFFSET 0x00000260 -#define DMA_CH9_AL2_CTRL_BITS 0xffffffff +#define DMA_CH9_AL2_CTRL_OFFSET _u(0x00000260) +#define DMA_CH9_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH9_AL2_CTRL_RESET "-" -#define DMA_CH9_AL2_CTRL_MSB 31 -#define DMA_CH9_AL2_CTRL_LSB 0 -#define DMA_CH9_AL2_CTRL_ACCESS "RO" +#define DMA_CH9_AL2_CTRL_MSB _u(31) +#define DMA_CH9_AL2_CTRL_LSB _u(0) +#define DMA_CH9_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL2_TRANS_COUNT // Description : Alias for channel 9 TRANS_COUNT register -#define DMA_CH9_AL2_TRANS_COUNT_OFFSET 0x00000264 -#define DMA_CH9_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH9_AL2_TRANS_COUNT_OFFSET _u(0x00000264) +#define DMA_CH9_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH9_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH9_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH9_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH9_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH9_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH9_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH9_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL2_READ_ADDR // Description : Alias for channel 9 READ_ADDR register -#define DMA_CH9_AL2_READ_ADDR_OFFSET 0x00000268 -#define DMA_CH9_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH9_AL2_READ_ADDR_OFFSET _u(0x00000268) +#define DMA_CH9_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH9_AL2_READ_ADDR_RESET "-" -#define DMA_CH9_AL2_READ_ADDR_MSB 31 -#define DMA_CH9_AL2_READ_ADDR_LSB 0 -#define DMA_CH9_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH9_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH9_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH9_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 9 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000026c -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000026c) +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH9_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL3_CTRL // Description : Alias for channel 9 CTRL register -#define DMA_CH9_AL3_CTRL_OFFSET 0x00000270 -#define DMA_CH9_AL3_CTRL_BITS 0xffffffff +#define DMA_CH9_AL3_CTRL_OFFSET _u(0x00000270) +#define DMA_CH9_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH9_AL3_CTRL_RESET "-" -#define DMA_CH9_AL3_CTRL_MSB 31 -#define DMA_CH9_AL3_CTRL_LSB 0 -#define DMA_CH9_AL3_CTRL_ACCESS "RO" +#define DMA_CH9_AL3_CTRL_MSB _u(31) +#define DMA_CH9_AL3_CTRL_LSB _u(0) +#define DMA_CH9_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL3_WRITE_ADDR // Description : Alias for channel 9 WRITE_ADDR register -#define DMA_CH9_AL3_WRITE_ADDR_OFFSET 0x00000274 -#define DMA_CH9_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH9_AL3_WRITE_ADDR_OFFSET _u(0x00000274) +#define DMA_CH9_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH9_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH9_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH9_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH9_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH9_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH9_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH9_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL3_TRANS_COUNT // Description : Alias for channel 9 TRANS_COUNT register -#define DMA_CH9_AL3_TRANS_COUNT_OFFSET 0x00000278 -#define DMA_CH9_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH9_AL3_TRANS_COUNT_OFFSET _u(0x00000278) +#define DMA_CH9_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH9_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH9_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH9_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH9_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH9_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH9_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH9_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL3_READ_ADDR_TRIG // Description : Alias for channel 9 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH9_AL3_READ_ADDR_TRIG_OFFSET 0x0000027c -#define DMA_CH9_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH9_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000027c) +#define DMA_CH9_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH9_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH9_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH9_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH9_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH9_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_READ_ADDR // Description : DMA Channel 10 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH10_READ_ADDR_OFFSET 0x00000280 -#define DMA_CH10_READ_ADDR_BITS 0xffffffff -#define DMA_CH10_READ_ADDR_RESET 0x00000000 -#define DMA_CH10_READ_ADDR_MSB 31 -#define DMA_CH10_READ_ADDR_LSB 0 +#define DMA_CH10_READ_ADDR_OFFSET _u(0x00000280) +#define DMA_CH10_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH10_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH10_READ_ADDR_MSB _u(31) +#define DMA_CH10_READ_ADDR_LSB _u(0) #define DMA_CH10_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_WRITE_ADDR @@ -3919,11 +3919,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH10_WRITE_ADDR_OFFSET 0x00000284 -#define DMA_CH10_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH10_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH10_WRITE_ADDR_MSB 31 -#define DMA_CH10_WRITE_ADDR_LSB 0 +#define DMA_CH10_WRITE_ADDR_OFFSET _u(0x00000284) +#define DMA_CH10_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH10_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH10_WRITE_ADDR_MSB _u(31) +#define DMA_CH10_WRITE_ADDR_LSB _u(0) #define DMA_CH10_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_TRANS_COUNT @@ -3947,27 +3947,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH10_TRANS_COUNT_OFFSET 0x00000288 -#define DMA_CH10_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH10_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH10_TRANS_COUNT_MSB 31 -#define DMA_CH10_TRANS_COUNT_LSB 0 +#define DMA_CH10_TRANS_COUNT_OFFSET _u(0x00000288) +#define DMA_CH10_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH10_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH10_TRANS_COUNT_MSB _u(31) +#define DMA_CH10_TRANS_COUNT_LSB _u(0) #define DMA_CH10_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_CTRL_TRIG // Description : DMA Channel 10 Control and Status -#define DMA_CH10_CTRL_TRIG_OFFSET 0x0000028c -#define DMA_CH10_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH10_CTRL_TRIG_RESET 0x00005000 +#define DMA_CH10_CTRL_TRIG_OFFSET _u(0x0000028c) +#define DMA_CH10_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH10_CTRL_TRIG_RESET _u(0x00005000) // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH10_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH10_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH10_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH10_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_READ_ERROR @@ -3976,10 +3976,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH10_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH10_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH10_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH10_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH10_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH10_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH10_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_WRITE_ERROR @@ -3988,10 +3988,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH10_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_BUSY @@ -4002,10 +4002,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH10_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH10_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH10_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH10_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH10_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH10_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH10_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_SNIFF_EN @@ -4016,10 +4016,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH10_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH10_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH10_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH10_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_BSWAP @@ -4027,10 +4027,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH10_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH10_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH10_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH10_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH10_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH10_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH10_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_IRQ_QUIET @@ -4041,10 +4041,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH10_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_TREQ_SEL @@ -4058,36 +4058,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH10_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (10). -#define DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET 0xa -#define DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET _u(0xa) +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH10_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH10_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH10_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH10_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH10_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH10_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH10_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH10_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_RING_SIZE @@ -4100,12 +4100,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH10_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH10_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH10_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH10_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH10_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH10_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH10_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -4113,10 +4113,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH10_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH10_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_INCR_READ @@ -4125,10 +4125,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH10_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH10_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH10_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH10_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH10_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH10_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH10_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_DATA_SIZE @@ -4138,14 +4138,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH10_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -4158,10 +4158,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_EN @@ -4171,136 +4171,136 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH10_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH10_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH10_CTRL_TRIG_EN_MSB 0 -#define DMA_CH10_CTRL_TRIG_EN_LSB 0 +#define DMA_CH10_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH10_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH10_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH10_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL1_CTRL // Description : Alias for channel 10 CTRL register -#define DMA_CH10_AL1_CTRL_OFFSET 0x00000290 -#define DMA_CH10_AL1_CTRL_BITS 0xffffffff +#define DMA_CH10_AL1_CTRL_OFFSET _u(0x00000290) +#define DMA_CH10_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH10_AL1_CTRL_RESET "-" -#define DMA_CH10_AL1_CTRL_MSB 31 -#define DMA_CH10_AL1_CTRL_LSB 0 -#define DMA_CH10_AL1_CTRL_ACCESS "RO" +#define DMA_CH10_AL1_CTRL_MSB _u(31) +#define DMA_CH10_AL1_CTRL_LSB _u(0) +#define DMA_CH10_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL1_READ_ADDR // Description : Alias for channel 10 READ_ADDR register -#define DMA_CH10_AL1_READ_ADDR_OFFSET 0x00000294 -#define DMA_CH10_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH10_AL1_READ_ADDR_OFFSET _u(0x00000294) +#define DMA_CH10_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH10_AL1_READ_ADDR_RESET "-" -#define DMA_CH10_AL1_READ_ADDR_MSB 31 -#define DMA_CH10_AL1_READ_ADDR_LSB 0 -#define DMA_CH10_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH10_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH10_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH10_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL1_WRITE_ADDR // Description : Alias for channel 10 WRITE_ADDR register -#define DMA_CH10_AL1_WRITE_ADDR_OFFSET 0x00000298 -#define DMA_CH10_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH10_AL1_WRITE_ADDR_OFFSET _u(0x00000298) +#define DMA_CH10_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH10_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH10_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH10_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH10_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH10_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH10_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH10_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 10 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000029c -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000029c) +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH10_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL2_CTRL // Description : Alias for channel 10 CTRL register -#define DMA_CH10_AL2_CTRL_OFFSET 0x000002a0 -#define DMA_CH10_AL2_CTRL_BITS 0xffffffff +#define DMA_CH10_AL2_CTRL_OFFSET _u(0x000002a0) +#define DMA_CH10_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH10_AL2_CTRL_RESET "-" -#define DMA_CH10_AL2_CTRL_MSB 31 -#define DMA_CH10_AL2_CTRL_LSB 0 -#define DMA_CH10_AL2_CTRL_ACCESS "RO" +#define DMA_CH10_AL2_CTRL_MSB _u(31) +#define DMA_CH10_AL2_CTRL_LSB _u(0) +#define DMA_CH10_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL2_TRANS_COUNT // Description : Alias for channel 10 TRANS_COUNT register -#define DMA_CH10_AL2_TRANS_COUNT_OFFSET 0x000002a4 -#define DMA_CH10_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH10_AL2_TRANS_COUNT_OFFSET _u(0x000002a4) +#define DMA_CH10_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH10_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH10_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH10_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH10_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH10_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH10_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH10_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL2_READ_ADDR // Description : Alias for channel 10 READ_ADDR register -#define DMA_CH10_AL2_READ_ADDR_OFFSET 0x000002a8 -#define DMA_CH10_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH10_AL2_READ_ADDR_OFFSET _u(0x000002a8) +#define DMA_CH10_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH10_AL2_READ_ADDR_RESET "-" -#define DMA_CH10_AL2_READ_ADDR_MSB 31 -#define DMA_CH10_AL2_READ_ADDR_LSB 0 -#define DMA_CH10_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH10_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH10_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH10_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 10 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_OFFSET 0x000002ac -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ac) +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH10_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL3_CTRL // Description : Alias for channel 10 CTRL register -#define DMA_CH10_AL3_CTRL_OFFSET 0x000002b0 -#define DMA_CH10_AL3_CTRL_BITS 0xffffffff +#define DMA_CH10_AL3_CTRL_OFFSET _u(0x000002b0) +#define DMA_CH10_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH10_AL3_CTRL_RESET "-" -#define DMA_CH10_AL3_CTRL_MSB 31 -#define DMA_CH10_AL3_CTRL_LSB 0 -#define DMA_CH10_AL3_CTRL_ACCESS "RO" +#define DMA_CH10_AL3_CTRL_MSB _u(31) +#define DMA_CH10_AL3_CTRL_LSB _u(0) +#define DMA_CH10_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL3_WRITE_ADDR // Description : Alias for channel 10 WRITE_ADDR register -#define DMA_CH10_AL3_WRITE_ADDR_OFFSET 0x000002b4 -#define DMA_CH10_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH10_AL3_WRITE_ADDR_OFFSET _u(0x000002b4) +#define DMA_CH10_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH10_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH10_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH10_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH10_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH10_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH10_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH10_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL3_TRANS_COUNT // Description : Alias for channel 10 TRANS_COUNT register -#define DMA_CH10_AL3_TRANS_COUNT_OFFSET 0x000002b8 -#define DMA_CH10_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH10_AL3_TRANS_COUNT_OFFSET _u(0x000002b8) +#define DMA_CH10_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH10_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH10_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH10_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH10_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH10_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH10_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH10_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL3_READ_ADDR_TRIG // Description : Alias for channel 10 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH10_AL3_READ_ADDR_TRIG_OFFSET 0x000002bc -#define DMA_CH10_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH10_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002bc) +#define DMA_CH10_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH10_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH10_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH10_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH10_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH10_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_READ_ADDR // Description : DMA Channel 11 Read Address pointer // This register updates automatically each time a read completes. // The current value is the next address to be read by this // channel. -#define DMA_CH11_READ_ADDR_OFFSET 0x000002c0 -#define DMA_CH11_READ_ADDR_BITS 0xffffffff -#define DMA_CH11_READ_ADDR_RESET 0x00000000 -#define DMA_CH11_READ_ADDR_MSB 31 -#define DMA_CH11_READ_ADDR_LSB 0 +#define DMA_CH11_READ_ADDR_OFFSET _u(0x000002c0) +#define DMA_CH11_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH11_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH11_READ_ADDR_MSB _u(31) +#define DMA_CH11_READ_ADDR_LSB _u(0) #define DMA_CH11_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_WRITE_ADDR @@ -4308,11 +4308,11 @@ // This register updates automatically each time a write // completes. The current value is the next address to be written // by this channel. -#define DMA_CH11_WRITE_ADDR_OFFSET 0x000002c4 -#define DMA_CH11_WRITE_ADDR_BITS 0xffffffff -#define DMA_CH11_WRITE_ADDR_RESET 0x00000000 -#define DMA_CH11_WRITE_ADDR_MSB 31 -#define DMA_CH11_WRITE_ADDR_LSB 0 +#define DMA_CH11_WRITE_ADDR_OFFSET _u(0x000002c4) +#define DMA_CH11_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH11_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH11_WRITE_ADDR_MSB _u(31) +#define DMA_CH11_WRITE_ADDR_LSB _u(0) #define DMA_CH11_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_TRANS_COUNT @@ -4336,27 +4336,27 @@ // is used as a trigger, the written value is used immediately as // the length of the new transfer sequence, as well as being // written to RELOAD. -#define DMA_CH11_TRANS_COUNT_OFFSET 0x000002c8 -#define DMA_CH11_TRANS_COUNT_BITS 0xffffffff -#define DMA_CH11_TRANS_COUNT_RESET 0x00000000 -#define DMA_CH11_TRANS_COUNT_MSB 31 -#define DMA_CH11_TRANS_COUNT_LSB 0 +#define DMA_CH11_TRANS_COUNT_OFFSET _u(0x000002c8) +#define DMA_CH11_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH11_TRANS_COUNT_RESET _u(0x00000000) +#define DMA_CH11_TRANS_COUNT_MSB _u(31) +#define DMA_CH11_TRANS_COUNT_LSB _u(0) #define DMA_CH11_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_CTRL_TRIG // Description : DMA Channel 11 Control and Status -#define DMA_CH11_CTRL_TRIG_OFFSET 0x000002cc -#define DMA_CH11_CTRL_TRIG_BITS 0xe1ffffff -#define DMA_CH11_CTRL_TRIG_RESET 0x00005800 +#define DMA_CH11_CTRL_TRIG_OFFSET _u(0x000002cc) +#define DMA_CH11_CTRL_TRIG_BITS _u(0xe1ffffff) +#define DMA_CH11_CTRL_TRIG_RESET _u(0x00005800) // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel // halts when it encounters any bus error, and always raises its // channel IRQ flag. -#define DMA_CH11_CTRL_TRIG_AHB_ERROR_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 -#define DMA_CH11_CTRL_TRIG_AHB_ERROR_MSB 31 -#define DMA_CH11_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_LSB _u(31) #define DMA_CH11_CTRL_TRIG_AHB_ERROR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_READ_ERROR @@ -4365,10 +4365,10 @@ // READ_ADDR shows the approximate address where the bus error was // encountered (will not to be earlier, or more than 3 transfers // later) -#define DMA_CH11_CTRL_TRIG_READ_ERROR_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_READ_ERROR_BITS 0x40000000 -#define DMA_CH11_CTRL_TRIG_READ_ERROR_MSB 30 -#define DMA_CH11_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH11_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH11_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH11_CTRL_TRIG_READ_ERROR_LSB _u(30) #define DMA_CH11_CTRL_TRIG_READ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_WRITE_ERROR @@ -4377,10 +4377,10 @@ // WRITE_ADDR shows the approximate address where the bus error // was encountered (will not to be earlier, or more than 5 // transfers later) -#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 -#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_MSB 29 -#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_LSB _u(29) #define DMA_CH11_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_BUSY @@ -4391,10 +4391,10 @@ // // To terminate a sequence early (and clear the BUSY flag), see // CHAN_ABORT. -#define DMA_CH11_CTRL_TRIG_BUSY_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_BUSY_BITS 0x01000000 -#define DMA_CH11_CTRL_TRIG_BUSY_MSB 24 -#define DMA_CH11_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH11_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_BUSY_BITS _u(0x01000000) +#define DMA_CH11_CTRL_TRIG_BUSY_MSB _u(24) +#define DMA_CH11_CTRL_TRIG_BUSY_LSB _u(24) #define DMA_CH11_CTRL_TRIG_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_SNIFF_EN @@ -4405,10 +4405,10 @@ // // This allows checksum to be enabled or disabled on a // per-control- block basis. -#define DMA_CH11_CTRL_TRIG_SNIFF_EN_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 -#define DMA_CH11_CTRL_TRIG_SNIFF_EN_MSB 23 -#define DMA_CH11_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_MSB _u(23) +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_LSB _u(23) #define DMA_CH11_CTRL_TRIG_SNIFF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_BSWAP @@ -4416,10 +4416,10 @@ // For byte data, this has no effect. For halfword data, the two // bytes of each halfword are swapped. For word data, the four // bytes of each word are swapped to reverse order. -#define DMA_CH11_CTRL_TRIG_BSWAP_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_BSWAP_BITS 0x00400000 -#define DMA_CH11_CTRL_TRIG_BSWAP_MSB 22 -#define DMA_CH11_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH11_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_BSWAP_BITS _u(0x00400000) +#define DMA_CH11_CTRL_TRIG_BSWAP_MSB _u(22) +#define DMA_CH11_CTRL_TRIG_BSWAP_LSB _u(22) #define DMA_CH11_CTRL_TRIG_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_IRQ_QUIET @@ -4430,10 +4430,10 @@ // // This reduces the number of interrupts to be serviced by the CPU // when transferring a DMA chain of many small control blocks. -#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 -#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_MSB 21 -#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000) +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_MSB _u(21) +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_LSB _u(21) #define DMA_CH11_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_TREQ_SEL @@ -4447,36 +4447,36 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET 0x00 -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB 20 -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB _u(15) #define DMA_CH11_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. // Reset value is equal to channel number (11). -#define DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET 0xb -#define DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 -#define DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB 14 -#define DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET _u(0xb) +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB _u(14) +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB _u(11) #define DMA_CH11_CTRL_TRIG_CHAIN_TO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_RING_SEL // Description : Select whether RING_SIZE applies to read or write addresses. // If 0, read addresses are wrapped on a (1 << RING_SIZE) // boundary. If 1, write addresses are wrapped. -#define DMA_CH11_CTRL_TRIG_RING_SEL_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_RING_SEL_BITS 0x00000400 -#define DMA_CH11_CTRL_TRIG_RING_SEL_MSB 10 -#define DMA_CH11_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH11_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_RING_SEL_BITS _u(0x00000400) +#define DMA_CH11_CTRL_TRIG_RING_SEL_MSB _u(10) +#define DMA_CH11_CTRL_TRIG_RING_SEL_LSB _u(10) #define DMA_CH11_CTRL_TRIG_RING_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_RING_SIZE @@ -4489,12 +4489,12 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH11_CTRL_TRIG_RING_SIZE_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 -#define DMA_CH11_CTRL_TRIG_RING_SIZE_MSB 9 -#define DMA_CH11_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH11_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_LSB _u(6) #define DMA_CH11_CTRL_TRIG_RING_SIZE_ACCESS "RW" -#define DMA_CH11_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +#define DMA_CH11_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_INCR_WRITE // Description : If 1, the write address increments with each transfer. If 0, @@ -4502,10 +4502,10 @@ // // Generally this should be disabled for memory-to-peripheral // transfers. -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_MSB 5 -#define DMA_CH11_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_MSB _u(5) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_LSB _u(5) #define DMA_CH11_CTRL_TRIG_INCR_WRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_INCR_READ @@ -4514,10 +4514,10 @@ // // Generally this should be disabled for peripheral-to-memory // transfers. -#define DMA_CH11_CTRL_TRIG_INCR_READ_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_INCR_READ_BITS 0x00000010 -#define DMA_CH11_CTRL_TRIG_INCR_READ_MSB 4 -#define DMA_CH11_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH11_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH11_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH11_CTRL_TRIG_INCR_READ_LSB _u(4) #define DMA_CH11_CTRL_TRIG_INCR_READ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_DATA_SIZE @@ -4527,14 +4527,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB 3 -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB _u(2) #define DMA_CH11_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -4547,10 +4547,10 @@ // channels. The DMA's bus priority is not changed. If the DMA is // not saturated then a low priority channel will see no loss of // throughput. -#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 -#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_MSB 1 -#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) #define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_EN @@ -4560,125 +4560,125 @@ // 0, the channel will ignore triggers, stop issuing transfers, // and pause the current transfer sequence (i.e. BUSY will remain // high if already high) -#define DMA_CH11_CTRL_TRIG_EN_RESET 0x0 -#define DMA_CH11_CTRL_TRIG_EN_BITS 0x00000001 -#define DMA_CH11_CTRL_TRIG_EN_MSB 0 -#define DMA_CH11_CTRL_TRIG_EN_LSB 0 +#define DMA_CH11_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH11_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH11_CTRL_TRIG_EN_LSB _u(0) #define DMA_CH11_CTRL_TRIG_EN_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL1_CTRL // Description : Alias for channel 11 CTRL register -#define DMA_CH11_AL1_CTRL_OFFSET 0x000002d0 -#define DMA_CH11_AL1_CTRL_BITS 0xffffffff +#define DMA_CH11_AL1_CTRL_OFFSET _u(0x000002d0) +#define DMA_CH11_AL1_CTRL_BITS _u(0xffffffff) #define DMA_CH11_AL1_CTRL_RESET "-" -#define DMA_CH11_AL1_CTRL_MSB 31 -#define DMA_CH11_AL1_CTRL_LSB 0 -#define DMA_CH11_AL1_CTRL_ACCESS "RO" +#define DMA_CH11_AL1_CTRL_MSB _u(31) +#define DMA_CH11_AL1_CTRL_LSB _u(0) +#define DMA_CH11_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL1_READ_ADDR // Description : Alias for channel 11 READ_ADDR register -#define DMA_CH11_AL1_READ_ADDR_OFFSET 0x000002d4 -#define DMA_CH11_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH11_AL1_READ_ADDR_OFFSET _u(0x000002d4) +#define DMA_CH11_AL1_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH11_AL1_READ_ADDR_RESET "-" -#define DMA_CH11_AL1_READ_ADDR_MSB 31 -#define DMA_CH11_AL1_READ_ADDR_LSB 0 -#define DMA_CH11_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH11_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH11_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH11_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL1_WRITE_ADDR // Description : Alias for channel 11 WRITE_ADDR register -#define DMA_CH11_AL1_WRITE_ADDR_OFFSET 0x000002d8 -#define DMA_CH11_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH11_AL1_WRITE_ADDR_OFFSET _u(0x000002d8) +#define DMA_CH11_AL1_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH11_AL1_WRITE_ADDR_RESET "-" -#define DMA_CH11_AL1_WRITE_ADDR_MSB 31 -#define DMA_CH11_AL1_WRITE_ADDR_LSB 0 -#define DMA_CH11_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH11_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH11_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH11_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 11 TRANS_COUNT register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_OFFSET 0x000002dc -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000002dc) +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) #define DMA_CH11_AL1_TRANS_COUNT_TRIG_RESET "-" -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_MSB 31 -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_LSB 0 -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL2_CTRL // Description : Alias for channel 11 CTRL register -#define DMA_CH11_AL2_CTRL_OFFSET 0x000002e0 -#define DMA_CH11_AL2_CTRL_BITS 0xffffffff +#define DMA_CH11_AL2_CTRL_OFFSET _u(0x000002e0) +#define DMA_CH11_AL2_CTRL_BITS _u(0xffffffff) #define DMA_CH11_AL2_CTRL_RESET "-" -#define DMA_CH11_AL2_CTRL_MSB 31 -#define DMA_CH11_AL2_CTRL_LSB 0 -#define DMA_CH11_AL2_CTRL_ACCESS "RO" +#define DMA_CH11_AL2_CTRL_MSB _u(31) +#define DMA_CH11_AL2_CTRL_LSB _u(0) +#define DMA_CH11_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL2_TRANS_COUNT // Description : Alias for channel 11 TRANS_COUNT register -#define DMA_CH11_AL2_TRANS_COUNT_OFFSET 0x000002e4 -#define DMA_CH11_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH11_AL2_TRANS_COUNT_OFFSET _u(0x000002e4) +#define DMA_CH11_AL2_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH11_AL2_TRANS_COUNT_RESET "-" -#define DMA_CH11_AL2_TRANS_COUNT_MSB 31 -#define DMA_CH11_AL2_TRANS_COUNT_LSB 0 -#define DMA_CH11_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH11_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH11_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH11_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL2_READ_ADDR // Description : Alias for channel 11 READ_ADDR register -#define DMA_CH11_AL2_READ_ADDR_OFFSET 0x000002e8 -#define DMA_CH11_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH11_AL2_READ_ADDR_OFFSET _u(0x000002e8) +#define DMA_CH11_AL2_READ_ADDR_BITS _u(0xffffffff) #define DMA_CH11_AL2_READ_ADDR_RESET "-" -#define DMA_CH11_AL2_READ_ADDR_MSB 31 -#define DMA_CH11_AL2_READ_ADDR_LSB 0 -#define DMA_CH11_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH11_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH11_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH11_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 11 WRITE_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_OFFSET 0x000002ec -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ec) +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH11_AL2_WRITE_ADDR_TRIG_RESET "-" -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_MSB 31 -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_LSB 0 -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL3_CTRL // Description : Alias for channel 11 CTRL register -#define DMA_CH11_AL3_CTRL_OFFSET 0x000002f0 -#define DMA_CH11_AL3_CTRL_BITS 0xffffffff +#define DMA_CH11_AL3_CTRL_OFFSET _u(0x000002f0) +#define DMA_CH11_AL3_CTRL_BITS _u(0xffffffff) #define DMA_CH11_AL3_CTRL_RESET "-" -#define DMA_CH11_AL3_CTRL_MSB 31 -#define DMA_CH11_AL3_CTRL_LSB 0 -#define DMA_CH11_AL3_CTRL_ACCESS "RO" +#define DMA_CH11_AL3_CTRL_MSB _u(31) +#define DMA_CH11_AL3_CTRL_LSB _u(0) +#define DMA_CH11_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL3_WRITE_ADDR // Description : Alias for channel 11 WRITE_ADDR register -#define DMA_CH11_AL3_WRITE_ADDR_OFFSET 0x000002f4 -#define DMA_CH11_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH11_AL3_WRITE_ADDR_OFFSET _u(0x000002f4) +#define DMA_CH11_AL3_WRITE_ADDR_BITS _u(0xffffffff) #define DMA_CH11_AL3_WRITE_ADDR_RESET "-" -#define DMA_CH11_AL3_WRITE_ADDR_MSB 31 -#define DMA_CH11_AL3_WRITE_ADDR_LSB 0 -#define DMA_CH11_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH11_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH11_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH11_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL3_TRANS_COUNT // Description : Alias for channel 11 TRANS_COUNT register -#define DMA_CH11_AL3_TRANS_COUNT_OFFSET 0x000002f8 -#define DMA_CH11_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH11_AL3_TRANS_COUNT_OFFSET _u(0x000002f8) +#define DMA_CH11_AL3_TRANS_COUNT_BITS _u(0xffffffff) #define DMA_CH11_AL3_TRANS_COUNT_RESET "-" -#define DMA_CH11_AL3_TRANS_COUNT_MSB 31 -#define DMA_CH11_AL3_TRANS_COUNT_LSB 0 -#define DMA_CH11_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH11_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH11_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH11_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL3_READ_ADDR_TRIG // Description : Alias for channel 11 READ_ADDR register // This is a trigger register (0xc). Writing a nonzero value will // reload the channel counter and start the channel. -#define DMA_CH11_AL3_READ_ADDR_TRIG_OFFSET 0x000002fc -#define DMA_CH11_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH11_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002fc) +#define DMA_CH11_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) #define DMA_CH11_AL3_READ_ADDR_TRIG_RESET "-" -#define DMA_CH11_AL3_READ_ADDR_TRIG_MSB 31 -#define DMA_CH11_AL3_READ_ADDR_TRIG_LSB 0 -#define DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH11_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH11_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_INTR // Description : Interrupt Status (raw) @@ -4697,32 +4697,32 @@ // // It is also valid to ignore this behaviour and just use // INTE0/INTS0/IRQ 0. -#define DMA_INTR_OFFSET 0x00000400 -#define DMA_INTR_BITS 0x0000ffff -#define DMA_INTR_RESET 0x00000000 -#define DMA_INTR_MSB 15 -#define DMA_INTR_LSB 0 +#define DMA_INTR_OFFSET _u(0x00000400) +#define DMA_INTR_BITS _u(0x0000ffff) +#define DMA_INTR_RESET _u(0x00000000) +#define DMA_INTR_MSB _u(15) +#define DMA_INTR_LSB _u(0) #define DMA_INTR_ACCESS "RO" // ============================================================================= // Register : DMA_INTE0 // Description : Interrupt Enables for IRQ 0 // Set bit n to pass interrupts from channel n to DMA IRQ 0. -#define DMA_INTE0_OFFSET 0x00000404 -#define DMA_INTE0_BITS 0x0000ffff -#define DMA_INTE0_RESET 0x00000000 -#define DMA_INTE0_MSB 15 -#define DMA_INTE0_LSB 0 +#define DMA_INTE0_OFFSET _u(0x00000404) +#define DMA_INTE0_BITS _u(0x0000ffff) +#define DMA_INTE0_RESET _u(0x00000000) +#define DMA_INTE0_MSB _u(15) +#define DMA_INTE0_LSB _u(0) #define DMA_INTE0_ACCESS "RW" // ============================================================================= // Register : DMA_INTF0 // Description : Force Interrupts // Write 1s to force the corresponding bits in INTE0. The // interrupt remains asserted until INTF0 is cleared. -#define DMA_INTF0_OFFSET 0x00000408 -#define DMA_INTF0_BITS 0x0000ffff -#define DMA_INTF0_RESET 0x00000000 -#define DMA_INTF0_MSB 15 -#define DMA_INTF0_LSB 0 +#define DMA_INTF0_OFFSET _u(0x00000408) +#define DMA_INTF0_BITS _u(0x0000ffff) +#define DMA_INTF0_RESET _u(0x00000000) +#define DMA_INTF0_MSB _u(15) +#define DMA_INTF0_LSB _u(0) #define DMA_INTF0_ACCESS "RW" // ============================================================================= // Register : DMA_INTS0 @@ -4730,32 +4730,32 @@ // Indicates active channel interrupt requests which are currently // causing IRQ 0 to be asserted. // Channel interrupts can be cleared by writing a bit mask here. -#define DMA_INTS0_OFFSET 0x0000040c -#define DMA_INTS0_BITS 0x0000ffff -#define DMA_INTS0_RESET 0x00000000 -#define DMA_INTS0_MSB 15 -#define DMA_INTS0_LSB 0 +#define DMA_INTS0_OFFSET _u(0x0000040c) +#define DMA_INTS0_BITS _u(0x0000ffff) +#define DMA_INTS0_RESET _u(0x00000000) +#define DMA_INTS0_MSB _u(15) +#define DMA_INTS0_LSB _u(0) #define DMA_INTS0_ACCESS "WC" // ============================================================================= // Register : DMA_INTE1 // Description : Interrupt Enables for IRQ 1 // Set bit n to pass interrupts from channel n to DMA IRQ 1. -#define DMA_INTE1_OFFSET 0x00000414 -#define DMA_INTE1_BITS 0x0000ffff -#define DMA_INTE1_RESET 0x00000000 -#define DMA_INTE1_MSB 15 -#define DMA_INTE1_LSB 0 +#define DMA_INTE1_OFFSET _u(0x00000414) +#define DMA_INTE1_BITS _u(0x0000ffff) +#define DMA_INTE1_RESET _u(0x00000000) +#define DMA_INTE1_MSB _u(15) +#define DMA_INTE1_LSB _u(0) #define DMA_INTE1_ACCESS "RW" // ============================================================================= // Register : DMA_INTF1 // Description : Force Interrupts for IRQ 1 // Write 1s to force the corresponding bits in INTE0. The // interrupt remains asserted until INTF0 is cleared. -#define DMA_INTF1_OFFSET 0x00000418 -#define DMA_INTF1_BITS 0x0000ffff -#define DMA_INTF1_RESET 0x00000000 -#define DMA_INTF1_MSB 15 -#define DMA_INTF1_LSB 0 +#define DMA_INTF1_OFFSET _u(0x00000418) +#define DMA_INTF1_BITS _u(0x0000ffff) +#define DMA_INTF1_RESET _u(0x00000000) +#define DMA_INTF1_MSB _u(15) +#define DMA_INTF1_LSB _u(0) #define DMA_INTF1_ACCESS "RW" // ============================================================================= // Register : DMA_INTS1 @@ -4763,11 +4763,11 @@ // Indicates active channel interrupt requests which are currently // causing IRQ 1 to be asserted. // Channel interrupts can be cleared by writing a bit mask here. -#define DMA_INTS1_OFFSET 0x0000041c -#define DMA_INTS1_BITS 0x0000ffff -#define DMA_INTS1_RESET 0x00000000 -#define DMA_INTS1_MSB 15 -#define DMA_INTS1_LSB 0 +#define DMA_INTS1_OFFSET _u(0x0000041c) +#define DMA_INTS1_BITS _u(0x0000ffff) +#define DMA_INTS1_RESET _u(0x00000000) +#define DMA_INTS1_MSB _u(15) +#define DMA_INTS1_LSB _u(0) #define DMA_INTS1_ACCESS "WC" // ============================================================================= // Register : DMA_TIMER0 @@ -4776,26 +4776,26 @@ // ((X/Y) * sys_clk). This equation is evaluated every sys_clk // cycles and therefore can only generate TREQs at a rate of 1 per // sys_clk (i.e. permanent TREQ) or less. -#define DMA_TIMER0_OFFSET 0x00000420 -#define DMA_TIMER0_BITS 0xffffffff -#define DMA_TIMER0_RESET 0x00000000 +#define DMA_TIMER0_OFFSET _u(0x00000420) +#define DMA_TIMER0_BITS _u(0xffffffff) +#define DMA_TIMER0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_TIMER0_X // Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) // fractional timer. -#define DMA_TIMER0_X_RESET 0x0000 -#define DMA_TIMER0_X_BITS 0xffff0000 -#define DMA_TIMER0_X_MSB 31 -#define DMA_TIMER0_X_LSB 16 +#define DMA_TIMER0_X_RESET _u(0x0000) +#define DMA_TIMER0_X_BITS _u(0xffff0000) +#define DMA_TIMER0_X_MSB _u(31) +#define DMA_TIMER0_X_LSB _u(16) #define DMA_TIMER0_X_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_TIMER0_Y // Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) // fractional timer. -#define DMA_TIMER0_Y_RESET 0x0000 -#define DMA_TIMER0_Y_BITS 0x0000ffff -#define DMA_TIMER0_Y_MSB 15 -#define DMA_TIMER0_Y_LSB 0 +#define DMA_TIMER0_Y_RESET _u(0x0000) +#define DMA_TIMER0_Y_BITS _u(0x0000ffff) +#define DMA_TIMER0_Y_MSB _u(15) +#define DMA_TIMER0_Y_LSB _u(0) #define DMA_TIMER0_Y_ACCESS "RW" // ============================================================================= // Register : DMA_TIMER1 @@ -4804,26 +4804,26 @@ // ((X/Y) * sys_clk). This equation is evaluated every sys_clk // cycles and therefore can only generate TREQs at a rate of 1 per // sys_clk (i.e. permanent TREQ) or less. -#define DMA_TIMER1_OFFSET 0x00000424 -#define DMA_TIMER1_BITS 0xffffffff -#define DMA_TIMER1_RESET 0x00000000 +#define DMA_TIMER1_OFFSET _u(0x00000424) +#define DMA_TIMER1_BITS _u(0xffffffff) +#define DMA_TIMER1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_TIMER1_X // Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) // fractional timer. -#define DMA_TIMER1_X_RESET 0x0000 -#define DMA_TIMER1_X_BITS 0xffff0000 -#define DMA_TIMER1_X_MSB 31 -#define DMA_TIMER1_X_LSB 16 +#define DMA_TIMER1_X_RESET _u(0x0000) +#define DMA_TIMER1_X_BITS _u(0xffff0000) +#define DMA_TIMER1_X_MSB _u(31) +#define DMA_TIMER1_X_LSB _u(16) #define DMA_TIMER1_X_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_TIMER1_Y // Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) // fractional timer. -#define DMA_TIMER1_Y_RESET 0x0000 -#define DMA_TIMER1_Y_BITS 0x0000ffff -#define DMA_TIMER1_Y_MSB 15 -#define DMA_TIMER1_Y_LSB 0 +#define DMA_TIMER1_Y_RESET _u(0x0000) +#define DMA_TIMER1_Y_BITS _u(0x0000ffff) +#define DMA_TIMER1_Y_MSB _u(15) +#define DMA_TIMER1_Y_LSB _u(0) #define DMA_TIMER1_Y_ACCESS "RW" // ============================================================================= // Register : DMA_TIMER2 @@ -4832,26 +4832,26 @@ // ((X/Y) * sys_clk). This equation is evaluated every sys_clk // cycles and therefore can only generate TREQs at a rate of 1 per // sys_clk (i.e. permanent TREQ) or less. -#define DMA_TIMER2_OFFSET 0x00000428 -#define DMA_TIMER2_BITS 0xffffffff -#define DMA_TIMER2_RESET 0x00000000 +#define DMA_TIMER2_OFFSET _u(0x00000428) +#define DMA_TIMER2_BITS _u(0xffffffff) +#define DMA_TIMER2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_TIMER2_X // Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) // fractional timer. -#define DMA_TIMER2_X_RESET 0x0000 -#define DMA_TIMER2_X_BITS 0xffff0000 -#define DMA_TIMER2_X_MSB 31 -#define DMA_TIMER2_X_LSB 16 +#define DMA_TIMER2_X_RESET _u(0x0000) +#define DMA_TIMER2_X_BITS _u(0xffff0000) +#define DMA_TIMER2_X_MSB _u(31) +#define DMA_TIMER2_X_LSB _u(16) #define DMA_TIMER2_X_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_TIMER2_Y // Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) // fractional timer. -#define DMA_TIMER2_Y_RESET 0x0000 -#define DMA_TIMER2_Y_BITS 0x0000ffff -#define DMA_TIMER2_Y_MSB 15 -#define DMA_TIMER2_Y_LSB 0 +#define DMA_TIMER2_Y_RESET _u(0x0000) +#define DMA_TIMER2_Y_BITS _u(0x0000ffff) +#define DMA_TIMER2_Y_MSB _u(15) +#define DMA_TIMER2_Y_LSB _u(0) #define DMA_TIMER2_Y_ACCESS "RW" // ============================================================================= // Register : DMA_TIMER3 @@ -4860,26 +4860,26 @@ // ((X/Y) * sys_clk). This equation is evaluated every sys_clk // cycles and therefore can only generate TREQs at a rate of 1 per // sys_clk (i.e. permanent TREQ) or less. -#define DMA_TIMER3_OFFSET 0x0000042c -#define DMA_TIMER3_BITS 0xffffffff -#define DMA_TIMER3_RESET 0x00000000 +#define DMA_TIMER3_OFFSET _u(0x0000042c) +#define DMA_TIMER3_BITS _u(0xffffffff) +#define DMA_TIMER3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_TIMER3_X // Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) // fractional timer. -#define DMA_TIMER3_X_RESET 0x0000 -#define DMA_TIMER3_X_BITS 0xffff0000 -#define DMA_TIMER3_X_MSB 31 -#define DMA_TIMER3_X_LSB 16 +#define DMA_TIMER3_X_RESET _u(0x0000) +#define DMA_TIMER3_X_BITS _u(0xffff0000) +#define DMA_TIMER3_X_MSB _u(31) +#define DMA_TIMER3_X_LSB _u(16) #define DMA_TIMER3_X_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_TIMER3_Y // Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) // fractional timer. -#define DMA_TIMER3_Y_RESET 0x0000 -#define DMA_TIMER3_Y_BITS 0x0000ffff -#define DMA_TIMER3_Y_MSB 15 -#define DMA_TIMER3_Y_LSB 0 +#define DMA_TIMER3_Y_RESET _u(0x0000) +#define DMA_TIMER3_Y_BITS _u(0x0000ffff) +#define DMA_TIMER3_Y_MSB _u(15) +#define DMA_TIMER3_Y_LSB _u(0) #define DMA_TIMER3_Y_ACCESS "RW" // ============================================================================= // Register : DMA_MULTI_CHAN_TRIGGER @@ -4888,38 +4888,38 @@ // a 1 to the relevant bit is the same as writing to that // channel's trigger register; the channel will start if it is // currently enabled and not already busy. -#define DMA_MULTI_CHAN_TRIGGER_OFFSET 0x00000430 -#define DMA_MULTI_CHAN_TRIGGER_BITS 0x0000ffff -#define DMA_MULTI_CHAN_TRIGGER_RESET 0x00000000 -#define DMA_MULTI_CHAN_TRIGGER_MSB 15 -#define DMA_MULTI_CHAN_TRIGGER_LSB 0 +#define DMA_MULTI_CHAN_TRIGGER_OFFSET _u(0x00000430) +#define DMA_MULTI_CHAN_TRIGGER_BITS _u(0x0000ffff) +#define DMA_MULTI_CHAN_TRIGGER_RESET _u(0x00000000) +#define DMA_MULTI_CHAN_TRIGGER_MSB _u(15) +#define DMA_MULTI_CHAN_TRIGGER_LSB _u(0) #define DMA_MULTI_CHAN_TRIGGER_ACCESS "SC" // ============================================================================= // Register : DMA_SNIFF_CTRL // Description : Sniffer Control -#define DMA_SNIFF_CTRL_OFFSET 0x00000434 -#define DMA_SNIFF_CTRL_BITS 0x00000fff -#define DMA_SNIFF_CTRL_RESET 0x00000000 +#define DMA_SNIFF_CTRL_OFFSET _u(0x00000434) +#define DMA_SNIFF_CTRL_BITS _u(0x00000fff) +#define DMA_SNIFF_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_SNIFF_CTRL_OUT_INV // Description : If set, the result appears inverted (bitwise complement) when // read. This does not affect the way the checksum is calculated; // the result is transformed on-the-fly between the result // register and the bus. -#define DMA_SNIFF_CTRL_OUT_INV_RESET 0x0 -#define DMA_SNIFF_CTRL_OUT_INV_BITS 0x00000800 -#define DMA_SNIFF_CTRL_OUT_INV_MSB 11 -#define DMA_SNIFF_CTRL_OUT_INV_LSB 11 +#define DMA_SNIFF_CTRL_OUT_INV_RESET _u(0x0) +#define DMA_SNIFF_CTRL_OUT_INV_BITS _u(0x00000800) +#define DMA_SNIFF_CTRL_OUT_INV_MSB _u(11) +#define DMA_SNIFF_CTRL_OUT_INV_LSB _u(11) #define DMA_SNIFF_CTRL_OUT_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_SNIFF_CTRL_OUT_REV // Description : If set, the result appears bit-reversed when read. This does // not affect the way the checksum is calculated; the result is // transformed on-the-fly between the result register and the bus. -#define DMA_SNIFF_CTRL_OUT_REV_RESET 0x0 -#define DMA_SNIFF_CTRL_OUT_REV_BITS 0x00000400 -#define DMA_SNIFF_CTRL_OUT_REV_MSB 10 -#define DMA_SNIFF_CTRL_OUT_REV_LSB 10 +#define DMA_SNIFF_CTRL_OUT_REV_RESET _u(0x0) +#define DMA_SNIFF_CTRL_OUT_REV_BITS _u(0x00000400) +#define DMA_SNIFF_CTRL_OUT_REV_MSB _u(10) +#define DMA_SNIFF_CTRL_OUT_REV_LSB _u(10) #define DMA_SNIFF_CTRL_OUT_REV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_SNIFF_CTRL_BSWAP @@ -4930,10 +4930,10 @@ // byteswap performed in the read master: if channel CTRL_BSWAP // and SNIFF_CTRL_BSWAP are both enabled, their effects cancel // from the sniffer's point of view. -#define DMA_SNIFF_CTRL_BSWAP_RESET 0x0 -#define DMA_SNIFF_CTRL_BSWAP_BITS 0x00000200 -#define DMA_SNIFF_CTRL_BSWAP_MSB 9 -#define DMA_SNIFF_CTRL_BSWAP_LSB 9 +#define DMA_SNIFF_CTRL_BSWAP_RESET _u(0x0) +#define DMA_SNIFF_CTRL_BSWAP_BITS _u(0x00000200) +#define DMA_SNIFF_CTRL_BSWAP_MSB _u(9) +#define DMA_SNIFF_CTRL_BSWAP_LSB _u(9) #define DMA_SNIFF_CTRL_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_SNIFF_CTRL_CALC @@ -4946,32 +4946,32 @@ // population count is odd. // 0xf -> Calculate a simple 32-bit checksum (addition with a 32 // bit accumulator) -#define DMA_SNIFF_CTRL_CALC_RESET 0x0 -#define DMA_SNIFF_CTRL_CALC_BITS 0x000001e0 -#define DMA_SNIFF_CTRL_CALC_MSB 8 -#define DMA_SNIFF_CTRL_CALC_LSB 5 +#define DMA_SNIFF_CTRL_CALC_RESET _u(0x0) +#define DMA_SNIFF_CTRL_CALC_BITS _u(0x000001e0) +#define DMA_SNIFF_CTRL_CALC_MSB _u(8) +#define DMA_SNIFF_CTRL_CALC_LSB _u(5) #define DMA_SNIFF_CTRL_CALC_ACCESS "RW" -#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32 0x0 -#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32R 0x1 -#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16 0x2 -#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16R 0x3 -#define DMA_SNIFF_CTRL_CALC_VALUE_EVEN 0xe -#define DMA_SNIFF_CTRL_CALC_VALUE_SUM 0xf +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32 _u(0x0) +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32R _u(0x1) +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16 _u(0x2) +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16R _u(0x3) +#define DMA_SNIFF_CTRL_CALC_VALUE_EVEN _u(0xe) +#define DMA_SNIFF_CTRL_CALC_VALUE_SUM _u(0xf) // ----------------------------------------------------------------------------- // Field : DMA_SNIFF_CTRL_DMACH // Description : DMA channel for Sniffer to observe -#define DMA_SNIFF_CTRL_DMACH_RESET 0x0 -#define DMA_SNIFF_CTRL_DMACH_BITS 0x0000001e -#define DMA_SNIFF_CTRL_DMACH_MSB 4 -#define DMA_SNIFF_CTRL_DMACH_LSB 1 +#define DMA_SNIFF_CTRL_DMACH_RESET _u(0x0) +#define DMA_SNIFF_CTRL_DMACH_BITS _u(0x0000001e) +#define DMA_SNIFF_CTRL_DMACH_MSB _u(4) +#define DMA_SNIFF_CTRL_DMACH_LSB _u(1) #define DMA_SNIFF_CTRL_DMACH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_SNIFF_CTRL_EN // Description : Enable sniffer -#define DMA_SNIFF_CTRL_EN_RESET 0x0 -#define DMA_SNIFF_CTRL_EN_BITS 0x00000001 -#define DMA_SNIFF_CTRL_EN_MSB 0 -#define DMA_SNIFF_CTRL_EN_LSB 0 +#define DMA_SNIFF_CTRL_EN_RESET _u(0x0) +#define DMA_SNIFF_CTRL_EN_BITS _u(0x00000001) +#define DMA_SNIFF_CTRL_EN_MSB _u(0) +#define DMA_SNIFF_CTRL_EN_LSB _u(0) #define DMA_SNIFF_CTRL_EN_ACCESS "RW" // ============================================================================= // Register : DMA_SNIFF_DATA @@ -4981,41 +4981,41 @@ // update this register each time it observes a read from the // indicated channel. Once the channel completes, the final result // can be read from this register. -#define DMA_SNIFF_DATA_OFFSET 0x00000438 -#define DMA_SNIFF_DATA_BITS 0xffffffff -#define DMA_SNIFF_DATA_RESET 0x00000000 -#define DMA_SNIFF_DATA_MSB 31 -#define DMA_SNIFF_DATA_LSB 0 +#define DMA_SNIFF_DATA_OFFSET _u(0x00000438) +#define DMA_SNIFF_DATA_BITS _u(0xffffffff) +#define DMA_SNIFF_DATA_RESET _u(0x00000000) +#define DMA_SNIFF_DATA_MSB _u(31) +#define DMA_SNIFF_DATA_LSB _u(0) #define DMA_SNIFF_DATA_ACCESS "RW" // ============================================================================= // Register : DMA_FIFO_LEVELS // Description : Debug RAF, WAF, TDF levels -#define DMA_FIFO_LEVELS_OFFSET 0x00000440 -#define DMA_FIFO_LEVELS_BITS 0x00ffffff -#define DMA_FIFO_LEVELS_RESET 0x00000000 +#define DMA_FIFO_LEVELS_OFFSET _u(0x00000440) +#define DMA_FIFO_LEVELS_BITS _u(0x00ffffff) +#define DMA_FIFO_LEVELS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_FIFO_LEVELS_RAF_LVL // Description : Current Read-Address-FIFO fill level -#define DMA_FIFO_LEVELS_RAF_LVL_RESET 0x00 -#define DMA_FIFO_LEVELS_RAF_LVL_BITS 0x00ff0000 -#define DMA_FIFO_LEVELS_RAF_LVL_MSB 23 -#define DMA_FIFO_LEVELS_RAF_LVL_LSB 16 +#define DMA_FIFO_LEVELS_RAF_LVL_RESET _u(0x00) +#define DMA_FIFO_LEVELS_RAF_LVL_BITS _u(0x00ff0000) +#define DMA_FIFO_LEVELS_RAF_LVL_MSB _u(23) +#define DMA_FIFO_LEVELS_RAF_LVL_LSB _u(16) #define DMA_FIFO_LEVELS_RAF_LVL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_FIFO_LEVELS_WAF_LVL // Description : Current Write-Address-FIFO fill level -#define DMA_FIFO_LEVELS_WAF_LVL_RESET 0x00 -#define DMA_FIFO_LEVELS_WAF_LVL_BITS 0x0000ff00 -#define DMA_FIFO_LEVELS_WAF_LVL_MSB 15 -#define DMA_FIFO_LEVELS_WAF_LVL_LSB 8 +#define DMA_FIFO_LEVELS_WAF_LVL_RESET _u(0x00) +#define DMA_FIFO_LEVELS_WAF_LVL_BITS _u(0x0000ff00) +#define DMA_FIFO_LEVELS_WAF_LVL_MSB _u(15) +#define DMA_FIFO_LEVELS_WAF_LVL_LSB _u(8) #define DMA_FIFO_LEVELS_WAF_LVL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : DMA_FIFO_LEVELS_TDF_LVL // Description : Current Transfer-Data-FIFO fill level -#define DMA_FIFO_LEVELS_TDF_LVL_RESET 0x00 -#define DMA_FIFO_LEVELS_TDF_LVL_BITS 0x000000ff -#define DMA_FIFO_LEVELS_TDF_LVL_MSB 7 -#define DMA_FIFO_LEVELS_TDF_LVL_LSB 0 +#define DMA_FIFO_LEVELS_TDF_LVL_RESET _u(0x00) +#define DMA_FIFO_LEVELS_TDF_LVL_BITS _u(0x000000ff) +#define DMA_FIFO_LEVELS_TDF_LVL_MSB _u(7) +#define DMA_FIFO_LEVELS_TDF_LVL_LSB _u(0) #define DMA_FIFO_LEVELS_TDF_LVL_ACCESS "RO" // ============================================================================= // Register : DMA_CHAN_ABORT @@ -5028,22 +5028,22 @@ // After writing, this register must be polled until it returns // all-zero. Until this point, it is unsafe to restart the // channel. -#define DMA_CHAN_ABORT_OFFSET 0x00000444 -#define DMA_CHAN_ABORT_BITS 0x0000ffff -#define DMA_CHAN_ABORT_RESET 0x00000000 -#define DMA_CHAN_ABORT_MSB 15 -#define DMA_CHAN_ABORT_LSB 0 +#define DMA_CHAN_ABORT_OFFSET _u(0x00000444) +#define DMA_CHAN_ABORT_BITS _u(0x0000ffff) +#define DMA_CHAN_ABORT_RESET _u(0x00000000) +#define DMA_CHAN_ABORT_MSB _u(15) +#define DMA_CHAN_ABORT_LSB _u(0) #define DMA_CHAN_ABORT_ACCESS "SC" // ============================================================================= // Register : DMA_N_CHANNELS // Description : The number of channels this DMA instance is equipped with. This // DMA supports up to 16 hardware channels, but can be configured // with as few as one, to minimise silicon area. -#define DMA_N_CHANNELS_OFFSET 0x00000448 -#define DMA_N_CHANNELS_BITS 0x0000001f +#define DMA_N_CHANNELS_OFFSET _u(0x00000448) +#define DMA_N_CHANNELS_BITS _u(0x0000001f) #define DMA_N_CHANNELS_RESET "-" -#define DMA_N_CHANNELS_MSB 4 -#define DMA_N_CHANNELS_LSB 0 +#define DMA_N_CHANNELS_MSB _u(4) +#define DMA_N_CHANNELS_LSB _u(0) #define DMA_N_CHANNELS_ACCESS "RO" // ============================================================================= // Register : DMA_CH0_DBG_CTDREQ @@ -5051,21 +5051,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH0_DBG_CTDREQ_OFFSET 0x00000800 -#define DMA_CH0_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH0_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH0_DBG_CTDREQ_MSB 5 -#define DMA_CH0_DBG_CTDREQ_LSB 0 -#define DMA_CH0_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH0_DBG_CTDREQ_OFFSET _u(0x00000800) +#define DMA_CH0_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH0_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH0_DBG_CTDREQ_MSB _u(5) +#define DMA_CH0_DBG_CTDREQ_LSB _u(0) +#define DMA_CH0_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH0_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH0_DBG_TCR_OFFSET 0x00000804 -#define DMA_CH0_DBG_TCR_BITS 0xffffffff -#define DMA_CH0_DBG_TCR_RESET 0x00000000 -#define DMA_CH0_DBG_TCR_MSB 31 -#define DMA_CH0_DBG_TCR_LSB 0 +#define DMA_CH0_DBG_TCR_OFFSET _u(0x00000804) +#define DMA_CH0_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH0_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH0_DBG_TCR_MSB _u(31) +#define DMA_CH0_DBG_TCR_LSB _u(0) #define DMA_CH0_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH1_DBG_CTDREQ @@ -5073,21 +5073,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH1_DBG_CTDREQ_OFFSET 0x00000840 -#define DMA_CH1_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH1_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH1_DBG_CTDREQ_MSB 5 -#define DMA_CH1_DBG_CTDREQ_LSB 0 -#define DMA_CH1_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH1_DBG_CTDREQ_OFFSET _u(0x00000840) +#define DMA_CH1_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH1_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH1_DBG_CTDREQ_MSB _u(5) +#define DMA_CH1_DBG_CTDREQ_LSB _u(0) +#define DMA_CH1_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH1_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH1_DBG_TCR_OFFSET 0x00000844 -#define DMA_CH1_DBG_TCR_BITS 0xffffffff -#define DMA_CH1_DBG_TCR_RESET 0x00000000 -#define DMA_CH1_DBG_TCR_MSB 31 -#define DMA_CH1_DBG_TCR_LSB 0 +#define DMA_CH1_DBG_TCR_OFFSET _u(0x00000844) +#define DMA_CH1_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH1_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH1_DBG_TCR_MSB _u(31) +#define DMA_CH1_DBG_TCR_LSB _u(0) #define DMA_CH1_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH2_DBG_CTDREQ @@ -5095,21 +5095,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH2_DBG_CTDREQ_OFFSET 0x00000880 -#define DMA_CH2_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH2_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH2_DBG_CTDREQ_MSB 5 -#define DMA_CH2_DBG_CTDREQ_LSB 0 -#define DMA_CH2_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH2_DBG_CTDREQ_OFFSET _u(0x00000880) +#define DMA_CH2_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH2_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH2_DBG_CTDREQ_MSB _u(5) +#define DMA_CH2_DBG_CTDREQ_LSB _u(0) +#define DMA_CH2_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH2_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH2_DBG_TCR_OFFSET 0x00000884 -#define DMA_CH2_DBG_TCR_BITS 0xffffffff -#define DMA_CH2_DBG_TCR_RESET 0x00000000 -#define DMA_CH2_DBG_TCR_MSB 31 -#define DMA_CH2_DBG_TCR_LSB 0 +#define DMA_CH2_DBG_TCR_OFFSET _u(0x00000884) +#define DMA_CH2_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH2_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH2_DBG_TCR_MSB _u(31) +#define DMA_CH2_DBG_TCR_LSB _u(0) #define DMA_CH2_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH3_DBG_CTDREQ @@ -5117,21 +5117,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH3_DBG_CTDREQ_OFFSET 0x000008c0 -#define DMA_CH3_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH3_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH3_DBG_CTDREQ_MSB 5 -#define DMA_CH3_DBG_CTDREQ_LSB 0 -#define DMA_CH3_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH3_DBG_CTDREQ_OFFSET _u(0x000008c0) +#define DMA_CH3_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH3_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH3_DBG_CTDREQ_MSB _u(5) +#define DMA_CH3_DBG_CTDREQ_LSB _u(0) +#define DMA_CH3_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH3_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH3_DBG_TCR_OFFSET 0x000008c4 -#define DMA_CH3_DBG_TCR_BITS 0xffffffff -#define DMA_CH3_DBG_TCR_RESET 0x00000000 -#define DMA_CH3_DBG_TCR_MSB 31 -#define DMA_CH3_DBG_TCR_LSB 0 +#define DMA_CH3_DBG_TCR_OFFSET _u(0x000008c4) +#define DMA_CH3_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH3_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH3_DBG_TCR_MSB _u(31) +#define DMA_CH3_DBG_TCR_LSB _u(0) #define DMA_CH3_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH4_DBG_CTDREQ @@ -5139,21 +5139,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH4_DBG_CTDREQ_OFFSET 0x00000900 -#define DMA_CH4_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH4_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH4_DBG_CTDREQ_MSB 5 -#define DMA_CH4_DBG_CTDREQ_LSB 0 -#define DMA_CH4_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH4_DBG_CTDREQ_OFFSET _u(0x00000900) +#define DMA_CH4_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH4_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH4_DBG_CTDREQ_MSB _u(5) +#define DMA_CH4_DBG_CTDREQ_LSB _u(0) +#define DMA_CH4_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH4_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH4_DBG_TCR_OFFSET 0x00000904 -#define DMA_CH4_DBG_TCR_BITS 0xffffffff -#define DMA_CH4_DBG_TCR_RESET 0x00000000 -#define DMA_CH4_DBG_TCR_MSB 31 -#define DMA_CH4_DBG_TCR_LSB 0 +#define DMA_CH4_DBG_TCR_OFFSET _u(0x00000904) +#define DMA_CH4_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH4_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH4_DBG_TCR_MSB _u(31) +#define DMA_CH4_DBG_TCR_LSB _u(0) #define DMA_CH4_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH5_DBG_CTDREQ @@ -5161,21 +5161,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH5_DBG_CTDREQ_OFFSET 0x00000940 -#define DMA_CH5_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH5_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH5_DBG_CTDREQ_MSB 5 -#define DMA_CH5_DBG_CTDREQ_LSB 0 -#define DMA_CH5_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH5_DBG_CTDREQ_OFFSET _u(0x00000940) +#define DMA_CH5_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH5_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH5_DBG_CTDREQ_MSB _u(5) +#define DMA_CH5_DBG_CTDREQ_LSB _u(0) +#define DMA_CH5_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH5_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH5_DBG_TCR_OFFSET 0x00000944 -#define DMA_CH5_DBG_TCR_BITS 0xffffffff -#define DMA_CH5_DBG_TCR_RESET 0x00000000 -#define DMA_CH5_DBG_TCR_MSB 31 -#define DMA_CH5_DBG_TCR_LSB 0 +#define DMA_CH5_DBG_TCR_OFFSET _u(0x00000944) +#define DMA_CH5_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH5_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH5_DBG_TCR_MSB _u(31) +#define DMA_CH5_DBG_TCR_LSB _u(0) #define DMA_CH5_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH6_DBG_CTDREQ @@ -5183,21 +5183,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH6_DBG_CTDREQ_OFFSET 0x00000980 -#define DMA_CH6_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH6_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH6_DBG_CTDREQ_MSB 5 -#define DMA_CH6_DBG_CTDREQ_LSB 0 -#define DMA_CH6_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH6_DBG_CTDREQ_OFFSET _u(0x00000980) +#define DMA_CH6_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH6_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH6_DBG_CTDREQ_MSB _u(5) +#define DMA_CH6_DBG_CTDREQ_LSB _u(0) +#define DMA_CH6_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH6_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH6_DBG_TCR_OFFSET 0x00000984 -#define DMA_CH6_DBG_TCR_BITS 0xffffffff -#define DMA_CH6_DBG_TCR_RESET 0x00000000 -#define DMA_CH6_DBG_TCR_MSB 31 -#define DMA_CH6_DBG_TCR_LSB 0 +#define DMA_CH6_DBG_TCR_OFFSET _u(0x00000984) +#define DMA_CH6_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH6_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH6_DBG_TCR_MSB _u(31) +#define DMA_CH6_DBG_TCR_LSB _u(0) #define DMA_CH6_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH7_DBG_CTDREQ @@ -5205,21 +5205,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH7_DBG_CTDREQ_OFFSET 0x000009c0 -#define DMA_CH7_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH7_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH7_DBG_CTDREQ_MSB 5 -#define DMA_CH7_DBG_CTDREQ_LSB 0 -#define DMA_CH7_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH7_DBG_CTDREQ_OFFSET _u(0x000009c0) +#define DMA_CH7_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH7_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH7_DBG_CTDREQ_MSB _u(5) +#define DMA_CH7_DBG_CTDREQ_LSB _u(0) +#define DMA_CH7_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH7_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH7_DBG_TCR_OFFSET 0x000009c4 -#define DMA_CH7_DBG_TCR_BITS 0xffffffff -#define DMA_CH7_DBG_TCR_RESET 0x00000000 -#define DMA_CH7_DBG_TCR_MSB 31 -#define DMA_CH7_DBG_TCR_LSB 0 +#define DMA_CH7_DBG_TCR_OFFSET _u(0x000009c4) +#define DMA_CH7_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH7_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH7_DBG_TCR_MSB _u(31) +#define DMA_CH7_DBG_TCR_LSB _u(0) #define DMA_CH7_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH8_DBG_CTDREQ @@ -5227,21 +5227,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH8_DBG_CTDREQ_OFFSET 0x00000a00 -#define DMA_CH8_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH8_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH8_DBG_CTDREQ_MSB 5 -#define DMA_CH8_DBG_CTDREQ_LSB 0 -#define DMA_CH8_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH8_DBG_CTDREQ_OFFSET _u(0x00000a00) +#define DMA_CH8_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH8_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH8_DBG_CTDREQ_MSB _u(5) +#define DMA_CH8_DBG_CTDREQ_LSB _u(0) +#define DMA_CH8_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH8_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH8_DBG_TCR_OFFSET 0x00000a04 -#define DMA_CH8_DBG_TCR_BITS 0xffffffff -#define DMA_CH8_DBG_TCR_RESET 0x00000000 -#define DMA_CH8_DBG_TCR_MSB 31 -#define DMA_CH8_DBG_TCR_LSB 0 +#define DMA_CH8_DBG_TCR_OFFSET _u(0x00000a04) +#define DMA_CH8_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH8_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH8_DBG_TCR_MSB _u(31) +#define DMA_CH8_DBG_TCR_LSB _u(0) #define DMA_CH8_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH9_DBG_CTDREQ @@ -5249,21 +5249,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH9_DBG_CTDREQ_OFFSET 0x00000a40 -#define DMA_CH9_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH9_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH9_DBG_CTDREQ_MSB 5 -#define DMA_CH9_DBG_CTDREQ_LSB 0 -#define DMA_CH9_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH9_DBG_CTDREQ_OFFSET _u(0x00000a40) +#define DMA_CH9_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH9_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH9_DBG_CTDREQ_MSB _u(5) +#define DMA_CH9_DBG_CTDREQ_LSB _u(0) +#define DMA_CH9_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH9_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH9_DBG_TCR_OFFSET 0x00000a44 -#define DMA_CH9_DBG_TCR_BITS 0xffffffff -#define DMA_CH9_DBG_TCR_RESET 0x00000000 -#define DMA_CH9_DBG_TCR_MSB 31 -#define DMA_CH9_DBG_TCR_LSB 0 +#define DMA_CH9_DBG_TCR_OFFSET _u(0x00000a44) +#define DMA_CH9_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH9_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH9_DBG_TCR_MSB _u(31) +#define DMA_CH9_DBG_TCR_LSB _u(0) #define DMA_CH9_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH10_DBG_CTDREQ @@ -5271,21 +5271,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH10_DBG_CTDREQ_OFFSET 0x00000a80 -#define DMA_CH10_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH10_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH10_DBG_CTDREQ_MSB 5 -#define DMA_CH10_DBG_CTDREQ_LSB 0 -#define DMA_CH10_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH10_DBG_CTDREQ_OFFSET _u(0x00000a80) +#define DMA_CH10_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH10_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH10_DBG_CTDREQ_MSB _u(5) +#define DMA_CH10_DBG_CTDREQ_LSB _u(0) +#define DMA_CH10_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH10_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH10_DBG_TCR_OFFSET 0x00000a84 -#define DMA_CH10_DBG_TCR_BITS 0xffffffff -#define DMA_CH10_DBG_TCR_RESET 0x00000000 -#define DMA_CH10_DBG_TCR_MSB 31 -#define DMA_CH10_DBG_TCR_LSB 0 +#define DMA_CH10_DBG_TCR_OFFSET _u(0x00000a84) +#define DMA_CH10_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH10_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH10_DBG_TCR_MSB _u(31) +#define DMA_CH10_DBG_TCR_LSB _u(0) #define DMA_CH10_DBG_TCR_ACCESS "RO" // ============================================================================= // Register : DMA_CH11_DBG_CTDREQ @@ -5293,21 +5293,21 @@ // expects it can perform on the peripheral without // overflow/underflow. Write any value: clears the counter, and // cause channel to re-initiate DREQ handshake. -#define DMA_CH11_DBG_CTDREQ_OFFSET 0x00000ac0 -#define DMA_CH11_DBG_CTDREQ_BITS 0x0000003f -#define DMA_CH11_DBG_CTDREQ_RESET 0x00000000 -#define DMA_CH11_DBG_CTDREQ_MSB 5 -#define DMA_CH11_DBG_CTDREQ_LSB 0 -#define DMA_CH11_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH11_DBG_CTDREQ_OFFSET _u(0x00000ac0) +#define DMA_CH11_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH11_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH11_DBG_CTDREQ_MSB _u(5) +#define DMA_CH11_DBG_CTDREQ_LSB _u(0) +#define DMA_CH11_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH11_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length // of the next transfer -#define DMA_CH11_DBG_TCR_OFFSET 0x00000ac4 -#define DMA_CH11_DBG_TCR_BITS 0xffffffff -#define DMA_CH11_DBG_TCR_RESET 0x00000000 -#define DMA_CH11_DBG_TCR_MSB 31 -#define DMA_CH11_DBG_TCR_LSB 0 +#define DMA_CH11_DBG_TCR_OFFSET _u(0x00000ac4) +#define DMA_CH11_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH11_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH11_DBG_TCR_MSB _u(31) +#define DMA_CH11_DBG_TCR_LSB _u(0) #define DMA_CH11_DBG_TCR_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_DMA_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/i2c.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/i2c.h index c027119a8..dcddb06a0 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/i2c.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/i2c.h @@ -8,6 +8,80 @@ // Version : 1 // Bus type : apb // Description : DW_apb_i2c address block +// +// List of configuration constants for the Synopsys I2C +// hardware (you may see references to these in I2C register +// header; these are *fixed* values, set at hardware design +// time): +// +// IC_ULTRA_FAST_MODE ................ 0x0 +// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 +// IC_UFM_SCL_LOW_COUNT .............. 0x0008 +// IC_UFM_SCL_HIGH_COUNT ............. 0x0006 +// IC_TX_TL .......................... 0x0 +// IC_TX_CMD_BLOCK ................... 0x1 +// IC_HAS_DMA ........................ 0x1 +// IC_HAS_ASYNC_FIFO ................. 0x0 +// IC_SMBUS_ARP ...................... 0x0 +// IC_FIRST_DATA_BYTE_STATUS ......... 0x1 +// IC_INTR_IO ........................ 0x1 +// IC_MASTER_MODE .................... 0x1 +// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 +// IC_INTR_POL ....................... 0x1 +// IC_OPTIONAL_SAR ................... 0x0 +// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 +// IC_DEFAULT_SLAVE_ADDR ............. 0x055 +// IC_DEFAULT_HS_SPKLEN .............. 0x1 +// IC_FS_SCL_HIGH_COUNT .............. 0x0006 +// IC_HS_SCL_LOW_COUNT ............... 0x0008 +// IC_DEVICE_ID_VALUE ................ 0x0 +// IC_10BITADDR_MASTER ............... 0x0 +// IC_CLK_FREQ_OPTIMIZATION .......... 0x0 +// IC_DEFAULT_FS_SPKLEN .............. 0x7 +// IC_ADD_ENCODED_PARAMS ............. 0x0 +// IC_DEFAULT_SDA_HOLD ............... 0x000001 +// IC_DEFAULT_SDA_SETUP .............. 0x64 +// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 +// IC_CLOCK_PERIOD ................... 100 +// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 +// IC_RESTART_EN ..................... 0x1 +// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 +// IC_BUS_CLEAR_FEATURE .............. 0x0 +// IC_CAP_LOADING .................... 100 +// IC_FS_SCL_LOW_COUNT ............... 0x000d +// APB_DATA_WIDTH .................... 32 +// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff +// IC_SLV_DATA_NACK_ONLY ............. 0x1 +// IC_10BITADDR_SLAVE ................ 0x0 +// IC_CLK_TYPE ....................... 0x0 +// IC_SMBUS_UDID_MSB ................. 0x0 +// IC_SMBUS_SUSPEND_ALERT ............ 0x0 +// IC_HS_SCL_HIGH_COUNT .............. 0x0006 +// IC_SLV_RESTART_DET_EN ............. 0x1 +// IC_SMBUS .......................... 0x0 +// IC_OPTIONAL_SAR_DEFAULT ........... 0x0 +// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 +// IC_USE_COUNTS ..................... 0x0 +// IC_RX_BUFFER_DEPTH ................ 16 +// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff +// IC_RX_FULL_HLD_BUS_EN ............. 0x1 +// IC_SLAVE_DISABLE .................. 0x1 +// IC_RX_TL .......................... 0x0 +// IC_DEVICE_ID ...................... 0x0 +// IC_HC_COUNT_VALUES ................ 0x0 +// I2C_DYNAMIC_TAR_UPDATE ............ 0 +// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff +// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff +// IC_HS_MASTER_CODE ................. 0x1 +// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff +// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff +// IC_SS_SCL_HIGH_COUNT .............. 0x0028 +// IC_SS_SCL_LOW_COUNT ............... 0x002f +// IC_MAX_SPEED_MODE ................. 0x2 +// IC_STAT_FOR_CLK_STRETCH ........... 0x0 +// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 +// IC_DEFAULT_UFM_SPKLEN ............. 0x1 +// IC_TX_BUFFER_DEPTH ................ 16 // ============================================================================= #ifndef HARDWARE_REGS_I2C_DEFINED #define HARDWARE_REGS_I2C_DEFINED @@ -21,17 +95,17 @@ // Read/Write Access: - bit 10 is read only. - bit 11 is read only // - bit 16 is read only - bit 17 is read only - bits 18 and 19 // are read only. -#define I2C_IC_CON_OFFSET 0x00000000 -#define I2C_IC_CON_BITS 0x000007ff -#define I2C_IC_CON_RESET 0x00000065 +#define I2C_IC_CON_OFFSET _u(0x00000000) +#define I2C_IC_CON_BITS _u(0x000007ff) +#define I2C_IC_CON_RESET _u(0x00000065) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE // Description : Master issues the STOP_DET interrupt irrespective of whether // master is active or not -#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_RESET 0x0 -#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_BITS 0x00000400 -#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_MSB 10 -#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_LSB 10 +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_RESET _u(0x0) +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_BITS _u(0x00000400) +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_MSB _u(10) +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_LSB _u(10) #define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL @@ -42,13 +116,13 @@ // Reset value: 0x0. // 0x0 -> Overflow when RX_FIFO is full // 0x1 -> Hold bus when RX_FIFO is full -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_RESET 0x0 -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS 0x00000200 -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_MSB 9 -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_LSB 9 +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_RESET _u(0x0) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS _u(0x00000200) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_MSB _u(9) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_LSB _u(9) #define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_ACCESS "RW" -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_DISABLED 0x0 -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_ENABLED 0x1 +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_DISABLED _u(0x0) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_TX_EMPTY_CTRL // Description : This bit controls the generation of the TX_EMPTY interrupt, as @@ -57,13 +131,13 @@ // Reset value: 0x0. // 0x0 -> Default behaviour of TX_EMPTY interrupt // 0x1 -> Controlled generation of TX_EMPTY interrupt -#define I2C_IC_CON_TX_EMPTY_CTRL_RESET 0x0 -#define I2C_IC_CON_TX_EMPTY_CTRL_BITS 0x00000100 -#define I2C_IC_CON_TX_EMPTY_CTRL_MSB 8 -#define I2C_IC_CON_TX_EMPTY_CTRL_LSB 8 +#define I2C_IC_CON_TX_EMPTY_CTRL_RESET _u(0x0) +#define I2C_IC_CON_TX_EMPTY_CTRL_BITS _u(0x00000100) +#define I2C_IC_CON_TX_EMPTY_CTRL_MSB _u(8) +#define I2C_IC_CON_TX_EMPTY_CTRL_LSB _u(8) #define I2C_IC_CON_TX_EMPTY_CTRL_ACCESS "RW" -#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_DISABLED 0x0 -#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_ENABLED 0x1 +#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_DISABLED _u(0x0) +#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_STOP_DET_IFADDRESSED // Description : In slave mode: - 1'b1: issues the STOP_DET interrupt only when @@ -77,13 +151,13 @@ // transmitted address matches the slave address (SAR). // 0x0 -> slave issues STOP_DET intr always // 0x1 -> slave issues STOP_DET intr only if addressed -#define I2C_IC_CON_STOP_DET_IFADDRESSED_RESET 0x0 -#define I2C_IC_CON_STOP_DET_IFADDRESSED_BITS 0x00000080 -#define I2C_IC_CON_STOP_DET_IFADDRESSED_MSB 7 -#define I2C_IC_CON_STOP_DET_IFADDRESSED_LSB 7 +#define I2C_IC_CON_STOP_DET_IFADDRESSED_RESET _u(0x0) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_BITS _u(0x00000080) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_MSB _u(7) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_LSB _u(7) #define I2C_IC_CON_STOP_DET_IFADDRESSED_ACCESS "RW" -#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_DISABLED 0x0 -#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_ENABLED 0x1 +#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_DISABLED _u(0x0) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_IC_SLAVE_DISABLE // Description : This bit controls whether I2C has its slave disabled, which @@ -98,13 +172,13 @@ // 0, then bit 0 should also be written with a 0. // 0x0 -> Slave mode is enabled // 0x1 -> Slave mode is disabled -#define I2C_IC_CON_IC_SLAVE_DISABLE_RESET 0x1 -#define I2C_IC_CON_IC_SLAVE_DISABLE_BITS 0x00000040 -#define I2C_IC_CON_IC_SLAVE_DISABLE_MSB 6 -#define I2C_IC_CON_IC_SLAVE_DISABLE_LSB 6 +#define I2C_IC_CON_IC_SLAVE_DISABLE_RESET _u(0x1) +#define I2C_IC_CON_IC_SLAVE_DISABLE_BITS _u(0x00000040) +#define I2C_IC_CON_IC_SLAVE_DISABLE_MSB _u(6) +#define I2C_IC_CON_IC_SLAVE_DISABLE_LSB _u(6) #define I2C_IC_CON_IC_SLAVE_DISABLE_ACCESS "RW" -#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_ENABLED 0x0 -#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_DISABLED 0x1 +#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_ENABLED _u(0x0) +#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_IC_RESTART_EN // Description : Determines whether RESTART conditions may be sent when acting @@ -124,13 +198,13 @@ // Reset value: ENABLED // 0x0 -> Master restart disabled // 0x1 -> Master restart enabled -#define I2C_IC_CON_IC_RESTART_EN_RESET 0x1 -#define I2C_IC_CON_IC_RESTART_EN_BITS 0x00000020 -#define I2C_IC_CON_IC_RESTART_EN_MSB 5 -#define I2C_IC_CON_IC_RESTART_EN_LSB 5 +#define I2C_IC_CON_IC_RESTART_EN_RESET _u(0x1) +#define I2C_IC_CON_IC_RESTART_EN_BITS _u(0x00000020) +#define I2C_IC_CON_IC_RESTART_EN_MSB _u(5) +#define I2C_IC_CON_IC_RESTART_EN_LSB _u(5) #define I2C_IC_CON_IC_RESTART_EN_ACCESS "RW" -#define I2C_IC_CON_IC_RESTART_EN_VALUE_DISABLED 0x0 -#define I2C_IC_CON_IC_RESTART_EN_VALUE_ENABLED 0x1 +#define I2C_IC_CON_IC_RESTART_EN_VALUE_DISABLED _u(0x0) +#define I2C_IC_CON_IC_RESTART_EN_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_IC_10BITADDR_MASTER // Description : Controls whether the DW_apb_i2c starts its transfers in 7- or @@ -138,13 +212,13 @@ // addressing - 1: 10-bit addressing // 0x0 -> Master 7Bit addressing mode // 0x1 -> Master 10Bit addressing mode -#define I2C_IC_CON_IC_10BITADDR_MASTER_RESET 0x0 -#define I2C_IC_CON_IC_10BITADDR_MASTER_BITS 0x00000010 -#define I2C_IC_CON_IC_10BITADDR_MASTER_MSB 4 -#define I2C_IC_CON_IC_10BITADDR_MASTER_LSB 4 +#define I2C_IC_CON_IC_10BITADDR_MASTER_RESET _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_MASTER_BITS _u(0x00000010) +#define I2C_IC_CON_IC_10BITADDR_MASTER_MSB _u(4) +#define I2C_IC_CON_IC_10BITADDR_MASTER_LSB _u(4) #define I2C_IC_CON_IC_10BITADDR_MASTER_ACCESS "RW" -#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS 0x0 -#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_10BITS 0x1 +#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_10BITS _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_IC_10BITADDR_SLAVE // Description : When acting as a slave, this bit controls whether the @@ -156,13 +230,13 @@ // that match the full 10 bits of the IC_SAR register. // 0x0 -> Slave 7Bit addressing // 0x1 -> Slave 10Bit addressing -#define I2C_IC_CON_IC_10BITADDR_SLAVE_RESET 0x0 -#define I2C_IC_CON_IC_10BITADDR_SLAVE_BITS 0x00000008 -#define I2C_IC_CON_IC_10BITADDR_SLAVE_MSB 3 -#define I2C_IC_CON_IC_10BITADDR_SLAVE_LSB 3 +#define I2C_IC_CON_IC_10BITADDR_SLAVE_RESET _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_BITS _u(0x00000008) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_MSB _u(3) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_LSB _u(3) #define I2C_IC_CON_IC_10BITADDR_SLAVE_ACCESS "RW" -#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_7BITS 0x0 -#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_10BITS 0x1 +#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_7BITS _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_10BITS _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_SPEED // Description : These bits control at which speed the DW_apb_i2c operates; its @@ -186,14 +260,14 @@ // 0x1 -> Standard Speed mode of operation // 0x2 -> Fast or Fast Plus mode of operation // 0x3 -> High Speed mode of operation -#define I2C_IC_CON_SPEED_RESET 0x2 -#define I2C_IC_CON_SPEED_BITS 0x00000006 -#define I2C_IC_CON_SPEED_MSB 2 -#define I2C_IC_CON_SPEED_LSB 1 +#define I2C_IC_CON_SPEED_RESET _u(0x2) +#define I2C_IC_CON_SPEED_BITS _u(0x00000006) +#define I2C_IC_CON_SPEED_MSB _u(2) +#define I2C_IC_CON_SPEED_LSB _u(1) #define I2C_IC_CON_SPEED_ACCESS "RW" -#define I2C_IC_CON_SPEED_VALUE_STANDARD 0x1 -#define I2C_IC_CON_SPEED_VALUE_FAST 0x2 -#define I2C_IC_CON_SPEED_VALUE_HIGH 0x3 +#define I2C_IC_CON_SPEED_VALUE_STANDARD _u(0x1) +#define I2C_IC_CON_SPEED_VALUE_FAST _u(0x2) +#define I2C_IC_CON_SPEED_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_MASTER_MODE // Description : This bit controls whether the DW_apb_i2c master is enabled. @@ -202,13 +276,13 @@ // '1' then bit 6 should also be written with a '1'. // 0x0 -> Master mode is disabled // 0x1 -> Master mode is enabled -#define I2C_IC_CON_MASTER_MODE_RESET 0x1 -#define I2C_IC_CON_MASTER_MODE_BITS 0x00000001 -#define I2C_IC_CON_MASTER_MODE_MSB 0 -#define I2C_IC_CON_MASTER_MODE_LSB 0 +#define I2C_IC_CON_MASTER_MODE_RESET _u(0x1) +#define I2C_IC_CON_MASTER_MODE_BITS _u(0x00000001) +#define I2C_IC_CON_MASTER_MODE_MSB _u(0) +#define I2C_IC_CON_MASTER_MODE_LSB _u(0) #define I2C_IC_CON_MASTER_MODE_ACCESS "RW" -#define I2C_IC_CON_MASTER_MODE_VALUE_DISABLED 0x0 -#define I2C_IC_CON_MASTER_MODE_VALUE_ENABLED 0x1 +#define I2C_IC_CON_MASTER_MODE_VALUE_DISABLED _u(0x0) +#define I2C_IC_CON_MASTER_MODE_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_TAR // Description : I2C Target Address Register @@ -223,9 +297,9 @@ // address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - // It is not necessary to perform any write to this register if // DW_apb_i2c is enabled as an I2C slave only. -#define I2C_IC_TAR_OFFSET 0x00000004 -#define I2C_IC_TAR_BITS 0x00000fff -#define I2C_IC_TAR_RESET 0x00000055 +#define I2C_IC_TAR_OFFSET _u(0x00000004) +#define I2C_IC_TAR_BITS _u(0x00000fff) +#define I2C_IC_TAR_RESET _u(0x00000055) // ----------------------------------------------------------------------------- // Field : I2C_IC_TAR_SPECIAL // Description : This bit indicates whether software performs a Device-ID or @@ -237,13 +311,13 @@ // transmission // 0x1 -> Enables programming of GENERAL_CALL or START_BYTE // transmission -#define I2C_IC_TAR_SPECIAL_RESET 0x0 -#define I2C_IC_TAR_SPECIAL_BITS 0x00000800 -#define I2C_IC_TAR_SPECIAL_MSB 11 -#define I2C_IC_TAR_SPECIAL_LSB 11 +#define I2C_IC_TAR_SPECIAL_RESET _u(0x0) +#define I2C_IC_TAR_SPECIAL_BITS _u(0x00000800) +#define I2C_IC_TAR_SPECIAL_MSB _u(11) +#define I2C_IC_TAR_SPECIAL_LSB _u(11) #define I2C_IC_TAR_SPECIAL_ACCESS "RW" -#define I2C_IC_TAR_SPECIAL_VALUE_DISABLED 0x0 -#define I2C_IC_TAR_SPECIAL_VALUE_ENABLED 0x1 +#define I2C_IC_TAR_SPECIAL_VALUE_DISABLED _u(0x0) +#define I2C_IC_TAR_SPECIAL_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TAR_GC_OR_START // Description : If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to @@ -256,13 +330,13 @@ // value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 // 0x0 -> GENERAL_CALL byte transmission // 0x1 -> START byte transmission -#define I2C_IC_TAR_GC_OR_START_RESET 0x0 -#define I2C_IC_TAR_GC_OR_START_BITS 0x00000400 -#define I2C_IC_TAR_GC_OR_START_MSB 10 -#define I2C_IC_TAR_GC_OR_START_LSB 10 +#define I2C_IC_TAR_GC_OR_START_RESET _u(0x0) +#define I2C_IC_TAR_GC_OR_START_BITS _u(0x00000400) +#define I2C_IC_TAR_GC_OR_START_MSB _u(10) +#define I2C_IC_TAR_GC_OR_START_LSB _u(10) #define I2C_IC_TAR_GC_OR_START_ACCESS "RW" -#define I2C_IC_TAR_GC_OR_START_VALUE_GENERAL_CALL 0x0 -#define I2C_IC_TAR_GC_OR_START_VALUE_START_BYTE 0x1 +#define I2C_IC_TAR_GC_OR_START_VALUE_GENERAL_CALL _u(0x0) +#define I2C_IC_TAR_GC_OR_START_VALUE_START_BYTE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TAR_IC_TAR // Description : This is the target address for any master transaction. When @@ -275,17 +349,17 @@ // not feasible. Only one direction loopback mode is supported // (simplex), not duplex. A master cannot transmit to itself; it // can transmit to only a slave. -#define I2C_IC_TAR_IC_TAR_RESET 0x055 -#define I2C_IC_TAR_IC_TAR_BITS 0x000003ff -#define I2C_IC_TAR_IC_TAR_MSB 9 -#define I2C_IC_TAR_IC_TAR_LSB 0 +#define I2C_IC_TAR_IC_TAR_RESET _u(0x055) +#define I2C_IC_TAR_IC_TAR_BITS _u(0x000003ff) +#define I2C_IC_TAR_IC_TAR_MSB _u(9) +#define I2C_IC_TAR_IC_TAR_LSB _u(0) #define I2C_IC_TAR_IC_TAR_ACCESS "RW" // ============================================================================= // Register : I2C_IC_SAR // Description : I2C Slave Address Register -#define I2C_IC_SAR_OFFSET 0x00000008 -#define I2C_IC_SAR_BITS 0x000003ff -#define I2C_IC_SAR_RESET 0x00000055 +#define I2C_IC_SAR_OFFSET _u(0x00000008) +#define I2C_IC_SAR_BITS _u(0x000003ff) +#define I2C_IC_SAR_RESET _u(0x00000055) // ----------------------------------------------------------------------------- // Field : I2C_IC_SAR_IC_SAR // Description : The IC_SAR holds the slave address when the I2C is operating as @@ -301,10 +375,10 @@ // IC_SAR or IC_TAR to a reserved value. Refer to // <> for a complete list of these // reserved values. -#define I2C_IC_SAR_IC_SAR_RESET 0x055 -#define I2C_IC_SAR_IC_SAR_BITS 0x000003ff -#define I2C_IC_SAR_IC_SAR_MSB 9 -#define I2C_IC_SAR_IC_SAR_LSB 0 +#define I2C_IC_SAR_IC_SAR_RESET _u(0x055) +#define I2C_IC_SAR_IC_SAR_BITS _u(0x000003ff) +#define I2C_IC_SAR_IC_SAR_MSB _u(9) +#define I2C_IC_SAR_IC_SAR_LSB _u(0) #define I2C_IC_SAR_IC_SAR_ACCESS "RW" // ============================================================================= // Register : I2C_IC_DATA_CMD @@ -321,9 +395,9 @@ // to continue acknowledging reads, a read command should be // written for every byte that is to be received; otherwise the // DW_apb_i2c will stop acknowledging. -#define I2C_IC_DATA_CMD_OFFSET 0x00000010 -#define I2C_IC_DATA_CMD_BITS 0x00000fff -#define I2C_IC_DATA_CMD_RESET 0x00000000 +#define I2C_IC_DATA_CMD_OFFSET _u(0x00000010) +#define I2C_IC_DATA_CMD_BITS _u(0x00000fff) +#define I2C_IC_DATA_CMD_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_DATA_CMD_FIRST_DATA_BYTE // Description : Indicates the first data byte received after the address phase @@ -347,13 +421,13 @@ // FIRST_DATA_BYTE status. // 0x0 -> Sequential data byte received // 0x1 -> Non sequential data byte received -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_RESET 0x0 -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_BITS 0x00000800 -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_MSB 11 -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_LSB 11 +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_RESET _u(0x0) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_BITS _u(0x00000800) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_MSB _u(11) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_LSB _u(11) #define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_ACCESS "RO" -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_INACTIVE 0x0 -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_ACTIVE 0x1 +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_INACTIVE _u(0x0) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_DATA_CMD_RESTART // Description : This bit controls whether a RESTART is issued before the byte @@ -373,13 +447,13 @@ // Reset value: 0x0 // 0x0 -> Don't Issue RESTART before this command // 0x1 -> Issue RESTART before this command -#define I2C_IC_DATA_CMD_RESTART_RESET 0x0 -#define I2C_IC_DATA_CMD_RESTART_BITS 0x00000400 -#define I2C_IC_DATA_CMD_RESTART_MSB 10 -#define I2C_IC_DATA_CMD_RESTART_LSB 10 +#define I2C_IC_DATA_CMD_RESTART_RESET _u(0x0) +#define I2C_IC_DATA_CMD_RESTART_BITS _u(0x00000400) +#define I2C_IC_DATA_CMD_RESTART_MSB _u(10) +#define I2C_IC_DATA_CMD_RESTART_LSB _u(10) #define I2C_IC_DATA_CMD_RESTART_ACCESS "SC" -#define I2C_IC_DATA_CMD_RESTART_VALUE_DISABLE 0x0 -#define I2C_IC_DATA_CMD_RESTART_VALUE_ENABLE 0x1 +#define I2C_IC_DATA_CMD_RESTART_VALUE_DISABLE _u(0x0) +#define I2C_IC_DATA_CMD_RESTART_VALUE_ENABLE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_DATA_CMD_STOP // Description : This bit controls whether a STOP is issued after the byte is @@ -397,13 +471,13 @@ // is available in the Tx FIFO. Reset value: 0x0 // 0x0 -> Don't Issue STOP after this command // 0x1 -> Issue STOP after this command -#define I2C_IC_DATA_CMD_STOP_RESET 0x0 -#define I2C_IC_DATA_CMD_STOP_BITS 0x00000200 -#define I2C_IC_DATA_CMD_STOP_MSB 9 -#define I2C_IC_DATA_CMD_STOP_LSB 9 +#define I2C_IC_DATA_CMD_STOP_RESET _u(0x0) +#define I2C_IC_DATA_CMD_STOP_BITS _u(0x00000200) +#define I2C_IC_DATA_CMD_STOP_MSB _u(9) +#define I2C_IC_DATA_CMD_STOP_LSB _u(9) #define I2C_IC_DATA_CMD_STOP_ACCESS "SC" -#define I2C_IC_DATA_CMD_STOP_VALUE_DISABLE 0x0 -#define I2C_IC_DATA_CMD_STOP_VALUE_ENABLE 0x1 +#define I2C_IC_DATA_CMD_STOP_VALUE_DISABLE _u(0x0) +#define I2C_IC_DATA_CMD_STOP_VALUE_ENABLE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_DATA_CMD_CMD // Description : This bit controls whether a read or a write is performed. This @@ -428,13 +502,13 @@ // Reset value: 0x0 // 0x0 -> Master Write Command // 0x1 -> Master Read Command -#define I2C_IC_DATA_CMD_CMD_RESET 0x0 -#define I2C_IC_DATA_CMD_CMD_BITS 0x00000100 -#define I2C_IC_DATA_CMD_CMD_MSB 8 -#define I2C_IC_DATA_CMD_CMD_LSB 8 +#define I2C_IC_DATA_CMD_CMD_RESET _u(0x0) +#define I2C_IC_DATA_CMD_CMD_BITS _u(0x00000100) +#define I2C_IC_DATA_CMD_CMD_MSB _u(8) +#define I2C_IC_DATA_CMD_CMD_LSB _u(8) #define I2C_IC_DATA_CMD_CMD_ACCESS "SC" -#define I2C_IC_DATA_CMD_CMD_VALUE_WRITE 0x0 -#define I2C_IC_DATA_CMD_CMD_VALUE_READ 0x1 +#define I2C_IC_DATA_CMD_CMD_VALUE_WRITE _u(0x0) +#define I2C_IC_DATA_CMD_CMD_VALUE_READ _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_DATA_CMD_DAT // Description : This register contains the data to be transmitted or received @@ -444,17 +518,17 @@ // value of data received on the DW_apb_i2c interface. // // Reset value: 0x0 -#define I2C_IC_DATA_CMD_DAT_RESET 0x00 -#define I2C_IC_DATA_CMD_DAT_BITS 0x000000ff -#define I2C_IC_DATA_CMD_DAT_MSB 7 -#define I2C_IC_DATA_CMD_DAT_LSB 0 +#define I2C_IC_DATA_CMD_DAT_RESET _u(0x00) +#define I2C_IC_DATA_CMD_DAT_BITS _u(0x000000ff) +#define I2C_IC_DATA_CMD_DAT_MSB _u(7) +#define I2C_IC_DATA_CMD_DAT_LSB _u(0) #define I2C_IC_DATA_CMD_DAT_ACCESS "RW" // ============================================================================= // Register : I2C_IC_SS_SCL_HCNT // Description : Standard Speed I2C Clock SCL High Count Register -#define I2C_IC_SS_SCL_HCNT_OFFSET 0x00000014 -#define I2C_IC_SS_SCL_HCNT_BITS 0x0000ffff -#define I2C_IC_SS_SCL_HCNT_RESET 0x00000028 +#define I2C_IC_SS_SCL_HCNT_OFFSET _u(0x00000014) +#define I2C_IC_SS_SCL_HCNT_BITS _u(0x0000ffff) +#define I2C_IC_SS_SCL_HCNT_RESET _u(0x00000028) // ----------------------------------------------------------------------------- // Field : I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT // Description : This register must be set before any I2C bus transaction can @@ -477,17 +551,17 @@ // than 65525, because DW_apb_i2c uses a 16-bit counter to flag an // I2C bus idle condition when this counter reaches a value of // IC_SS_SCL_HCNT + 10. -#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET 0x0028 -#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_BITS 0x0000ffff -#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB 15 -#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB 0 +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET _u(0x0028) +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_BITS _u(0x0000ffff) +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB _u(15) +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB _u(0) #define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_ACCESS "RW" // ============================================================================= // Register : I2C_IC_SS_SCL_LCNT // Description : Standard Speed I2C Clock SCL Low Count Register -#define I2C_IC_SS_SCL_LCNT_OFFSET 0x00000018 -#define I2C_IC_SS_SCL_LCNT_BITS 0x0000ffff -#define I2C_IC_SS_SCL_LCNT_RESET 0x0000002f +#define I2C_IC_SS_SCL_LCNT_OFFSET _u(0x00000018) +#define I2C_IC_SS_SCL_LCNT_BITS _u(0x0000ffff) +#define I2C_IC_SS_SCL_LCNT_RESET _u(0x0000002f) // ----------------------------------------------------------------------------- // Field : I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT // Description : This register must be set before any I2C bus transaction can @@ -505,17 +579,17 @@ // programming is important to ensure the correct operation of // DW_apb_i2c. The lower byte must be programmed first, and then // the upper byte is programmed. -#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET 0x002f -#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_BITS 0x0000ffff -#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB 15 -#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB 0 +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET _u(0x002f) +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_BITS _u(0x0000ffff) +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB _u(15) +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB _u(0) #define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_ACCESS "RW" // ============================================================================= // Register : I2C_IC_FS_SCL_HCNT // Description : Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register -#define I2C_IC_FS_SCL_HCNT_OFFSET 0x0000001c -#define I2C_IC_FS_SCL_HCNT_BITS 0x0000ffff -#define I2C_IC_FS_SCL_HCNT_RESET 0x00000006 +#define I2C_IC_FS_SCL_HCNT_OFFSET _u(0x0000001c) +#define I2C_IC_FS_SCL_HCNT_BITS _u(0x0000ffff) +#define I2C_IC_FS_SCL_HCNT_RESET _u(0x00000006) // ----------------------------------------------------------------------------- // Field : I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT // Description : This register must be set before any I2C bus transaction can @@ -537,17 +611,17 @@ // programming is important to ensure the correct operation of the // DW_apb_i2c. The lower byte must be programmed first. Then the // upper byte is programmed. -#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET 0x0006 -#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS 0x0000ffff -#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB 15 -#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB 0 +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET _u(0x0006) +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS _u(0x0000ffff) +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB _u(15) +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB _u(0) #define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_ACCESS "RW" // ============================================================================= // Register : I2C_IC_FS_SCL_LCNT // Description : Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register -#define I2C_IC_FS_SCL_LCNT_OFFSET 0x00000020 -#define I2C_IC_FS_SCL_LCNT_BITS 0x0000ffff -#define I2C_IC_FS_SCL_LCNT_RESET 0x0000000d +#define I2C_IC_FS_SCL_LCNT_OFFSET _u(0x00000020) +#define I2C_IC_FS_SCL_LCNT_BITS _u(0x0000ffff) +#define I2C_IC_FS_SCL_LCNT_RESET _u(0x0000000d) // ----------------------------------------------------------------------------- // Field : I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT // Description : This register must be set before any I2C bus transaction can @@ -571,10 +645,10 @@ // DW_apb_i2c. The lower byte must be programmed first. Then the // upper byte is programmed. If the value is less than 8 then the // count value gets changed to 8. -#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET 0x000d -#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS 0x0000ffff -#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB 15 -#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB 0 +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET _u(0x000d) +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS _u(0x0000ffff) +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB _u(15) +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB _u(0) #define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_ACCESS "RW" // ============================================================================= // Register : I2C_IC_INTR_STAT @@ -584,24 +658,9 @@ // IC_INTR_MASK register. These bits are cleared by reading the // matching interrupt clear register. The unmasked raw versions of // these bits are available in the IC_RAW_INTR_STAT register. -#define I2C_IC_INTR_STAT_OFFSET 0x0000002c -#define I2C_IC_INTR_STAT_BITS 0x00003fff -#define I2C_IC_INTR_STAT_RESET 0x00000000 -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_STAT_R_MASTER_ON_HOLD -// Description : See IC_RAW_INTR_STAT for a detailed description of -// R_MASTER_ON_HOLD bit. -// -// Reset value: 0x0 -// 0x0 -> R_MASTER_ON_HOLD interrupt is inactive -// 0x1 -> R_MASTER_ON_HOLD interrupt is active -#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_RESET 0x0 -#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_BITS 0x00002000 -#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_MSB 13 -#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_LSB 13 -#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_OFFSET _u(0x0000002c) +#define I2C_IC_INTR_STAT_BITS _u(0x00001fff) +#define I2C_IC_INTR_STAT_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RESTART_DET // Description : See IC_RAW_INTR_STAT for a detailed description of @@ -610,13 +669,13 @@ // Reset value: 0x0 // 0x0 -> R_RESTART_DET interrupt is inactive // 0x1 -> R_RESTART_DET interrupt is active -#define I2C_IC_INTR_STAT_R_RESTART_DET_RESET 0x0 -#define I2C_IC_INTR_STAT_R_RESTART_DET_BITS 0x00001000 -#define I2C_IC_INTR_STAT_R_RESTART_DET_MSB 12 -#define I2C_IC_INTR_STAT_R_RESTART_DET_LSB 12 +#define I2C_IC_INTR_STAT_R_RESTART_DET_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RESTART_DET_BITS _u(0x00001000) +#define I2C_IC_INTR_STAT_R_RESTART_DET_MSB _u(12) +#define I2C_IC_INTR_STAT_R_RESTART_DET_LSB _u(12) #define I2C_IC_INTR_STAT_R_RESTART_DET_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_GEN_CALL // Description : See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL @@ -625,13 +684,13 @@ // Reset value: 0x0 // 0x0 -> R_GEN_CALL interrupt is inactive // 0x1 -> R_GEN_CALL interrupt is active -#define I2C_IC_INTR_STAT_R_GEN_CALL_RESET 0x0 -#define I2C_IC_INTR_STAT_R_GEN_CALL_BITS 0x00000800 -#define I2C_IC_INTR_STAT_R_GEN_CALL_MSB 11 -#define I2C_IC_INTR_STAT_R_GEN_CALL_LSB 11 +#define I2C_IC_INTR_STAT_R_GEN_CALL_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_GEN_CALL_BITS _u(0x00000800) +#define I2C_IC_INTR_STAT_R_GEN_CALL_MSB _u(11) +#define I2C_IC_INTR_STAT_R_GEN_CALL_LSB _u(11) #define I2C_IC_INTR_STAT_R_GEN_CALL_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_START_DET // Description : See IC_RAW_INTR_STAT for a detailed description of R_START_DET @@ -640,13 +699,13 @@ // Reset value: 0x0 // 0x0 -> R_START_DET interrupt is inactive // 0x1 -> R_START_DET interrupt is active -#define I2C_IC_INTR_STAT_R_START_DET_RESET 0x0 -#define I2C_IC_INTR_STAT_R_START_DET_BITS 0x00000400 -#define I2C_IC_INTR_STAT_R_START_DET_MSB 10 -#define I2C_IC_INTR_STAT_R_START_DET_LSB 10 +#define I2C_IC_INTR_STAT_R_START_DET_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_START_DET_BITS _u(0x00000400) +#define I2C_IC_INTR_STAT_R_START_DET_MSB _u(10) +#define I2C_IC_INTR_STAT_R_START_DET_LSB _u(10) #define I2C_IC_INTR_STAT_R_START_DET_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_START_DET_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_START_DET_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_START_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_START_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_STOP_DET // Description : See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET @@ -655,13 +714,13 @@ // Reset value: 0x0 // 0x0 -> R_STOP_DET interrupt is inactive // 0x1 -> R_STOP_DET interrupt is active -#define I2C_IC_INTR_STAT_R_STOP_DET_RESET 0x0 -#define I2C_IC_INTR_STAT_R_STOP_DET_BITS 0x00000200 -#define I2C_IC_INTR_STAT_R_STOP_DET_MSB 9 -#define I2C_IC_INTR_STAT_R_STOP_DET_LSB 9 +#define I2C_IC_INTR_STAT_R_STOP_DET_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_STOP_DET_BITS _u(0x00000200) +#define I2C_IC_INTR_STAT_R_STOP_DET_MSB _u(9) +#define I2C_IC_INTR_STAT_R_STOP_DET_LSB _u(9) #define I2C_IC_INTR_STAT_R_STOP_DET_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_ACTIVITY // Description : See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY @@ -670,13 +729,13 @@ // Reset value: 0x0 // 0x0 -> R_ACTIVITY interrupt is inactive // 0x1 -> R_ACTIVITY interrupt is active -#define I2C_IC_INTR_STAT_R_ACTIVITY_RESET 0x0 -#define I2C_IC_INTR_STAT_R_ACTIVITY_BITS 0x00000100 -#define I2C_IC_INTR_STAT_R_ACTIVITY_MSB 8 -#define I2C_IC_INTR_STAT_R_ACTIVITY_LSB 8 +#define I2C_IC_INTR_STAT_R_ACTIVITY_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_ACTIVITY_BITS _u(0x00000100) +#define I2C_IC_INTR_STAT_R_ACTIVITY_MSB _u(8) +#define I2C_IC_INTR_STAT_R_ACTIVITY_LSB _u(8) #define I2C_IC_INTR_STAT_R_ACTIVITY_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RX_DONE // Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE @@ -685,13 +744,13 @@ // Reset value: 0x0 // 0x0 -> R_RX_DONE interrupt is inactive // 0x1 -> R_RX_DONE interrupt is active -#define I2C_IC_INTR_STAT_R_RX_DONE_RESET 0x0 -#define I2C_IC_INTR_STAT_R_RX_DONE_BITS 0x00000080 -#define I2C_IC_INTR_STAT_R_RX_DONE_MSB 7 -#define I2C_IC_INTR_STAT_R_RX_DONE_LSB 7 +#define I2C_IC_INTR_STAT_R_RX_DONE_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_DONE_BITS _u(0x00000080) +#define I2C_IC_INTR_STAT_R_RX_DONE_MSB _u(7) +#define I2C_IC_INTR_STAT_R_RX_DONE_LSB _u(7) #define I2C_IC_INTR_STAT_R_RX_DONE_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_TX_ABRT // Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT @@ -700,13 +759,13 @@ // Reset value: 0x0 // 0x0 -> R_TX_ABRT interrupt is inactive // 0x1 -> R_TX_ABRT interrupt is active -#define I2C_IC_INTR_STAT_R_TX_ABRT_RESET 0x0 -#define I2C_IC_INTR_STAT_R_TX_ABRT_BITS 0x00000040 -#define I2C_IC_INTR_STAT_R_TX_ABRT_MSB 6 -#define I2C_IC_INTR_STAT_R_TX_ABRT_LSB 6 +#define I2C_IC_INTR_STAT_R_TX_ABRT_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_ABRT_BITS _u(0x00000040) +#define I2C_IC_INTR_STAT_R_TX_ABRT_MSB _u(6) +#define I2C_IC_INTR_STAT_R_TX_ABRT_LSB _u(6) #define I2C_IC_INTR_STAT_R_TX_ABRT_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RD_REQ // Description : See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ @@ -715,13 +774,13 @@ // Reset value: 0x0 // 0x0 -> R_RD_REQ interrupt is inactive // 0x1 -> R_RD_REQ interrupt is active -#define I2C_IC_INTR_STAT_R_RD_REQ_RESET 0x0 -#define I2C_IC_INTR_STAT_R_RD_REQ_BITS 0x00000020 -#define I2C_IC_INTR_STAT_R_RD_REQ_MSB 5 -#define I2C_IC_INTR_STAT_R_RD_REQ_LSB 5 +#define I2C_IC_INTR_STAT_R_RD_REQ_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RD_REQ_BITS _u(0x00000020) +#define I2C_IC_INTR_STAT_R_RD_REQ_MSB _u(5) +#define I2C_IC_INTR_STAT_R_RD_REQ_LSB _u(5) #define I2C_IC_INTR_STAT_R_RD_REQ_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_TX_EMPTY // Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY @@ -730,13 +789,13 @@ // Reset value: 0x0 // 0x0 -> R_TX_EMPTY interrupt is inactive // 0x1 -> R_TX_EMPTY interrupt is active -#define I2C_IC_INTR_STAT_R_TX_EMPTY_RESET 0x0 -#define I2C_IC_INTR_STAT_R_TX_EMPTY_BITS 0x00000010 -#define I2C_IC_INTR_STAT_R_TX_EMPTY_MSB 4 -#define I2C_IC_INTR_STAT_R_TX_EMPTY_LSB 4 +#define I2C_IC_INTR_STAT_R_TX_EMPTY_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_BITS _u(0x00000010) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_MSB _u(4) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_LSB _u(4) #define I2C_IC_INTR_STAT_R_TX_EMPTY_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_TX_OVER // Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER @@ -745,13 +804,13 @@ // Reset value: 0x0 // 0x0 -> R_TX_OVER interrupt is inactive // 0x1 -> R_TX_OVER interrupt is active -#define I2C_IC_INTR_STAT_R_TX_OVER_RESET 0x0 -#define I2C_IC_INTR_STAT_R_TX_OVER_BITS 0x00000008 -#define I2C_IC_INTR_STAT_R_TX_OVER_MSB 3 -#define I2C_IC_INTR_STAT_R_TX_OVER_LSB 3 +#define I2C_IC_INTR_STAT_R_TX_OVER_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_OVER_BITS _u(0x00000008) +#define I2C_IC_INTR_STAT_R_TX_OVER_MSB _u(3) +#define I2C_IC_INTR_STAT_R_TX_OVER_LSB _u(3) #define I2C_IC_INTR_STAT_R_TX_OVER_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RX_FULL // Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL @@ -760,13 +819,13 @@ // Reset value: 0x0 // 0x0 -> R_RX_FULL interrupt is inactive // 0x1 -> R_RX_FULL interrupt is active -#define I2C_IC_INTR_STAT_R_RX_FULL_RESET 0x0 -#define I2C_IC_INTR_STAT_R_RX_FULL_BITS 0x00000004 -#define I2C_IC_INTR_STAT_R_RX_FULL_MSB 2 -#define I2C_IC_INTR_STAT_R_RX_FULL_LSB 2 +#define I2C_IC_INTR_STAT_R_RX_FULL_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_FULL_BITS _u(0x00000004) +#define I2C_IC_INTR_STAT_R_RX_FULL_MSB _u(2) +#define I2C_IC_INTR_STAT_R_RX_FULL_LSB _u(2) #define I2C_IC_INTR_STAT_R_RX_FULL_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RX_OVER // Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER @@ -775,13 +834,13 @@ // Reset value: 0x0 // 0x0 -> R_RX_OVER interrupt is inactive // 0x1 -> R_RX_OVER interrupt is active -#define I2C_IC_INTR_STAT_R_RX_OVER_RESET 0x0 -#define I2C_IC_INTR_STAT_R_RX_OVER_BITS 0x00000002 -#define I2C_IC_INTR_STAT_R_RX_OVER_MSB 1 -#define I2C_IC_INTR_STAT_R_RX_OVER_LSB 1 +#define I2C_IC_INTR_STAT_R_RX_OVER_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_OVER_BITS _u(0x00000002) +#define I2C_IC_INTR_STAT_R_RX_OVER_MSB _u(1) +#define I2C_IC_INTR_STAT_R_RX_OVER_LSB _u(1) #define I2C_IC_INTR_STAT_R_RX_OVER_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RX_UNDER // Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER @@ -790,13 +849,13 @@ // Reset value: 0x0 // 0x0 -> RX_UNDER interrupt is inactive // 0x1 -> RX_UNDER interrupt is active -#define I2C_IC_INTR_STAT_R_RX_UNDER_RESET 0x0 -#define I2C_IC_INTR_STAT_R_RX_UNDER_BITS 0x00000001 -#define I2C_IC_INTR_STAT_R_RX_UNDER_MSB 0 -#define I2C_IC_INTR_STAT_R_RX_UNDER_LSB 0 +#define I2C_IC_INTR_STAT_R_RX_UNDER_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_INTR_STAT_R_RX_UNDER_MSB _u(0) +#define I2C_IC_INTR_STAT_R_RX_UNDER_LSB _u(0) #define I2C_IC_INTR_STAT_R_RX_UNDER_ACCESS "RO" -#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_INACTIVE 0x0 -#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_ACTIVE 0x1 +#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_ACTIVE _u(0x1) // ============================================================================= // Register : I2C_IC_INTR_MASK // Description : I2C Interrupt Mask Register. @@ -804,24 +863,9 @@ // These bits mask their corresponding interrupt status bits. This // register is active low; a value of 0 masks the interrupt, // whereas a value of 1 unmasks the interrupt. -#define I2C_IC_INTR_MASK_OFFSET 0x00000030 -#define I2C_IC_INTR_MASK_BITS 0x00003fff -#define I2C_IC_INTR_MASK_RESET 0x000008ff -// ----------------------------------------------------------------------------- -// Field : I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY -// Description : This M_MASTER_ON_HOLD_read_only bit masks the R_MASTER_ON_HOLD -// interrupt in IC_INTR_STAT register. -// -// Reset value: 0x0 -// 0x0 -> MASTER_ON_HOLD interrupt is masked -// 0x1 -> MASTER_ON_HOLD interrupt is unmasked -#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_RESET 0x0 -#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_BITS 0x00002000 -#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_MSB 13 -#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_LSB 13 -#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_ACCESS "RO" -#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_OFFSET _u(0x00000030) +#define I2C_IC_INTR_MASK_BITS _u(0x00001fff) +#define I2C_IC_INTR_MASK_RESET _u(0x000008ff) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RESTART_DET // Description : This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT @@ -830,13 +874,13 @@ // Reset value: 0x0 // 0x0 -> RESTART_DET interrupt is masked // 0x1 -> RESTART_DET interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RESTART_DET_RESET 0x0 -#define I2C_IC_INTR_MASK_M_RESTART_DET_BITS 0x00001000 -#define I2C_IC_INTR_MASK_M_RESTART_DET_MSB 12 -#define I2C_IC_INTR_MASK_M_RESTART_DET_LSB 12 +#define I2C_IC_INTR_MASK_M_RESTART_DET_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_RESTART_DET_BITS _u(0x00001000) +#define I2C_IC_INTR_MASK_M_RESTART_DET_MSB _u(12) +#define I2C_IC_INTR_MASK_M_RESTART_DET_LSB _u(12) #define I2C_IC_INTR_MASK_M_RESTART_DET_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_GEN_CALL // Description : This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT @@ -845,13 +889,13 @@ // Reset value: 0x1 // 0x0 -> GEN_CALL interrupt is masked // 0x1 -> GEN_CALL interrupt is unmasked -#define I2C_IC_INTR_MASK_M_GEN_CALL_RESET 0x1 -#define I2C_IC_INTR_MASK_M_GEN_CALL_BITS 0x00000800 -#define I2C_IC_INTR_MASK_M_GEN_CALL_MSB 11 -#define I2C_IC_INTR_MASK_M_GEN_CALL_LSB 11 +#define I2C_IC_INTR_MASK_M_GEN_CALL_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_GEN_CALL_BITS _u(0x00000800) +#define I2C_IC_INTR_MASK_M_GEN_CALL_MSB _u(11) +#define I2C_IC_INTR_MASK_M_GEN_CALL_LSB _u(11) #define I2C_IC_INTR_MASK_M_GEN_CALL_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_START_DET // Description : This bit masks the R_START_DET interrupt in IC_INTR_STAT @@ -860,13 +904,13 @@ // Reset value: 0x0 // 0x0 -> START_DET interrupt is masked // 0x1 -> START_DET interrupt is unmasked -#define I2C_IC_INTR_MASK_M_START_DET_RESET 0x0 -#define I2C_IC_INTR_MASK_M_START_DET_BITS 0x00000400 -#define I2C_IC_INTR_MASK_M_START_DET_MSB 10 -#define I2C_IC_INTR_MASK_M_START_DET_LSB 10 +#define I2C_IC_INTR_MASK_M_START_DET_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_START_DET_BITS _u(0x00000400) +#define I2C_IC_INTR_MASK_M_START_DET_MSB _u(10) +#define I2C_IC_INTR_MASK_M_START_DET_LSB _u(10) #define I2C_IC_INTR_MASK_M_START_DET_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_START_DET_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_START_DET_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_START_DET_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_START_DET_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_STOP_DET // Description : This bit masks the R_STOP_DET interrupt in IC_INTR_STAT @@ -875,13 +919,13 @@ // Reset value: 0x0 // 0x0 -> STOP_DET interrupt is masked // 0x1 -> STOP_DET interrupt is unmasked -#define I2C_IC_INTR_MASK_M_STOP_DET_RESET 0x0 -#define I2C_IC_INTR_MASK_M_STOP_DET_BITS 0x00000200 -#define I2C_IC_INTR_MASK_M_STOP_DET_MSB 9 -#define I2C_IC_INTR_MASK_M_STOP_DET_LSB 9 +#define I2C_IC_INTR_MASK_M_STOP_DET_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_STOP_DET_BITS _u(0x00000200) +#define I2C_IC_INTR_MASK_M_STOP_DET_MSB _u(9) +#define I2C_IC_INTR_MASK_M_STOP_DET_LSB _u(9) #define I2C_IC_INTR_MASK_M_STOP_DET_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_ACTIVITY // Description : This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT @@ -890,13 +934,13 @@ // Reset value: 0x0 // 0x0 -> ACTIVITY interrupt is masked // 0x1 -> ACTIVITY interrupt is unmasked -#define I2C_IC_INTR_MASK_M_ACTIVITY_RESET 0x0 -#define I2C_IC_INTR_MASK_M_ACTIVITY_BITS 0x00000100 -#define I2C_IC_INTR_MASK_M_ACTIVITY_MSB 8 -#define I2C_IC_INTR_MASK_M_ACTIVITY_LSB 8 +#define I2C_IC_INTR_MASK_M_ACTIVITY_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_ACTIVITY_BITS _u(0x00000100) +#define I2C_IC_INTR_MASK_M_ACTIVITY_MSB _u(8) +#define I2C_IC_INTR_MASK_M_ACTIVITY_LSB _u(8) #define I2C_IC_INTR_MASK_M_ACTIVITY_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RX_DONE // Description : This bit masks the R_RX_DONE interrupt in IC_INTR_STAT @@ -905,13 +949,13 @@ // Reset value: 0x1 // 0x0 -> RX_DONE interrupt is masked // 0x1 -> RX_DONE interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_DONE_RESET 0x1 -#define I2C_IC_INTR_MASK_M_RX_DONE_BITS 0x00000080 -#define I2C_IC_INTR_MASK_M_RX_DONE_MSB 7 -#define I2C_IC_INTR_MASK_M_RX_DONE_LSB 7 +#define I2C_IC_INTR_MASK_M_RX_DONE_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_DONE_BITS _u(0x00000080) +#define I2C_IC_INTR_MASK_M_RX_DONE_MSB _u(7) +#define I2C_IC_INTR_MASK_M_RX_DONE_LSB _u(7) #define I2C_IC_INTR_MASK_M_RX_DONE_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_TX_ABRT // Description : This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT @@ -920,13 +964,13 @@ // Reset value: 0x1 // 0x0 -> TX_ABORT interrupt is masked // 0x1 -> TX_ABORT interrupt is unmasked -#define I2C_IC_INTR_MASK_M_TX_ABRT_RESET 0x1 -#define I2C_IC_INTR_MASK_M_TX_ABRT_BITS 0x00000040 -#define I2C_IC_INTR_MASK_M_TX_ABRT_MSB 6 -#define I2C_IC_INTR_MASK_M_TX_ABRT_LSB 6 +#define I2C_IC_INTR_MASK_M_TX_ABRT_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_TX_ABRT_BITS _u(0x00000040) +#define I2C_IC_INTR_MASK_M_TX_ABRT_MSB _u(6) +#define I2C_IC_INTR_MASK_M_TX_ABRT_LSB _u(6) #define I2C_IC_INTR_MASK_M_TX_ABRT_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RD_REQ // Description : This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. @@ -934,13 +978,13 @@ // Reset value: 0x1 // 0x0 -> RD_REQ interrupt is masked // 0x1 -> RD_REQ interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RD_REQ_RESET 0x1 -#define I2C_IC_INTR_MASK_M_RD_REQ_BITS 0x00000020 -#define I2C_IC_INTR_MASK_M_RD_REQ_MSB 5 -#define I2C_IC_INTR_MASK_M_RD_REQ_LSB 5 +#define I2C_IC_INTR_MASK_M_RD_REQ_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RD_REQ_BITS _u(0x00000020) +#define I2C_IC_INTR_MASK_M_RD_REQ_MSB _u(5) +#define I2C_IC_INTR_MASK_M_RD_REQ_LSB _u(5) #define I2C_IC_INTR_MASK_M_RD_REQ_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_TX_EMPTY // Description : This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT @@ -949,13 +993,13 @@ // Reset value: 0x1 // 0x0 -> TX_EMPTY interrupt is masked // 0x1 -> TX_EMPTY interrupt is unmasked -#define I2C_IC_INTR_MASK_M_TX_EMPTY_RESET 0x1 -#define I2C_IC_INTR_MASK_M_TX_EMPTY_BITS 0x00000010 -#define I2C_IC_INTR_MASK_M_TX_EMPTY_MSB 4 -#define I2C_IC_INTR_MASK_M_TX_EMPTY_LSB 4 +#define I2C_IC_INTR_MASK_M_TX_EMPTY_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_BITS _u(0x00000010) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_MSB _u(4) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_LSB _u(4) #define I2C_IC_INTR_MASK_M_TX_EMPTY_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_TX_OVER // Description : This bit masks the R_TX_OVER interrupt in IC_INTR_STAT @@ -964,13 +1008,13 @@ // Reset value: 0x1 // 0x0 -> TX_OVER interrupt is masked // 0x1 -> TX_OVER interrupt is unmasked -#define I2C_IC_INTR_MASK_M_TX_OVER_RESET 0x1 -#define I2C_IC_INTR_MASK_M_TX_OVER_BITS 0x00000008 -#define I2C_IC_INTR_MASK_M_TX_OVER_MSB 3 -#define I2C_IC_INTR_MASK_M_TX_OVER_LSB 3 +#define I2C_IC_INTR_MASK_M_TX_OVER_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_TX_OVER_BITS _u(0x00000008) +#define I2C_IC_INTR_MASK_M_TX_OVER_MSB _u(3) +#define I2C_IC_INTR_MASK_M_TX_OVER_LSB _u(3) #define I2C_IC_INTR_MASK_M_TX_OVER_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RX_FULL // Description : This bit masks the R_RX_FULL interrupt in IC_INTR_STAT @@ -979,13 +1023,13 @@ // Reset value: 0x1 // 0x0 -> RX_FULL interrupt is masked // 0x1 -> RX_FULL interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_FULL_RESET 0x1 -#define I2C_IC_INTR_MASK_M_RX_FULL_BITS 0x00000004 -#define I2C_IC_INTR_MASK_M_RX_FULL_MSB 2 -#define I2C_IC_INTR_MASK_M_RX_FULL_LSB 2 +#define I2C_IC_INTR_MASK_M_RX_FULL_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_FULL_BITS _u(0x00000004) +#define I2C_IC_INTR_MASK_M_RX_FULL_MSB _u(2) +#define I2C_IC_INTR_MASK_M_RX_FULL_LSB _u(2) #define I2C_IC_INTR_MASK_M_RX_FULL_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RX_OVER // Description : This bit masks the R_RX_OVER interrupt in IC_INTR_STAT @@ -994,13 +1038,13 @@ // Reset value: 0x1 // 0x0 -> RX_OVER interrupt is masked // 0x1 -> RX_OVER interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_OVER_RESET 0x1 -#define I2C_IC_INTR_MASK_M_RX_OVER_BITS 0x00000002 -#define I2C_IC_INTR_MASK_M_RX_OVER_MSB 1 -#define I2C_IC_INTR_MASK_M_RX_OVER_LSB 1 +#define I2C_IC_INTR_MASK_M_RX_OVER_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_OVER_BITS _u(0x00000002) +#define I2C_IC_INTR_MASK_M_RX_OVER_MSB _u(1) +#define I2C_IC_INTR_MASK_M_RX_OVER_LSB _u(1) #define I2C_IC_INTR_MASK_M_RX_OVER_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RX_UNDER // Description : This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT @@ -1009,38 +1053,22 @@ // Reset value: 0x1 // 0x0 -> RX_UNDER interrupt is masked // 0x1 -> RX_UNDER interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_UNDER_RESET 0x1 -#define I2C_IC_INTR_MASK_M_RX_UNDER_BITS 0x00000001 -#define I2C_IC_INTR_MASK_M_RX_UNDER_MSB 0 -#define I2C_IC_INTR_MASK_M_RX_UNDER_LSB 0 +#define I2C_IC_INTR_MASK_M_RX_UNDER_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_INTR_MASK_M_RX_UNDER_MSB _u(0) +#define I2C_IC_INTR_MASK_M_RX_UNDER_LSB _u(0) #define I2C_IC_INTR_MASK_M_RX_UNDER_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_ENABLED 0x0 -#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_DISABLED 0x1 +#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_DISABLED _u(0x1) // ============================================================================= // Register : I2C_IC_RAW_INTR_STAT // Description : I2C Raw Interrupt Status Register // // Unlike the IC_INTR_STAT register, these bits are not masked so // they always show the true status of the DW_apb_i2c. -#define I2C_IC_RAW_INTR_STAT_OFFSET 0x00000034 -#define I2C_IC_RAW_INTR_STAT_BITS 0x00003fff -#define I2C_IC_RAW_INTR_STAT_RESET 0x00000000 -// ----------------------------------------------------------------------------- -// Field : I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD -// Description : Indicates whether master is holding the bus and TX FIFO is -// empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and -// IC_EMPTYFIFO_HOLD_MASTER_EN=1. -// -// Reset value: 0x0 -// 0x0 -> MASTER_ON_HOLD interrupt is inactive -// 0x1 -> MASTER_ON_HOLD interrupt is active -#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_BITS 0x00002000 -#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_MSB 13 -#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_LSB 13 -#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_OFFSET _u(0x00000034) +#define I2C_IC_RAW_INTR_STAT_BITS _u(0x00001fff) +#define I2C_IC_RAW_INTR_STAT_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RESTART_DET // Description : Indicates whether a RESTART condition has occurred on the I2C @@ -1057,13 +1085,13 @@ // Reset value: 0x0 // 0x0 -> RESTART_DET interrupt is inactive // 0x1 -> RESTART_DET interrupt is active -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_BITS 0x00001000 -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_MSB 12 -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_LSB 12 +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_BITS _u(0x00001000) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_MSB _u(12) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_LSB _u(12) #define I2C_IC_RAW_INTR_STAT_RESTART_DET_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_GEN_CALL // Description : Set only when a General Call address is received and it is @@ -1075,13 +1103,13 @@ // Reset value: 0x0 // 0x0 -> GEN_CALL interrupt is inactive // 0x1 -> GEN_CALL interrupt is active -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_BITS 0x00000800 -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_MSB 11 -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_LSB 11 +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_BITS _u(0x00000800) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_MSB _u(11) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_LSB _u(11) #define I2C_IC_RAW_INTR_STAT_GEN_CALL_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_START_DET // Description : Indicates whether a START or RESTART condition has occurred on @@ -1091,13 +1119,13 @@ // Reset value: 0x0 // 0x0 -> START_DET interrupt is inactive // 0x1 -> START_DET interrupt is active -#define I2C_IC_RAW_INTR_STAT_START_DET_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_START_DET_BITS 0x00000400 -#define I2C_IC_RAW_INTR_STAT_START_DET_MSB 10 -#define I2C_IC_RAW_INTR_STAT_START_DET_LSB 10 +#define I2C_IC_RAW_INTR_STAT_START_DET_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_START_DET_BITS _u(0x00000400) +#define I2C_IC_RAW_INTR_STAT_START_DET_MSB _u(10) +#define I2C_IC_RAW_INTR_STAT_START_DET_LSB _u(10) #define I2C_IC_RAW_INTR_STAT_START_DET_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_STOP_DET // Description : Indicates whether a STOP condition has occurred on the I2C @@ -1120,13 +1148,13 @@ // Reset value: 0x0 // 0x0 -> STOP_DET interrupt is inactive // 0x1 -> STOP_DET interrupt is active -#define I2C_IC_RAW_INTR_STAT_STOP_DET_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_STOP_DET_BITS 0x00000200 -#define I2C_IC_RAW_INTR_STAT_STOP_DET_MSB 9 -#define I2C_IC_RAW_INTR_STAT_STOP_DET_LSB 9 +#define I2C_IC_RAW_INTR_STAT_STOP_DET_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_BITS _u(0x00000200) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_MSB _u(9) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_LSB _u(9) #define I2C_IC_RAW_INTR_STAT_STOP_DET_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_ACTIVITY // Description : This bit captures DW_apb_i2c activity and stays set until it is @@ -1140,13 +1168,13 @@ // Reset value: 0x0 // 0x0 -> RAW_INTR_ACTIVITY interrupt is inactive // 0x1 -> RAW_INTR_ACTIVITY interrupt is active -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_BITS 0x00000100 -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_MSB 8 -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_LSB 8 +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_BITS _u(0x00000100) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_MSB _u(8) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_LSB _u(8) #define I2C_IC_RAW_INTR_STAT_ACTIVITY_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RX_DONE // Description : When the DW_apb_i2c is acting as a slave-transmitter, this bit @@ -1157,13 +1185,13 @@ // Reset value: 0x0 // 0x0 -> RX_DONE interrupt is inactive // 0x1 -> RX_DONE interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_DONE_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_RX_DONE_BITS 0x00000080 -#define I2C_IC_RAW_INTR_STAT_RX_DONE_MSB 7 -#define I2C_IC_RAW_INTR_STAT_RX_DONE_LSB 7 +#define I2C_IC_RAW_INTR_STAT_RX_DONE_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_BITS _u(0x00000080) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_MSB _u(7) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_LSB _u(7) #define I2C_IC_RAW_INTR_STAT_RX_DONE_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_TX_ABRT // Description : This bit indicates if DW_apb_i2c, as an I2C transmitter, is @@ -1183,13 +1211,13 @@ // Reset value: 0x0 // 0x0 -> TX_ABRT interrupt is inactive // 0x1 -> TX_ABRT interrupt is active -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS 0x00000040 -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_MSB 6 -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_LSB 6 +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS _u(0x00000040) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_MSB _u(6) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_LSB _u(6) #define I2C_IC_RAW_INTR_STAT_TX_ABRT_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RD_REQ // Description : This bit is set to 1 when DW_apb_i2c is acting as a slave and @@ -1205,13 +1233,13 @@ // Reset value: 0x0 // 0x0 -> RD_REQ interrupt is inactive // 0x1 -> RD_REQ interrupt is active -#define I2C_IC_RAW_INTR_STAT_RD_REQ_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_RD_REQ_BITS 0x00000020 -#define I2C_IC_RAW_INTR_STAT_RD_REQ_MSB 5 -#define I2C_IC_RAW_INTR_STAT_RD_REQ_LSB 5 +#define I2C_IC_RAW_INTR_STAT_RD_REQ_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_BITS _u(0x00000020) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_MSB _u(5) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_LSB _u(5) #define I2C_IC_RAW_INTR_STAT_RD_REQ_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_TX_EMPTY // Description : The behavior of the TX_EMPTY interrupt status differs based on @@ -1233,13 +1261,13 @@ // Reset value: 0x0. // 0x0 -> TX_EMPTY interrupt is inactive // 0x1 -> TX_EMPTY interrupt is active -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS 0x00000010 -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_MSB 4 -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_LSB 4 +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS _u(0x00000010) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_MSB _u(4) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_LSB _u(4) #define I2C_IC_RAW_INTR_STAT_TX_EMPTY_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_TX_OVER // Description : Set during transmit if the transmit buffer is filled to @@ -1252,13 +1280,13 @@ // Reset value: 0x0 // 0x0 -> TX_OVER interrupt is inactive // 0x1 -> TX_OVER interrupt is active -#define I2C_IC_RAW_INTR_STAT_TX_OVER_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_TX_OVER_BITS 0x00000008 -#define I2C_IC_RAW_INTR_STAT_TX_OVER_MSB 3 -#define I2C_IC_RAW_INTR_STAT_TX_OVER_LSB 3 +#define I2C_IC_RAW_INTR_STAT_TX_OVER_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_BITS _u(0x00000008) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_MSB _u(3) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_LSB _u(3) #define I2C_IC_RAW_INTR_STAT_TX_OVER_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RX_FULL // Description : Set when the receive buffer reaches or goes above the RX_TL @@ -1272,13 +1300,13 @@ // Reset value: 0x0 // 0x0 -> RX_FULL interrupt is inactive // 0x1 -> RX_FULL interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_FULL_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_RX_FULL_BITS 0x00000004 -#define I2C_IC_RAW_INTR_STAT_RX_FULL_MSB 2 -#define I2C_IC_RAW_INTR_STAT_RX_FULL_LSB 2 +#define I2C_IC_RAW_INTR_STAT_RX_FULL_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_BITS _u(0x00000004) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_MSB _u(2) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_LSB _u(2) #define I2C_IC_RAW_INTR_STAT_RX_FULL_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RX_OVER // Description : Set if the receive buffer is completely filled to @@ -1296,13 +1324,13 @@ // Reset value: 0x0 // 0x0 -> RX_OVER interrupt is inactive // 0x1 -> RX_OVER interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_OVER_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_RX_OVER_BITS 0x00000002 -#define I2C_IC_RAW_INTR_STAT_RX_OVER_MSB 1 -#define I2C_IC_RAW_INTR_STAT_RX_OVER_LSB 1 +#define I2C_IC_RAW_INTR_STAT_RX_OVER_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_BITS _u(0x00000002) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_MSB _u(1) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_LSB _u(1) #define I2C_IC_RAW_INTR_STAT_RX_OVER_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RX_UNDER // Description : Set if the processor attempts to read the receive buffer when @@ -1314,19 +1342,19 @@ // Reset value: 0x0 // 0x0 -> RX_UNDER interrupt is inactive // 0x1 -> RX_UNDER interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_RESET 0x0 -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_BITS 0x00000001 -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_MSB 0 -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_LSB 0 +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_MSB _u(0) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_LSB _u(0) #define I2C_IC_RAW_INTR_STAT_RX_UNDER_ACCESS "RO" -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_INACTIVE 0x0 -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_ACTIVE 0x1 +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_ACTIVE _u(0x1) // ============================================================================= // Register : I2C_IC_RX_TL // Description : I2C Receive FIFO Threshold Register -#define I2C_IC_RX_TL_OFFSET 0x00000038 -#define I2C_IC_RX_TL_BITS 0x000000ff -#define I2C_IC_RX_TL_RESET 0x00000000 +#define I2C_IC_RX_TL_OFFSET _u(0x00000038) +#define I2C_IC_RX_TL_BITS _u(0x000000ff) +#define I2C_IC_RX_TL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_RX_TL_RX_TL // Description : Receive FIFO Threshold Level. @@ -1339,17 +1367,17 @@ // the actual value set will be the maximum depth of the buffer. A // value of 0 sets the threshold for 1 entry, and a value of 255 // sets the threshold for 256 entries. -#define I2C_IC_RX_TL_RX_TL_RESET 0x00 -#define I2C_IC_RX_TL_RX_TL_BITS 0x000000ff -#define I2C_IC_RX_TL_RX_TL_MSB 7 -#define I2C_IC_RX_TL_RX_TL_LSB 0 +#define I2C_IC_RX_TL_RX_TL_RESET _u(0x00) +#define I2C_IC_RX_TL_RX_TL_BITS _u(0x000000ff) +#define I2C_IC_RX_TL_RX_TL_MSB _u(7) +#define I2C_IC_RX_TL_RX_TL_LSB _u(0) #define I2C_IC_RX_TL_RX_TL_ACCESS "RW" // ============================================================================= // Register : I2C_IC_TX_TL // Description : I2C Transmit FIFO Threshold Register -#define I2C_IC_TX_TL_OFFSET 0x0000003c -#define I2C_IC_TX_TL_BITS 0x000000ff -#define I2C_IC_TX_TL_RESET 0x00000000 +#define I2C_IC_TX_TL_OFFSET _u(0x0000003c) +#define I2C_IC_TX_TL_BITS _u(0x000000ff) +#define I2C_IC_TX_TL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_TL_TX_TL // Description : Transmit FIFO Threshold Level. @@ -1362,17 +1390,17 @@ // maximum depth of the buffer. A value of 0 sets the threshold // for 0 entries, and a value of 255 sets the threshold for 255 // entries. -#define I2C_IC_TX_TL_TX_TL_RESET 0x00 -#define I2C_IC_TX_TL_TX_TL_BITS 0x000000ff -#define I2C_IC_TX_TL_TX_TL_MSB 7 -#define I2C_IC_TX_TL_TX_TL_LSB 0 +#define I2C_IC_TX_TL_TX_TL_RESET _u(0x00) +#define I2C_IC_TX_TL_TX_TL_BITS _u(0x000000ff) +#define I2C_IC_TX_TL_TX_TL_MSB _u(7) +#define I2C_IC_TX_TL_TX_TL_LSB _u(0) #define I2C_IC_TX_TL_TX_TL_ACCESS "RW" // ============================================================================= // Register : I2C_IC_CLR_INTR // Description : Clear Combined and Individual Interrupt Register -#define I2C_IC_CLR_INTR_OFFSET 0x00000040 -#define I2C_IC_CLR_INTR_BITS 0x00000001 -#define I2C_IC_CLR_INTR_RESET 0x00000000 +#define I2C_IC_CLR_INTR_OFFSET _u(0x00000040) +#define I2C_IC_CLR_INTR_BITS _u(0x00000001) +#define I2C_IC_CLR_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_INTR_CLR_INTR // Description : Read this register to clear the combined interrupt, all @@ -1382,85 +1410,85 @@ // register for an exception to clearing IC_TX_ABRT_SOURCE. // // Reset value: 0x0 -#define I2C_IC_CLR_INTR_CLR_INTR_RESET 0x0 -#define I2C_IC_CLR_INTR_CLR_INTR_BITS 0x00000001 -#define I2C_IC_CLR_INTR_CLR_INTR_MSB 0 -#define I2C_IC_CLR_INTR_CLR_INTR_LSB 0 +#define I2C_IC_CLR_INTR_CLR_INTR_RESET _u(0x0) +#define I2C_IC_CLR_INTR_CLR_INTR_BITS _u(0x00000001) +#define I2C_IC_CLR_INTR_CLR_INTR_MSB _u(0) +#define I2C_IC_CLR_INTR_CLR_INTR_LSB _u(0) #define I2C_IC_CLR_INTR_CLR_INTR_ACCESS "RO" // ============================================================================= // Register : I2C_IC_CLR_RX_UNDER // Description : Clear RX_UNDER Interrupt Register -#define I2C_IC_CLR_RX_UNDER_OFFSET 0x00000044 -#define I2C_IC_CLR_RX_UNDER_BITS 0x00000001 -#define I2C_IC_CLR_RX_UNDER_RESET 0x00000000 +#define I2C_IC_CLR_RX_UNDER_OFFSET _u(0x00000044) +#define I2C_IC_CLR_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_UNDER_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER // Description : Read this register to clear the RX_UNDER interrupt (bit 0) of // the IC_RAW_INTR_STAT register. // // Reset value: 0x0 -#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_RESET 0x0 -#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_BITS 0x00000001 -#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_MSB 0 -#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_LSB 0 +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_RESET _u(0x0) +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_MSB _u(0) +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_LSB _u(0) #define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_ACCESS "RO" // ============================================================================= // Register : I2C_IC_CLR_RX_OVER // Description : Clear RX_OVER Interrupt Register -#define I2C_IC_CLR_RX_OVER_OFFSET 0x00000048 -#define I2C_IC_CLR_RX_OVER_BITS 0x00000001 -#define I2C_IC_CLR_RX_OVER_RESET 0x00000000 +#define I2C_IC_CLR_RX_OVER_OFFSET _u(0x00000048) +#define I2C_IC_CLR_RX_OVER_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_OVER_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_RX_OVER_CLR_RX_OVER // Description : Read this register to clear the RX_OVER interrupt (bit 1) of // the IC_RAW_INTR_STAT register. // // Reset value: 0x0 -#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_RESET 0x0 -#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_BITS 0x00000001 -#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_MSB 0 -#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_LSB 0 +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_RESET _u(0x0) +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_MSB _u(0) +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_LSB _u(0) #define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_ACCESS "RO" // ============================================================================= // Register : I2C_IC_CLR_TX_OVER // Description : Clear TX_OVER Interrupt Register -#define I2C_IC_CLR_TX_OVER_OFFSET 0x0000004c -#define I2C_IC_CLR_TX_OVER_BITS 0x00000001 -#define I2C_IC_CLR_TX_OVER_RESET 0x00000000 +#define I2C_IC_CLR_TX_OVER_OFFSET _u(0x0000004c) +#define I2C_IC_CLR_TX_OVER_BITS _u(0x00000001) +#define I2C_IC_CLR_TX_OVER_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_TX_OVER_CLR_TX_OVER // Description : Read this register to clear the TX_OVER interrupt (bit 3) of // the IC_RAW_INTR_STAT register. // // Reset value: 0x0 -#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_RESET 0x0 -#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_BITS 0x00000001 -#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_MSB 0 -#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_LSB 0 +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_RESET _u(0x0) +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_BITS _u(0x00000001) +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_MSB _u(0) +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_LSB _u(0) #define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_ACCESS "RO" // ============================================================================= // Register : I2C_IC_CLR_RD_REQ // Description : Clear RD_REQ Interrupt Register -#define I2C_IC_CLR_RD_REQ_OFFSET 0x00000050 -#define I2C_IC_CLR_RD_REQ_BITS 0x00000001 -#define I2C_IC_CLR_RD_REQ_RESET 0x00000000 +#define I2C_IC_CLR_RD_REQ_OFFSET _u(0x00000050) +#define I2C_IC_CLR_RD_REQ_BITS _u(0x00000001) +#define I2C_IC_CLR_RD_REQ_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_RD_REQ_CLR_RD_REQ // Description : Read this register to clear the RD_REQ interrupt (bit 5) of the // IC_RAW_INTR_STAT register. // // Reset value: 0x0 -#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_RESET 0x0 -#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_BITS 0x00000001 -#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_MSB 0 -#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_LSB 0 +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_RESET _u(0x0) +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_BITS _u(0x00000001) +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_MSB _u(0) +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_LSB _u(0) #define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_ACCESS "RO" // ============================================================================= // Register : I2C_IC_CLR_TX_ABRT // Description : Clear TX_ABRT Interrupt Register -#define I2C_IC_CLR_TX_ABRT_OFFSET 0x00000054 -#define I2C_IC_CLR_TX_ABRT_BITS 0x00000001 -#define I2C_IC_CLR_TX_ABRT_RESET 0x00000000 +#define I2C_IC_CLR_TX_ABRT_OFFSET _u(0x00000054) +#define I2C_IC_CLR_TX_ABRT_BITS _u(0x00000001) +#define I2C_IC_CLR_TX_ABRT_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT // Description : Read this register to clear the TX_ABRT interrupt (bit 6) of @@ -1471,34 +1499,34 @@ // IC_TX_ABRT_SOURCE. // // Reset value: 0x0 -#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_RESET 0x0 -#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_BITS 0x00000001 -#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_MSB 0 -#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_LSB 0 +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_RESET _u(0x0) +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_BITS _u(0x00000001) +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_MSB _u(0) +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_LSB _u(0) #define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_ACCESS "RO" // ============================================================================= // Register : I2C_IC_CLR_RX_DONE // Description : Clear RX_DONE Interrupt Register -#define I2C_IC_CLR_RX_DONE_OFFSET 0x00000058 -#define I2C_IC_CLR_RX_DONE_BITS 0x00000001 -#define I2C_IC_CLR_RX_DONE_RESET 0x00000000 +#define I2C_IC_CLR_RX_DONE_OFFSET _u(0x00000058) +#define I2C_IC_CLR_RX_DONE_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_DONE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_RX_DONE_CLR_RX_DONE // Description : Read this register to clear the RX_DONE interrupt (bit 7) of // the IC_RAW_INTR_STAT register. // // Reset value: 0x0 -#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_RESET 0x0 -#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_BITS 0x00000001 -#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_MSB 0 -#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_LSB 0 +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_RESET _u(0x0) +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_MSB _u(0) +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_LSB _u(0) #define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_ACCESS "RO" // ============================================================================= // Register : I2C_IC_CLR_ACTIVITY // Description : Clear ACTIVITY Interrupt Register -#define I2C_IC_CLR_ACTIVITY_OFFSET 0x0000005c -#define I2C_IC_CLR_ACTIVITY_BITS 0x00000001 -#define I2C_IC_CLR_ACTIVITY_RESET 0x00000000 +#define I2C_IC_CLR_ACTIVITY_OFFSET _u(0x0000005c) +#define I2C_IC_CLR_ACTIVITY_BITS _u(0x00000001) +#define I2C_IC_CLR_ACTIVITY_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY // Description : Reading this register clears the ACTIVITY interrupt if the I2C @@ -1510,68 +1538,68 @@ // of the IC_RAW_INTR_STAT register. // // Reset value: 0x0 -#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_RESET 0x0 -#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_BITS 0x00000001 -#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_MSB 0 -#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_LSB 0 +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_RESET _u(0x0) +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_BITS _u(0x00000001) +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_MSB _u(0) +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_LSB _u(0) #define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_ACCESS "RO" // ============================================================================= // Register : I2C_IC_CLR_STOP_DET // Description : Clear STOP_DET Interrupt Register -#define I2C_IC_CLR_STOP_DET_OFFSET 0x00000060 -#define I2C_IC_CLR_STOP_DET_BITS 0x00000001 -#define I2C_IC_CLR_STOP_DET_RESET 0x00000000 +#define I2C_IC_CLR_STOP_DET_OFFSET _u(0x00000060) +#define I2C_IC_CLR_STOP_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_STOP_DET_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_STOP_DET_CLR_STOP_DET // Description : Read this register to clear the STOP_DET interrupt (bit 9) of // the IC_RAW_INTR_STAT register. // // Reset value: 0x0 -#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_RESET 0x0 -#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_BITS 0x00000001 -#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_MSB 0 -#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_LSB 0 +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_RESET _u(0x0) +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_MSB _u(0) +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_LSB _u(0) #define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_ACCESS "RO" // ============================================================================= // Register : I2C_IC_CLR_START_DET // Description : Clear START_DET Interrupt Register -#define I2C_IC_CLR_START_DET_OFFSET 0x00000064 -#define I2C_IC_CLR_START_DET_BITS 0x00000001 -#define I2C_IC_CLR_START_DET_RESET 0x00000000 +#define I2C_IC_CLR_START_DET_OFFSET _u(0x00000064) +#define I2C_IC_CLR_START_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_START_DET_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_START_DET_CLR_START_DET // Description : Read this register to clear the START_DET interrupt (bit 10) of // the IC_RAW_INTR_STAT register. // // Reset value: 0x0 -#define I2C_IC_CLR_START_DET_CLR_START_DET_RESET 0x0 -#define I2C_IC_CLR_START_DET_CLR_START_DET_BITS 0x00000001 -#define I2C_IC_CLR_START_DET_CLR_START_DET_MSB 0 -#define I2C_IC_CLR_START_DET_CLR_START_DET_LSB 0 +#define I2C_IC_CLR_START_DET_CLR_START_DET_RESET _u(0x0) +#define I2C_IC_CLR_START_DET_CLR_START_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_START_DET_CLR_START_DET_MSB _u(0) +#define I2C_IC_CLR_START_DET_CLR_START_DET_LSB _u(0) #define I2C_IC_CLR_START_DET_CLR_START_DET_ACCESS "RO" // ============================================================================= // Register : I2C_IC_CLR_GEN_CALL // Description : Clear GEN_CALL Interrupt Register -#define I2C_IC_CLR_GEN_CALL_OFFSET 0x00000068 -#define I2C_IC_CLR_GEN_CALL_BITS 0x00000001 -#define I2C_IC_CLR_GEN_CALL_RESET 0x00000000 +#define I2C_IC_CLR_GEN_CALL_OFFSET _u(0x00000068) +#define I2C_IC_CLR_GEN_CALL_BITS _u(0x00000001) +#define I2C_IC_CLR_GEN_CALL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL // Description : Read this register to clear the GEN_CALL interrupt (bit 11) of // IC_RAW_INTR_STAT register. // // Reset value: 0x0 -#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_RESET 0x0 -#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_BITS 0x00000001 -#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_MSB 0 -#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_LSB 0 +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_RESET _u(0x0) +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_BITS _u(0x00000001) +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_MSB _u(0) +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_LSB _u(0) #define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_ACCESS "RO" // ============================================================================= // Register : I2C_IC_ENABLE // Description : I2C Enable Register -#define I2C_IC_ENABLE_OFFSET 0x0000006c -#define I2C_IC_ENABLE_BITS 0x00000007 -#define I2C_IC_ENABLE_RESET 0x00000000 +#define I2C_IC_ENABLE_OFFSET _u(0x0000006c) +#define I2C_IC_ENABLE_BITS _u(0x00000007) +#define I2C_IC_ENABLE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_ENABLE_TX_CMD_BLOCK // Description : In Master mode: - 1'b1: Blocks the transmission of data on I2C @@ -1585,13 +1613,13 @@ // value: IC_TX_CMD_BLOCK_DEFAULT // 0x0 -> Tx Command execution not blocked // 0x1 -> Tx Command execution blocked -#define I2C_IC_ENABLE_TX_CMD_BLOCK_RESET 0x0 -#define I2C_IC_ENABLE_TX_CMD_BLOCK_BITS 0x00000004 -#define I2C_IC_ENABLE_TX_CMD_BLOCK_MSB 2 -#define I2C_IC_ENABLE_TX_CMD_BLOCK_LSB 2 +#define I2C_IC_ENABLE_TX_CMD_BLOCK_RESET _u(0x0) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_BITS _u(0x00000004) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_MSB _u(2) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_LSB _u(2) #define I2C_IC_ENABLE_TX_CMD_BLOCK_ACCESS "RW" -#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_NOT_BLOCKED 0x0 -#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_BLOCKED 0x1 +#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_NOT_BLOCKED _u(0x0) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_BLOCKED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_ENABLE_ABORT // Description : When set, the controller initiates the transfer abort. - 0: @@ -1611,13 +1639,13 @@ // Reset value: 0x0 // 0x0 -> ABORT operation not in progress // 0x1 -> ABORT operation in progress -#define I2C_IC_ENABLE_ABORT_RESET 0x0 -#define I2C_IC_ENABLE_ABORT_BITS 0x00000002 -#define I2C_IC_ENABLE_ABORT_MSB 1 -#define I2C_IC_ENABLE_ABORT_LSB 1 +#define I2C_IC_ENABLE_ABORT_RESET _u(0x0) +#define I2C_IC_ENABLE_ABORT_BITS _u(0x00000002) +#define I2C_IC_ENABLE_ABORT_MSB _u(1) +#define I2C_IC_ENABLE_ABORT_LSB _u(1) #define I2C_IC_ENABLE_ABORT_ACCESS "RW" -#define I2C_IC_ENABLE_ABORT_VALUE_DISABLE 0x0 -#define I2C_IC_ENABLE_ABORT_VALUE_ENABLED 0x1 +#define I2C_IC_ENABLE_ABORT_VALUE_DISABLE _u(0x0) +#define I2C_IC_ENABLE_ABORT_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_ENABLE_ENABLE // Description : Controls whether the DW_apb_i2c is enabled. - 0: Disables @@ -1645,13 +1673,13 @@ // Reset value: 0x0 // 0x0 -> I2C is disabled // 0x1 -> I2C is enabled -#define I2C_IC_ENABLE_ENABLE_RESET 0x0 -#define I2C_IC_ENABLE_ENABLE_BITS 0x00000001 -#define I2C_IC_ENABLE_ENABLE_MSB 0 -#define I2C_IC_ENABLE_ENABLE_LSB 0 +#define I2C_IC_ENABLE_ENABLE_RESET _u(0x0) +#define I2C_IC_ENABLE_ENABLE_BITS _u(0x00000001) +#define I2C_IC_ENABLE_ENABLE_MSB _u(0) +#define I2C_IC_ENABLE_ENABLE_LSB _u(0) #define I2C_IC_ENABLE_ENABLE_ACCESS "RW" -#define I2C_IC_ENABLE_ENABLE_VALUE_DISABLED 0x0 -#define I2C_IC_ENABLE_ENABLE_VALUE_ENABLED 0x1 +#define I2C_IC_ENABLE_ENABLE_VALUE_DISABLED _u(0x0) +#define I2C_IC_ENABLE_ENABLE_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_STATUS // Description : I2C Status Register @@ -1665,9 +1693,9 @@ // register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set // to 0 When the master or slave state machines goes to idle and // ic_en=0: - Bits 5 and 6 are set to 0 -#define I2C_IC_STATUS_OFFSET 0x00000070 -#define I2C_IC_STATUS_BITS 0x0000007f -#define I2C_IC_STATUS_RESET 0x00000006 +#define I2C_IC_STATUS_OFFSET _u(0x00000070) +#define I2C_IC_STATUS_BITS _u(0x0000007f) +#define I2C_IC_STATUS_RESET _u(0x00000006) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_SLV_ACTIVITY // Description : Slave FSM Activity Status. When the Slave Finite State Machine @@ -1677,13 +1705,13 @@ // DW_apb_i2c is Active Reset value: 0x0 // 0x0 -> Slave is idle // 0x1 -> Slave not idle -#define I2C_IC_STATUS_SLV_ACTIVITY_RESET 0x0 -#define I2C_IC_STATUS_SLV_ACTIVITY_BITS 0x00000040 -#define I2C_IC_STATUS_SLV_ACTIVITY_MSB 6 -#define I2C_IC_STATUS_SLV_ACTIVITY_LSB 6 +#define I2C_IC_STATUS_SLV_ACTIVITY_RESET _u(0x0) +#define I2C_IC_STATUS_SLV_ACTIVITY_BITS _u(0x00000040) +#define I2C_IC_STATUS_SLV_ACTIVITY_MSB _u(6) +#define I2C_IC_STATUS_SLV_ACTIVITY_LSB _u(6) #define I2C_IC_STATUS_SLV_ACTIVITY_ACCESS "RO" -#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_IDLE 0x0 -#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_ACTIVE 0x1 +#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_IDLE _u(0x0) +#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_MST_ACTIVITY // Description : Master FSM Activity Status. When the Master Finite State @@ -1696,13 +1724,13 @@ // Reset value: 0x0 // 0x0 -> Master is idle // 0x1 -> Master not idle -#define I2C_IC_STATUS_MST_ACTIVITY_RESET 0x0 -#define I2C_IC_STATUS_MST_ACTIVITY_BITS 0x00000020 -#define I2C_IC_STATUS_MST_ACTIVITY_MSB 5 -#define I2C_IC_STATUS_MST_ACTIVITY_LSB 5 +#define I2C_IC_STATUS_MST_ACTIVITY_RESET _u(0x0) +#define I2C_IC_STATUS_MST_ACTIVITY_BITS _u(0x00000020) +#define I2C_IC_STATUS_MST_ACTIVITY_MSB _u(5) +#define I2C_IC_STATUS_MST_ACTIVITY_LSB _u(5) #define I2C_IC_STATUS_MST_ACTIVITY_ACCESS "RO" -#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_IDLE 0x0 -#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_ACTIVE 0x1 +#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_IDLE _u(0x0) +#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_RFF // Description : Receive FIFO Completely Full. When the receive FIFO is @@ -1712,13 +1740,13 @@ // 0x0 // 0x0 -> Rx FIFO not full // 0x1 -> Rx FIFO is full -#define I2C_IC_STATUS_RFF_RESET 0x0 -#define I2C_IC_STATUS_RFF_BITS 0x00000010 -#define I2C_IC_STATUS_RFF_MSB 4 -#define I2C_IC_STATUS_RFF_LSB 4 +#define I2C_IC_STATUS_RFF_RESET _u(0x0) +#define I2C_IC_STATUS_RFF_BITS _u(0x00000010) +#define I2C_IC_STATUS_RFF_MSB _u(4) +#define I2C_IC_STATUS_RFF_LSB _u(4) #define I2C_IC_STATUS_RFF_ACCESS "RO" -#define I2C_IC_STATUS_RFF_VALUE_NOT_FULL 0x0 -#define I2C_IC_STATUS_RFF_VALUE_FULL 0x1 +#define I2C_IC_STATUS_RFF_VALUE_NOT_FULL _u(0x0) +#define I2C_IC_STATUS_RFF_VALUE_FULL _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_RFNE // Description : Receive FIFO Not Empty. This bit is set when the receive FIFO @@ -1727,13 +1755,13 @@ // not empty Reset value: 0x0 // 0x0 -> Rx FIFO is empty // 0x1 -> Rx FIFO not empty -#define I2C_IC_STATUS_RFNE_RESET 0x0 -#define I2C_IC_STATUS_RFNE_BITS 0x00000008 -#define I2C_IC_STATUS_RFNE_MSB 3 -#define I2C_IC_STATUS_RFNE_LSB 3 +#define I2C_IC_STATUS_RFNE_RESET _u(0x0) +#define I2C_IC_STATUS_RFNE_BITS _u(0x00000008) +#define I2C_IC_STATUS_RFNE_MSB _u(3) +#define I2C_IC_STATUS_RFNE_LSB _u(3) #define I2C_IC_STATUS_RFNE_ACCESS "RO" -#define I2C_IC_STATUS_RFNE_VALUE_EMPTY 0x0 -#define I2C_IC_STATUS_RFNE_VALUE_NOT_EMPTY 0x1 +#define I2C_IC_STATUS_RFNE_VALUE_EMPTY _u(0x0) +#define I2C_IC_STATUS_RFNE_VALUE_NOT_EMPTY _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_TFE // Description : Transmit FIFO Completely Empty. When the transmit FIFO is @@ -1743,13 +1771,13 @@ // Transmit FIFO is empty Reset value: 0x1 // 0x0 -> Tx FIFO not empty // 0x1 -> Tx FIFO is empty -#define I2C_IC_STATUS_TFE_RESET 0x1 -#define I2C_IC_STATUS_TFE_BITS 0x00000004 -#define I2C_IC_STATUS_TFE_MSB 2 -#define I2C_IC_STATUS_TFE_LSB 2 +#define I2C_IC_STATUS_TFE_RESET _u(0x1) +#define I2C_IC_STATUS_TFE_BITS _u(0x00000004) +#define I2C_IC_STATUS_TFE_MSB _u(2) +#define I2C_IC_STATUS_TFE_LSB _u(2) #define I2C_IC_STATUS_TFE_ACCESS "RO" -#define I2C_IC_STATUS_TFE_VALUE_NON_EMPTY 0x0 -#define I2C_IC_STATUS_TFE_VALUE_EMPTY 0x1 +#define I2C_IC_STATUS_TFE_VALUE_NON_EMPTY _u(0x0) +#define I2C_IC_STATUS_TFE_VALUE_EMPTY _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_TFNF // Description : Transmit FIFO Not Full. Set when the transmit FIFO contains one @@ -1758,25 +1786,25 @@ // value: 0x1 // 0x0 -> Tx FIFO is full // 0x1 -> Tx FIFO not full -#define I2C_IC_STATUS_TFNF_RESET 0x1 -#define I2C_IC_STATUS_TFNF_BITS 0x00000002 -#define I2C_IC_STATUS_TFNF_MSB 1 -#define I2C_IC_STATUS_TFNF_LSB 1 +#define I2C_IC_STATUS_TFNF_RESET _u(0x1) +#define I2C_IC_STATUS_TFNF_BITS _u(0x00000002) +#define I2C_IC_STATUS_TFNF_MSB _u(1) +#define I2C_IC_STATUS_TFNF_LSB _u(1) #define I2C_IC_STATUS_TFNF_ACCESS "RO" -#define I2C_IC_STATUS_TFNF_VALUE_FULL 0x0 -#define I2C_IC_STATUS_TFNF_VALUE_NOT_FULL 0x1 +#define I2C_IC_STATUS_TFNF_VALUE_FULL _u(0x0) +#define I2C_IC_STATUS_TFNF_VALUE_NOT_FULL _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_ACTIVITY // Description : I2C Activity Status. Reset value: 0x0 // 0x0 -> I2C is idle // 0x1 -> I2C is active -#define I2C_IC_STATUS_ACTIVITY_RESET 0x0 -#define I2C_IC_STATUS_ACTIVITY_BITS 0x00000001 -#define I2C_IC_STATUS_ACTIVITY_MSB 0 -#define I2C_IC_STATUS_ACTIVITY_LSB 0 +#define I2C_IC_STATUS_ACTIVITY_RESET _u(0x0) +#define I2C_IC_STATUS_ACTIVITY_BITS _u(0x00000001) +#define I2C_IC_STATUS_ACTIVITY_MSB _u(0) +#define I2C_IC_STATUS_ACTIVITY_LSB _u(0) #define I2C_IC_STATUS_ACTIVITY_ACCESS "RO" -#define I2C_IC_STATUS_ACTIVITY_VALUE_INACTIVE 0x0 -#define I2C_IC_STATUS_ACTIVITY_VALUE_ACTIVE 0x1 +#define I2C_IC_STATUS_ACTIVITY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_STATUS_ACTIVITY_VALUE_ACTIVE _u(0x1) // ============================================================================= // Register : I2C_IC_TXFLR // Description : I2C Transmit FIFO Level Register This register contains the @@ -1786,19 +1814,19 @@ // register - The slave bulk transmit mode is aborted The register // increments whenever data is placed into the transmit FIFO and // decrements when data is taken from the transmit FIFO. -#define I2C_IC_TXFLR_OFFSET 0x00000074 -#define I2C_IC_TXFLR_BITS 0x0000001f -#define I2C_IC_TXFLR_RESET 0x00000000 +#define I2C_IC_TXFLR_OFFSET _u(0x00000074) +#define I2C_IC_TXFLR_BITS _u(0x0000001f) +#define I2C_IC_TXFLR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_TXFLR_TXFLR // Description : Transmit FIFO Level. Contains the number of valid data entries // in the transmit FIFO. // // Reset value: 0x0 -#define I2C_IC_TXFLR_TXFLR_RESET 0x00 -#define I2C_IC_TXFLR_TXFLR_BITS 0x0000001f -#define I2C_IC_TXFLR_TXFLR_MSB 4 -#define I2C_IC_TXFLR_TXFLR_LSB 0 +#define I2C_IC_TXFLR_TXFLR_RESET _u(0x00) +#define I2C_IC_TXFLR_TXFLR_BITS _u(0x0000001f) +#define I2C_IC_TXFLR_TXFLR_MSB _u(4) +#define I2C_IC_TXFLR_TXFLR_LSB _u(0) #define I2C_IC_TXFLR_TXFLR_ACCESS "RO" // ============================================================================= // Register : I2C_IC_RXFLR @@ -1809,19 +1837,19 @@ // IC_TX_ABRT_SOURCE The register increments whenever data is // placed into the receive FIFO and decrements when data is taken // from the receive FIFO. -#define I2C_IC_RXFLR_OFFSET 0x00000078 -#define I2C_IC_RXFLR_BITS 0x0000001f -#define I2C_IC_RXFLR_RESET 0x00000000 +#define I2C_IC_RXFLR_OFFSET _u(0x00000078) +#define I2C_IC_RXFLR_BITS _u(0x0000001f) +#define I2C_IC_RXFLR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_RXFLR_RXFLR // Description : Receive FIFO Level. Contains the number of valid data entries // in the receive FIFO. // // Reset value: 0x0 -#define I2C_IC_RXFLR_RXFLR_RESET 0x00 -#define I2C_IC_RXFLR_RXFLR_BITS 0x0000001f -#define I2C_IC_RXFLR_RXFLR_MSB 4 -#define I2C_IC_RXFLR_RXFLR_LSB 0 +#define I2C_IC_RXFLR_RXFLR_RESET _u(0x00) +#define I2C_IC_RXFLR_RXFLR_BITS _u(0x0000001f) +#define I2C_IC_RXFLR_RXFLR_MSB _u(4) +#define I2C_IC_RXFLR_RXFLR_LSB _u(0) #define I2C_IC_RXFLR_RXFLR_ACCESS "RO" // ============================================================================= // Register : I2C_IC_SDA_HOLD @@ -1839,27 +1867,27 @@ // // The values in this register are in units of ic_clk period. The // value programmed in IC_SDA_TX_HOLD must be greater than the -// minimum hold time in each mode one cycle in master mode, seven -// cycles in slave mode for the value to be implemented. +// minimum hold time in each mode (one cycle in master mode, seven +// cycles in slave mode) for the value to be implemented. // // The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) // cannot exceed at any time the duration of the low part of scl. // Therefore the programmed value cannot be larger than // N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of // the scl period measured in ic_clk cycles. -#define I2C_IC_SDA_HOLD_OFFSET 0x0000007c -#define I2C_IC_SDA_HOLD_BITS 0x00ffffff -#define I2C_IC_SDA_HOLD_RESET 0x00000001 +#define I2C_IC_SDA_HOLD_OFFSET _u(0x0000007c) +#define I2C_IC_SDA_HOLD_BITS _u(0x00ffffff) +#define I2C_IC_SDA_HOLD_RESET _u(0x00000001) // ----------------------------------------------------------------------------- // Field : I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD // Description : Sets the required SDA hold time in units of ic_clk period, when // DW_apb_i2c acts as a receiver. // // Reset value: IC_DEFAULT_SDA_HOLD[23:16]. -#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_RESET 0x00 -#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_BITS 0x00ff0000 -#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_MSB 23 -#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_LSB 16 +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_RESET _u(0x00) +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_BITS _u(0x00ff0000) +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_MSB _u(23) +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_LSB _u(16) #define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD @@ -1867,10 +1895,10 @@ // DW_apb_i2c acts as a transmitter. // // Reset value: IC_DEFAULT_SDA_HOLD[15:0]. -#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_RESET 0x0001 -#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_BITS 0x0000ffff -#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_MSB 15 -#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_LSB 0 +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_RESET _u(0x0001) +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_BITS _u(0x0000ffff) +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_MSB _u(15) +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_LSB _u(0) #define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_ACCESS "RW" // ============================================================================= // Register : I2C_IC_TX_ABRT_SOURCE @@ -1889,9 +1917,9 @@ // register. If the source of the ABRT_SBYTE_NORSTRT is not fixed // before attempting to clear this bit, Bit 9 clears for one cycle // and is then re-asserted. -#define I2C_IC_TX_ABRT_SOURCE_OFFSET 0x00000080 -#define I2C_IC_TX_ABRT_SOURCE_BITS 0xff81ffff -#define I2C_IC_TX_ABRT_SOURCE_RESET 0x00000000 +#define I2C_IC_TX_ABRT_SOURCE_OFFSET _u(0x00000080) +#define I2C_IC_TX_ABRT_SOURCE_BITS _u(0xff81ffff) +#define I2C_IC_TX_ABRT_SOURCE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT // Description : This field indicates the number of Tx FIFO Data Commands which @@ -1901,10 +1929,10 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter -#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_RESET 0x000 -#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_BITS 0xff800000 -#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_MSB 31 -#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_LSB 23 +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_RESET _u(0x000) +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_BITS _u(0xff800000) +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_MSB _u(31) +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_LSB _u(23) #define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT @@ -1916,13 +1944,13 @@ // Role of DW_apb_i2c: Master-Transmitter // 0x0 -> Transfer abort detected by master- scenario not present // 0x1 -> Transfer abort detected by master -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_BITS 0x00010000 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_MSB 16 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_LSB 16 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_BITS _u(0x00010000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_MSB _u(16) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_LSB _u(16) #define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX // Description : 1: When the processor side responds to a slave mode request for @@ -1935,13 +1963,13 @@ // 0x0 -> Slave trying to transmit to remote master in read mode- // scenario not present // 0x1 -> Slave trying to transmit to remote master in read mode -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS 0x00008000 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MSB 15 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_LSB 15 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS _u(0x00008000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MSB _u(15) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_LSB _u(15) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST // Description : This field indicates that a Slave has lost the bus while @@ -1959,13 +1987,13 @@ // 0x0 -> Slave lost arbitration to remote master- scenario not // present // 0x1 -> Slave lost arbitration to remote master -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_BITS 0x00004000 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MSB 14 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_LSB 14 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_BITS _u(0x00004000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MSB _u(14) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_LSB _u(14) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO // Description : This field specifies that the Slave has received a read command @@ -1979,13 +2007,13 @@ // command- scenario not present // 0x1 -> Slave flushes existing data in TX-FIFO upon getting read // command -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS 0x00002000 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB 13 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_LSB 13 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS _u(0x00002000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB _u(13) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_LSB _u(13) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ARB_LOST // Description : This field specifies that the Master has lost arbitration, or @@ -1998,13 +2026,13 @@ // 0x0 -> Master or Slave-Transmitter lost arbitration- scenario // not present // 0x1 -> Master or Slave-Transmitter lost arbitration -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS 0x00001000 -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MSB 12 -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_LSB 12 +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS _u(0x00001000) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MSB _u(12) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_LSB _u(12) #define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS // Description : This field indicates that the User tries to initiate a Master @@ -2016,13 +2044,13 @@ // 0x0 -> User initiating master operation when MASTER disabled- // scenario not present // 0x1 -> User initiating master operation when MASTER disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS 0x00000800 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MSB 11 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_LSB 11 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS _u(0x00000800) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MSB _u(11) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_LSB _u(11) #define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT // Description : This field indicates that the restart is disabled @@ -2036,13 +2064,13 @@ // RESTART disabled // 0x1 -> Master trying to read in 10Bit addressing mode when // RESTART disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS 0x00000400 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB 10 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_LSB 10 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS _u(0x00000400) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB _u(10) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_LSB _u(10) #define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT // Description : To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be @@ -2063,13 +2091,13 @@ // 0x0 -> User trying to send START byte when RESTART disabled- // scenario not present // 0x1 -> User trying to send START byte when RESTART disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS 0x00000200 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MSB 9 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_LSB 9 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS _u(0x00000200) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MSB _u(9) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_LSB _u(9) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT // Description : This field indicates that the restart is disabled @@ -2083,13 +2111,13 @@ // disabled- scenario not present // 0x1 -> User trying to switch Master to HS mode when RESTART // disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS 0x00000100 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MSB 8 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_LSB 8 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS _u(0x00000100) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MSB _u(8) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_LSB _u(8) #define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET // Description : This field indicates that the Master has sent a START Byte and @@ -2100,13 +2128,13 @@ // Role of DW_apb_i2c: Master // 0x0 -> ACK detected for START byte- scenario not present // 0x1 -> ACK detected for START byte -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_BITS 0x00000080 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MSB 7 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_LSB 7 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_BITS _u(0x00000080) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MSB _u(7) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_LSB _u(7) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET // Description : This field indicates that the Master is in High Speed mode and @@ -2117,13 +2145,13 @@ // Role of DW_apb_i2c: Master // 0x0 -> HS Master code ACKed in HS Mode- scenario not present // 0x1 -> HS Master code ACKed in HS Mode -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_BITS 0x00000040 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MSB 6 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_LSB 6 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_BITS _u(0x00000040) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MSB _u(6) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_LSB _u(6) #define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ // Description : This field indicates that DW_apb_i2c in the master mode has @@ -2136,13 +2164,13 @@ // Role of DW_apb_i2c: Master-Transmitter // 0x0 -> GCALL is followed by read from bus-scenario not present // 0x1 -> GCALL is followed by read from bus -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_BITS 0x00000020 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MSB 5 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_LSB 5 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_BITS _u(0x00000020) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MSB _u(5) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_LSB _u(5) #define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK // Description : This field indicates that DW_apb_i2c in master mode has sent a @@ -2154,13 +2182,13 @@ // Role of DW_apb_i2c: Master-Transmitter // 0x0 -> GCALL not ACKed by any slave-scenario not present // 0x1 -> GCALL not ACKed by any slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_BITS 0x00000010 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MSB 4 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_LSB 4 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_BITS _u(0x00000010) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MSB _u(4) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_LSB _u(4) #define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK // Description : This field indicates the master-mode only bit. When the master @@ -2174,13 +2202,13 @@ // 0x0 -> Transmitted data non-ACKed by addressed slave-scenario // not present // 0x1 -> Transmitted data not ACKed by addressed slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS 0x00000008 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MSB 3 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_LSB 3 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS _u(0x00000008) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MSB _u(3) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_LSB _u(3) #define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_VOID 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_GENERATED 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK // Description : This field indicates that the Master is in 10-bit address mode @@ -2192,13 +2220,13 @@ // Role of DW_apb_i2c: Master-Transmitter or Master-Receiver // 0x0 -> This abort is not generated // 0x1 -> Byte 2 of 10Bit Address not ACKed by any slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS 0x00000004 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MSB 2 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_LSB 2 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS _u(0x00000004) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MSB _u(2) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_LSB _u(2) #define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_INACTIVE 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_ACTIVE 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_INACTIVE _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK // Description : This field indicates that the Master is in 10-bit address mode @@ -2210,13 +2238,13 @@ // Role of DW_apb_i2c: Master-Transmitter or Master-Receiver // 0x0 -> This abort is not generated // 0x1 -> Byte 1 of 10Bit Address not ACKed by any slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS 0x00000002 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MSB 1 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_LSB 1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS _u(0x00000002) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MSB _u(1) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_LSB _u(1) #define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_INACTIVE 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_ACTIVE 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_INACTIVE _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK // Description : This field indicates that the Master is in 7-bit addressing @@ -2228,13 +2256,13 @@ // 0x0 -> This abort is not generated // 0x1 -> This abort is generated because of NOACK for 7-bit // address -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_RESET 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS 0x00000001 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MSB 0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_LSB 0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS _u(0x00000001) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MSB _u(0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_LSB _u(0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_INACTIVE 0x0 -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_ACTIVE 0x1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_INACTIVE _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_ACTIVE _u(0x1) // ============================================================================= // Register : I2C_IC_SLV_DATA_NACK_ONLY // Description : Generate Slave Data NACK Register @@ -2251,9 +2279,9 @@ // IC_STATUS[6] is a register read-back location for the internal // slv_activity signal; the user should poll this before writing // the ic_slv_data_nack_only bit. -#define I2C_IC_SLV_DATA_NACK_ONLY_OFFSET 0x00000084 -#define I2C_IC_SLV_DATA_NACK_ONLY_BITS 0x00000001 -#define I2C_IC_SLV_DATA_NACK_ONLY_RESET 0x00000000 +#define I2C_IC_SLV_DATA_NACK_ONLY_OFFSET _u(0x00000084) +#define I2C_IC_SLV_DATA_NACK_ONLY_BITS _u(0x00000001) +#define I2C_IC_SLV_DATA_NACK_ONLY_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_SLV_DATA_NACK_ONLY_NACK // Description : Generate NACK. This NACK generation only occurs when DW_apb_i2c @@ -2268,13 +2296,13 @@ // value: 0x0 // 0x0 -> Slave receiver generates NACK normally // 0x1 -> Slave receiver generates NACK upon data reception only -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_RESET 0x0 -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_BITS 0x00000001 -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_MSB 0 -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_LSB 0 +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_RESET _u(0x0) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_BITS _u(0x00000001) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_MSB _u(0) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_LSB _u(0) #define I2C_IC_SLV_DATA_NACK_ONLY_NACK_ACCESS "RW" -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_DISABLED 0x0 -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_ENABLED 0x1 +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_DISABLED _u(0x0) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_DMA_CR // Description : DMA Control Register @@ -2282,41 +2310,41 @@ // The register is used to enable the DMA Controller interface // operation. There is a separate bit for transmit and receive. // This can be programmed regardless of the state of IC_ENABLE. -#define I2C_IC_DMA_CR_OFFSET 0x00000088 -#define I2C_IC_DMA_CR_BITS 0x00000003 -#define I2C_IC_DMA_CR_RESET 0x00000000 +#define I2C_IC_DMA_CR_OFFSET _u(0x00000088) +#define I2C_IC_DMA_CR_BITS _u(0x00000003) +#define I2C_IC_DMA_CR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_DMA_CR_TDMAE // Description : Transmit DMA Enable. This bit enables/disables the transmit // FIFO DMA channel. Reset value: 0x0 // 0x0 -> transmit FIFO DMA channel disabled // 0x1 -> Transmit FIFO DMA channel enabled -#define I2C_IC_DMA_CR_TDMAE_RESET 0x0 -#define I2C_IC_DMA_CR_TDMAE_BITS 0x00000002 -#define I2C_IC_DMA_CR_TDMAE_MSB 1 -#define I2C_IC_DMA_CR_TDMAE_LSB 1 +#define I2C_IC_DMA_CR_TDMAE_RESET _u(0x0) +#define I2C_IC_DMA_CR_TDMAE_BITS _u(0x00000002) +#define I2C_IC_DMA_CR_TDMAE_MSB _u(1) +#define I2C_IC_DMA_CR_TDMAE_LSB _u(1) #define I2C_IC_DMA_CR_TDMAE_ACCESS "RW" -#define I2C_IC_DMA_CR_TDMAE_VALUE_DISABLED 0x0 -#define I2C_IC_DMA_CR_TDMAE_VALUE_ENABLED 0x1 +#define I2C_IC_DMA_CR_TDMAE_VALUE_DISABLED _u(0x0) +#define I2C_IC_DMA_CR_TDMAE_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_DMA_CR_RDMAE // Description : Receive DMA Enable. This bit enables/disables the receive FIFO // DMA channel. Reset value: 0x0 // 0x0 -> Receive FIFO DMA channel disabled // 0x1 -> Receive FIFO DMA channel enabled -#define I2C_IC_DMA_CR_RDMAE_RESET 0x0 -#define I2C_IC_DMA_CR_RDMAE_BITS 0x00000001 -#define I2C_IC_DMA_CR_RDMAE_MSB 0 -#define I2C_IC_DMA_CR_RDMAE_LSB 0 +#define I2C_IC_DMA_CR_RDMAE_RESET _u(0x0) +#define I2C_IC_DMA_CR_RDMAE_BITS _u(0x00000001) +#define I2C_IC_DMA_CR_RDMAE_MSB _u(0) +#define I2C_IC_DMA_CR_RDMAE_LSB _u(0) #define I2C_IC_DMA_CR_RDMAE_ACCESS "RW" -#define I2C_IC_DMA_CR_RDMAE_VALUE_DISABLED 0x0 -#define I2C_IC_DMA_CR_RDMAE_VALUE_ENABLED 0x1 +#define I2C_IC_DMA_CR_RDMAE_VALUE_DISABLED _u(0x0) +#define I2C_IC_DMA_CR_RDMAE_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_DMA_TDLR // Description : DMA Transmit Data Level Register -#define I2C_IC_DMA_TDLR_OFFSET 0x0000008c -#define I2C_IC_DMA_TDLR_BITS 0x0000000f -#define I2C_IC_DMA_TDLR_RESET 0x00000000 +#define I2C_IC_DMA_TDLR_OFFSET _u(0x0000008c) +#define I2C_IC_DMA_TDLR_BITS _u(0x0000000f) +#define I2C_IC_DMA_TDLR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_DMA_TDLR_DMATDL // Description : Transmit Data Level. This bit field controls the level at which @@ -2326,17 +2354,17 @@ // equal to or below this field value, and TDMAE = 1. // // Reset value: 0x0 -#define I2C_IC_DMA_TDLR_DMATDL_RESET 0x0 -#define I2C_IC_DMA_TDLR_DMATDL_BITS 0x0000000f -#define I2C_IC_DMA_TDLR_DMATDL_MSB 3 -#define I2C_IC_DMA_TDLR_DMATDL_LSB 0 +#define I2C_IC_DMA_TDLR_DMATDL_RESET _u(0x0) +#define I2C_IC_DMA_TDLR_DMATDL_BITS _u(0x0000000f) +#define I2C_IC_DMA_TDLR_DMATDL_MSB _u(3) +#define I2C_IC_DMA_TDLR_DMATDL_LSB _u(0) #define I2C_IC_DMA_TDLR_DMATDL_ACCESS "RW" // ============================================================================= // Register : I2C_IC_DMA_RDLR // Description : I2C Receive Data Level Register -#define I2C_IC_DMA_RDLR_OFFSET 0x00000090 -#define I2C_IC_DMA_RDLR_BITS 0x0000000f -#define I2C_IC_DMA_RDLR_RESET 0x00000000 +#define I2C_IC_DMA_RDLR_OFFSET _u(0x00000090) +#define I2C_IC_DMA_RDLR_BITS _u(0x0000000f) +#define I2C_IC_DMA_RDLR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_DMA_RDLR_DMARDL // Description : Receive Data Level. This bit field controls the level at which @@ -2348,10 +2376,10 @@ // are present in the receive FIFO. // // Reset value: 0x0 -#define I2C_IC_DMA_RDLR_DMARDL_RESET 0x0 -#define I2C_IC_DMA_RDLR_DMARDL_BITS 0x0000000f -#define I2C_IC_DMA_RDLR_DMARDL_MSB 3 -#define I2C_IC_DMA_RDLR_DMARDL_LSB 0 +#define I2C_IC_DMA_RDLR_DMARDL_RESET _u(0x0) +#define I2C_IC_DMA_RDLR_DMARDL_BITS _u(0x0000000f) +#define I2C_IC_DMA_RDLR_DMARDL_MSB _u(3) +#define I2C_IC_DMA_RDLR_DMARDL_LSB _u(0) #define I2C_IC_DMA_RDLR_DMARDL_ACCESS "RW" // ============================================================================= // Register : I2C_IC_SDA_SETUP @@ -2372,19 +2400,19 @@ // 10 ic_clk periods of setup time, they should program a value of // 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c // when operating as a slave transmitter. -#define I2C_IC_SDA_SETUP_OFFSET 0x00000094 -#define I2C_IC_SDA_SETUP_BITS 0x000000ff -#define I2C_IC_SDA_SETUP_RESET 0x00000064 +#define I2C_IC_SDA_SETUP_OFFSET _u(0x00000094) +#define I2C_IC_SDA_SETUP_BITS _u(0x000000ff) +#define I2C_IC_SDA_SETUP_RESET _u(0x00000064) // ----------------------------------------------------------------------------- // Field : I2C_IC_SDA_SETUP_SDA_SETUP // Description : SDA Setup. It is recommended that if the required delay is // 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP // should be programmed to a value of 11. IC_SDA_SETUP must be // programmed with a minimum value of 2. -#define I2C_IC_SDA_SETUP_SDA_SETUP_RESET 0x64 -#define I2C_IC_SDA_SETUP_SDA_SETUP_BITS 0x000000ff -#define I2C_IC_SDA_SETUP_SDA_SETUP_MSB 7 -#define I2C_IC_SDA_SETUP_SDA_SETUP_LSB 0 +#define I2C_IC_SDA_SETUP_SDA_SETUP_RESET _u(0x64) +#define I2C_IC_SDA_SETUP_SDA_SETUP_BITS _u(0x000000ff) +#define I2C_IC_SDA_SETUP_SDA_SETUP_MSB _u(7) +#define I2C_IC_SDA_SETUP_SDA_SETUP_LSB _u(0) #define I2C_IC_SDA_SETUP_SDA_SETUP_ACCESS "RW" // ============================================================================= // Register : I2C_IC_ACK_GENERAL_CALL @@ -2395,9 +2423,9 @@ // // This register is applicable only when the DW_apb_i2c is in // slave mode. -#define I2C_IC_ACK_GENERAL_CALL_OFFSET 0x00000098 -#define I2C_IC_ACK_GENERAL_CALL_BITS 0x00000001 -#define I2C_IC_ACK_GENERAL_CALL_RESET 0x00000001 +#define I2C_IC_ACK_GENERAL_CALL_OFFSET _u(0x00000098) +#define I2C_IC_ACK_GENERAL_CALL_BITS _u(0x00000001) +#define I2C_IC_ACK_GENERAL_CALL_RESET _u(0x00000001) // ----------------------------------------------------------------------------- // Field : I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL // Description : ACK General Call. When set to 1, DW_apb_i2c responds with a ACK @@ -2406,13 +2434,13 @@ // ic_data_oe). // 0x0 -> Generate NACK for a General Call // 0x1 -> Generate ACK for a General Call -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET 0x1 -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_BITS 0x00000001 -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB 0 -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB 0 +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET _u(0x1) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_BITS _u(0x00000001) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB _u(0) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB _u(0) #define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_ACCESS "RW" -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_DISABLED 0x0 -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_ENABLED 0x1 +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_DISABLED _u(0x0) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_ENABLE_STATUS // Description : I2C Enable Status Register @@ -2430,9 +2458,9 @@ // Note: When IC_ENABLE[0] has been set to 0, a delay occurs for // bit 0 to be read as 0 because disabling the DW_apb_i2c depends // on I2C bus activities. -#define I2C_IC_ENABLE_STATUS_OFFSET 0x0000009c -#define I2C_IC_ENABLE_STATUS_BITS 0x00000007 -#define I2C_IC_ENABLE_STATUS_RESET 0x00000000 +#define I2C_IC_ENABLE_STATUS_OFFSET _u(0x0000009c) +#define I2C_IC_ENABLE_STATUS_BITS _u(0x00000007) +#define I2C_IC_ENABLE_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST // Description : Slave Received Data Lost. This bit indicates if a @@ -2459,13 +2487,13 @@ // Reset value: 0x0 // 0x0 -> Slave RX Data is not lost // 0x1 -> Slave RX Data is lost -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_RESET 0x0 -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_BITS 0x00000004 -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MSB 2 -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_LSB 2 +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_RESET _u(0x0) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_BITS _u(0x00000004) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MSB _u(2) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_LSB _u(2) #define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_ACCESS "RO" -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_INACTIVE 0x0 -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_ACTIVE 0x1 +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_INACTIVE _u(0x0) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY // Description : Slave Disabled While Busy (Transmit, Receive). This bit @@ -2502,13 +2530,13 @@ // Reset value: 0x0 // 0x0 -> Slave is disabled when it is idle // 0x1 -> Slave is disabled when it is active -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_RESET 0x0 -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_BITS 0x00000002 -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MSB 1 -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_LSB 1 +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_RESET _u(0x0) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_BITS _u(0x00000002) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MSB _u(1) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_LSB _u(1) #define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_ACCESS "RO" -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_INACTIVE 0x0 -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_ACTIVE 0x1 +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_ENABLE_STATUS_IC_EN // Description : ic_en Status. This bit always reflects the value driven on the @@ -2521,13 +2549,13 @@ // Reset value: 0x0 // 0x0 -> I2C disabled // 0x1 -> I2C enabled -#define I2C_IC_ENABLE_STATUS_IC_EN_RESET 0x0 -#define I2C_IC_ENABLE_STATUS_IC_EN_BITS 0x00000001 -#define I2C_IC_ENABLE_STATUS_IC_EN_MSB 0 -#define I2C_IC_ENABLE_STATUS_IC_EN_LSB 0 +#define I2C_IC_ENABLE_STATUS_IC_EN_RESET _u(0x0) +#define I2C_IC_ENABLE_STATUS_IC_EN_BITS _u(0x00000001) +#define I2C_IC_ENABLE_STATUS_IC_EN_MSB _u(0) +#define I2C_IC_ENABLE_STATUS_IC_EN_LSB _u(0) #define I2C_IC_ENABLE_STATUS_IC_EN_ACCESS "RO" -#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_DISABLED 0x0 -#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_ENABLED 0x1 +#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_DISABLED _u(0x0) +#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_FS_SPKLEN // Description : I2C SS, FS or FM+ spike suppression limit @@ -2538,9 +2566,9 @@ // FM+ modes. The relevant I2C requirement is tSP (table 4) as // detailed in the I2C Bus Specification. This register must be // programmed with a minimum value of 1. -#define I2C_IC_FS_SPKLEN_OFFSET 0x000000a0 -#define I2C_IC_FS_SPKLEN_BITS 0x000000ff -#define I2C_IC_FS_SPKLEN_RESET 0x00000007 +#define I2C_IC_FS_SPKLEN_OFFSET _u(0x000000a0) +#define I2C_IC_FS_SPKLEN_BITS _u(0x000000ff) +#define I2C_IC_FS_SPKLEN_RESET _u(0x00000007) // ----------------------------------------------------------------------------- // Field : I2C_IC_FS_SPKLEN_IC_FS_SPKLEN // Description : This register must be set before any I2C bus transaction can @@ -2553,27 +2581,27 @@ // The minimum valid value is 1; hardware prevents values less // than this being written, and if attempted results in 1 being // set. or more information, refer to 'Spike Suppression'. -#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_RESET 0x07 -#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_BITS 0x000000ff -#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_MSB 7 -#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_LSB 0 +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_RESET _u(0x07) +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_BITS _u(0x000000ff) +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_MSB _u(7) +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_LSB _u(0) #define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_ACCESS "RW" // ============================================================================= // Register : I2C_IC_CLR_RESTART_DET // Description : Clear RESTART_DET Interrupt Register -#define I2C_IC_CLR_RESTART_DET_OFFSET 0x000000a8 -#define I2C_IC_CLR_RESTART_DET_BITS 0x00000001 -#define I2C_IC_CLR_RESTART_DET_RESET 0x00000000 +#define I2C_IC_CLR_RESTART_DET_OFFSET _u(0x000000a8) +#define I2C_IC_CLR_RESTART_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_RESTART_DET_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET // Description : Read this register to clear the RESTART_DET interrupt (bit 12) // of IC_RAW_INTR_STAT register. // // Reset value: 0x0 -#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_RESET 0x0 -#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_BITS 0x00000001 -#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_MSB 0 -#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_LSB 0 +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_RESET _u(0x0) +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_MSB _u(0) +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_LSB _u(0) #define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_ACCESS "RO" // ============================================================================= // Register : I2C_IC_COMP_PARAM_1 @@ -2584,102 +2612,102 @@ // that contains encoded information about the component's // parameter settings. Fields shown below are the settings for // those parameters -#define I2C_IC_COMP_PARAM_1_OFFSET 0x000000f4 -#define I2C_IC_COMP_PARAM_1_BITS 0x00ffffff -#define I2C_IC_COMP_PARAM_1_RESET 0x00000000 +#define I2C_IC_COMP_PARAM_1_OFFSET _u(0x000000f4) +#define I2C_IC_COMP_PARAM_1_BITS _u(0x00ffffff) +#define I2C_IC_COMP_PARAM_1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH // Description : TX Buffer Depth = 16 -#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_RESET 0x00 -#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_BITS 0x00ff0000 -#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_MSB 23 -#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_LSB 16 +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_RESET _u(0x00) +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_BITS _u(0x00ff0000) +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_MSB _u(23) +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_LSB _u(16) #define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH // Description : RX Buffer Depth = 16 -#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_RESET 0x00 -#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_BITS 0x0000ff00 -#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_MSB 15 -#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_LSB 8 +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_RESET _u(0x00) +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_BITS _u(0x0000ff00) +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_MSB _u(15) +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_LSB _u(8) #define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS // Description : Encoded parameters not visible -#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_RESET 0x0 -#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_BITS 0x00000080 -#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_MSB 7 -#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_LSB 7 +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_BITS _u(0x00000080) +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_MSB _u(7) +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_LSB _u(7) #define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_PARAM_1_HAS_DMA // Description : DMA handshaking signals are enabled -#define I2C_IC_COMP_PARAM_1_HAS_DMA_RESET 0x0 -#define I2C_IC_COMP_PARAM_1_HAS_DMA_BITS 0x00000040 -#define I2C_IC_COMP_PARAM_1_HAS_DMA_MSB 6 -#define I2C_IC_COMP_PARAM_1_HAS_DMA_LSB 6 +#define I2C_IC_COMP_PARAM_1_HAS_DMA_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_HAS_DMA_BITS _u(0x00000040) +#define I2C_IC_COMP_PARAM_1_HAS_DMA_MSB _u(6) +#define I2C_IC_COMP_PARAM_1_HAS_DMA_LSB _u(6) #define I2C_IC_COMP_PARAM_1_HAS_DMA_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_PARAM_1_INTR_IO // Description : COMBINED Interrupt outputs -#define I2C_IC_COMP_PARAM_1_INTR_IO_RESET 0x0 -#define I2C_IC_COMP_PARAM_1_INTR_IO_BITS 0x00000020 -#define I2C_IC_COMP_PARAM_1_INTR_IO_MSB 5 -#define I2C_IC_COMP_PARAM_1_INTR_IO_LSB 5 +#define I2C_IC_COMP_PARAM_1_INTR_IO_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_INTR_IO_BITS _u(0x00000020) +#define I2C_IC_COMP_PARAM_1_INTR_IO_MSB _u(5) +#define I2C_IC_COMP_PARAM_1_INTR_IO_LSB _u(5) #define I2C_IC_COMP_PARAM_1_INTR_IO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES // Description : Programmable count values for each mode. -#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_RESET 0x0 -#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_BITS 0x00000010 -#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_MSB 4 -#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_LSB 4 +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_BITS _u(0x00000010) +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_MSB _u(4) +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_LSB _u(4) #define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE // Description : MAX SPEED MODE = FAST MODE -#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_RESET 0x0 -#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_BITS 0x0000000c -#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_MSB 3 -#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_LSB 2 +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_BITS _u(0x0000000c) +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_MSB _u(3) +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_LSB _u(2) #define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH // Description : APB data bus width is 32 bits -#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_RESET 0x0 -#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_BITS 0x00000003 -#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_MSB 1 -#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_LSB 0 +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_BITS _u(0x00000003) +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_MSB _u(1) +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_LSB _u(0) #define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_ACCESS "RO" // ============================================================================= // Register : I2C_IC_COMP_VERSION // Description : I2C Component Version Register -#define I2C_IC_COMP_VERSION_OFFSET 0x000000f8 -#define I2C_IC_COMP_VERSION_BITS 0xffffffff -#define I2C_IC_COMP_VERSION_RESET 0x3230312a +#define I2C_IC_COMP_VERSION_OFFSET _u(0x000000f8) +#define I2C_IC_COMP_VERSION_BITS _u(0xffffffff) +#define I2C_IC_COMP_VERSION_RESET _u(0x3230312a) // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_VERSION_IC_COMP_VERSION // Description : None -#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_RESET 0x3230312a -#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_BITS 0xffffffff -#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_MSB 31 -#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_LSB 0 +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_RESET _u(0x3230312a) +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_BITS _u(0xffffffff) +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_MSB _u(31) +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_LSB _u(0) #define I2C_IC_COMP_VERSION_IC_COMP_VERSION_ACCESS "RO" // ============================================================================= // Register : I2C_IC_COMP_TYPE // Description : I2C Component Type Register -#define I2C_IC_COMP_TYPE_OFFSET 0x000000fc -#define I2C_IC_COMP_TYPE_BITS 0xffffffff -#define I2C_IC_COMP_TYPE_RESET 0x44570140 +#define I2C_IC_COMP_TYPE_OFFSET _u(0x000000fc) +#define I2C_IC_COMP_TYPE_BITS _u(0xffffffff) +#define I2C_IC_COMP_TYPE_RESET _u(0x44570140) // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_TYPE_IC_COMP_TYPE // Description : Designware Component Type number = 0x44_57_01_40. This assigned // unique hex value is constant and is derived from the two ASCII // letters 'DW' followed by a 16-bit unsigned number. -#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_RESET 0x44570140 -#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_BITS 0xffffffff -#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_MSB 31 -#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_LSB 0 +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_RESET _u(0x44570140) +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_BITS _u(0xffffffff) +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_MSB _u(31) +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_LSB _u(0) #define I2C_IC_COMP_TYPE_IC_COMP_TYPE_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_I2C_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_bank0.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_bank0.h index f7b15610c..26f139e36 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_bank0.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_bank0.h @@ -14,111 +14,111 @@ // ============================================================================= // Register : IO_BANK0_GPIO0_STATUS // Description : GPIO status -#define IO_BANK0_GPIO0_STATUS_OFFSET 0x00000000 -#define IO_BANK0_GPIO0_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO0_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO0_STATUS_OFFSET _u(0x00000000) +#define IO_BANK0_GPIO0_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO0_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO0_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO0_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO0_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO0_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO0_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO0_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO0_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO0_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO0_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO0_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO0_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO0_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO0_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO0_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO0_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO0_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO0_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO0_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO0_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO0_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO0_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO0_CTRL_OFFSET 0x00000004 -#define IO_BANK0_GPIO0_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO0_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO0_CTRL_OFFSET _u(0x00000004) +#define IO_BANK0_GPIO0_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO0_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO0_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO0_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO0_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO0_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO0_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO0_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO0_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO0_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO0_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -127,15 +127,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO0_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO0_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO0_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO0_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO0_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO0_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO0_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO0_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -143,15 +143,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO0_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -166,129 +166,129 @@ // 0x07 -> pio1_0 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO0_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK 0x00 -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX 0x01 -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX 0x02 -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 0x04 -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIO_0 0x05 -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 0x06 -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 0x07 -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK _u(0x00) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIO_0 _u(0x05) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 _u(0x06) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 _u(0x07) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO1_STATUS // Description : GPIO status -#define IO_BANK0_GPIO1_STATUS_OFFSET 0x00000008 -#define IO_BANK0_GPIO1_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO1_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO1_STATUS_OFFSET _u(0x00000008) +#define IO_BANK0_GPIO1_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO1_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO1_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO1_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO1_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO1_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO1_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO1_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO1_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO1_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO1_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO1_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO1_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO1_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO1_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO1_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO1_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO1_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO1_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO1_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO1_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO1_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO1_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO1_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO1_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO1_CTRL_OFFSET 0x0000000c -#define IO_BANK0_GPIO1_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO1_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO1_CTRL_OFFSET _u(0x0000000c) +#define IO_BANK0_GPIO1_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO1_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO1_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO1_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO1_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO1_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO1_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO1_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO1_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO1_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO1_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -297,15 +297,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO1_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO1_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO1_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO1_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO1_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO1_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO1_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO1_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -313,15 +313,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO1_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -336,129 +336,129 @@ // 0x07 -> pio1_1 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO1_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS 0x00 -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N 0x01 -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX 0x02 -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 0x04 -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIO_1 0x05 -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 0x06 -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 0x07 -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS _u(0x00) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIO_1 _u(0x05) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 _u(0x06) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 _u(0x07) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO2_STATUS // Description : GPIO status -#define IO_BANK0_GPIO2_STATUS_OFFSET 0x00000010 -#define IO_BANK0_GPIO2_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO2_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO2_STATUS_OFFSET _u(0x00000010) +#define IO_BANK0_GPIO2_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO2_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO2_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO2_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO2_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO2_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO2_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO2_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO2_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO2_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO2_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO2_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO2_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO2_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO2_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO2_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO2_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO2_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO2_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO2_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO2_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO2_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO2_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO2_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO2_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO2_CTRL_OFFSET 0x00000014 -#define IO_BANK0_GPIO2_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO2_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO2_CTRL_OFFSET _u(0x00000014) +#define IO_BANK0_GPIO2_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO2_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO2_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO2_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO2_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO2_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO2_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO2_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO2_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO2_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO2_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -467,15 +467,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO2_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO2_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO2_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO2_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO2_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO2_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO2_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO2_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -483,15 +483,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO2_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -506,129 +506,129 @@ // 0x07 -> pio1_2 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO2_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI 0x00 -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK 0x01 -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS 0x02 -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 0x04 -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIO_2 0x05 -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 0x06 -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 0x07 -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI _u(0x00) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIO_2 _u(0x05) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 _u(0x06) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 _u(0x07) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO3_STATUS // Description : GPIO status -#define IO_BANK0_GPIO3_STATUS_OFFSET 0x00000018 -#define IO_BANK0_GPIO3_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO3_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO3_STATUS_OFFSET _u(0x00000018) +#define IO_BANK0_GPIO3_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO3_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO3_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO3_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO3_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO3_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO3_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO3_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO3_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO3_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO3_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO3_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO3_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO3_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO3_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO3_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO3_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO3_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO3_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO3_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO3_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO3_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO3_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO3_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO3_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO3_CTRL_OFFSET 0x0000001c -#define IO_BANK0_GPIO3_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO3_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO3_CTRL_OFFSET _u(0x0000001c) +#define IO_BANK0_GPIO3_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO3_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO3_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO3_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO3_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO3_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO3_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO3_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO3_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO3_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO3_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -637,15 +637,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO3_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO3_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO3_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO3_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO3_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO3_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO3_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO3_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -653,15 +653,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO3_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -676,129 +676,129 @@ // 0x07 -> pio1_3 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO3_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO 0x00 -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX 0x01 -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS 0x02 -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 0x04 -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIO_3 0x05 -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 0x06 -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 0x07 -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO _u(0x00) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIO_3 _u(0x05) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 _u(0x06) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 _u(0x07) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO4_STATUS // Description : GPIO status -#define IO_BANK0_GPIO4_STATUS_OFFSET 0x00000020 -#define IO_BANK0_GPIO4_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO4_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO4_STATUS_OFFSET _u(0x00000020) +#define IO_BANK0_GPIO4_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO4_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO4_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO4_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO4_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO4_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO4_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO4_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO4_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO4_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO4_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO4_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO4_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO4_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO4_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO4_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO4_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO4_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO4_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO4_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO4_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO4_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO4_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO4_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO4_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO4_CTRL_OFFSET 0x00000024 -#define IO_BANK0_GPIO4_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO4_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO4_CTRL_OFFSET _u(0x00000024) +#define IO_BANK0_GPIO4_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO4_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO4_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO4_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO4_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO4_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO4_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO4_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO4_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO4_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO4_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -807,15 +807,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO4_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO4_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO4_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO4_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO4_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO4_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO4_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO4_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -823,15 +823,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO4_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -845,128 +845,128 @@ // 0x07 -> pio1_4 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO4_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX 0x01 -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX 0x02 -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 0x04 -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIO_4 0x05 -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 0x06 -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 0x07 -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIO_4 _u(0x05) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 _u(0x06) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 _u(0x07) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO5_STATUS // Description : GPIO status -#define IO_BANK0_GPIO5_STATUS_OFFSET 0x00000028 -#define IO_BANK0_GPIO5_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO5_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO5_STATUS_OFFSET _u(0x00000028) +#define IO_BANK0_GPIO5_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO5_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO5_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO5_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO5_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO5_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO5_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO5_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO5_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO5_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO5_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO5_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO5_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO5_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO5_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO5_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO5_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO5_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO5_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO5_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO5_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO5_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO5_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO5_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO5_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO5_CTRL_OFFSET 0x0000002c -#define IO_BANK0_GPIO5_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO5_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO5_CTRL_OFFSET _u(0x0000002c) +#define IO_BANK0_GPIO5_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO5_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO5_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO5_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO5_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO5_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO5_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO5_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO5_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO5_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO5_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -975,15 +975,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO5_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO5_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO5_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO5_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO5_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO5_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO5_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO5_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -991,15 +991,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO5_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1013,128 +1013,128 @@ // 0x07 -> pio1_5 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO5_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N 0x01 -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX 0x02 -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 0x04 -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIO_5 0x05 -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 0x06 -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 0x07 -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIO_5 _u(0x05) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 _u(0x06) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 _u(0x07) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO6_STATUS // Description : GPIO status -#define IO_BANK0_GPIO6_STATUS_OFFSET 0x00000030 -#define IO_BANK0_GPIO6_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO6_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO6_STATUS_OFFSET _u(0x00000030) +#define IO_BANK0_GPIO6_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO6_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO6_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO6_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO6_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO6_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO6_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO6_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO6_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO6_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO6_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO6_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO6_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO6_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO6_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO6_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO6_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO6_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO6_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO6_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO6_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO6_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO6_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO6_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO6_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO6_CTRL_OFFSET 0x00000034 -#define IO_BANK0_GPIO6_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO6_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO6_CTRL_OFFSET _u(0x00000034) +#define IO_BANK0_GPIO6_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO6_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO6_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO6_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO6_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO6_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO6_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO6_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO6_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO6_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO6_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -1143,15 +1143,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO6_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO6_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO6_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO6_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO6_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO6_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO6_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO6_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -1159,15 +1159,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO6_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1182,129 +1182,129 @@ // 0x08 -> usb_muxing_extphy_softcon // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO6_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK 0x01 -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS 0x02 -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 0x04 -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIO_6 0x05 -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 0x06 -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 0x07 -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SOFTCON 0x08 -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIO_6 _u(0x05) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 _u(0x06) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 _u(0x07) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SOFTCON _u(0x08) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO7_STATUS // Description : GPIO status -#define IO_BANK0_GPIO7_STATUS_OFFSET 0x00000038 -#define IO_BANK0_GPIO7_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO7_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO7_STATUS_OFFSET _u(0x00000038) +#define IO_BANK0_GPIO7_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO7_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO7_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO7_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO7_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO7_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO7_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO7_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO7_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO7_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO7_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO7_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO7_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO7_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO7_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO7_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO7_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO7_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO7_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO7_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO7_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO7_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO7_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO7_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO7_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO7_CTRL_OFFSET 0x0000003c -#define IO_BANK0_GPIO7_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO7_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO7_CTRL_OFFSET _u(0x0000003c) +#define IO_BANK0_GPIO7_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO7_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO7_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO7_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO7_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO7_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO7_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO7_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO7_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO7_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO7_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -1313,15 +1313,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO7_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO7_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO7_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO7_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO7_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO7_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO7_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO7_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -1329,15 +1329,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO7_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1352,129 +1352,129 @@ // 0x08 -> usb_muxing_extphy_oe_n // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO7_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX 0x01 -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS 0x02 -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 0x04 -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIO_7 0x05 -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 0x06 -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 0x07 -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_OE_N 0x08 -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIO_7 _u(0x05) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 _u(0x06) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 _u(0x07) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_OE_N _u(0x08) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO8_STATUS // Description : GPIO status -#define IO_BANK0_GPIO8_STATUS_OFFSET 0x00000040 -#define IO_BANK0_GPIO8_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO8_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO8_STATUS_OFFSET _u(0x00000040) +#define IO_BANK0_GPIO8_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO8_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO8_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO8_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO8_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO8_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO8_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO8_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO8_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO8_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO8_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO8_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO8_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO8_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO8_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO8_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO8_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO8_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO8_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO8_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO8_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO8_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO8_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO8_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO8_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO8_CTRL_OFFSET 0x00000044 -#define IO_BANK0_GPIO8_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO8_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO8_CTRL_OFFSET _u(0x00000044) +#define IO_BANK0_GPIO8_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO8_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO8_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO8_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO8_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO8_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO8_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO8_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO8_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO8_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO8_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -1483,15 +1483,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO8_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO8_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO8_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO8_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO8_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO8_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO8_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO8_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -1499,15 +1499,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO8_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1522,129 +1522,129 @@ // 0x08 -> usb_muxing_extphy_rcv // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO8_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX 0x01 -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX 0x02 -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 0x04 -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIO_8 0x05 -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 0x06 -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 0x07 -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_RCV 0x08 -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIO_8 _u(0x05) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 _u(0x06) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 _u(0x07) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_RCV _u(0x08) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO9_STATUS // Description : GPIO status -#define IO_BANK0_GPIO9_STATUS_OFFSET 0x00000048 -#define IO_BANK0_GPIO9_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO9_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO9_STATUS_OFFSET _u(0x00000048) +#define IO_BANK0_GPIO9_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO9_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO9_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO9_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO9_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO9_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO9_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO9_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO9_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO9_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO9_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO9_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO9_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO9_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO9_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO9_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO9_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO9_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO9_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO9_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO9_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO9_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO9_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO9_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO9_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO9_CTRL_OFFSET 0x0000004c -#define IO_BANK0_GPIO9_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO9_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO9_CTRL_OFFSET _u(0x0000004c) +#define IO_BANK0_GPIO9_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO9_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO9_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO9_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO9_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO9_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO9_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO9_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO9_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO9_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO9_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -1653,15 +1653,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO9_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO9_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO9_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO9_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO9_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO9_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO9_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO9_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -1669,15 +1669,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO9_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1692,129 +1692,129 @@ // 0x08 -> usb_muxing_extphy_vp // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO9_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N 0x01 -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX 0x02 -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 0x04 -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIO_9 0x05 -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 0x06 -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 0x07 -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VP 0x08 -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIO_9 _u(0x05) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 _u(0x06) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 _u(0x07) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VP _u(0x08) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO10_STATUS // Description : GPIO status -#define IO_BANK0_GPIO10_STATUS_OFFSET 0x00000050 -#define IO_BANK0_GPIO10_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO10_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO10_STATUS_OFFSET _u(0x00000050) +#define IO_BANK0_GPIO10_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO10_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO10_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO10_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO10_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO10_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO10_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO10_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO10_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO10_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO10_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO10_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO10_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO10_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO10_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO10_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO10_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO10_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO10_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO10_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO10_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO10_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO10_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO10_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO10_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO10_CTRL_OFFSET 0x00000054 -#define IO_BANK0_GPIO10_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO10_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO10_CTRL_OFFSET _u(0x00000054) +#define IO_BANK0_GPIO10_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO10_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO10_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO10_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO10_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO10_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO10_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO10_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO10_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO10_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO10_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -1823,15 +1823,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO10_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO10_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO10_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO10_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO10_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO10_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO10_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO10_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -1839,15 +1839,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO10_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1862,129 +1862,129 @@ // 0x08 -> usb_muxing_extphy_vm // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO10_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK 0x01 -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS 0x02 -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 0x04 -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIO_10 0x05 -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 0x06 -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 0x07 -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VM 0x08 -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIO_10 _u(0x05) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 _u(0x06) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 _u(0x07) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VM _u(0x08) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO11_STATUS // Description : GPIO status -#define IO_BANK0_GPIO11_STATUS_OFFSET 0x00000058 -#define IO_BANK0_GPIO11_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO11_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO11_STATUS_OFFSET _u(0x00000058) +#define IO_BANK0_GPIO11_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO11_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO11_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO11_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO11_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO11_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO11_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO11_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO11_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO11_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO11_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO11_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO11_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO11_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO11_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO11_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO11_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO11_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO11_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO11_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO11_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO11_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO11_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO11_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO11_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO11_CTRL_OFFSET 0x0000005c -#define IO_BANK0_GPIO11_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO11_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO11_CTRL_OFFSET _u(0x0000005c) +#define IO_BANK0_GPIO11_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO11_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO11_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO11_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO11_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO11_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO11_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO11_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO11_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO11_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO11_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -1993,15 +1993,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO11_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO11_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO11_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO11_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO11_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO11_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO11_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO11_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -2009,15 +2009,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO11_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2032,129 +2032,129 @@ // 0x08 -> usb_muxing_extphy_suspnd // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO11_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX 0x01 -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS 0x02 -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 0x04 -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIO_11 0x05 -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 0x06 -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 0x07 -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SUSPND 0x08 -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIO_11 _u(0x05) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 _u(0x06) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 _u(0x07) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SUSPND _u(0x08) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO12_STATUS // Description : GPIO status -#define IO_BANK0_GPIO12_STATUS_OFFSET 0x00000060 -#define IO_BANK0_GPIO12_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO12_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO12_STATUS_OFFSET _u(0x00000060) +#define IO_BANK0_GPIO12_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO12_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO12_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO12_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO12_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO12_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO12_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO12_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO12_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO12_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO12_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO12_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO12_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO12_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO12_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO12_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO12_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO12_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO12_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO12_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO12_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO12_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO12_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO12_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO12_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO12_CTRL_OFFSET 0x00000064 -#define IO_BANK0_GPIO12_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO12_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO12_CTRL_OFFSET _u(0x00000064) +#define IO_BANK0_GPIO12_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO12_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO12_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO12_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO12_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO12_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO12_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO12_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO12_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO12_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO12_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -2163,15 +2163,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO12_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO12_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO12_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO12_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO12_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO12_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO12_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO12_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -2179,15 +2179,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO12_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2202,129 +2202,129 @@ // 0x08 -> usb_muxing_extphy_speed // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO12_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX 0x01 -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX 0x02 -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 0x04 -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIO_12 0x05 -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 0x06 -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 0x07 -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SPEED 0x08 -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIO_12 _u(0x05) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 _u(0x06) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 _u(0x07) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SPEED _u(0x08) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO13_STATUS // Description : GPIO status -#define IO_BANK0_GPIO13_STATUS_OFFSET 0x00000068 -#define IO_BANK0_GPIO13_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO13_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO13_STATUS_OFFSET _u(0x00000068) +#define IO_BANK0_GPIO13_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO13_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO13_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO13_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO13_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO13_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO13_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO13_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO13_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO13_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO13_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO13_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO13_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO13_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO13_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO13_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO13_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO13_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO13_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO13_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO13_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO13_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO13_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO13_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO13_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO13_CTRL_OFFSET 0x0000006c -#define IO_BANK0_GPIO13_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO13_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO13_CTRL_OFFSET _u(0x0000006c) +#define IO_BANK0_GPIO13_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO13_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO13_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO13_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO13_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO13_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO13_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO13_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO13_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO13_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO13_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -2333,15 +2333,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO13_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO13_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO13_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO13_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO13_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO13_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO13_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO13_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -2349,15 +2349,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO13_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2372,129 +2372,129 @@ // 0x08 -> usb_muxing_extphy_vpo // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO13_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N 0x01 -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX 0x02 -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 0x04 -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIO_13 0x05 -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 0x06 -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 0x07 -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VPO 0x08 -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIO_13 _u(0x05) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 _u(0x06) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 _u(0x07) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VPO _u(0x08) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO14_STATUS // Description : GPIO status -#define IO_BANK0_GPIO14_STATUS_OFFSET 0x00000070 -#define IO_BANK0_GPIO14_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO14_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO14_STATUS_OFFSET _u(0x00000070) +#define IO_BANK0_GPIO14_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO14_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO14_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO14_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO14_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO14_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO14_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO14_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO14_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO14_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO14_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO14_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO14_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO14_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO14_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO14_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO14_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO14_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO14_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO14_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO14_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO14_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO14_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO14_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO14_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO14_CTRL_OFFSET 0x00000074 -#define IO_BANK0_GPIO14_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO14_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO14_CTRL_OFFSET _u(0x00000074) +#define IO_BANK0_GPIO14_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO14_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO14_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO14_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO14_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO14_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO14_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO14_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO14_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO14_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO14_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -2503,15 +2503,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO14_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO14_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO14_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO14_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO14_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO14_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO14_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO14_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -2519,15 +2519,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO14_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2542,129 +2542,129 @@ // 0x08 -> usb_muxing_extphy_vmo // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO14_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK 0x01 -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS 0x02 -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 0x04 -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIO_14 0x05 -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 0x06 -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 0x07 -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VMO 0x08 -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 _u(0x04) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIO_14 _u(0x05) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 _u(0x06) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 _u(0x07) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VMO _u(0x08) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO15_STATUS // Description : GPIO status -#define IO_BANK0_GPIO15_STATUS_OFFSET 0x00000078 -#define IO_BANK0_GPIO15_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO15_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO15_STATUS_OFFSET _u(0x00000078) +#define IO_BANK0_GPIO15_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO15_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO15_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO15_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO15_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO15_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO15_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO15_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO15_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO15_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO15_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO15_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO15_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO15_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO15_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO15_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO15_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO15_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO15_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO15_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO15_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO15_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO15_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO15_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO15_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO15_CTRL_OFFSET 0x0000007c -#define IO_BANK0_GPIO15_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO15_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO15_CTRL_OFFSET _u(0x0000007c) +#define IO_BANK0_GPIO15_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO15_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO15_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO15_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO15_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO15_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO15_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO15_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO15_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO15_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO15_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -2673,15 +2673,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO15_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO15_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO15_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO15_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO15_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO15_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO15_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO15_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -2689,15 +2689,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO15_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2712,129 +2712,129 @@ // 0x08 -> usb_muxing_digital_dp // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO15_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX 0x01 -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS 0x02 -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 0x04 -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIO_15 0x05 -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 0x06 -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 0x07 -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DP 0x08 -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 _u(0x04) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIO_15 _u(0x05) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 _u(0x06) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 _u(0x07) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DP _u(0x08) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO16_STATUS // Description : GPIO status -#define IO_BANK0_GPIO16_STATUS_OFFSET 0x00000080 -#define IO_BANK0_GPIO16_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO16_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO16_STATUS_OFFSET _u(0x00000080) +#define IO_BANK0_GPIO16_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO16_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO16_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO16_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO16_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO16_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO16_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO16_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO16_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO16_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO16_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO16_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO16_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO16_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO16_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO16_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO16_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO16_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO16_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO16_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO16_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO16_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO16_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO16_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO16_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO16_CTRL_OFFSET 0x00000084 -#define IO_BANK0_GPIO16_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO16_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO16_CTRL_OFFSET _u(0x00000084) +#define IO_BANK0_GPIO16_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO16_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO16_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO16_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO16_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO16_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO16_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO16_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO16_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO16_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO16_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -2843,15 +2843,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO16_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO16_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO16_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO16_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO16_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO16_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO16_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO16_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -2859,15 +2859,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO16_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2882,129 +2882,129 @@ // 0x08 -> usb_muxing_digital_dm // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO16_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX 0x01 -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX 0x02 -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 0x04 -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIO_16 0x05 -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 0x06 -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 0x07 -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DM 0x08 -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIO_16 _u(0x05) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 _u(0x06) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 _u(0x07) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DM _u(0x08) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO17_STATUS // Description : GPIO status -#define IO_BANK0_GPIO17_STATUS_OFFSET 0x00000088 -#define IO_BANK0_GPIO17_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO17_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO17_STATUS_OFFSET _u(0x00000088) +#define IO_BANK0_GPIO17_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO17_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO17_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO17_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO17_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO17_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO17_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO17_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO17_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO17_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO17_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO17_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO17_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO17_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO17_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO17_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO17_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO17_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO17_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO17_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO17_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO17_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO17_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO17_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO17_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO17_CTRL_OFFSET 0x0000008c -#define IO_BANK0_GPIO17_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO17_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO17_CTRL_OFFSET _u(0x0000008c) +#define IO_BANK0_GPIO17_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO17_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO17_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO17_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO17_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO17_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO17_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO17_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO17_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO17_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO17_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -3013,15 +3013,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO17_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO17_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO17_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO17_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO17_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO17_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO17_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO17_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -3029,15 +3029,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO17_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3051,128 +3051,128 @@ // 0x07 -> pio1_17 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO17_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N 0x01 -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX 0x02 -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 0x04 -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIO_17 0x05 -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 0x06 -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 0x07 -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIO_17 _u(0x05) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 _u(0x06) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 _u(0x07) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO18_STATUS // Description : GPIO status -#define IO_BANK0_GPIO18_STATUS_OFFSET 0x00000090 -#define IO_BANK0_GPIO18_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO18_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO18_STATUS_OFFSET _u(0x00000090) +#define IO_BANK0_GPIO18_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO18_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO18_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO18_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO18_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO18_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO18_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO18_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO18_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO18_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO18_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO18_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO18_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO18_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO18_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO18_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO18_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO18_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO18_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO18_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO18_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO18_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO18_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO18_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO18_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO18_CTRL_OFFSET 0x00000094 -#define IO_BANK0_GPIO18_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO18_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO18_CTRL_OFFSET _u(0x00000094) +#define IO_BANK0_GPIO18_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO18_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO18_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO18_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO18_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO18_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO18_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO18_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO18_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO18_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO18_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -3181,15 +3181,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO18_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO18_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO18_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO18_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO18_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO18_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO18_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO18_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -3197,15 +3197,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO18_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3219,128 +3219,128 @@ // 0x07 -> pio1_18 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO18_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK 0x01 -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS 0x02 -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 0x04 -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIO_18 0x05 -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 0x06 -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 0x07 -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIO_18 _u(0x05) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 _u(0x06) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 _u(0x07) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO19_STATUS // Description : GPIO status -#define IO_BANK0_GPIO19_STATUS_OFFSET 0x00000098 -#define IO_BANK0_GPIO19_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO19_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO19_STATUS_OFFSET _u(0x00000098) +#define IO_BANK0_GPIO19_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO19_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO19_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO19_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO19_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO19_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO19_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO19_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO19_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO19_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO19_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO19_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO19_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO19_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO19_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO19_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO19_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO19_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO19_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO19_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO19_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO19_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO19_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO19_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO19_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO19_CTRL_OFFSET 0x0000009c -#define IO_BANK0_GPIO19_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO19_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO19_CTRL_OFFSET _u(0x0000009c) +#define IO_BANK0_GPIO19_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO19_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO19_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO19_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO19_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO19_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO19_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO19_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO19_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO19_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO19_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -3349,15 +3349,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO19_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO19_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO19_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO19_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO19_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO19_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO19_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO19_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -3365,15 +3365,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO19_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3387,128 +3387,128 @@ // 0x07 -> pio1_19 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO19_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX 0x01 -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS 0x02 -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 0x04 -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIO_19 0x05 -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 0x06 -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 0x07 -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIO_19 _u(0x05) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 _u(0x06) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 _u(0x07) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO20_STATUS // Description : GPIO status -#define IO_BANK0_GPIO20_STATUS_OFFSET 0x000000a0 -#define IO_BANK0_GPIO20_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO20_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO20_STATUS_OFFSET _u(0x000000a0) +#define IO_BANK0_GPIO20_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO20_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO20_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO20_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO20_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO20_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO20_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO20_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO20_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO20_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO20_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO20_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO20_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO20_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO20_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO20_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO20_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO20_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO20_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO20_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO20_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO20_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO20_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO20_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO20_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO20_CTRL_OFFSET 0x000000a4 -#define IO_BANK0_GPIO20_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO20_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO20_CTRL_OFFSET _u(0x000000a4) +#define IO_BANK0_GPIO20_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO20_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO20_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO20_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO20_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO20_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO20_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO20_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO20_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO20_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO20_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -3517,15 +3517,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO20_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO20_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO20_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO20_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO20_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO20_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO20_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO20_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -3533,15 +3533,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO20_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3556,129 +3556,129 @@ // 0x08 -> clocks_gpin_0 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO20_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX 0x01 -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX 0x02 -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2 0x04 -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIO_20 0x05 -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20 0x06 -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20 0x07 -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 0x08 -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIO_20 _u(0x05) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20 _u(0x06) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20 _u(0x07) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 _u(0x08) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO21_STATUS // Description : GPIO status -#define IO_BANK0_GPIO21_STATUS_OFFSET 0x000000a8 -#define IO_BANK0_GPIO21_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO21_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO21_STATUS_OFFSET _u(0x000000a8) +#define IO_BANK0_GPIO21_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO21_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO21_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO21_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO21_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO21_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO21_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO21_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO21_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO21_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO21_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO21_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO21_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO21_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO21_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO21_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO21_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO21_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO21_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO21_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO21_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO21_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO21_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO21_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO21_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO21_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO21_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO21_CTRL_OFFSET 0x000000ac -#define IO_BANK0_GPIO21_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO21_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO21_CTRL_OFFSET _u(0x000000ac) +#define IO_BANK0_GPIO21_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO21_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO21_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO21_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO21_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO21_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO21_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO21_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO21_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO21_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO21_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -3687,15 +3687,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO21_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO21_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO21_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO21_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO21_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO21_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO21_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO21_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -3703,15 +3703,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO21_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3726,129 +3726,129 @@ // 0x08 -> clocks_gpout_0 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO21_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N 0x01 -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX 0x02 -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2 0x04 -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIO_21 0x05 -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21 0x06 -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21 0x07 -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 0x08 -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIO_21 _u(0x05) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21 _u(0x06) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21 _u(0x07) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 _u(0x08) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO22_STATUS // Description : GPIO status -#define IO_BANK0_GPIO22_STATUS_OFFSET 0x000000b0 -#define IO_BANK0_GPIO22_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO22_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO22_STATUS_OFFSET _u(0x000000b0) +#define IO_BANK0_GPIO22_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO22_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO22_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO22_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO22_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO22_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO22_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO22_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO22_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO22_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO22_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO22_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO22_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO22_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO22_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO22_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO22_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO22_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO22_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO22_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO22_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO22_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO22_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO22_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO22_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO22_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO22_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO22_CTRL_OFFSET 0x000000b4 -#define IO_BANK0_GPIO22_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO22_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO22_CTRL_OFFSET _u(0x000000b4) +#define IO_BANK0_GPIO22_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO22_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO22_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO22_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO22_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO22_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO22_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO22_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO22_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO22_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO22_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -3857,15 +3857,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO22_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO22_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO22_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO22_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO22_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO22_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO22_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO22_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -3873,15 +3873,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO22_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3896,129 +3896,129 @@ // 0x08 -> clocks_gpin_1 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO22_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK 0x01 -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS 0x02 -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3 0x04 -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIO_22 0x05 -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22 0x06 -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22 0x07 -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 0x08 -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIO_22 _u(0x05) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22 _u(0x06) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22 _u(0x07) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 _u(0x08) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO23_STATUS // Description : GPIO status -#define IO_BANK0_GPIO23_STATUS_OFFSET 0x000000b8 -#define IO_BANK0_GPIO23_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO23_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO23_STATUS_OFFSET _u(0x000000b8) +#define IO_BANK0_GPIO23_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO23_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO23_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO23_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO23_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO23_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO23_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO23_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO23_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO23_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO23_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO23_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO23_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO23_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO23_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO23_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO23_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO23_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO23_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO23_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO23_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO23_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO23_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO23_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO23_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO23_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO23_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO23_CTRL_OFFSET 0x000000bc -#define IO_BANK0_GPIO23_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO23_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO23_CTRL_OFFSET _u(0x000000bc) +#define IO_BANK0_GPIO23_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO23_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO23_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO23_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO23_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO23_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO23_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO23_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO23_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO23_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO23_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -4027,15 +4027,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO23_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO23_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO23_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO23_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO23_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO23_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO23_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO23_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -4043,15 +4043,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO23_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4066,129 +4066,129 @@ // 0x08 -> clocks_gpout_1 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO23_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SPI0_TX 0x01 -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS 0x02 -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3 0x04 -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIO_23 0x05 -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23 0x06 -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23 0x07 -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 0x08 -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIO_23 _u(0x05) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23 _u(0x06) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23 _u(0x07) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 _u(0x08) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO24_STATUS // Description : GPIO status -#define IO_BANK0_GPIO24_STATUS_OFFSET 0x000000c0 -#define IO_BANK0_GPIO24_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO24_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO24_STATUS_OFFSET _u(0x000000c0) +#define IO_BANK0_GPIO24_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO24_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO24_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO24_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO24_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO24_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO24_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO24_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO24_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO24_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO24_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO24_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO24_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO24_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO24_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO24_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO24_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO24_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO24_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO24_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO24_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO24_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO24_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO24_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO24_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO24_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO24_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO24_CTRL_OFFSET 0x000000c4 -#define IO_BANK0_GPIO24_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO24_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO24_CTRL_OFFSET _u(0x000000c4) +#define IO_BANK0_GPIO24_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO24_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO24_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO24_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO24_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO24_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO24_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO24_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO24_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO24_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO24_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO24_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO24_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO24_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO24_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO24_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -4197,15 +4197,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO24_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO24_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO24_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO24_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO24_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO24_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO24_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO24_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -4213,15 +4213,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO24_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO24_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO24_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO24_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4236,129 +4236,129 @@ // 0x08 -> clocks_gpout_2 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO24_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SPI1_RX 0x01 -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX 0x02 -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4 0x04 -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIO_24 0x05 -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24 0x06 -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24 0x07 -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_2 0x08 -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIO_24 _u(0x05) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24 _u(0x06) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24 _u(0x07) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_2 _u(0x08) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO25_STATUS // Description : GPIO status -#define IO_BANK0_GPIO25_STATUS_OFFSET 0x000000c8 -#define IO_BANK0_GPIO25_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO25_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO25_STATUS_OFFSET _u(0x000000c8) +#define IO_BANK0_GPIO25_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO25_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO25_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO25_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO25_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO25_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO25_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO25_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO25_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO25_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO25_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO25_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO25_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO25_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO25_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO25_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO25_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO25_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO25_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO25_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO25_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO25_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO25_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO25_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO25_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO25_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO25_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO25_CTRL_OFFSET 0x000000cc -#define IO_BANK0_GPIO25_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO25_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO25_CTRL_OFFSET _u(0x000000cc) +#define IO_BANK0_GPIO25_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO25_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO25_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO25_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO25_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO25_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO25_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO25_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO25_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO25_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO25_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO25_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO25_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO25_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO25_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO25_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -4367,15 +4367,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO25_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO25_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO25_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO25_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO25_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO25_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO25_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO25_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -4383,15 +4383,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO25_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO25_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO25_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO25_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4406,129 +4406,129 @@ // 0x08 -> clocks_gpout_3 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO25_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SPI1_SS_N 0x01 -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX 0x02 -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4 0x04 -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIO_25 0x05 -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25 0x06 -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25 0x07 -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_3 0x08 -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIO_25 _u(0x05) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25 _u(0x06) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25 _u(0x07) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_3 _u(0x08) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO26_STATUS // Description : GPIO status -#define IO_BANK0_GPIO26_STATUS_OFFSET 0x000000d0 -#define IO_BANK0_GPIO26_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO26_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO26_STATUS_OFFSET _u(0x000000d0) +#define IO_BANK0_GPIO26_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO26_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO26_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO26_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO26_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO26_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO26_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO26_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO26_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO26_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO26_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO26_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO26_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO26_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO26_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO26_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO26_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO26_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO26_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO26_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO26_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO26_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO26_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO26_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO26_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO26_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO26_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO26_CTRL_OFFSET 0x000000d4 -#define IO_BANK0_GPIO26_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO26_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO26_CTRL_OFFSET _u(0x000000d4) +#define IO_BANK0_GPIO26_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO26_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO26_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO26_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO26_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO26_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO26_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO26_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO26_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO26_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO26_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO26_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO26_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO26_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO26_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO26_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -4537,15 +4537,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO26_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO26_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO26_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO26_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO26_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO26_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO26_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO26_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -4553,15 +4553,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO26_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO26_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO26_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO26_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4575,128 +4575,128 @@ // 0x07 -> pio1_26 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO26_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SPI1_SCLK 0x01 -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS 0x02 -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5 0x04 -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIO_26 0x05 -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26 0x06 -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26 0x07 -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIO_26 _u(0x05) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26 _u(0x06) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26 _u(0x07) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO27_STATUS // Description : GPIO status -#define IO_BANK0_GPIO27_STATUS_OFFSET 0x000000d8 -#define IO_BANK0_GPIO27_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO27_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO27_STATUS_OFFSET _u(0x000000d8) +#define IO_BANK0_GPIO27_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO27_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO27_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO27_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO27_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO27_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO27_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO27_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO27_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO27_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO27_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO27_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO27_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO27_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO27_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO27_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO27_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO27_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO27_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO27_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO27_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO27_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO27_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO27_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO27_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO27_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO27_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO27_CTRL_OFFSET 0x000000dc -#define IO_BANK0_GPIO27_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO27_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO27_CTRL_OFFSET _u(0x000000dc) +#define IO_BANK0_GPIO27_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO27_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO27_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO27_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO27_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO27_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO27_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO27_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO27_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO27_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO27_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO27_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO27_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO27_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO27_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO27_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -4705,15 +4705,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO27_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO27_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO27_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO27_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO27_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO27_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO27_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO27_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -4721,15 +4721,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO27_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO27_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO27_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO27_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4743,128 +4743,128 @@ // 0x07 -> pio1_27 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO27_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SPI1_TX 0x01 -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS 0x02 -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5 0x04 -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIO_27 0x05 -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27 0x06 -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27 0x07 -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIO_27 _u(0x05) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27 _u(0x06) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27 _u(0x07) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO28_STATUS // Description : GPIO status -#define IO_BANK0_GPIO28_STATUS_OFFSET 0x000000e0 -#define IO_BANK0_GPIO28_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO28_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO28_STATUS_OFFSET _u(0x000000e0) +#define IO_BANK0_GPIO28_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO28_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO28_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO28_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO28_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO28_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO28_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO28_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO28_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO28_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO28_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO28_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO28_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO28_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO28_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO28_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO28_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO28_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO28_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO28_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO28_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO28_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO28_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO28_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO28_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO28_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO28_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO28_CTRL_OFFSET 0x000000e4 -#define IO_BANK0_GPIO28_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO28_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO28_CTRL_OFFSET _u(0x000000e4) +#define IO_BANK0_GPIO28_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO28_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO28_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO28_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO28_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO28_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO28_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO28_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO28_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO28_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO28_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO28_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO28_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO28_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO28_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO28_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -4873,15 +4873,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO28_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO28_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO28_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO28_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO28_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO28_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO28_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO28_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -4889,15 +4889,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO28_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO28_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO28_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO28_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4911,128 +4911,128 @@ // 0x07 -> pio1_28 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO28_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SPI1_RX 0x01 -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX 0x02 -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6 0x04 -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIO_28 0x05 -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28 0x06 -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28 0x07 -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIO_28 _u(0x05) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28 _u(0x06) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28 _u(0x07) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO29_STATUS // Description : GPIO status -#define IO_BANK0_GPIO29_STATUS_OFFSET 0x000000e8 -#define IO_BANK0_GPIO29_STATUS_BITS 0x050a3300 -#define IO_BANK0_GPIO29_STATUS_RESET 0x00000000 +#define IO_BANK0_GPIO29_STATUS_OFFSET _u(0x000000e8) +#define IO_BANK0_GPIO29_STATUS_BITS _u(0x050a3300) +#define IO_BANK0_GPIO29_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_RESET 0x0 -#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_MSB 26 -#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_LSB _u(26) #define IO_BANK0_GPIO29_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_MSB 24 -#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_LSB _u(24) #define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_BANK0_GPIO29_STATUS_INTOPERI_RESET 0x0 -#define IO_BANK0_GPIO29_STATUS_INTOPERI_BITS 0x00080000 -#define IO_BANK0_GPIO29_STATUS_INTOPERI_MSB 19 -#define IO_BANK0_GPIO29_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO29_STATUS_INTOPERI_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_BANK0_GPIO29_STATUS_INTOPERI_MSB _u(19) +#define IO_BANK0_GPIO29_STATUS_INTOPERI_LSB _u(19) #define IO_BANK0_GPIO29_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_BANK0_GPIO29_STATUS_INFROMPAD_RESET 0x0 -#define IO_BANK0_GPIO29_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_BANK0_GPIO29_STATUS_INFROMPAD_MSB 17 -#define IO_BANK0_GPIO29_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_LSB _u(17) #define IO_BANK0_GPIO29_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_BANK0_GPIO29_STATUS_OETOPAD_RESET 0x0 -#define IO_BANK0_GPIO29_STATUS_OETOPAD_BITS 0x00002000 -#define IO_BANK0_GPIO29_STATUS_OETOPAD_MSB 13 -#define IO_BANK0_GPIO29_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO29_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO29_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO29_STATUS_OETOPAD_LSB _u(13) #define IO_BANK0_GPIO29_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_MSB 12 -#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_MSB _u(12) +#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_LSB _u(12) #define IO_BANK0_GPIO29_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_RESET 0x0 -#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_MSB 9 -#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_LSB _u(9) #define IO_BANK0_GPIO29_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_MSB 8 -#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_LSB _u(8) #define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_GPIO29_CTRL // Description : GPIO control including function select and overrides. -#define IO_BANK0_GPIO29_CTRL_OFFSET 0x000000ec -#define IO_BANK0_GPIO29_CTRL_BITS 0x3003331f -#define IO_BANK0_GPIO29_CTRL_RESET 0x0000001f +#define IO_BANK0_GPIO29_CTRL_OFFSET _u(0x000000ec) +#define IO_BANK0_GPIO29_CTRL_BITS _u(0x3003331f) +#define IO_BANK0_GPIO29_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO29_CTRL_IRQOVER_RESET 0x0 -#define IO_BANK0_GPIO29_CTRL_IRQOVER_BITS 0x30000000 -#define IO_BANK0_GPIO29_CTRL_IRQOVER_MSB 29 -#define IO_BANK0_GPIO29_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO29_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_LSB _u(28) #define IO_BANK0_GPIO29_CTRL_IRQOVER_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO29_CTRL_INOVER_RESET 0x0 -#define IO_BANK0_GPIO29_CTRL_INOVER_BITS 0x00030000 -#define IO_BANK0_GPIO29_CTRL_INOVER_MSB 17 -#define IO_BANK0_GPIO29_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO29_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO29_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO29_CTRL_INOVER_LSB _u(16) #define IO_BANK0_GPIO29_CTRL_INOVER_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -5041,15 +5041,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO29_CTRL_OEOVER_RESET 0x0 -#define IO_BANK0_GPIO29_CTRL_OEOVER_BITS 0x00003000 -#define IO_BANK0_GPIO29_CTRL_OEOVER_MSB 13 -#define IO_BANK0_GPIO29_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO29_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO29_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO29_CTRL_OEOVER_LSB _u(12) #define IO_BANK0_GPIO29_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -5057,15 +5057,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET 0x0 -#define IO_BANK0_GPIO29_CTRL_OUTOVER_BITS 0x00000300 -#define IO_BANK0_GPIO29_CTRL_OUTOVER_MSB 9 -#define IO_BANK0_GPIO29_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_LSB _u(8) #define IO_BANK0_GPIO29_CTRL_OUTOVER_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -5079,9859 +5079,9859 @@ // 0x07 -> pio1_29 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_RESET 0x1f -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_MSB 4 -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_LSB _u(0) #define IO_BANK0_GPIO29_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SPI1_SS_N 0x01 -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX 0x02 -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6 0x04 -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIO_29 0x05 -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29 0x06 -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29 0x07 -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIO_29 _u(0x05) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29 _u(0x06) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29 _u(0x07) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_INTR0 // Description : Raw Interrupts -#define IO_BANK0_INTR0_OFFSET 0x000000f0 -#define IO_BANK0_INTR0_BITS 0xffffffff -#define IO_BANK0_INTR0_RESET 0x00000000 +#define IO_BANK0_INTR0_OFFSET _u(0x000000f0) +#define IO_BANK0_INTR0_BITS _u(0xffffffff) +#define IO_BANK0_INTR0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO7_EDGE_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_MSB 31 -#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_LSB _u(31) #define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO7_EDGE_LOW // Description : None -#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_MSB 30 -#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_LSB _u(30) #define IO_BANK0_INTR0_GPIO7_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO7_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_MSB 29 -#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO7_LEVEL_LOW // Description : None -#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_MSB 28 -#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_LSB _u(28) #define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO6_EDGE_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_MSB 27 -#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_LSB _u(27) #define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO6_EDGE_LOW // Description : None -#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_MSB 26 -#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_LSB _u(26) #define IO_BANK0_INTR0_GPIO6_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO6_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_MSB 25 -#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO6_LEVEL_LOW // Description : None -#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_MSB 24 -#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_LSB _u(24) #define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO5_EDGE_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_MSB 23 -#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_LSB _u(23) #define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO5_EDGE_LOW // Description : None -#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_MSB 22 -#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_LSB _u(22) #define IO_BANK0_INTR0_GPIO5_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO5_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_MSB 21 -#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO5_LEVEL_LOW // Description : None -#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_MSB 20 -#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_LSB _u(20) #define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO4_EDGE_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_MSB 19 -#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_LSB _u(19) #define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO4_EDGE_LOW // Description : None -#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_MSB 18 -#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_LSB _u(18) #define IO_BANK0_INTR0_GPIO4_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO4_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_MSB 17 -#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO4_LEVEL_LOW // Description : None -#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_MSB 16 -#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_LSB _u(16) #define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO3_EDGE_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_MSB 15 -#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_LSB _u(15) #define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO3_EDGE_LOW // Description : None -#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_MSB 14 -#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_LSB _u(14) #define IO_BANK0_INTR0_GPIO3_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO3_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_MSB 13 -#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO3_LEVEL_LOW // Description : None -#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_MSB 12 -#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_LSB _u(12) #define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO2_EDGE_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_MSB 11 -#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_LSB _u(11) #define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO2_EDGE_LOW // Description : None -#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_MSB 10 -#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_LSB _u(10) #define IO_BANK0_INTR0_GPIO2_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO2_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_MSB 9 -#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO2_LEVEL_LOW // Description : None -#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_MSB 8 -#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_LSB _u(8) #define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO1_EDGE_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_MSB 7 -#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_LSB _u(7) #define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO1_EDGE_LOW // Description : None -#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_MSB 6 -#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_LSB _u(6) #define IO_BANK0_INTR0_GPIO1_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO1_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_MSB 5 -#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO1_LEVEL_LOW // Description : None -#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_MSB 4 -#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_LSB _u(4) #define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO0_EDGE_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_MSB 3 -#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_LSB _u(3) #define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO0_EDGE_LOW // Description : None -#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_MSB 2 -#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_LSB _u(2) #define IO_BANK0_INTR0_GPIO0_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO0_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_MSB 1 -#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO0_LEVEL_LOW // Description : None -#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_MSB 0 -#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_LSB _u(0) #define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_INTR1 // Description : Raw Interrupts -#define IO_BANK0_INTR1_OFFSET 0x000000f4 -#define IO_BANK0_INTR1_BITS 0xffffffff -#define IO_BANK0_INTR1_RESET 0x00000000 +#define IO_BANK0_INTR1_OFFSET _u(0x000000f4) +#define IO_BANK0_INTR1_BITS _u(0xffffffff) +#define IO_BANK0_INTR1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO15_EDGE_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_MSB 31 -#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_LSB _u(31) #define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO15_EDGE_LOW // Description : None -#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_MSB 30 -#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_LSB _u(30) #define IO_BANK0_INTR1_GPIO15_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO15_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_MSB 29 -#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO15_LEVEL_LOW // Description : None -#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_MSB 28 -#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_LSB _u(28) #define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO14_EDGE_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_MSB 27 -#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_LSB _u(27) #define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO14_EDGE_LOW // Description : None -#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_MSB 26 -#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_LSB _u(26) #define IO_BANK0_INTR1_GPIO14_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO14_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_MSB 25 -#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO14_LEVEL_LOW // Description : None -#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_MSB 24 -#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_LSB _u(24) #define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO13_EDGE_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_MSB 23 -#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_LSB _u(23) #define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO13_EDGE_LOW // Description : None -#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_MSB 22 -#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_LSB _u(22) #define IO_BANK0_INTR1_GPIO13_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO13_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_MSB 21 -#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO13_LEVEL_LOW // Description : None -#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_MSB 20 -#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_LSB _u(20) #define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO12_EDGE_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_MSB 19 -#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_LSB _u(19) #define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO12_EDGE_LOW // Description : None -#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_MSB 18 -#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_LSB _u(18) #define IO_BANK0_INTR1_GPIO12_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO12_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_MSB 17 -#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO12_LEVEL_LOW // Description : None -#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_MSB 16 -#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_LSB _u(16) #define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO11_EDGE_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_MSB 15 -#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_LSB _u(15) #define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO11_EDGE_LOW // Description : None -#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_MSB 14 -#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_LSB _u(14) #define IO_BANK0_INTR1_GPIO11_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO11_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_MSB 13 -#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO11_LEVEL_LOW // Description : None -#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_MSB 12 -#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_LSB _u(12) #define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO10_EDGE_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_MSB 11 -#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_LSB _u(11) #define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO10_EDGE_LOW // Description : None -#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_MSB 10 -#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_LSB _u(10) #define IO_BANK0_INTR1_GPIO10_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO10_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_MSB 9 -#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO10_LEVEL_LOW // Description : None -#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_MSB 8 -#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_LSB _u(8) #define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO9_EDGE_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_MSB 7 -#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_LSB _u(7) #define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO9_EDGE_LOW // Description : None -#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_MSB 6 -#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_LSB _u(6) #define IO_BANK0_INTR1_GPIO9_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO9_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_MSB 5 -#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO9_LEVEL_LOW // Description : None -#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_MSB 4 -#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_LSB _u(4) #define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO8_EDGE_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_MSB 3 -#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_LSB _u(3) #define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO8_EDGE_LOW // Description : None -#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_MSB 2 -#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_LSB _u(2) #define IO_BANK0_INTR1_GPIO8_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO8_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_MSB 1 -#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO8_LEVEL_LOW // Description : None -#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_MSB 0 -#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_LSB _u(0) #define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_INTR2 // Description : Raw Interrupts -#define IO_BANK0_INTR2_OFFSET 0x000000f8 -#define IO_BANK0_INTR2_BITS 0xffffffff -#define IO_BANK0_INTR2_RESET 0x00000000 +#define IO_BANK0_INTR2_OFFSET _u(0x000000f8) +#define IO_BANK0_INTR2_BITS _u(0xffffffff) +#define IO_BANK0_INTR2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO23_EDGE_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_MSB 31 -#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_LSB _u(31) #define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO23_EDGE_LOW // Description : None -#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_MSB 30 -#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_LSB _u(30) #define IO_BANK0_INTR2_GPIO23_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO23_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_MSB 29 -#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO23_LEVEL_LOW // Description : None -#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_MSB 28 -#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_LSB _u(28) #define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO22_EDGE_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_MSB 27 -#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_LSB _u(27) #define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO22_EDGE_LOW // Description : None -#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_MSB 26 -#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_LSB _u(26) #define IO_BANK0_INTR2_GPIO22_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO22_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_MSB 25 -#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO22_LEVEL_LOW // Description : None -#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_MSB 24 -#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_LSB _u(24) #define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO21_EDGE_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_MSB 23 -#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_LSB _u(23) #define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO21_EDGE_LOW // Description : None -#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_MSB 22 -#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_LSB _u(22) #define IO_BANK0_INTR2_GPIO21_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO21_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_MSB 21 -#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO21_LEVEL_LOW // Description : None -#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_MSB 20 -#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_LSB _u(20) #define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO20_EDGE_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_MSB 19 -#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_LSB _u(19) #define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO20_EDGE_LOW // Description : None -#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_MSB 18 -#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_LSB _u(18) #define IO_BANK0_INTR2_GPIO20_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO20_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_MSB 17 -#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO20_LEVEL_LOW // Description : None -#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_MSB 16 -#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_LSB _u(16) #define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO19_EDGE_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_MSB 15 -#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_LSB _u(15) #define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO19_EDGE_LOW // Description : None -#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_MSB 14 -#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_LSB _u(14) #define IO_BANK0_INTR2_GPIO19_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO19_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_MSB 13 -#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO19_LEVEL_LOW // Description : None -#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_MSB 12 -#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_LSB _u(12) #define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO18_EDGE_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_MSB 11 -#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_LSB _u(11) #define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO18_EDGE_LOW // Description : None -#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_MSB 10 -#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_LSB _u(10) #define IO_BANK0_INTR2_GPIO18_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO18_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_MSB 9 -#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO18_LEVEL_LOW // Description : None -#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_MSB 8 -#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_LSB _u(8) #define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO17_EDGE_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_MSB 7 -#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_LSB _u(7) #define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO17_EDGE_LOW // Description : None -#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_MSB 6 -#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_LSB _u(6) #define IO_BANK0_INTR2_GPIO17_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO17_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_MSB 5 -#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO17_LEVEL_LOW // Description : None -#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_MSB 4 -#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_LSB _u(4) #define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO16_EDGE_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_MSB 3 -#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_LSB _u(3) #define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO16_EDGE_LOW // Description : None -#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_MSB 2 -#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_LSB _u(2) #define IO_BANK0_INTR2_GPIO16_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO16_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_MSB 1 -#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO16_LEVEL_LOW // Description : None -#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_MSB 0 -#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_LSB _u(0) #define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_INTR3 // Description : Raw Interrupts -#define IO_BANK0_INTR3_OFFSET 0x000000fc -#define IO_BANK0_INTR3_BITS 0x00ffffff -#define IO_BANK0_INTR3_RESET 0x00000000 +#define IO_BANK0_INTR3_OFFSET _u(0x000000fc) +#define IO_BANK0_INTR3_BITS _u(0x00ffffff) +#define IO_BANK0_INTR3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO29_EDGE_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_MSB 23 -#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_LSB _u(23) #define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO29_EDGE_LOW // Description : None -#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_MSB 22 -#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_LSB _u(22) #define IO_BANK0_INTR3_GPIO29_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO29_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_MSB 21 -#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO29_LEVEL_LOW // Description : None -#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_MSB 20 -#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_LSB _u(20) #define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO28_EDGE_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_MSB 19 -#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_LSB _u(19) #define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO28_EDGE_LOW // Description : None -#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_MSB 18 -#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_LSB _u(18) #define IO_BANK0_INTR3_GPIO28_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO28_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_MSB 17 -#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO28_LEVEL_LOW // Description : None -#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_MSB 16 -#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_LSB _u(16) #define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO27_EDGE_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_MSB 15 -#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_LSB _u(15) #define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO27_EDGE_LOW // Description : None -#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_MSB 14 -#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_LSB _u(14) #define IO_BANK0_INTR3_GPIO27_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO27_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_MSB 13 -#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO27_LEVEL_LOW // Description : None -#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_MSB 12 -#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_LSB _u(12) #define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO26_EDGE_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_MSB 11 -#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_LSB _u(11) #define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO26_EDGE_LOW // Description : None -#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_MSB 10 -#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_LSB _u(10) #define IO_BANK0_INTR3_GPIO26_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO26_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_MSB 9 -#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO26_LEVEL_LOW // Description : None -#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_MSB 8 -#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_LSB _u(8) #define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO25_EDGE_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_MSB 7 -#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_LSB _u(7) #define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO25_EDGE_LOW // Description : None -#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_MSB 6 -#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_LSB _u(6) #define IO_BANK0_INTR3_GPIO25_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO25_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_MSB 5 -#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO25_LEVEL_LOW // Description : None -#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_MSB 4 -#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_LSB _u(4) #define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO24_EDGE_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_MSB 3 -#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_LSB _u(3) #define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO24_EDGE_LOW // Description : None -#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_MSB 2 -#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_LSB _u(2) #define IO_BANK0_INTR3_GPIO24_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO24_LEVEL_HIGH // Description : None -#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_MSB 1 -#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO24_LEVEL_LOW // Description : None -#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_MSB 0 -#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_PROC0_INTE0 // Description : Interrupt Enable for proc0 -#define IO_BANK0_PROC0_INTE0_OFFSET 0x00000100 -#define IO_BANK0_PROC0_INTE0_BITS 0xffffffff -#define IO_BANK0_PROC0_INTE0_RESET 0x00000000 +#define IO_BANK0_PROC0_INTE0_OFFSET _u(0x00000100) +#define IO_BANK0_PROC0_INTE0_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTE0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC0_INTE1 // Description : Interrupt Enable for proc0 -#define IO_BANK0_PROC0_INTE1_OFFSET 0x00000104 -#define IO_BANK0_PROC0_INTE1_BITS 0xffffffff -#define IO_BANK0_PROC0_INTE1_RESET 0x00000000 +#define IO_BANK0_PROC0_INTE1_OFFSET _u(0x00000104) +#define IO_BANK0_PROC0_INTE1_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTE1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC0_INTE2 // Description : Interrupt Enable for proc0 -#define IO_BANK0_PROC0_INTE2_OFFSET 0x00000108 -#define IO_BANK0_PROC0_INTE2_BITS 0xffffffff -#define IO_BANK0_PROC0_INTE2_RESET 0x00000000 +#define IO_BANK0_PROC0_INTE2_OFFSET _u(0x00000108) +#define IO_BANK0_PROC0_INTE2_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTE2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC0_INTE3 // Description : Interrupt Enable for proc0 -#define IO_BANK0_PROC0_INTE3_OFFSET 0x0000010c -#define IO_BANK0_PROC0_INTE3_BITS 0x00ffffff -#define IO_BANK0_PROC0_INTE3_RESET 0x00000000 +#define IO_BANK0_PROC0_INTE3_OFFSET _u(0x0000010c) +#define IO_BANK0_PROC0_INTE3_BITS _u(0x00ffffff) +#define IO_BANK0_PROC0_INTE3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC0_INTF0 // Description : Interrupt Force for proc0 -#define IO_BANK0_PROC0_INTF0_OFFSET 0x00000110 -#define IO_BANK0_PROC0_INTF0_BITS 0xffffffff -#define IO_BANK0_PROC0_INTF0_RESET 0x00000000 +#define IO_BANK0_PROC0_INTF0_OFFSET _u(0x00000110) +#define IO_BANK0_PROC0_INTF0_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTF0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC0_INTF1 // Description : Interrupt Force for proc0 -#define IO_BANK0_PROC0_INTF1_OFFSET 0x00000114 -#define IO_BANK0_PROC0_INTF1_BITS 0xffffffff -#define IO_BANK0_PROC0_INTF1_RESET 0x00000000 +#define IO_BANK0_PROC0_INTF1_OFFSET _u(0x00000114) +#define IO_BANK0_PROC0_INTF1_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTF1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC0_INTF2 // Description : Interrupt Force for proc0 -#define IO_BANK0_PROC0_INTF2_OFFSET 0x00000118 -#define IO_BANK0_PROC0_INTF2_BITS 0xffffffff -#define IO_BANK0_PROC0_INTF2_RESET 0x00000000 +#define IO_BANK0_PROC0_INTF2_OFFSET _u(0x00000118) +#define IO_BANK0_PROC0_INTF2_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTF2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC0_INTF3 // Description : Interrupt Force for proc0 -#define IO_BANK0_PROC0_INTF3_OFFSET 0x0000011c -#define IO_BANK0_PROC0_INTF3_BITS 0x00ffffff -#define IO_BANK0_PROC0_INTF3_RESET 0x00000000 +#define IO_BANK0_PROC0_INTF3_OFFSET _u(0x0000011c) +#define IO_BANK0_PROC0_INTF3_BITS _u(0x00ffffff) +#define IO_BANK0_PROC0_INTF3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC0_INTS0 // Description : Interrupt status after masking & forcing for proc0 -#define IO_BANK0_PROC0_INTS0_OFFSET 0x00000120 -#define IO_BANK0_PROC0_INTS0_BITS 0xffffffff -#define IO_BANK0_PROC0_INTS0_RESET 0x00000000 +#define IO_BANK0_PROC0_INTS0_OFFSET _u(0x00000120) +#define IO_BANK0_PROC0_INTS0_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTS0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_PROC0_INTS1 // Description : Interrupt status after masking & forcing for proc0 -#define IO_BANK0_PROC0_INTS1_OFFSET 0x00000124 -#define IO_BANK0_PROC0_INTS1_BITS 0xffffffff -#define IO_BANK0_PROC0_INTS1_RESET 0x00000000 +#define IO_BANK0_PROC0_INTS1_OFFSET _u(0x00000124) +#define IO_BANK0_PROC0_INTS1_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTS1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_PROC0_INTS2 // Description : Interrupt status after masking & forcing for proc0 -#define IO_BANK0_PROC0_INTS2_OFFSET 0x00000128 -#define IO_BANK0_PROC0_INTS2_BITS 0xffffffff -#define IO_BANK0_PROC0_INTS2_RESET 0x00000000 +#define IO_BANK0_PROC0_INTS2_OFFSET _u(0x00000128) +#define IO_BANK0_PROC0_INTS2_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTS2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_PROC0_INTS3 // Description : Interrupt status after masking & forcing for proc0 -#define IO_BANK0_PROC0_INTS3_OFFSET 0x0000012c -#define IO_BANK0_PROC0_INTS3_BITS 0x00ffffff -#define IO_BANK0_PROC0_INTS3_RESET 0x00000000 +#define IO_BANK0_PROC0_INTS3_OFFSET _u(0x0000012c) +#define IO_BANK0_PROC0_INTS3_BITS _u(0x00ffffff) +#define IO_BANK0_PROC0_INTS3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW // Description : None -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_PROC1_INTE0 // Description : Interrupt Enable for proc1 -#define IO_BANK0_PROC1_INTE0_OFFSET 0x00000130 -#define IO_BANK0_PROC1_INTE0_BITS 0xffffffff -#define IO_BANK0_PROC1_INTE0_RESET 0x00000000 +#define IO_BANK0_PROC1_INTE0_OFFSET _u(0x00000130) +#define IO_BANK0_PROC1_INTE0_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTE0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC1_INTE1 // Description : Interrupt Enable for proc1 -#define IO_BANK0_PROC1_INTE1_OFFSET 0x00000134 -#define IO_BANK0_PROC1_INTE1_BITS 0xffffffff -#define IO_BANK0_PROC1_INTE1_RESET 0x00000000 +#define IO_BANK0_PROC1_INTE1_OFFSET _u(0x00000134) +#define IO_BANK0_PROC1_INTE1_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTE1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC1_INTE2 // Description : Interrupt Enable for proc1 -#define IO_BANK0_PROC1_INTE2_OFFSET 0x00000138 -#define IO_BANK0_PROC1_INTE2_BITS 0xffffffff -#define IO_BANK0_PROC1_INTE2_RESET 0x00000000 +#define IO_BANK0_PROC1_INTE2_OFFSET _u(0x00000138) +#define IO_BANK0_PROC1_INTE2_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTE2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC1_INTE3 // Description : Interrupt Enable for proc1 -#define IO_BANK0_PROC1_INTE3_OFFSET 0x0000013c -#define IO_BANK0_PROC1_INTE3_BITS 0x00ffffff -#define IO_BANK0_PROC1_INTE3_RESET 0x00000000 +#define IO_BANK0_PROC1_INTE3_OFFSET _u(0x0000013c) +#define IO_BANK0_PROC1_INTE3_BITS _u(0x00ffffff) +#define IO_BANK0_PROC1_INTE3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC1_INTF0 // Description : Interrupt Force for proc1 -#define IO_BANK0_PROC1_INTF0_OFFSET 0x00000140 -#define IO_BANK0_PROC1_INTF0_BITS 0xffffffff -#define IO_BANK0_PROC1_INTF0_RESET 0x00000000 +#define IO_BANK0_PROC1_INTF0_OFFSET _u(0x00000140) +#define IO_BANK0_PROC1_INTF0_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTF0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC1_INTF1 // Description : Interrupt Force for proc1 -#define IO_BANK0_PROC1_INTF1_OFFSET 0x00000144 -#define IO_BANK0_PROC1_INTF1_BITS 0xffffffff -#define IO_BANK0_PROC1_INTF1_RESET 0x00000000 +#define IO_BANK0_PROC1_INTF1_OFFSET _u(0x00000144) +#define IO_BANK0_PROC1_INTF1_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTF1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC1_INTF2 // Description : Interrupt Force for proc1 -#define IO_BANK0_PROC1_INTF2_OFFSET 0x00000148 -#define IO_BANK0_PROC1_INTF2_BITS 0xffffffff -#define IO_BANK0_PROC1_INTF2_RESET 0x00000000 +#define IO_BANK0_PROC1_INTF2_OFFSET _u(0x00000148) +#define IO_BANK0_PROC1_INTF2_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTF2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC1_INTF3 // Description : Interrupt Force for proc1 -#define IO_BANK0_PROC1_INTF3_OFFSET 0x0000014c -#define IO_BANK0_PROC1_INTF3_BITS 0x00ffffff -#define IO_BANK0_PROC1_INTF3_RESET 0x00000000 +#define IO_BANK0_PROC1_INTF3_OFFSET _u(0x0000014c) +#define IO_BANK0_PROC1_INTF3_BITS _u(0x00ffffff) +#define IO_BANK0_PROC1_INTF3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_PROC1_INTS0 // Description : Interrupt status after masking & forcing for proc1 -#define IO_BANK0_PROC1_INTS0_OFFSET 0x00000150 -#define IO_BANK0_PROC1_INTS0_BITS 0xffffffff -#define IO_BANK0_PROC1_INTS0_RESET 0x00000000 +#define IO_BANK0_PROC1_INTS0_OFFSET _u(0x00000150) +#define IO_BANK0_PROC1_INTS0_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTS0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_PROC1_INTS1 // Description : Interrupt status after masking & forcing for proc1 -#define IO_BANK0_PROC1_INTS1_OFFSET 0x00000154 -#define IO_BANK0_PROC1_INTS1_BITS 0xffffffff -#define IO_BANK0_PROC1_INTS1_RESET 0x00000000 +#define IO_BANK0_PROC1_INTS1_OFFSET _u(0x00000154) +#define IO_BANK0_PROC1_INTS1_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTS1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_PROC1_INTS2 // Description : Interrupt status after masking & forcing for proc1 -#define IO_BANK0_PROC1_INTS2_OFFSET 0x00000158 -#define IO_BANK0_PROC1_INTS2_BITS 0xffffffff -#define IO_BANK0_PROC1_INTS2_RESET 0x00000000 +#define IO_BANK0_PROC1_INTS2_OFFSET _u(0x00000158) +#define IO_BANK0_PROC1_INTS2_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTS2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_MSB 31 -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_LSB _u(31) #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_MSB 30 -#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_LSB _u(30) #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_MSB 29 -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_MSB 28 -#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_LSB _u(28) #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_MSB 27 -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_LSB _u(27) #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_MSB 26 -#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_LSB _u(26) #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_MSB 25 -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_MSB 24 -#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_LSB _u(24) #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_PROC1_INTS3 // Description : Interrupt status after masking & forcing for proc1 -#define IO_BANK0_PROC1_INTS3_OFFSET 0x0000015c -#define IO_BANK0_PROC1_INTS3_BITS 0x00ffffff -#define IO_BANK0_PROC1_INTS3_RESET 0x00000000 +#define IO_BANK0_PROC1_INTS3_OFFSET _u(0x0000015c) +#define IO_BANK0_PROC1_INTS3_BITS _u(0x00ffffff) +#define IO_BANK0_PROC1_INTS3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_MSB 23 -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_LSB _u(23) #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_MSB 22 -#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_LSB _u(22) #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_MSB 21 -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_MSB 20 -#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_LSB _u(20) #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_MSB 19 -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_LSB _u(19) #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_MSB 18 -#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_LSB _u(18) #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_MSB 17 -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_MSB 16 -#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_LSB _u(16) #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_MSB 15 -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_LSB _u(15) #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_MSB 14 -#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_LSB _u(14) #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_MSB 13 -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_MSB 12 -#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_LSB _u(12) #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_MSB 11 -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_LSB _u(11) #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_MSB 10 -#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_LSB _u(10) #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_MSB 9 -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_MSB 8 -#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_LSB _u(8) #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_MSB 7 -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_LSB _u(7) #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_MSB 6 -#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_LSB _u(6) #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_MSB 5 -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_MSB 4 -#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_LSB _u(4) #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_MSB 3 -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_LSB _u(3) #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_MSB 2 -#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_LSB _u(2) #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_MSB 1 -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW // Description : None -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_MSB 0 -#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTE0 // Description : Interrupt Enable for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTE0_OFFSET 0x00000160 -#define IO_BANK0_DORMANT_WAKE_INTE0_BITS 0xffffffff -#define IO_BANK0_DORMANT_WAKE_INTE0_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTE0_OFFSET _u(0x00000160) +#define IO_BANK0_DORMANT_WAKE_INTE0_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTE0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_MSB 31 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_LSB _u(31) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_MSB 30 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_LSB _u(30) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_MSB 29 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_MSB 28 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_LSB _u(28) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_MSB 27 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_LSB _u(27) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_MSB 26 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_LSB _u(26) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_MSB 25 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_MSB 24 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_LSB _u(24) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTE1 // Description : Interrupt Enable for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTE1_OFFSET 0x00000164 -#define IO_BANK0_DORMANT_WAKE_INTE1_BITS 0xffffffff -#define IO_BANK0_DORMANT_WAKE_INTE1_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTE1_OFFSET _u(0x00000164) +#define IO_BANK0_DORMANT_WAKE_INTE1_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTE1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_MSB 31 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_LSB _u(31) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_MSB 30 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_LSB _u(30) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_MSB 29 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_MSB 28 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_LSB _u(28) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_MSB 27 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_LSB _u(27) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_MSB 26 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_LSB _u(26) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_MSB 25 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_MSB 24 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_LSB _u(24) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTE2 // Description : Interrupt Enable for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTE2_OFFSET 0x00000168 -#define IO_BANK0_DORMANT_WAKE_INTE2_BITS 0xffffffff -#define IO_BANK0_DORMANT_WAKE_INTE2_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTE2_OFFSET _u(0x00000168) +#define IO_BANK0_DORMANT_WAKE_INTE2_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTE2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_MSB 31 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_LSB _u(31) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_MSB 30 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_LSB _u(30) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_MSB 29 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_MSB 28 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_LSB _u(28) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_MSB 27 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_LSB _u(27) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_MSB 26 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_LSB _u(26) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_MSB 25 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_MSB 24 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_LSB _u(24) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTE3 // Description : Interrupt Enable for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTE3_OFFSET 0x0000016c -#define IO_BANK0_DORMANT_WAKE_INTE3_BITS 0x00ffffff -#define IO_BANK0_DORMANT_WAKE_INTE3_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTE3_OFFSET _u(0x0000016c) +#define IO_BANK0_DORMANT_WAKE_INTE3_BITS _u(0x00ffffff) +#define IO_BANK0_DORMANT_WAKE_INTE3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTF0 // Description : Interrupt Force for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTF0_OFFSET 0x00000170 -#define IO_BANK0_DORMANT_WAKE_INTF0_BITS 0xffffffff -#define IO_BANK0_DORMANT_WAKE_INTF0_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTF0_OFFSET _u(0x00000170) +#define IO_BANK0_DORMANT_WAKE_INTF0_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTF0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_MSB 31 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_LSB _u(31) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_MSB 30 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_LSB _u(30) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_MSB 29 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_MSB 28 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_LSB _u(28) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_MSB 27 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_LSB _u(27) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_MSB 26 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_LSB _u(26) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_MSB 25 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_MSB 24 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_LSB _u(24) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTF1 // Description : Interrupt Force for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTF1_OFFSET 0x00000174 -#define IO_BANK0_DORMANT_WAKE_INTF1_BITS 0xffffffff -#define IO_BANK0_DORMANT_WAKE_INTF1_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTF1_OFFSET _u(0x00000174) +#define IO_BANK0_DORMANT_WAKE_INTF1_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTF1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_MSB 31 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_LSB _u(31) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_MSB 30 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_LSB _u(30) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_MSB 29 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_MSB 28 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_LSB _u(28) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_MSB 27 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_LSB _u(27) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_MSB 26 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_LSB _u(26) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_MSB 25 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_MSB 24 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_LSB _u(24) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTF2 // Description : Interrupt Force for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTF2_OFFSET 0x00000178 -#define IO_BANK0_DORMANT_WAKE_INTF2_BITS 0xffffffff -#define IO_BANK0_DORMANT_WAKE_INTF2_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTF2_OFFSET _u(0x00000178) +#define IO_BANK0_DORMANT_WAKE_INTF2_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTF2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_MSB 31 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_LSB _u(31) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_MSB 30 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_LSB _u(30) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_MSB 29 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_MSB 28 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_LSB _u(28) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_MSB 27 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_LSB _u(27) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_MSB 26 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_LSB _u(26) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_MSB 25 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_MSB 24 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_LSB _u(24) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTF3 // Description : Interrupt Force for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTF3_OFFSET 0x0000017c -#define IO_BANK0_DORMANT_WAKE_INTF3_BITS 0x00ffffff -#define IO_BANK0_DORMANT_WAKE_INTF3_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTF3_OFFSET _u(0x0000017c) +#define IO_BANK0_DORMANT_WAKE_INTF3_BITS _u(0x00ffffff) +#define IO_BANK0_DORMANT_WAKE_INTF3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTS0 // Description : Interrupt status after masking & forcing for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTS0_OFFSET 0x00000180 -#define IO_BANK0_DORMANT_WAKE_INTS0_BITS 0xffffffff -#define IO_BANK0_DORMANT_WAKE_INTS0_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTS0_OFFSET _u(0x00000180) +#define IO_BANK0_DORMANT_WAKE_INTS0_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTS0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_MSB 31 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_LSB _u(31) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_MSB 30 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_LSB _u(30) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_MSB 29 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_MSB 28 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_LSB _u(28) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_MSB 27 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_LSB _u(27) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_MSB 26 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_LSB _u(26) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_MSB 25 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_MSB 24 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_LSB _u(24) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTS1 // Description : Interrupt status after masking & forcing for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTS1_OFFSET 0x00000184 -#define IO_BANK0_DORMANT_WAKE_INTS1_BITS 0xffffffff -#define IO_BANK0_DORMANT_WAKE_INTS1_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTS1_OFFSET _u(0x00000184) +#define IO_BANK0_DORMANT_WAKE_INTS1_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTS1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_MSB 31 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_LSB _u(31) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_MSB 30 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_LSB _u(30) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_MSB 29 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_MSB 28 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_LSB _u(28) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_MSB 27 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_LSB _u(27) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_MSB 26 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_LSB _u(26) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_MSB 25 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_MSB 24 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_LSB _u(24) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTS2 // Description : Interrupt status after masking & forcing for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTS2_OFFSET 0x00000188 -#define IO_BANK0_DORMANT_WAKE_INTS2_BITS 0xffffffff -#define IO_BANK0_DORMANT_WAKE_INTS2_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTS2_OFFSET _u(0x00000188) +#define IO_BANK0_DORMANT_WAKE_INTS2_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTS2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_BITS 0x80000000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_MSB 31 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_LSB _u(31) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_BITS 0x40000000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_MSB 30 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_LSB _u(30) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_BITS 0x20000000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_MSB 29 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_BITS 0x10000000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_MSB 28 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_LSB _u(28) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_BITS 0x08000000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_MSB 27 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_LSB _u(27) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_BITS 0x04000000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_MSB 26 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_LSB _u(26) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_BITS 0x02000000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_MSB 25 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_BITS 0x01000000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_MSB 24 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_LSB _u(24) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_BANK0_DORMANT_WAKE_INTS3 // Description : Interrupt status after masking & forcing for dormant_wake -#define IO_BANK0_DORMANT_WAKE_INTS3_OFFSET 0x0000018c -#define IO_BANK0_DORMANT_WAKE_INTS3_BITS 0x00ffffff -#define IO_BANK0_DORMANT_WAKE_INTS3_RESET 0x00000000 +#define IO_BANK0_DORMANT_WAKE_INTS3_OFFSET _u(0x0000018c) +#define IO_BANK0_DORMANT_WAKE_INTS3_BITS _u(0x00ffffff) +#define IO_BANK0_DORMANT_WAKE_INTS3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_BITS 0x00800000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_MSB 23 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_LSB _u(23) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_BITS 0x00400000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_MSB 22 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_LSB _u(22) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_BITS 0x00200000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_MSB 21 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_BITS 0x00100000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_MSB 20 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_LSB _u(20) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_BITS 0x00080000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_MSB 19 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_LSB _u(19) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_BITS 0x00040000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_MSB 18 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_LSB _u(18) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_BITS 0x00020000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_MSB 17 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_BITS 0x00010000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_MSB 16 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_LSB _u(16) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_BITS 0x00008000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_MSB 15 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_LSB _u(15) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_BITS 0x00004000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_MSB 14 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_LSB _u(14) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_BITS 0x00002000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_MSB 13 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_BITS 0x00001000 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_MSB 12 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_LSB _u(12) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_BITS 0x00000800 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_MSB 11 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_LSB _u(11) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_BITS 0x00000400 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_MSB 10 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_LSB _u(10) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_BITS 0x00000200 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_MSB 9 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_BITS 0x00000100 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_MSB 8 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_LSB _u(8) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_BITS 0x00000080 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_MSB 7 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_LSB _u(7) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_BITS 0x00000040 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_MSB 6 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_LSB _u(6) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_BITS 0x00000020 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_MSB 5 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_BITS 0x00000010 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_MSB 4 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_LSB _u(4) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_BITS 0x00000008 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_MSB 3 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_LSB _u(3) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_BITS 0x00000004 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_MSB 2 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_LSB _u(2) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_BITS 0x00000002 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_MSB 1 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW // Description : None -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_RESET 0x0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_BITS 0x00000001 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_MSB 0 -#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_IO_BANK0_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_qspi.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_qspi.h index 0c7c88d53..7c381b7a5 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_qspi.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/io_qspi.h @@ -14,111 +14,111 @@ // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SCLK_STATUS // Description : GPIO status -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET 0x00000000 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_BITS 0x050a3300 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_RESET 0x00000000 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET _u(0x00000000) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_BITS _u(0x050a3300) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_MSB 26 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_LSB _u(26) #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_MSB 24 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_LSB _u(24) #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_BITS 0x00080000 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_MSB 19 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_MSB _u(19) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_LSB _u(19) #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_MSB 17 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_LSB _u(17) #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_BITS 0x00002000 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_MSB 13 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_LSB _u(13) #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_MSB 12 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_MSB _u(12) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_MSB 9 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_LSB _u(9) #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_MSB 8 -#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SCLK_CTRL // Description : GPIO control including function select and overrides. -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET 0x00000004 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_BITS 0x3003331f -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_RESET 0x0000001f +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET _u(0x00000004) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_BITS _u(0x3003331f) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_BITS 0x30000000 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_MSB 29 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LSB _u(28) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_BITS 0x00030000 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_MSB 17 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LSB _u(16) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -127,15 +127,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_BITS 0x00003000 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_MSB 13 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -143,15 +143,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_BITS 0x00000300 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_MSB 9 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -159,122 +159,122 @@ // 0x00 -> xip_sclk // 0x05 -> sio_30 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_RESET 0x1f -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_MSB 4 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_LSB _u(0) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_XIP_SCLK 0x00 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIO_30 0x05 -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_XIP_SCLK _u(0x00) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIO_30 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SS_STATUS // Description : GPIO status -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OFFSET 0x00000008 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_BITS 0x050a3300 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_RESET 0x00000000 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OFFSET _u(0x00000008) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_BITS _u(0x050a3300) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_MSB 26 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_LSB _u(26) #define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_MSB 24 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_LSB _u(24) #define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_BITS 0x00080000 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_MSB 19 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_MSB _u(19) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_LSB _u(19) #define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_MSB 17 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_LSB _u(17) #define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_BITS 0x00002000 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_MSB 13 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_LSB _u(13) #define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_MSB 12 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_MSB _u(12) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_MSB 9 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_LSB _u(9) #define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_MSB 8 -#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SS_CTRL // Description : GPIO control including function select and overrides. -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OFFSET 0x0000000c -#define IO_QSPI_GPIO_QSPI_SS_CTRL_BITS 0x3003331f -#define IO_QSPI_GPIO_QSPI_SS_CTRL_RESET 0x0000001f +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OFFSET _u(0x0000000c) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_BITS _u(0x3003331f) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_BITS 0x30000000 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_MSB 29 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LSB _u(28) #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_BITS 0x00030000 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_MSB 17 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LSB _u(16) #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -283,15 +283,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS 0x00003000 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_MSB 13 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -299,15 +299,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS 0x00000300 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MSB 9 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -315,122 +315,122 @@ // 0x00 -> xip_ss_n // 0x05 -> sio_31 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_RESET 0x1f -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_MSB 4 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_LSB _u(0) #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_XIP_SS_N 0x00 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIO_31 0x05 -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_XIP_SS_N _u(0x00) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIO_31 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD0_STATUS // Description : GPIO status -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OFFSET 0x00000010 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_BITS 0x050a3300 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_RESET 0x00000000 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OFFSET _u(0x00000010) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_BITS _u(0x050a3300) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_MSB 26 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_LSB _u(26) #define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_MSB 24 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_LSB _u(24) #define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_BITS 0x00080000 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_MSB 19 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_MSB _u(19) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_LSB _u(19) #define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_MSB 17 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_LSB _u(17) #define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_BITS 0x00002000 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_MSB 13 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_LSB _u(13) #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_MSB 12 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_MSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_MSB 9 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_LSB _u(9) #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_MSB 8 -#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD0_CTRL // Description : GPIO control including function select and overrides. -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OFFSET 0x00000014 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_BITS 0x3003331f -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_RESET 0x0000001f +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OFFSET _u(0x00000014) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_BITS _u(0x3003331f) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_BITS 0x30000000 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_MSB 29 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LSB _u(28) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_BITS 0x00030000 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_MSB 17 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LSB _u(16) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -439,15 +439,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_BITS 0x00003000 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_MSB 13 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -455,15 +455,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_BITS 0x00000300 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_MSB 9 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -471,122 +471,122 @@ // 0x00 -> xip_sd0 // 0x05 -> sio_32 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_RESET 0x1f -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_MSB 4 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_LSB _u(0) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_XIP_SD0 0x00 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIO_32 0x05 -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_XIP_SD0 _u(0x00) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIO_32 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD1_STATUS // Description : GPIO status -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OFFSET 0x00000018 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_BITS 0x050a3300 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_RESET 0x00000000 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OFFSET _u(0x00000018) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_BITS _u(0x050a3300) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_MSB 26 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_LSB _u(26) #define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_MSB 24 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_LSB _u(24) #define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_BITS 0x00080000 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_MSB 19 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_MSB _u(19) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_LSB _u(19) #define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_MSB 17 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_LSB _u(17) #define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_BITS 0x00002000 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_MSB 13 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_LSB _u(13) #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_MSB 12 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_MSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_MSB 9 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_LSB _u(9) #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_MSB 8 -#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD1_CTRL // Description : GPIO control including function select and overrides. -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OFFSET 0x0000001c -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_BITS 0x3003331f -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_RESET 0x0000001f +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OFFSET _u(0x0000001c) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_BITS _u(0x3003331f) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_BITS 0x30000000 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_MSB 29 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LSB _u(28) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_BITS 0x00030000 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_MSB 17 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LSB _u(16) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -595,15 +595,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_BITS 0x00003000 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_MSB 13 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -611,15 +611,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_BITS 0x00000300 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_MSB 9 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -627,122 +627,122 @@ // 0x00 -> xip_sd1 // 0x05 -> sio_33 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_RESET 0x1f -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_MSB 4 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_LSB _u(0) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_XIP_SD1 0x00 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIO_33 0x05 -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_XIP_SD1 _u(0x00) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIO_33 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD2_STATUS // Description : GPIO status -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OFFSET 0x00000020 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_BITS 0x050a3300 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_RESET 0x00000000 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OFFSET _u(0x00000020) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_BITS _u(0x050a3300) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_MSB 26 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_LSB _u(26) #define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_MSB 24 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_LSB _u(24) #define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_BITS 0x00080000 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_MSB 19 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_MSB _u(19) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_LSB _u(19) #define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_MSB 17 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_LSB _u(17) #define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_BITS 0x00002000 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_MSB 13 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_LSB _u(13) #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_MSB 12 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_MSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_MSB 9 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_LSB _u(9) #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_MSB 8 -#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD2_CTRL // Description : GPIO control including function select and overrides. -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OFFSET 0x00000024 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_BITS 0x3003331f -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_RESET 0x0000001f +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OFFSET _u(0x00000024) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_BITS _u(0x3003331f) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_BITS 0x30000000 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_MSB 29 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LSB _u(28) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_BITS 0x00030000 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_MSB 17 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LSB _u(16) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -751,15 +751,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_BITS 0x00003000 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_MSB 13 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -767,15 +767,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_BITS 0x00000300 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_MSB 9 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -783,122 +783,122 @@ // 0x00 -> xip_sd2 // 0x05 -> sio_34 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_RESET 0x1f -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_MSB 4 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_LSB _u(0) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_XIP_SD2 0x00 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIO_34 0x05 -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_XIP_SD2 _u(0x00) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIO_34 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD3_STATUS // Description : GPIO status -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OFFSET 0x00000028 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_BITS 0x050a3300 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_RESET 0x00000000 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OFFSET _u(0x00000028) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_BITS _u(0x050a3300) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC // Description : interrupt to processors, after override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_BITS 0x04000000 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_MSB 26 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_LSB _u(26) #define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD // Description : interrupt from pad before override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_BITS 0x01000000 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_MSB 24 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_BITS _u(0x01000000) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_MSB _u(24) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_LSB _u(24) #define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI // Description : input signal to peripheral, after override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_BITS 0x00080000 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_MSB 19 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_BITS _u(0x00080000) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_MSB _u(19) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_LSB _u(19) #define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD // Description : input signal from pad, before override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_BITS 0x00020000 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_MSB 17 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_LSB _u(17) #define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD // Description : output enable to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_BITS 0x00002000 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_MSB 13 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_LSB _u(13) #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI // Description : output enable from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_BITS 0x00001000 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_MSB 12 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_BITS _u(0x00001000) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_MSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD // Description : output signal to pad after register override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_BITS 0x00000200 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_MSB 9 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_LSB _u(9) #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI // Description : output signal from selected peripheral, before register // override is applied -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_BITS 0x00000100 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_MSB 8 -#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_BITS _u(0x00000100) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_MSB _u(8) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_ACCESS "RO" // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD3_CTRL // Description : GPIO control including function select and overrides. -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OFFSET 0x0000002c -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_BITS 0x3003331f -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_RESET 0x0000001f +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OFFSET _u(0x0000002c) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_BITS _u(0x3003331f) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER // Description : 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_BITS 0x30000000 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_MSB 29 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LSB _u(28) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER // Description : 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_BITS 0x00030000 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_MSB 17 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LSB _u(16) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER // Description : 0x0 -> drive output enable from peripheral signal selected by @@ -907,15 +907,15 @@ // selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_BITS 0x00003000 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_MSB 13 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_LSB _u(12) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_DISABLE 0x2 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_ENABLE 0x3 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER // Description : 0x0 -> drive output from peripheral signal selected by funcsel @@ -923,15 +923,15 @@ // by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_BITS 0x00000300 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_MSB 9 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LSB _u(8) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_NORMAL 0x0 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_INVERT 0x1 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_LOW 0x2 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -939,1993 +939,1993 @@ // 0x00 -> xip_sd3 // 0x05 -> sio_35 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_RESET 0x1f -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_BITS 0x0000001f -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_MSB 4 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_LSB _u(0) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_XIP_SD3 0x00 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIO_35 0x05 -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_NULL 0x1f +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_XIP_SD3 _u(0x00) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIO_35 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_INTR // Description : Raw Interrupts -#define IO_QSPI_INTR_OFFSET 0x00000030 -#define IO_QSPI_INTR_BITS 0x00ffffff -#define IO_QSPI_INTR_RESET 0x00000000 +#define IO_QSPI_INTR_OFFSET _u(0x00000030) +#define IO_QSPI_INTR_BITS _u(0x00ffffff) +#define IO_QSPI_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 -#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 -#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 -#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 -#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_MSB 6 -#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 -#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW // Description : None -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 -#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_QSPI_PROC0_INTE // Description : Interrupt Enable for proc0 -#define IO_QSPI_PROC0_INTE_OFFSET 0x00000034 -#define IO_QSPI_PROC0_INTE_BITS 0x00ffffff -#define IO_QSPI_PROC0_INTE_RESET 0x00000000 +#define IO_QSPI_PROC0_INTE_OFFSET _u(0x00000034) +#define IO_QSPI_PROC0_INTE_BITS _u(0x00ffffff) +#define IO_QSPI_PROC0_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB 6 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 -#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_QSPI_PROC0_INTF // Description : Interrupt Force for proc0 -#define IO_QSPI_PROC0_INTF_OFFSET 0x00000038 -#define IO_QSPI_PROC0_INTF_BITS 0x00ffffff -#define IO_QSPI_PROC0_INTF_RESET 0x00000000 +#define IO_QSPI_PROC0_INTF_OFFSET _u(0x00000038) +#define IO_QSPI_PROC0_INTF_BITS _u(0x00ffffff) +#define IO_QSPI_PROC0_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB 6 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 -#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_QSPI_PROC0_INTS // Description : Interrupt status after masking & forcing for proc0 -#define IO_QSPI_PROC0_INTS_OFFSET 0x0000003c -#define IO_QSPI_PROC0_INTS_BITS 0x00ffffff -#define IO_QSPI_PROC0_INTS_RESET 0x00000000 +#define IO_QSPI_PROC0_INTS_OFFSET _u(0x0000003c) +#define IO_QSPI_PROC0_INTS_BITS _u(0x00ffffff) +#define IO_QSPI_PROC0_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB 6 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW // Description : None -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 -#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_QSPI_PROC1_INTE // Description : Interrupt Enable for proc1 -#define IO_QSPI_PROC1_INTE_OFFSET 0x00000040 -#define IO_QSPI_PROC1_INTE_BITS 0x00ffffff -#define IO_QSPI_PROC1_INTE_RESET 0x00000000 +#define IO_QSPI_PROC1_INTE_OFFSET _u(0x00000040) +#define IO_QSPI_PROC1_INTE_BITS _u(0x00ffffff) +#define IO_QSPI_PROC1_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB 6 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 -#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_QSPI_PROC1_INTF // Description : Interrupt Force for proc1 -#define IO_QSPI_PROC1_INTF_OFFSET 0x00000044 -#define IO_QSPI_PROC1_INTF_BITS 0x00ffffff -#define IO_QSPI_PROC1_INTF_RESET 0x00000000 +#define IO_QSPI_PROC1_INTF_OFFSET _u(0x00000044) +#define IO_QSPI_PROC1_INTF_BITS _u(0x00ffffff) +#define IO_QSPI_PROC1_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB 6 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 -#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_QSPI_PROC1_INTS // Description : Interrupt status after masking & forcing for proc1 -#define IO_QSPI_PROC1_INTS_OFFSET 0x00000048 -#define IO_QSPI_PROC1_INTS_BITS 0x00ffffff -#define IO_QSPI_PROC1_INTS_RESET 0x00000000 +#define IO_QSPI_PROC1_INTS_OFFSET _u(0x00000048) +#define IO_QSPI_PROC1_INTS_BITS _u(0x00ffffff) +#define IO_QSPI_PROC1_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB 6 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW // Description : None -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 -#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" // ============================================================================= // Register : IO_QSPI_DORMANT_WAKE_INTE // Description : Interrupt Enable for dormant_wake -#define IO_QSPI_DORMANT_WAKE_INTE_OFFSET 0x0000004c -#define IO_QSPI_DORMANT_WAKE_INTE_BITS 0x00ffffff -#define IO_QSPI_DORMANT_WAKE_INTE_RESET 0x00000000 +#define IO_QSPI_DORMANT_WAKE_INTE_OFFSET _u(0x0000004c) +#define IO_QSPI_DORMANT_WAKE_INTE_BITS _u(0x00ffffff) +#define IO_QSPI_DORMANT_WAKE_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB 6 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 -#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_QSPI_DORMANT_WAKE_INTF // Description : Interrupt Force for dormant_wake -#define IO_QSPI_DORMANT_WAKE_INTF_OFFSET 0x00000050 -#define IO_QSPI_DORMANT_WAKE_INTF_BITS 0x00ffffff -#define IO_QSPI_DORMANT_WAKE_INTF_RESET 0x00000000 +#define IO_QSPI_DORMANT_WAKE_INTF_OFFSET _u(0x00000050) +#define IO_QSPI_DORMANT_WAKE_INTF_BITS _u(0x00ffffff) +#define IO_QSPI_DORMANT_WAKE_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB 6 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 -#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" // ============================================================================= // Register : IO_QSPI_DORMANT_WAKE_INTS // Description : Interrupt status after masking & forcing for dormant_wake -#define IO_QSPI_DORMANT_WAKE_INTS_OFFSET 0x00000054 -#define IO_QSPI_DORMANT_WAKE_INTS_BITS 0x00ffffff -#define IO_QSPI_DORMANT_WAKE_INTS_RESET 0x00000000 +#define IO_QSPI_DORMANT_WAKE_INTS_OFFSET _u(0x00000054) +#define IO_QSPI_DORMANT_WAKE_INTS_BITS _u(0x00ffffff) +#define IO_QSPI_DORMANT_WAKE_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB 6 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW // Description : None -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 -#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_IO_QSPI_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/m0plus.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/m0plus.h index fac8e8b55..cef5ab0a1 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/m0plus.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/m0plus.h @@ -15,17 +15,17 @@ // Register : M0PLUS_SYST_CSR // Description : Use the SysTick Control and Status Register to enable the // SysTick features. -#define M0PLUS_SYST_CSR_OFFSET 0x0000e010 -#define M0PLUS_SYST_CSR_BITS 0x00010007 -#define M0PLUS_SYST_CSR_RESET 0x00000000 +#define M0PLUS_SYST_CSR_OFFSET _u(0x0000e010) +#define M0PLUS_SYST_CSR_BITS _u(0x00010007) +#define M0PLUS_SYST_CSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_SYST_CSR_COUNTFLAG // Description : Returns 1 if timer counted to 0 since last time this was read. // Clears on read by application or debugger. -#define M0PLUS_SYST_CSR_COUNTFLAG_RESET 0x0 -#define M0PLUS_SYST_CSR_COUNTFLAG_BITS 0x00010000 -#define M0PLUS_SYST_CSR_COUNTFLAG_MSB 16 -#define M0PLUS_SYST_CSR_COUNTFLAG_LSB 16 +#define M0PLUS_SYST_CSR_COUNTFLAG_RESET _u(0x0) +#define M0PLUS_SYST_CSR_COUNTFLAG_BITS _u(0x00010000) +#define M0PLUS_SYST_CSR_COUNTFLAG_MSB _u(16) +#define M0PLUS_SYST_CSR_COUNTFLAG_LSB _u(16) #define M0PLUS_SYST_CSR_COUNTFLAG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_SYST_CSR_CLKSOURCE @@ -34,10 +34,10 @@ // Selects the SysTick timer clock source: // 0 = External reference clock. // 1 = Processor clock. -#define M0PLUS_SYST_CSR_CLKSOURCE_RESET 0x0 -#define M0PLUS_SYST_CSR_CLKSOURCE_BITS 0x00000004 -#define M0PLUS_SYST_CSR_CLKSOURCE_MSB 2 -#define M0PLUS_SYST_CSR_CLKSOURCE_LSB 2 +#define M0PLUS_SYST_CSR_CLKSOURCE_RESET _u(0x0) +#define M0PLUS_SYST_CSR_CLKSOURCE_BITS _u(0x00000004) +#define M0PLUS_SYST_CSR_CLKSOURCE_MSB _u(2) +#define M0PLUS_SYST_CSR_CLKSOURCE_LSB _u(2) #define M0PLUS_SYST_CSR_CLKSOURCE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_SYST_CSR_TICKINT @@ -46,20 +46,20 @@ // request. // 1 = Counting down to zero to asserts the SysTick exception // request. -#define M0PLUS_SYST_CSR_TICKINT_RESET 0x0 -#define M0PLUS_SYST_CSR_TICKINT_BITS 0x00000002 -#define M0PLUS_SYST_CSR_TICKINT_MSB 1 -#define M0PLUS_SYST_CSR_TICKINT_LSB 1 +#define M0PLUS_SYST_CSR_TICKINT_RESET _u(0x0) +#define M0PLUS_SYST_CSR_TICKINT_BITS _u(0x00000002) +#define M0PLUS_SYST_CSR_TICKINT_MSB _u(1) +#define M0PLUS_SYST_CSR_TICKINT_LSB _u(1) #define M0PLUS_SYST_CSR_TICKINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_SYST_CSR_ENABLE // Description : Enable SysTick counter: // 0 = Counter disabled. // 1 = Counter enabled. -#define M0PLUS_SYST_CSR_ENABLE_RESET 0x0 -#define M0PLUS_SYST_CSR_ENABLE_BITS 0x00000001 -#define M0PLUS_SYST_CSR_ENABLE_MSB 0 -#define M0PLUS_SYST_CSR_ENABLE_LSB 0 +#define M0PLUS_SYST_CSR_ENABLE_RESET _u(0x0) +#define M0PLUS_SYST_CSR_ENABLE_BITS _u(0x00000001) +#define M0PLUS_SYST_CSR_ENABLE_MSB _u(0) +#define M0PLUS_SYST_CSR_ENABLE_LSB _u(0) #define M0PLUS_SYST_CSR_ENABLE_ACCESS "RW" // ============================================================================= // Register : M0PLUS_SYST_RVR @@ -73,72 +73,72 @@ // clock cycles, use a RELOAD value of N-1. For example, if the // SysTick interrupt is required every 100 clock pulses, set // RELOAD to 99. -#define M0PLUS_SYST_RVR_OFFSET 0x0000e014 -#define M0PLUS_SYST_RVR_BITS 0x00ffffff -#define M0PLUS_SYST_RVR_RESET 0x00000000 +#define M0PLUS_SYST_RVR_OFFSET _u(0x0000e014) +#define M0PLUS_SYST_RVR_BITS _u(0x00ffffff) +#define M0PLUS_SYST_RVR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_SYST_RVR_RELOAD // Description : Value to load into the SysTick Current Value Register when the // counter reaches 0. -#define M0PLUS_SYST_RVR_RELOAD_RESET 0x000000 -#define M0PLUS_SYST_RVR_RELOAD_BITS 0x00ffffff -#define M0PLUS_SYST_RVR_RELOAD_MSB 23 -#define M0PLUS_SYST_RVR_RELOAD_LSB 0 +#define M0PLUS_SYST_RVR_RELOAD_RESET _u(0x000000) +#define M0PLUS_SYST_RVR_RELOAD_BITS _u(0x00ffffff) +#define M0PLUS_SYST_RVR_RELOAD_MSB _u(23) +#define M0PLUS_SYST_RVR_RELOAD_LSB _u(0) #define M0PLUS_SYST_RVR_RELOAD_ACCESS "RW" // ============================================================================= // Register : M0PLUS_SYST_CVR // Description : Use the SysTick Current Value Register to find the current // value in the register. The reset value of this register is // UNKNOWN. -#define M0PLUS_SYST_CVR_OFFSET 0x0000e018 -#define M0PLUS_SYST_CVR_BITS 0x00ffffff -#define M0PLUS_SYST_CVR_RESET 0x00000000 +#define M0PLUS_SYST_CVR_OFFSET _u(0x0000e018) +#define M0PLUS_SYST_CVR_BITS _u(0x00ffffff) +#define M0PLUS_SYST_CVR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_SYST_CVR_CURRENT // Description : Reads return the current value of the SysTick counter. This // register is write-clear. Writing to it with any value clears // the register to 0. Clearing this register also clears the // COUNTFLAG bit of the SysTick Control and Status Register. -#define M0PLUS_SYST_CVR_CURRENT_RESET 0x000000 -#define M0PLUS_SYST_CVR_CURRENT_BITS 0x00ffffff -#define M0PLUS_SYST_CVR_CURRENT_MSB 23 -#define M0PLUS_SYST_CVR_CURRENT_LSB 0 +#define M0PLUS_SYST_CVR_CURRENT_RESET _u(0x000000) +#define M0PLUS_SYST_CVR_CURRENT_BITS _u(0x00ffffff) +#define M0PLUS_SYST_CVR_CURRENT_MSB _u(23) +#define M0PLUS_SYST_CVR_CURRENT_LSB _u(0) #define M0PLUS_SYST_CVR_CURRENT_ACCESS "RW" // ============================================================================= // Register : M0PLUS_SYST_CALIB // Description : Use the SysTick Calibration Value Register to enable software // to scale to any required speed using divide and multiply. -#define M0PLUS_SYST_CALIB_OFFSET 0x0000e01c -#define M0PLUS_SYST_CALIB_BITS 0xc0ffffff -#define M0PLUS_SYST_CALIB_RESET 0x00000000 +#define M0PLUS_SYST_CALIB_OFFSET _u(0x0000e01c) +#define M0PLUS_SYST_CALIB_BITS _u(0xc0ffffff) +#define M0PLUS_SYST_CALIB_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_SYST_CALIB_NOREF // Description : If reads as 1, the Reference clock is not provided - the // CLKSOURCE bit of the SysTick Control and Status register will // be forced to 1 and cannot be cleared to 0. -#define M0PLUS_SYST_CALIB_NOREF_RESET 0x0 -#define M0PLUS_SYST_CALIB_NOREF_BITS 0x80000000 -#define M0PLUS_SYST_CALIB_NOREF_MSB 31 -#define M0PLUS_SYST_CALIB_NOREF_LSB 31 +#define M0PLUS_SYST_CALIB_NOREF_RESET _u(0x0) +#define M0PLUS_SYST_CALIB_NOREF_BITS _u(0x80000000) +#define M0PLUS_SYST_CALIB_NOREF_MSB _u(31) +#define M0PLUS_SYST_CALIB_NOREF_LSB _u(31) #define M0PLUS_SYST_CALIB_NOREF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_SYST_CALIB_SKEW // Description : If reads as 1, the calibration value for 10ms is inexact (due // to clock frequency). -#define M0PLUS_SYST_CALIB_SKEW_RESET 0x0 -#define M0PLUS_SYST_CALIB_SKEW_BITS 0x40000000 -#define M0PLUS_SYST_CALIB_SKEW_MSB 30 -#define M0PLUS_SYST_CALIB_SKEW_LSB 30 +#define M0PLUS_SYST_CALIB_SKEW_RESET _u(0x0) +#define M0PLUS_SYST_CALIB_SKEW_BITS _u(0x40000000) +#define M0PLUS_SYST_CALIB_SKEW_MSB _u(30) +#define M0PLUS_SYST_CALIB_SKEW_LSB _u(30) #define M0PLUS_SYST_CALIB_SKEW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_SYST_CALIB_TENMS // Description : An optional Reload value to be used for 10ms (100Hz) timing, // subject to system clock skew errors. If the value reads as 0, // the calibration value is not known. -#define M0PLUS_SYST_CALIB_TENMS_RESET 0x000000 -#define M0PLUS_SYST_CALIB_TENMS_BITS 0x00ffffff -#define M0PLUS_SYST_CALIB_TENMS_MSB 23 -#define M0PLUS_SYST_CALIB_TENMS_LSB 0 +#define M0PLUS_SYST_CALIB_TENMS_RESET _u(0x000000) +#define M0PLUS_SYST_CALIB_TENMS_BITS _u(0x00ffffff) +#define M0PLUS_SYST_CALIB_TENMS_MSB _u(23) +#define M0PLUS_SYST_CALIB_TENMS_LSB _u(0) #define M0PLUS_SYST_CALIB_TENMS_ACCESS "RO" // ============================================================================= // Register : M0PLUS_NVIC_ISER @@ -149,9 +149,9 @@ // enabled, asserting its interrupt signal changes the interrupt // state to pending, but the NVIC never activates the interrupt, // regardless of its priority. -#define M0PLUS_NVIC_ISER_OFFSET 0x0000e100 -#define M0PLUS_NVIC_ISER_BITS 0xffffffff -#define M0PLUS_NVIC_ISER_RESET 0x00000000 +#define M0PLUS_NVIC_ISER_OFFSET _u(0x0000e100) +#define M0PLUS_NVIC_ISER_BITS _u(0xffffffff) +#define M0PLUS_NVIC_ISER_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_ISER_SETENA // Description : Interrupt set-enable bits. @@ -161,18 +161,18 @@ // Read: // 0 = Interrupt disabled. // 1 = Interrupt enabled. -#define M0PLUS_NVIC_ISER_SETENA_RESET 0x00000000 -#define M0PLUS_NVIC_ISER_SETENA_BITS 0xffffffff -#define M0PLUS_NVIC_ISER_SETENA_MSB 31 -#define M0PLUS_NVIC_ISER_SETENA_LSB 0 +#define M0PLUS_NVIC_ISER_SETENA_RESET _u(0x00000000) +#define M0PLUS_NVIC_ISER_SETENA_BITS _u(0xffffffff) +#define M0PLUS_NVIC_ISER_SETENA_MSB _u(31) +#define M0PLUS_NVIC_ISER_SETENA_LSB _u(0) #define M0PLUS_NVIC_ISER_SETENA_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_ICER // Description : Use the Interrupt Clear-Enable Registers to disable interrupts // and determine which interrupts are currently enabled. -#define M0PLUS_NVIC_ICER_OFFSET 0x0000e180 -#define M0PLUS_NVIC_ICER_BITS 0xffffffff -#define M0PLUS_NVIC_ICER_RESET 0x00000000 +#define M0PLUS_NVIC_ICER_OFFSET _u(0x0000e180) +#define M0PLUS_NVIC_ICER_BITS _u(0xffffffff) +#define M0PLUS_NVIC_ICER_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_ICER_CLRENA // Description : Interrupt clear-enable bits. @@ -182,18 +182,18 @@ // Read: // 0 = Interrupt disabled. // 1 = Interrupt enabled. -#define M0PLUS_NVIC_ICER_CLRENA_RESET 0x00000000 -#define M0PLUS_NVIC_ICER_CLRENA_BITS 0xffffffff -#define M0PLUS_NVIC_ICER_CLRENA_MSB 31 -#define M0PLUS_NVIC_ICER_CLRENA_LSB 0 +#define M0PLUS_NVIC_ICER_CLRENA_RESET _u(0x00000000) +#define M0PLUS_NVIC_ICER_CLRENA_BITS _u(0xffffffff) +#define M0PLUS_NVIC_ICER_CLRENA_MSB _u(31) +#define M0PLUS_NVIC_ICER_CLRENA_LSB _u(0) #define M0PLUS_NVIC_ICER_CLRENA_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_ISPR // Description : The NVIC_ISPR forces interrupts into the pending state, and // shows which interrupts are pending. -#define M0PLUS_NVIC_ISPR_OFFSET 0x0000e200 -#define M0PLUS_NVIC_ISPR_BITS 0xffffffff -#define M0PLUS_NVIC_ISPR_RESET 0x00000000 +#define M0PLUS_NVIC_ISPR_OFFSET _u(0x0000e200) +#define M0PLUS_NVIC_ISPR_BITS _u(0xffffffff) +#define M0PLUS_NVIC_ISPR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_ISPR_SETPEND // Description : Interrupt set-pending bits. @@ -207,19 +207,19 @@ // An interrupt that is pending has no effect. // A disabled interrupt sets the state of that interrupt to // pending. -#define M0PLUS_NVIC_ISPR_SETPEND_RESET 0x00000000 -#define M0PLUS_NVIC_ISPR_SETPEND_BITS 0xffffffff -#define M0PLUS_NVIC_ISPR_SETPEND_MSB 31 -#define M0PLUS_NVIC_ISPR_SETPEND_LSB 0 +#define M0PLUS_NVIC_ISPR_SETPEND_RESET _u(0x00000000) +#define M0PLUS_NVIC_ISPR_SETPEND_BITS _u(0xffffffff) +#define M0PLUS_NVIC_ISPR_SETPEND_MSB _u(31) +#define M0PLUS_NVIC_ISPR_SETPEND_LSB _u(0) #define M0PLUS_NVIC_ISPR_SETPEND_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_ICPR // Description : Use the Interrupt Clear-Pending Register to clear pending // interrupts and determine which interrupts are currently // pending. -#define M0PLUS_NVIC_ICPR_OFFSET 0x0000e280 -#define M0PLUS_NVIC_ICPR_BITS 0xffffffff -#define M0PLUS_NVIC_ICPR_RESET 0x00000000 +#define M0PLUS_NVIC_ICPR_OFFSET _u(0x0000e280) +#define M0PLUS_NVIC_ICPR_BITS _u(0xffffffff) +#define M0PLUS_NVIC_ICPR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_ICPR_CLRPEND // Description : Interrupt clear-pending bits. @@ -229,10 +229,10 @@ // Read: // 0 = Interrupt is not pending. // 1 = Interrupt is pending. -#define M0PLUS_NVIC_ICPR_CLRPEND_RESET 0x00000000 -#define M0PLUS_NVIC_ICPR_CLRPEND_BITS 0xffffffff -#define M0PLUS_NVIC_ICPR_CLRPEND_MSB 31 -#define M0PLUS_NVIC_ICPR_CLRPEND_LSB 0 +#define M0PLUS_NVIC_ICPR_CLRPEND_RESET _u(0x00000000) +#define M0PLUS_NVIC_ICPR_CLRPEND_BITS _u(0xffffffff) +#define M0PLUS_NVIC_ICPR_CLRPEND_MSB _u(31) +#define M0PLUS_NVIC_ICPR_CLRPEND_LSB _u(0) #define M0PLUS_NVIC_ICPR_CLRPEND_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_IPR0 @@ -242,371 +242,371 @@ // Note: Writing 1 to an NVIC_ICPR bit does not affect the active // state of the corresponding interrupt. // These registers are only word-accessible -#define M0PLUS_NVIC_IPR0_OFFSET 0x0000e400 -#define M0PLUS_NVIC_IPR0_BITS 0xc0c0c0c0 -#define M0PLUS_NVIC_IPR0_RESET 0x00000000 +#define M0PLUS_NVIC_IPR0_OFFSET _u(0x0000e400) +#define M0PLUS_NVIC_IPR0_BITS _u(0xc0c0c0c0) +#define M0PLUS_NVIC_IPR0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR0_IP_3 // Description : Priority of interrupt 3 -#define M0PLUS_NVIC_IPR0_IP_3_RESET 0x0 -#define M0PLUS_NVIC_IPR0_IP_3_BITS 0xc0000000 -#define M0PLUS_NVIC_IPR0_IP_3_MSB 31 -#define M0PLUS_NVIC_IPR0_IP_3_LSB 30 +#define M0PLUS_NVIC_IPR0_IP_3_RESET _u(0x0) +#define M0PLUS_NVIC_IPR0_IP_3_BITS _u(0xc0000000) +#define M0PLUS_NVIC_IPR0_IP_3_MSB _u(31) +#define M0PLUS_NVIC_IPR0_IP_3_LSB _u(30) #define M0PLUS_NVIC_IPR0_IP_3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR0_IP_2 // Description : Priority of interrupt 2 -#define M0PLUS_NVIC_IPR0_IP_2_RESET 0x0 -#define M0PLUS_NVIC_IPR0_IP_2_BITS 0x00c00000 -#define M0PLUS_NVIC_IPR0_IP_2_MSB 23 -#define M0PLUS_NVIC_IPR0_IP_2_LSB 22 +#define M0PLUS_NVIC_IPR0_IP_2_RESET _u(0x0) +#define M0PLUS_NVIC_IPR0_IP_2_BITS _u(0x00c00000) +#define M0PLUS_NVIC_IPR0_IP_2_MSB _u(23) +#define M0PLUS_NVIC_IPR0_IP_2_LSB _u(22) #define M0PLUS_NVIC_IPR0_IP_2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR0_IP_1 // Description : Priority of interrupt 1 -#define M0PLUS_NVIC_IPR0_IP_1_RESET 0x0 -#define M0PLUS_NVIC_IPR0_IP_1_BITS 0x0000c000 -#define M0PLUS_NVIC_IPR0_IP_1_MSB 15 -#define M0PLUS_NVIC_IPR0_IP_1_LSB 14 +#define M0PLUS_NVIC_IPR0_IP_1_RESET _u(0x0) +#define M0PLUS_NVIC_IPR0_IP_1_BITS _u(0x0000c000) +#define M0PLUS_NVIC_IPR0_IP_1_MSB _u(15) +#define M0PLUS_NVIC_IPR0_IP_1_LSB _u(14) #define M0PLUS_NVIC_IPR0_IP_1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR0_IP_0 // Description : Priority of interrupt 0 -#define M0PLUS_NVIC_IPR0_IP_0_RESET 0x0 -#define M0PLUS_NVIC_IPR0_IP_0_BITS 0x000000c0 -#define M0PLUS_NVIC_IPR0_IP_0_MSB 7 -#define M0PLUS_NVIC_IPR0_IP_0_LSB 6 +#define M0PLUS_NVIC_IPR0_IP_0_RESET _u(0x0) +#define M0PLUS_NVIC_IPR0_IP_0_BITS _u(0x000000c0) +#define M0PLUS_NVIC_IPR0_IP_0_MSB _u(7) +#define M0PLUS_NVIC_IPR0_IP_0_LSB _u(6) #define M0PLUS_NVIC_IPR0_IP_0_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_IPR1 // Description : Use the Interrupt Priority Registers to assign a priority from // 0 to 3 to each of the available interrupts. 0 is the highest // priority, and 3 is the lowest. -#define M0PLUS_NVIC_IPR1_OFFSET 0x0000e404 -#define M0PLUS_NVIC_IPR1_BITS 0xc0c0c0c0 -#define M0PLUS_NVIC_IPR1_RESET 0x00000000 +#define M0PLUS_NVIC_IPR1_OFFSET _u(0x0000e404) +#define M0PLUS_NVIC_IPR1_BITS _u(0xc0c0c0c0) +#define M0PLUS_NVIC_IPR1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR1_IP_7 // Description : Priority of interrupt 7 -#define M0PLUS_NVIC_IPR1_IP_7_RESET 0x0 -#define M0PLUS_NVIC_IPR1_IP_7_BITS 0xc0000000 -#define M0PLUS_NVIC_IPR1_IP_7_MSB 31 -#define M0PLUS_NVIC_IPR1_IP_7_LSB 30 +#define M0PLUS_NVIC_IPR1_IP_7_RESET _u(0x0) +#define M0PLUS_NVIC_IPR1_IP_7_BITS _u(0xc0000000) +#define M0PLUS_NVIC_IPR1_IP_7_MSB _u(31) +#define M0PLUS_NVIC_IPR1_IP_7_LSB _u(30) #define M0PLUS_NVIC_IPR1_IP_7_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR1_IP_6 // Description : Priority of interrupt 6 -#define M0PLUS_NVIC_IPR1_IP_6_RESET 0x0 -#define M0PLUS_NVIC_IPR1_IP_6_BITS 0x00c00000 -#define M0PLUS_NVIC_IPR1_IP_6_MSB 23 -#define M0PLUS_NVIC_IPR1_IP_6_LSB 22 +#define M0PLUS_NVIC_IPR1_IP_6_RESET _u(0x0) +#define M0PLUS_NVIC_IPR1_IP_6_BITS _u(0x00c00000) +#define M0PLUS_NVIC_IPR1_IP_6_MSB _u(23) +#define M0PLUS_NVIC_IPR1_IP_6_LSB _u(22) #define M0PLUS_NVIC_IPR1_IP_6_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR1_IP_5 // Description : Priority of interrupt 5 -#define M0PLUS_NVIC_IPR1_IP_5_RESET 0x0 -#define M0PLUS_NVIC_IPR1_IP_5_BITS 0x0000c000 -#define M0PLUS_NVIC_IPR1_IP_5_MSB 15 -#define M0PLUS_NVIC_IPR1_IP_5_LSB 14 +#define M0PLUS_NVIC_IPR1_IP_5_RESET _u(0x0) +#define M0PLUS_NVIC_IPR1_IP_5_BITS _u(0x0000c000) +#define M0PLUS_NVIC_IPR1_IP_5_MSB _u(15) +#define M0PLUS_NVIC_IPR1_IP_5_LSB _u(14) #define M0PLUS_NVIC_IPR1_IP_5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR1_IP_4 // Description : Priority of interrupt 4 -#define M0PLUS_NVIC_IPR1_IP_4_RESET 0x0 -#define M0PLUS_NVIC_IPR1_IP_4_BITS 0x000000c0 -#define M0PLUS_NVIC_IPR1_IP_4_MSB 7 -#define M0PLUS_NVIC_IPR1_IP_4_LSB 6 +#define M0PLUS_NVIC_IPR1_IP_4_RESET _u(0x0) +#define M0PLUS_NVIC_IPR1_IP_4_BITS _u(0x000000c0) +#define M0PLUS_NVIC_IPR1_IP_4_MSB _u(7) +#define M0PLUS_NVIC_IPR1_IP_4_LSB _u(6) #define M0PLUS_NVIC_IPR1_IP_4_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_IPR2 // Description : Use the Interrupt Priority Registers to assign a priority from // 0 to 3 to each of the available interrupts. 0 is the highest // priority, and 3 is the lowest. -#define M0PLUS_NVIC_IPR2_OFFSET 0x0000e408 -#define M0PLUS_NVIC_IPR2_BITS 0xc0c0c0c0 -#define M0PLUS_NVIC_IPR2_RESET 0x00000000 +#define M0PLUS_NVIC_IPR2_OFFSET _u(0x0000e408) +#define M0PLUS_NVIC_IPR2_BITS _u(0xc0c0c0c0) +#define M0PLUS_NVIC_IPR2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR2_IP_11 // Description : Priority of interrupt 11 -#define M0PLUS_NVIC_IPR2_IP_11_RESET 0x0 -#define M0PLUS_NVIC_IPR2_IP_11_BITS 0xc0000000 -#define M0PLUS_NVIC_IPR2_IP_11_MSB 31 -#define M0PLUS_NVIC_IPR2_IP_11_LSB 30 +#define M0PLUS_NVIC_IPR2_IP_11_RESET _u(0x0) +#define M0PLUS_NVIC_IPR2_IP_11_BITS _u(0xc0000000) +#define M0PLUS_NVIC_IPR2_IP_11_MSB _u(31) +#define M0PLUS_NVIC_IPR2_IP_11_LSB _u(30) #define M0PLUS_NVIC_IPR2_IP_11_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR2_IP_10 // Description : Priority of interrupt 10 -#define M0PLUS_NVIC_IPR2_IP_10_RESET 0x0 -#define M0PLUS_NVIC_IPR2_IP_10_BITS 0x00c00000 -#define M0PLUS_NVIC_IPR2_IP_10_MSB 23 -#define M0PLUS_NVIC_IPR2_IP_10_LSB 22 +#define M0PLUS_NVIC_IPR2_IP_10_RESET _u(0x0) +#define M0PLUS_NVIC_IPR2_IP_10_BITS _u(0x00c00000) +#define M0PLUS_NVIC_IPR2_IP_10_MSB _u(23) +#define M0PLUS_NVIC_IPR2_IP_10_LSB _u(22) #define M0PLUS_NVIC_IPR2_IP_10_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR2_IP_9 // Description : Priority of interrupt 9 -#define M0PLUS_NVIC_IPR2_IP_9_RESET 0x0 -#define M0PLUS_NVIC_IPR2_IP_9_BITS 0x0000c000 -#define M0PLUS_NVIC_IPR2_IP_9_MSB 15 -#define M0PLUS_NVIC_IPR2_IP_9_LSB 14 +#define M0PLUS_NVIC_IPR2_IP_9_RESET _u(0x0) +#define M0PLUS_NVIC_IPR2_IP_9_BITS _u(0x0000c000) +#define M0PLUS_NVIC_IPR2_IP_9_MSB _u(15) +#define M0PLUS_NVIC_IPR2_IP_9_LSB _u(14) #define M0PLUS_NVIC_IPR2_IP_9_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR2_IP_8 // Description : Priority of interrupt 8 -#define M0PLUS_NVIC_IPR2_IP_8_RESET 0x0 -#define M0PLUS_NVIC_IPR2_IP_8_BITS 0x000000c0 -#define M0PLUS_NVIC_IPR2_IP_8_MSB 7 -#define M0PLUS_NVIC_IPR2_IP_8_LSB 6 +#define M0PLUS_NVIC_IPR2_IP_8_RESET _u(0x0) +#define M0PLUS_NVIC_IPR2_IP_8_BITS _u(0x000000c0) +#define M0PLUS_NVIC_IPR2_IP_8_MSB _u(7) +#define M0PLUS_NVIC_IPR2_IP_8_LSB _u(6) #define M0PLUS_NVIC_IPR2_IP_8_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_IPR3 // Description : Use the Interrupt Priority Registers to assign a priority from // 0 to 3 to each of the available interrupts. 0 is the highest // priority, and 3 is the lowest. -#define M0PLUS_NVIC_IPR3_OFFSET 0x0000e40c -#define M0PLUS_NVIC_IPR3_BITS 0xc0c0c0c0 -#define M0PLUS_NVIC_IPR3_RESET 0x00000000 +#define M0PLUS_NVIC_IPR3_OFFSET _u(0x0000e40c) +#define M0PLUS_NVIC_IPR3_BITS _u(0xc0c0c0c0) +#define M0PLUS_NVIC_IPR3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR3_IP_15 // Description : Priority of interrupt 15 -#define M0PLUS_NVIC_IPR3_IP_15_RESET 0x0 -#define M0PLUS_NVIC_IPR3_IP_15_BITS 0xc0000000 -#define M0PLUS_NVIC_IPR3_IP_15_MSB 31 -#define M0PLUS_NVIC_IPR3_IP_15_LSB 30 +#define M0PLUS_NVIC_IPR3_IP_15_RESET _u(0x0) +#define M0PLUS_NVIC_IPR3_IP_15_BITS _u(0xc0000000) +#define M0PLUS_NVIC_IPR3_IP_15_MSB _u(31) +#define M0PLUS_NVIC_IPR3_IP_15_LSB _u(30) #define M0PLUS_NVIC_IPR3_IP_15_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR3_IP_14 // Description : Priority of interrupt 14 -#define M0PLUS_NVIC_IPR3_IP_14_RESET 0x0 -#define M0PLUS_NVIC_IPR3_IP_14_BITS 0x00c00000 -#define M0PLUS_NVIC_IPR3_IP_14_MSB 23 -#define M0PLUS_NVIC_IPR3_IP_14_LSB 22 +#define M0PLUS_NVIC_IPR3_IP_14_RESET _u(0x0) +#define M0PLUS_NVIC_IPR3_IP_14_BITS _u(0x00c00000) +#define M0PLUS_NVIC_IPR3_IP_14_MSB _u(23) +#define M0PLUS_NVIC_IPR3_IP_14_LSB _u(22) #define M0PLUS_NVIC_IPR3_IP_14_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR3_IP_13 // Description : Priority of interrupt 13 -#define M0PLUS_NVIC_IPR3_IP_13_RESET 0x0 -#define M0PLUS_NVIC_IPR3_IP_13_BITS 0x0000c000 -#define M0PLUS_NVIC_IPR3_IP_13_MSB 15 -#define M0PLUS_NVIC_IPR3_IP_13_LSB 14 +#define M0PLUS_NVIC_IPR3_IP_13_RESET _u(0x0) +#define M0PLUS_NVIC_IPR3_IP_13_BITS _u(0x0000c000) +#define M0PLUS_NVIC_IPR3_IP_13_MSB _u(15) +#define M0PLUS_NVIC_IPR3_IP_13_LSB _u(14) #define M0PLUS_NVIC_IPR3_IP_13_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR3_IP_12 // Description : Priority of interrupt 12 -#define M0PLUS_NVIC_IPR3_IP_12_RESET 0x0 -#define M0PLUS_NVIC_IPR3_IP_12_BITS 0x000000c0 -#define M0PLUS_NVIC_IPR3_IP_12_MSB 7 -#define M0PLUS_NVIC_IPR3_IP_12_LSB 6 +#define M0PLUS_NVIC_IPR3_IP_12_RESET _u(0x0) +#define M0PLUS_NVIC_IPR3_IP_12_BITS _u(0x000000c0) +#define M0PLUS_NVIC_IPR3_IP_12_MSB _u(7) +#define M0PLUS_NVIC_IPR3_IP_12_LSB _u(6) #define M0PLUS_NVIC_IPR3_IP_12_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_IPR4 // Description : Use the Interrupt Priority Registers to assign a priority from // 0 to 3 to each of the available interrupts. 0 is the highest // priority, and 3 is the lowest. -#define M0PLUS_NVIC_IPR4_OFFSET 0x0000e410 -#define M0PLUS_NVIC_IPR4_BITS 0xc0c0c0c0 -#define M0PLUS_NVIC_IPR4_RESET 0x00000000 +#define M0PLUS_NVIC_IPR4_OFFSET _u(0x0000e410) +#define M0PLUS_NVIC_IPR4_BITS _u(0xc0c0c0c0) +#define M0PLUS_NVIC_IPR4_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR4_IP_19 // Description : Priority of interrupt 19 -#define M0PLUS_NVIC_IPR4_IP_19_RESET 0x0 -#define M0PLUS_NVIC_IPR4_IP_19_BITS 0xc0000000 -#define M0PLUS_NVIC_IPR4_IP_19_MSB 31 -#define M0PLUS_NVIC_IPR4_IP_19_LSB 30 +#define M0PLUS_NVIC_IPR4_IP_19_RESET _u(0x0) +#define M0PLUS_NVIC_IPR4_IP_19_BITS _u(0xc0000000) +#define M0PLUS_NVIC_IPR4_IP_19_MSB _u(31) +#define M0PLUS_NVIC_IPR4_IP_19_LSB _u(30) #define M0PLUS_NVIC_IPR4_IP_19_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR4_IP_18 // Description : Priority of interrupt 18 -#define M0PLUS_NVIC_IPR4_IP_18_RESET 0x0 -#define M0PLUS_NVIC_IPR4_IP_18_BITS 0x00c00000 -#define M0PLUS_NVIC_IPR4_IP_18_MSB 23 -#define M0PLUS_NVIC_IPR4_IP_18_LSB 22 +#define M0PLUS_NVIC_IPR4_IP_18_RESET _u(0x0) +#define M0PLUS_NVIC_IPR4_IP_18_BITS _u(0x00c00000) +#define M0PLUS_NVIC_IPR4_IP_18_MSB _u(23) +#define M0PLUS_NVIC_IPR4_IP_18_LSB _u(22) #define M0PLUS_NVIC_IPR4_IP_18_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR4_IP_17 // Description : Priority of interrupt 17 -#define M0PLUS_NVIC_IPR4_IP_17_RESET 0x0 -#define M0PLUS_NVIC_IPR4_IP_17_BITS 0x0000c000 -#define M0PLUS_NVIC_IPR4_IP_17_MSB 15 -#define M0PLUS_NVIC_IPR4_IP_17_LSB 14 +#define M0PLUS_NVIC_IPR4_IP_17_RESET _u(0x0) +#define M0PLUS_NVIC_IPR4_IP_17_BITS _u(0x0000c000) +#define M0PLUS_NVIC_IPR4_IP_17_MSB _u(15) +#define M0PLUS_NVIC_IPR4_IP_17_LSB _u(14) #define M0PLUS_NVIC_IPR4_IP_17_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR4_IP_16 // Description : Priority of interrupt 16 -#define M0PLUS_NVIC_IPR4_IP_16_RESET 0x0 -#define M0PLUS_NVIC_IPR4_IP_16_BITS 0x000000c0 -#define M0PLUS_NVIC_IPR4_IP_16_MSB 7 -#define M0PLUS_NVIC_IPR4_IP_16_LSB 6 +#define M0PLUS_NVIC_IPR4_IP_16_RESET _u(0x0) +#define M0PLUS_NVIC_IPR4_IP_16_BITS _u(0x000000c0) +#define M0PLUS_NVIC_IPR4_IP_16_MSB _u(7) +#define M0PLUS_NVIC_IPR4_IP_16_LSB _u(6) #define M0PLUS_NVIC_IPR4_IP_16_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_IPR5 // Description : Use the Interrupt Priority Registers to assign a priority from // 0 to 3 to each of the available interrupts. 0 is the highest // priority, and 3 is the lowest. -#define M0PLUS_NVIC_IPR5_OFFSET 0x0000e414 -#define M0PLUS_NVIC_IPR5_BITS 0xc0c0c0c0 -#define M0PLUS_NVIC_IPR5_RESET 0x00000000 +#define M0PLUS_NVIC_IPR5_OFFSET _u(0x0000e414) +#define M0PLUS_NVIC_IPR5_BITS _u(0xc0c0c0c0) +#define M0PLUS_NVIC_IPR5_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR5_IP_23 // Description : Priority of interrupt 23 -#define M0PLUS_NVIC_IPR5_IP_23_RESET 0x0 -#define M0PLUS_NVIC_IPR5_IP_23_BITS 0xc0000000 -#define M0PLUS_NVIC_IPR5_IP_23_MSB 31 -#define M0PLUS_NVIC_IPR5_IP_23_LSB 30 +#define M0PLUS_NVIC_IPR5_IP_23_RESET _u(0x0) +#define M0PLUS_NVIC_IPR5_IP_23_BITS _u(0xc0000000) +#define M0PLUS_NVIC_IPR5_IP_23_MSB _u(31) +#define M0PLUS_NVIC_IPR5_IP_23_LSB _u(30) #define M0PLUS_NVIC_IPR5_IP_23_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR5_IP_22 // Description : Priority of interrupt 22 -#define M0PLUS_NVIC_IPR5_IP_22_RESET 0x0 -#define M0PLUS_NVIC_IPR5_IP_22_BITS 0x00c00000 -#define M0PLUS_NVIC_IPR5_IP_22_MSB 23 -#define M0PLUS_NVIC_IPR5_IP_22_LSB 22 +#define M0PLUS_NVIC_IPR5_IP_22_RESET _u(0x0) +#define M0PLUS_NVIC_IPR5_IP_22_BITS _u(0x00c00000) +#define M0PLUS_NVIC_IPR5_IP_22_MSB _u(23) +#define M0PLUS_NVIC_IPR5_IP_22_LSB _u(22) #define M0PLUS_NVIC_IPR5_IP_22_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR5_IP_21 // Description : Priority of interrupt 21 -#define M0PLUS_NVIC_IPR5_IP_21_RESET 0x0 -#define M0PLUS_NVIC_IPR5_IP_21_BITS 0x0000c000 -#define M0PLUS_NVIC_IPR5_IP_21_MSB 15 -#define M0PLUS_NVIC_IPR5_IP_21_LSB 14 +#define M0PLUS_NVIC_IPR5_IP_21_RESET _u(0x0) +#define M0PLUS_NVIC_IPR5_IP_21_BITS _u(0x0000c000) +#define M0PLUS_NVIC_IPR5_IP_21_MSB _u(15) +#define M0PLUS_NVIC_IPR5_IP_21_LSB _u(14) #define M0PLUS_NVIC_IPR5_IP_21_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR5_IP_20 // Description : Priority of interrupt 20 -#define M0PLUS_NVIC_IPR5_IP_20_RESET 0x0 -#define M0PLUS_NVIC_IPR5_IP_20_BITS 0x000000c0 -#define M0PLUS_NVIC_IPR5_IP_20_MSB 7 -#define M0PLUS_NVIC_IPR5_IP_20_LSB 6 +#define M0PLUS_NVIC_IPR5_IP_20_RESET _u(0x0) +#define M0PLUS_NVIC_IPR5_IP_20_BITS _u(0x000000c0) +#define M0PLUS_NVIC_IPR5_IP_20_MSB _u(7) +#define M0PLUS_NVIC_IPR5_IP_20_LSB _u(6) #define M0PLUS_NVIC_IPR5_IP_20_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_IPR6 // Description : Use the Interrupt Priority Registers to assign a priority from // 0 to 3 to each of the available interrupts. 0 is the highest // priority, and 3 is the lowest. -#define M0PLUS_NVIC_IPR6_OFFSET 0x0000e418 -#define M0PLUS_NVIC_IPR6_BITS 0xc0c0c0c0 -#define M0PLUS_NVIC_IPR6_RESET 0x00000000 +#define M0PLUS_NVIC_IPR6_OFFSET _u(0x0000e418) +#define M0PLUS_NVIC_IPR6_BITS _u(0xc0c0c0c0) +#define M0PLUS_NVIC_IPR6_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR6_IP_27 // Description : Priority of interrupt 27 -#define M0PLUS_NVIC_IPR6_IP_27_RESET 0x0 -#define M0PLUS_NVIC_IPR6_IP_27_BITS 0xc0000000 -#define M0PLUS_NVIC_IPR6_IP_27_MSB 31 -#define M0PLUS_NVIC_IPR6_IP_27_LSB 30 +#define M0PLUS_NVIC_IPR6_IP_27_RESET _u(0x0) +#define M0PLUS_NVIC_IPR6_IP_27_BITS _u(0xc0000000) +#define M0PLUS_NVIC_IPR6_IP_27_MSB _u(31) +#define M0PLUS_NVIC_IPR6_IP_27_LSB _u(30) #define M0PLUS_NVIC_IPR6_IP_27_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR6_IP_26 // Description : Priority of interrupt 26 -#define M0PLUS_NVIC_IPR6_IP_26_RESET 0x0 -#define M0PLUS_NVIC_IPR6_IP_26_BITS 0x00c00000 -#define M0PLUS_NVIC_IPR6_IP_26_MSB 23 -#define M0PLUS_NVIC_IPR6_IP_26_LSB 22 +#define M0PLUS_NVIC_IPR6_IP_26_RESET _u(0x0) +#define M0PLUS_NVIC_IPR6_IP_26_BITS _u(0x00c00000) +#define M0PLUS_NVIC_IPR6_IP_26_MSB _u(23) +#define M0PLUS_NVIC_IPR6_IP_26_LSB _u(22) #define M0PLUS_NVIC_IPR6_IP_26_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR6_IP_25 // Description : Priority of interrupt 25 -#define M0PLUS_NVIC_IPR6_IP_25_RESET 0x0 -#define M0PLUS_NVIC_IPR6_IP_25_BITS 0x0000c000 -#define M0PLUS_NVIC_IPR6_IP_25_MSB 15 -#define M0PLUS_NVIC_IPR6_IP_25_LSB 14 +#define M0PLUS_NVIC_IPR6_IP_25_RESET _u(0x0) +#define M0PLUS_NVIC_IPR6_IP_25_BITS _u(0x0000c000) +#define M0PLUS_NVIC_IPR6_IP_25_MSB _u(15) +#define M0PLUS_NVIC_IPR6_IP_25_LSB _u(14) #define M0PLUS_NVIC_IPR6_IP_25_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR6_IP_24 // Description : Priority of interrupt 24 -#define M0PLUS_NVIC_IPR6_IP_24_RESET 0x0 -#define M0PLUS_NVIC_IPR6_IP_24_BITS 0x000000c0 -#define M0PLUS_NVIC_IPR6_IP_24_MSB 7 -#define M0PLUS_NVIC_IPR6_IP_24_LSB 6 +#define M0PLUS_NVIC_IPR6_IP_24_RESET _u(0x0) +#define M0PLUS_NVIC_IPR6_IP_24_BITS _u(0x000000c0) +#define M0PLUS_NVIC_IPR6_IP_24_MSB _u(7) +#define M0PLUS_NVIC_IPR6_IP_24_LSB _u(6) #define M0PLUS_NVIC_IPR6_IP_24_ACCESS "RW" // ============================================================================= // Register : M0PLUS_NVIC_IPR7 // Description : Use the Interrupt Priority Registers to assign a priority from // 0 to 3 to each of the available interrupts. 0 is the highest // priority, and 3 is the lowest. -#define M0PLUS_NVIC_IPR7_OFFSET 0x0000e41c -#define M0PLUS_NVIC_IPR7_BITS 0xc0c0c0c0 -#define M0PLUS_NVIC_IPR7_RESET 0x00000000 +#define M0PLUS_NVIC_IPR7_OFFSET _u(0x0000e41c) +#define M0PLUS_NVIC_IPR7_BITS _u(0xc0c0c0c0) +#define M0PLUS_NVIC_IPR7_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR7_IP_31 // Description : Priority of interrupt 31 -#define M0PLUS_NVIC_IPR7_IP_31_RESET 0x0 -#define M0PLUS_NVIC_IPR7_IP_31_BITS 0xc0000000 -#define M0PLUS_NVIC_IPR7_IP_31_MSB 31 -#define M0PLUS_NVIC_IPR7_IP_31_LSB 30 +#define M0PLUS_NVIC_IPR7_IP_31_RESET _u(0x0) +#define M0PLUS_NVIC_IPR7_IP_31_BITS _u(0xc0000000) +#define M0PLUS_NVIC_IPR7_IP_31_MSB _u(31) +#define M0PLUS_NVIC_IPR7_IP_31_LSB _u(30) #define M0PLUS_NVIC_IPR7_IP_31_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR7_IP_30 // Description : Priority of interrupt 30 -#define M0PLUS_NVIC_IPR7_IP_30_RESET 0x0 -#define M0PLUS_NVIC_IPR7_IP_30_BITS 0x00c00000 -#define M0PLUS_NVIC_IPR7_IP_30_MSB 23 -#define M0PLUS_NVIC_IPR7_IP_30_LSB 22 +#define M0PLUS_NVIC_IPR7_IP_30_RESET _u(0x0) +#define M0PLUS_NVIC_IPR7_IP_30_BITS _u(0x00c00000) +#define M0PLUS_NVIC_IPR7_IP_30_MSB _u(23) +#define M0PLUS_NVIC_IPR7_IP_30_LSB _u(22) #define M0PLUS_NVIC_IPR7_IP_30_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR7_IP_29 // Description : Priority of interrupt 29 -#define M0PLUS_NVIC_IPR7_IP_29_RESET 0x0 -#define M0PLUS_NVIC_IPR7_IP_29_BITS 0x0000c000 -#define M0PLUS_NVIC_IPR7_IP_29_MSB 15 -#define M0PLUS_NVIC_IPR7_IP_29_LSB 14 +#define M0PLUS_NVIC_IPR7_IP_29_RESET _u(0x0) +#define M0PLUS_NVIC_IPR7_IP_29_BITS _u(0x0000c000) +#define M0PLUS_NVIC_IPR7_IP_29_MSB _u(15) +#define M0PLUS_NVIC_IPR7_IP_29_LSB _u(14) #define M0PLUS_NVIC_IPR7_IP_29_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_NVIC_IPR7_IP_28 // Description : Priority of interrupt 28 -#define M0PLUS_NVIC_IPR7_IP_28_RESET 0x0 -#define M0PLUS_NVIC_IPR7_IP_28_BITS 0x000000c0 -#define M0PLUS_NVIC_IPR7_IP_28_MSB 7 -#define M0PLUS_NVIC_IPR7_IP_28_LSB 6 +#define M0PLUS_NVIC_IPR7_IP_28_RESET _u(0x0) +#define M0PLUS_NVIC_IPR7_IP_28_BITS _u(0x000000c0) +#define M0PLUS_NVIC_IPR7_IP_28_MSB _u(7) +#define M0PLUS_NVIC_IPR7_IP_28_LSB _u(6) #define M0PLUS_NVIC_IPR7_IP_28_ACCESS "RW" // ============================================================================= // Register : M0PLUS_CPUID // Description : Read the CPU ID Base Register to determine: the ID number of // the processor core, the version number of the processor core, // the implementation details of the processor core. -#define M0PLUS_CPUID_OFFSET 0x0000ed00 -#define M0PLUS_CPUID_BITS 0xffffffff -#define M0PLUS_CPUID_RESET 0x410cc601 +#define M0PLUS_CPUID_OFFSET _u(0x0000ed00) +#define M0PLUS_CPUID_BITS _u(0xffffffff) +#define M0PLUS_CPUID_RESET _u(0x410cc601) // ----------------------------------------------------------------------------- // Field : M0PLUS_CPUID_IMPLEMENTER // Description : Implementor code: 0x41 = ARM -#define M0PLUS_CPUID_IMPLEMENTER_RESET 0x41 -#define M0PLUS_CPUID_IMPLEMENTER_BITS 0xff000000 -#define M0PLUS_CPUID_IMPLEMENTER_MSB 31 -#define M0PLUS_CPUID_IMPLEMENTER_LSB 24 +#define M0PLUS_CPUID_IMPLEMENTER_RESET _u(0x41) +#define M0PLUS_CPUID_IMPLEMENTER_BITS _u(0xff000000) +#define M0PLUS_CPUID_IMPLEMENTER_MSB _u(31) +#define M0PLUS_CPUID_IMPLEMENTER_LSB _u(24) #define M0PLUS_CPUID_IMPLEMENTER_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_CPUID_VARIANT // Description : Major revision number n in the rnpm revision status: // 0x0 = Revision 0. -#define M0PLUS_CPUID_VARIANT_RESET 0x0 -#define M0PLUS_CPUID_VARIANT_BITS 0x00f00000 -#define M0PLUS_CPUID_VARIANT_MSB 23 -#define M0PLUS_CPUID_VARIANT_LSB 20 +#define M0PLUS_CPUID_VARIANT_RESET _u(0x0) +#define M0PLUS_CPUID_VARIANT_BITS _u(0x00f00000) +#define M0PLUS_CPUID_VARIANT_MSB _u(23) +#define M0PLUS_CPUID_VARIANT_LSB _u(20) #define M0PLUS_CPUID_VARIANT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_CPUID_ARCHITECTURE // Description : Constant that defines the architecture of the processor: // 0xC = ARMv6-M architecture. -#define M0PLUS_CPUID_ARCHITECTURE_RESET 0xc -#define M0PLUS_CPUID_ARCHITECTURE_BITS 0x000f0000 -#define M0PLUS_CPUID_ARCHITECTURE_MSB 19 -#define M0PLUS_CPUID_ARCHITECTURE_LSB 16 +#define M0PLUS_CPUID_ARCHITECTURE_RESET _u(0xc) +#define M0PLUS_CPUID_ARCHITECTURE_BITS _u(0x000f0000) +#define M0PLUS_CPUID_ARCHITECTURE_MSB _u(19) +#define M0PLUS_CPUID_ARCHITECTURE_LSB _u(16) #define M0PLUS_CPUID_ARCHITECTURE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_CPUID_PARTNO // Description : Number of processor within family: 0xC60 = Cortex-M0+ -#define M0PLUS_CPUID_PARTNO_RESET 0xc60 -#define M0PLUS_CPUID_PARTNO_BITS 0x0000fff0 -#define M0PLUS_CPUID_PARTNO_MSB 15 -#define M0PLUS_CPUID_PARTNO_LSB 4 +#define M0PLUS_CPUID_PARTNO_RESET _u(0xc60) +#define M0PLUS_CPUID_PARTNO_BITS _u(0x0000fff0) +#define M0PLUS_CPUID_PARTNO_MSB _u(15) +#define M0PLUS_CPUID_PARTNO_LSB _u(4) #define M0PLUS_CPUID_PARTNO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_CPUID_REVISION // Description : Minor revision number m in the rnpm revision status: // 0x1 = Patch 1. -#define M0PLUS_CPUID_REVISION_RESET 0x1 -#define M0PLUS_CPUID_REVISION_BITS 0x0000000f -#define M0PLUS_CPUID_REVISION_MSB 3 -#define M0PLUS_CPUID_REVISION_LSB 0 +#define M0PLUS_CPUID_REVISION_RESET _u(0x1) +#define M0PLUS_CPUID_REVISION_BITS _u(0x0000000f) +#define M0PLUS_CPUID_REVISION_MSB _u(3) +#define M0PLUS_CPUID_REVISION_LSB _u(0) #define M0PLUS_CPUID_REVISION_ACCESS "RO" // ============================================================================= // Register : M0PLUS_ICSR @@ -615,9 +615,9 @@ // set or clear a pending SysTick, check for pending exceptions, // check the vector number of the highest priority pended // exception, check the vector number of the active exception. -#define M0PLUS_ICSR_OFFSET 0x0000ed04 -#define M0PLUS_ICSR_BITS 0x9edff1ff -#define M0PLUS_ICSR_RESET 0x00000000 +#define M0PLUS_ICSR_OFFSET _u(0x0000ed04) +#define M0PLUS_ICSR_BITS _u(0x9edff1ff) +#define M0PLUS_ICSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_ICSR_NMIPENDSET // Description : Setting this bit will activate an NMI. Since NMI is the highest @@ -638,10 +638,10 @@ // exception handler returns 1 only if the // NMI signal is reasserted while the processor is executing that // handler. -#define M0PLUS_ICSR_NMIPENDSET_RESET 0x0 -#define M0PLUS_ICSR_NMIPENDSET_BITS 0x80000000 -#define M0PLUS_ICSR_NMIPENDSET_MSB 31 -#define M0PLUS_ICSR_NMIPENDSET_LSB 31 +#define M0PLUS_ICSR_NMIPENDSET_RESET _u(0x0) +#define M0PLUS_ICSR_NMIPENDSET_BITS _u(0x80000000) +#define M0PLUS_ICSR_NMIPENDSET_MSB _u(31) +#define M0PLUS_ICSR_NMIPENDSET_LSB _u(31) #define M0PLUS_ICSR_NMIPENDSET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_ICSR_PENDSVSET @@ -654,10 +654,10 @@ // 1 = PendSV exception is pending. // Writing 1 to this bit is the only way to set the PendSV // exception state to pending. -#define M0PLUS_ICSR_PENDSVSET_RESET 0x0 -#define M0PLUS_ICSR_PENDSVSET_BITS 0x10000000 -#define M0PLUS_ICSR_PENDSVSET_MSB 28 -#define M0PLUS_ICSR_PENDSVSET_LSB 28 +#define M0PLUS_ICSR_PENDSVSET_RESET _u(0x0) +#define M0PLUS_ICSR_PENDSVSET_BITS _u(0x10000000) +#define M0PLUS_ICSR_PENDSVSET_MSB _u(28) +#define M0PLUS_ICSR_PENDSVSET_LSB _u(28) #define M0PLUS_ICSR_PENDSVSET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_ICSR_PENDSVCLR @@ -665,10 +665,10 @@ // Write: // 0 = No effect. // 1 = Removes the pending state from the PendSV exception. -#define M0PLUS_ICSR_PENDSVCLR_RESET 0x0 -#define M0PLUS_ICSR_PENDSVCLR_BITS 0x08000000 -#define M0PLUS_ICSR_PENDSVCLR_MSB 27 -#define M0PLUS_ICSR_PENDSVCLR_LSB 27 +#define M0PLUS_ICSR_PENDSVCLR_RESET _u(0x0) +#define M0PLUS_ICSR_PENDSVCLR_BITS _u(0x08000000) +#define M0PLUS_ICSR_PENDSVCLR_MSB _u(27) +#define M0PLUS_ICSR_PENDSVCLR_LSB _u(27) #define M0PLUS_ICSR_PENDSVCLR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_ICSR_PENDSTSET @@ -679,10 +679,10 @@ // Read: // 0 = SysTick exception is not pending. // 1 = SysTick exception is pending. -#define M0PLUS_ICSR_PENDSTSET_RESET 0x0 -#define M0PLUS_ICSR_PENDSTSET_BITS 0x04000000 -#define M0PLUS_ICSR_PENDSTSET_MSB 26 -#define M0PLUS_ICSR_PENDSTSET_LSB 26 +#define M0PLUS_ICSR_PENDSTSET_RESET _u(0x0) +#define M0PLUS_ICSR_PENDSTSET_BITS _u(0x04000000) +#define M0PLUS_ICSR_PENDSTSET_MSB _u(26) +#define M0PLUS_ICSR_PENDSTSET_LSB _u(26) #define M0PLUS_ICSR_PENDSTSET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_ICSR_PENDSTCLR @@ -691,10 +691,10 @@ // 0 = No effect. // 1 = Removes the pending state from the SysTick exception. // This bit is WO. On a register read its value is Unknown. -#define M0PLUS_ICSR_PENDSTCLR_RESET 0x0 -#define M0PLUS_ICSR_PENDSTCLR_BITS 0x02000000 -#define M0PLUS_ICSR_PENDSTCLR_MSB 25 -#define M0PLUS_ICSR_PENDSTCLR_LSB 25 +#define M0PLUS_ICSR_PENDSTCLR_RESET _u(0x0) +#define M0PLUS_ICSR_PENDSTCLR_BITS _u(0x02000000) +#define M0PLUS_ICSR_PENDSTCLR_MSB _u(25) +#define M0PLUS_ICSR_PENDSTCLR_LSB _u(25) #define M0PLUS_ICSR_PENDSTCLR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_ICSR_ISRPREEMPT @@ -702,18 +702,18 @@ // indicates that a pending interrupt is to be taken in the next // running cycle. If C_MASKINTS is clear in the Debug Halting // Control and Status Register, the interrupt is serviced. -#define M0PLUS_ICSR_ISRPREEMPT_RESET 0x0 -#define M0PLUS_ICSR_ISRPREEMPT_BITS 0x00800000 -#define M0PLUS_ICSR_ISRPREEMPT_MSB 23 -#define M0PLUS_ICSR_ISRPREEMPT_LSB 23 +#define M0PLUS_ICSR_ISRPREEMPT_RESET _u(0x0) +#define M0PLUS_ICSR_ISRPREEMPT_BITS _u(0x00800000) +#define M0PLUS_ICSR_ISRPREEMPT_MSB _u(23) +#define M0PLUS_ICSR_ISRPREEMPT_LSB _u(23) #define M0PLUS_ICSR_ISRPREEMPT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_ICSR_ISRPENDING // Description : External interrupt pending flag -#define M0PLUS_ICSR_ISRPENDING_RESET 0x0 -#define M0PLUS_ICSR_ISRPENDING_BITS 0x00400000 -#define M0PLUS_ICSR_ISRPENDING_MSB 22 -#define M0PLUS_ICSR_ISRPENDING_LSB 22 +#define M0PLUS_ICSR_ISRPENDING_RESET _u(0x0) +#define M0PLUS_ICSR_ISRPENDING_BITS _u(0x00400000) +#define M0PLUS_ICSR_ISRPENDING_MSB _u(22) +#define M0PLUS_ICSR_ISRPENDING_LSB _u(22) #define M0PLUS_ICSR_ISRPENDING_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_ICSR_VECTPENDING @@ -722,61 +722,61 @@ // state includes the effect of memory-mapped enable and mask // registers. It does not include the PRIMASK special-purpose // register qualifier. -#define M0PLUS_ICSR_VECTPENDING_RESET 0x000 -#define M0PLUS_ICSR_VECTPENDING_BITS 0x001ff000 -#define M0PLUS_ICSR_VECTPENDING_MSB 20 -#define M0PLUS_ICSR_VECTPENDING_LSB 12 +#define M0PLUS_ICSR_VECTPENDING_RESET _u(0x000) +#define M0PLUS_ICSR_VECTPENDING_BITS _u(0x001ff000) +#define M0PLUS_ICSR_VECTPENDING_MSB _u(20) +#define M0PLUS_ICSR_VECTPENDING_LSB _u(12) #define M0PLUS_ICSR_VECTPENDING_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_ICSR_VECTACTIVE // Description : Active exception number field. Reset clears the VECTACTIVE // field. -#define M0PLUS_ICSR_VECTACTIVE_RESET 0x000 -#define M0PLUS_ICSR_VECTACTIVE_BITS 0x000001ff -#define M0PLUS_ICSR_VECTACTIVE_MSB 8 -#define M0PLUS_ICSR_VECTACTIVE_LSB 0 +#define M0PLUS_ICSR_VECTACTIVE_RESET _u(0x000) +#define M0PLUS_ICSR_VECTACTIVE_BITS _u(0x000001ff) +#define M0PLUS_ICSR_VECTACTIVE_MSB _u(8) +#define M0PLUS_ICSR_VECTACTIVE_LSB _u(0) #define M0PLUS_ICSR_VECTACTIVE_ACCESS "RO" // ============================================================================= // Register : M0PLUS_VTOR // Description : The VTOR holds the vector table offset address. -#define M0PLUS_VTOR_OFFSET 0x0000ed08 -#define M0PLUS_VTOR_BITS 0xffffff00 -#define M0PLUS_VTOR_RESET 0x00000000 +#define M0PLUS_VTOR_OFFSET _u(0x0000ed08) +#define M0PLUS_VTOR_BITS _u(0xffffff00) +#define M0PLUS_VTOR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_VTOR_TBLOFF // Description : Bits [31:8] of the indicate the vector table offset address. -#define M0PLUS_VTOR_TBLOFF_RESET 0x000000 -#define M0PLUS_VTOR_TBLOFF_BITS 0xffffff00 -#define M0PLUS_VTOR_TBLOFF_MSB 31 -#define M0PLUS_VTOR_TBLOFF_LSB 8 +#define M0PLUS_VTOR_TBLOFF_RESET _u(0x000000) +#define M0PLUS_VTOR_TBLOFF_BITS _u(0xffffff00) +#define M0PLUS_VTOR_TBLOFF_MSB _u(31) +#define M0PLUS_VTOR_TBLOFF_LSB _u(8) #define M0PLUS_VTOR_TBLOFF_ACCESS "RW" // ============================================================================= // Register : M0PLUS_AIRCR // Description : Use the Application Interrupt and Reset Control Register to: // determine data endianness, clear all active state information // from debug halt mode, request a system reset. -#define M0PLUS_AIRCR_OFFSET 0x0000ed0c -#define M0PLUS_AIRCR_BITS 0xffff8006 -#define M0PLUS_AIRCR_RESET 0x00000000 +#define M0PLUS_AIRCR_OFFSET _u(0x0000ed0c) +#define M0PLUS_AIRCR_BITS _u(0xffff8006) +#define M0PLUS_AIRCR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_AIRCR_VECTKEY // Description : Register key: // Reads as Unknown // On writes, write 0x05FA to VECTKEY, otherwise the write is // ignored. -#define M0PLUS_AIRCR_VECTKEY_RESET 0x0000 -#define M0PLUS_AIRCR_VECTKEY_BITS 0xffff0000 -#define M0PLUS_AIRCR_VECTKEY_MSB 31 -#define M0PLUS_AIRCR_VECTKEY_LSB 16 +#define M0PLUS_AIRCR_VECTKEY_RESET _u(0x0000) +#define M0PLUS_AIRCR_VECTKEY_BITS _u(0xffff0000) +#define M0PLUS_AIRCR_VECTKEY_MSB _u(31) +#define M0PLUS_AIRCR_VECTKEY_LSB _u(16) #define M0PLUS_AIRCR_VECTKEY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_AIRCR_ENDIANESS // Description : Data endianness implemented: // 0 = Little-endian. -#define M0PLUS_AIRCR_ENDIANESS_RESET 0x0 -#define M0PLUS_AIRCR_ENDIANESS_BITS 0x00008000 -#define M0PLUS_AIRCR_ENDIANESS_MSB 15 -#define M0PLUS_AIRCR_ENDIANESS_LSB 15 +#define M0PLUS_AIRCR_ENDIANESS_RESET _u(0x0) +#define M0PLUS_AIRCR_ENDIANESS_BITS _u(0x00008000) +#define M0PLUS_AIRCR_ENDIANESS_MSB _u(15) +#define M0PLUS_AIRCR_ENDIANESS_LSB _u(15) #define M0PLUS_AIRCR_ENDIANESS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_AIRCR_SYSRESETREQ @@ -786,10 +786,10 @@ // for debug. The C_HALT bit in the DHCSR is cleared as a result // of the system reset requested. The debugger does not lose // contact with the device. -#define M0PLUS_AIRCR_SYSRESETREQ_RESET 0x0 -#define M0PLUS_AIRCR_SYSRESETREQ_BITS 0x00000004 -#define M0PLUS_AIRCR_SYSRESETREQ_MSB 2 -#define M0PLUS_AIRCR_SYSRESETREQ_LSB 2 +#define M0PLUS_AIRCR_SYSRESETREQ_RESET _u(0x0) +#define M0PLUS_AIRCR_SYSRESETREQ_BITS _u(0x00000004) +#define M0PLUS_AIRCR_SYSRESETREQ_MSB _u(2) +#define M0PLUS_AIRCR_SYSRESETREQ_LSB _u(2) #define M0PLUS_AIRCR_SYSRESETREQ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_AIRCR_VECTCLRACTIVE @@ -799,10 +799,10 @@ // exception status of the processor, forces a return to Thread // mode, forces an IPSR of 0. A debugger must re-initialize the // stack. -#define M0PLUS_AIRCR_VECTCLRACTIVE_RESET 0x0 -#define M0PLUS_AIRCR_VECTCLRACTIVE_BITS 0x00000002 -#define M0PLUS_AIRCR_VECTCLRACTIVE_MSB 1 -#define M0PLUS_AIRCR_VECTCLRACTIVE_LSB 1 +#define M0PLUS_AIRCR_VECTCLRACTIVE_RESET _u(0x0) +#define M0PLUS_AIRCR_VECTCLRACTIVE_BITS _u(0x00000002) +#define M0PLUS_AIRCR_VECTCLRACTIVE_MSB _u(1) +#define M0PLUS_AIRCR_VECTCLRACTIVE_LSB _u(1) #define M0PLUS_AIRCR_VECTCLRACTIVE_ACCESS "RW" // ============================================================================= // Register : M0PLUS_SCR @@ -810,9 +810,9 @@ // power-management functions: signal to the system when the // processor can enter a low power state, control how the // processor enters and exits low power states. -#define M0PLUS_SCR_OFFSET 0x0000ed10 -#define M0PLUS_SCR_BITS 0x00000016 -#define M0PLUS_SCR_RESET 0x00000000 +#define M0PLUS_SCR_OFFSET _u(0x0000ed10) +#define M0PLUS_SCR_BITS _u(0x00000016) +#define M0PLUS_SCR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_SCR_SEVONPEND // Description : Send Event on Pending bit: @@ -826,10 +826,10 @@ // and affects the next WFE. // The processor also wakes up on execution of an SEV instruction // or an external event. -#define M0PLUS_SCR_SEVONPEND_RESET 0x0 -#define M0PLUS_SCR_SEVONPEND_BITS 0x00000010 -#define M0PLUS_SCR_SEVONPEND_MSB 4 -#define M0PLUS_SCR_SEVONPEND_LSB 4 +#define M0PLUS_SCR_SEVONPEND_RESET _u(0x0) +#define M0PLUS_SCR_SEVONPEND_BITS _u(0x00000010) +#define M0PLUS_SCR_SEVONPEND_MSB _u(4) +#define M0PLUS_SCR_SEVONPEND_LSB _u(4) #define M0PLUS_SCR_SEVONPEND_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_SCR_SLEEPDEEP @@ -837,10 +837,10 @@ // low power mode: // 0 = Sleep. // 1 = Deep sleep. -#define M0PLUS_SCR_SLEEPDEEP_RESET 0x0 -#define M0PLUS_SCR_SLEEPDEEP_BITS 0x00000004 -#define M0PLUS_SCR_SLEEPDEEP_MSB 2 -#define M0PLUS_SCR_SLEEPDEEP_LSB 2 +#define M0PLUS_SCR_SLEEPDEEP_RESET _u(0x0) +#define M0PLUS_SCR_SLEEPDEEP_BITS _u(0x00000004) +#define M0PLUS_SCR_SLEEPDEEP_MSB _u(2) +#define M0PLUS_SCR_SLEEPDEEP_LSB _u(2) #define M0PLUS_SCR_SLEEPDEEP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_SCR_SLEEPONEXIT @@ -851,19 +851,19 @@ // mode. // Setting this bit to 1 enables an interrupt driven application // to avoid returning to an empty main application. -#define M0PLUS_SCR_SLEEPONEXIT_RESET 0x0 -#define M0PLUS_SCR_SLEEPONEXIT_BITS 0x00000002 -#define M0PLUS_SCR_SLEEPONEXIT_MSB 1 -#define M0PLUS_SCR_SLEEPONEXIT_LSB 1 +#define M0PLUS_SCR_SLEEPONEXIT_RESET _u(0x0) +#define M0PLUS_SCR_SLEEPONEXIT_BITS _u(0x00000002) +#define M0PLUS_SCR_SLEEPONEXIT_MSB _u(1) +#define M0PLUS_SCR_SLEEPONEXIT_LSB _u(1) #define M0PLUS_SCR_SLEEPONEXIT_ACCESS "RW" // ============================================================================= // Register : M0PLUS_CCR // Description : The Configuration and Control Register permanently enables // stack alignment and causes unaligned accesses to result in a // Hard Fault. -#define M0PLUS_CCR_OFFSET 0x0000ed14 -#define M0PLUS_CCR_BITS 0x00000208 -#define M0PLUS_CCR_RESET 0x00000000 +#define M0PLUS_CCR_OFFSET _u(0x0000ed14) +#define M0PLUS_CCR_BITS _u(0x00000208) +#define M0PLUS_CCR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_CCR_STKALIGN // Description : Always reads as one, indicates 8-byte stack alignment on @@ -871,19 +871,19 @@ // of the stacked PSR to indicate the stack alignment. On return // from the exception it uses this stacked bit to restore the // correct stack alignment. -#define M0PLUS_CCR_STKALIGN_RESET 0x0 -#define M0PLUS_CCR_STKALIGN_BITS 0x00000200 -#define M0PLUS_CCR_STKALIGN_MSB 9 -#define M0PLUS_CCR_STKALIGN_LSB 9 +#define M0PLUS_CCR_STKALIGN_RESET _u(0x0) +#define M0PLUS_CCR_STKALIGN_BITS _u(0x00000200) +#define M0PLUS_CCR_STKALIGN_MSB _u(9) +#define M0PLUS_CCR_STKALIGN_LSB _u(9) #define M0PLUS_CCR_STKALIGN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_CCR_UNALIGN_TRP // Description : Always reads as one, indicates that all unaligned accesses // generate a HardFault. -#define M0PLUS_CCR_UNALIGN_TRP_RESET 0x0 -#define M0PLUS_CCR_UNALIGN_TRP_BITS 0x00000008 -#define M0PLUS_CCR_UNALIGN_TRP_MSB 3 -#define M0PLUS_CCR_UNALIGN_TRP_LSB 3 +#define M0PLUS_CCR_UNALIGN_TRP_RESET _u(0x0) +#define M0PLUS_CCR_UNALIGN_TRP_BITS _u(0x00000008) +#define M0PLUS_CCR_UNALIGN_TRP_MSB _u(3) +#define M0PLUS_CCR_UNALIGN_TRP_LSB _u(3) #define M0PLUS_CCR_UNALIGN_TRP_ACCESS "RO" // ============================================================================= // Register : M0PLUS_SHPR2 @@ -891,16 +891,16 @@ // can have their priority set to any of the priority levels. Use // the System Handler Priority Register 2 to set the priority of // SVCall. -#define M0PLUS_SHPR2_OFFSET 0x0000ed1c -#define M0PLUS_SHPR2_BITS 0xc0000000 -#define M0PLUS_SHPR2_RESET 0x00000000 +#define M0PLUS_SHPR2_OFFSET _u(0x0000ed1c) +#define M0PLUS_SHPR2_BITS _u(0xc0000000) +#define M0PLUS_SHPR2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_SHPR2_PRI_11 // Description : Priority of system handler 11, SVCall -#define M0PLUS_SHPR2_PRI_11_RESET 0x0 -#define M0PLUS_SHPR2_PRI_11_BITS 0xc0000000 -#define M0PLUS_SHPR2_PRI_11_MSB 31 -#define M0PLUS_SHPR2_PRI_11_LSB 30 +#define M0PLUS_SHPR2_PRI_11_RESET _u(0x0) +#define M0PLUS_SHPR2_PRI_11_BITS _u(0xc0000000) +#define M0PLUS_SHPR2_PRI_11_MSB _u(31) +#define M0PLUS_SHPR2_PRI_11_LSB _u(30) #define M0PLUS_SHPR2_PRI_11_ACCESS "RW" // ============================================================================= // Register : M0PLUS_SHPR3 @@ -908,73 +908,73 @@ // can have their priority set to any of the priority levels. Use // the System Handler Priority Register 3 to set the priority of // PendSV and SysTick. -#define M0PLUS_SHPR3_OFFSET 0x0000ed20 -#define M0PLUS_SHPR3_BITS 0xc0c00000 -#define M0PLUS_SHPR3_RESET 0x00000000 +#define M0PLUS_SHPR3_OFFSET _u(0x0000ed20) +#define M0PLUS_SHPR3_BITS _u(0xc0c00000) +#define M0PLUS_SHPR3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_SHPR3_PRI_15 // Description : Priority of system handler 15, SysTick -#define M0PLUS_SHPR3_PRI_15_RESET 0x0 -#define M0PLUS_SHPR3_PRI_15_BITS 0xc0000000 -#define M0PLUS_SHPR3_PRI_15_MSB 31 -#define M0PLUS_SHPR3_PRI_15_LSB 30 +#define M0PLUS_SHPR3_PRI_15_RESET _u(0x0) +#define M0PLUS_SHPR3_PRI_15_BITS _u(0xc0000000) +#define M0PLUS_SHPR3_PRI_15_MSB _u(31) +#define M0PLUS_SHPR3_PRI_15_LSB _u(30) #define M0PLUS_SHPR3_PRI_15_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_SHPR3_PRI_14 // Description : Priority of system handler 14, PendSV -#define M0PLUS_SHPR3_PRI_14_RESET 0x0 -#define M0PLUS_SHPR3_PRI_14_BITS 0x00c00000 -#define M0PLUS_SHPR3_PRI_14_MSB 23 -#define M0PLUS_SHPR3_PRI_14_LSB 22 +#define M0PLUS_SHPR3_PRI_14_RESET _u(0x0) +#define M0PLUS_SHPR3_PRI_14_BITS _u(0x00c00000) +#define M0PLUS_SHPR3_PRI_14_MSB _u(23) +#define M0PLUS_SHPR3_PRI_14_LSB _u(22) #define M0PLUS_SHPR3_PRI_14_ACCESS "RW" // ============================================================================= // Register : M0PLUS_SHCSR // Description : Use the System Handler Control and State Register to determine // or clear the pending status of SVCall. -#define M0PLUS_SHCSR_OFFSET 0x0000ed24 -#define M0PLUS_SHCSR_BITS 0x00008000 -#define M0PLUS_SHCSR_RESET 0x00000000 +#define M0PLUS_SHCSR_OFFSET _u(0x0000ed24) +#define M0PLUS_SHCSR_BITS _u(0x00008000) +#define M0PLUS_SHCSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_SHCSR_SVCALLPENDED // Description : Reads as 1 if SVCall is Pending. Write 1 to set pending // SVCall, write 0 to clear pending SVCall. -#define M0PLUS_SHCSR_SVCALLPENDED_RESET 0x0 -#define M0PLUS_SHCSR_SVCALLPENDED_BITS 0x00008000 -#define M0PLUS_SHCSR_SVCALLPENDED_MSB 15 -#define M0PLUS_SHCSR_SVCALLPENDED_LSB 15 +#define M0PLUS_SHCSR_SVCALLPENDED_RESET _u(0x0) +#define M0PLUS_SHCSR_SVCALLPENDED_BITS _u(0x00008000) +#define M0PLUS_SHCSR_SVCALLPENDED_MSB _u(15) +#define M0PLUS_SHCSR_SVCALLPENDED_LSB _u(15) #define M0PLUS_SHCSR_SVCALLPENDED_ACCESS "RW" // ============================================================================= // Register : M0PLUS_MPU_TYPE // Description : Read the MPU Type Register to determine if the processor // implements an MPU, and how many regions the MPU supports. -#define M0PLUS_MPU_TYPE_OFFSET 0x0000ed90 -#define M0PLUS_MPU_TYPE_BITS 0x00ffff01 -#define M0PLUS_MPU_TYPE_RESET 0x00000800 +#define M0PLUS_MPU_TYPE_OFFSET _u(0x0000ed90) +#define M0PLUS_MPU_TYPE_BITS _u(0x00ffff01) +#define M0PLUS_MPU_TYPE_RESET _u(0x00000800) // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_TYPE_IREGION // Description : Instruction region. Reads as zero as ARMv6-M only supports a // unified MPU. -#define M0PLUS_MPU_TYPE_IREGION_RESET 0x00 -#define M0PLUS_MPU_TYPE_IREGION_BITS 0x00ff0000 -#define M0PLUS_MPU_TYPE_IREGION_MSB 23 -#define M0PLUS_MPU_TYPE_IREGION_LSB 16 +#define M0PLUS_MPU_TYPE_IREGION_RESET _u(0x00) +#define M0PLUS_MPU_TYPE_IREGION_BITS _u(0x00ff0000) +#define M0PLUS_MPU_TYPE_IREGION_MSB _u(23) +#define M0PLUS_MPU_TYPE_IREGION_LSB _u(16) #define M0PLUS_MPU_TYPE_IREGION_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_TYPE_DREGION // Description : Number of regions supported by the MPU. -#define M0PLUS_MPU_TYPE_DREGION_RESET 0x08 -#define M0PLUS_MPU_TYPE_DREGION_BITS 0x0000ff00 -#define M0PLUS_MPU_TYPE_DREGION_MSB 15 -#define M0PLUS_MPU_TYPE_DREGION_LSB 8 +#define M0PLUS_MPU_TYPE_DREGION_RESET _u(0x08) +#define M0PLUS_MPU_TYPE_DREGION_BITS _u(0x0000ff00) +#define M0PLUS_MPU_TYPE_DREGION_MSB _u(15) +#define M0PLUS_MPU_TYPE_DREGION_LSB _u(8) #define M0PLUS_MPU_TYPE_DREGION_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_TYPE_SEPARATE // Description : Indicates support for separate instruction and data address // maps. Reads as 0 as ARMv6-M only supports a unified MPU. -#define M0PLUS_MPU_TYPE_SEPARATE_RESET 0x0 -#define M0PLUS_MPU_TYPE_SEPARATE_BITS 0x00000001 -#define M0PLUS_MPU_TYPE_SEPARATE_MSB 0 -#define M0PLUS_MPU_TYPE_SEPARATE_LSB 0 +#define M0PLUS_MPU_TYPE_SEPARATE_RESET _u(0x0) +#define M0PLUS_MPU_TYPE_SEPARATE_BITS _u(0x00000001) +#define M0PLUS_MPU_TYPE_SEPARATE_MSB _u(0) +#define M0PLUS_MPU_TYPE_SEPARATE_LSB _u(0) #define M0PLUS_MPU_TYPE_SEPARATE_ACCESS "RO" // ============================================================================= // Register : M0PLUS_MPU_CTRL @@ -982,9 +982,9 @@ // to control whether the default memory map is enabled as a // background region for privileged accesses, and whether the MPU // is enabled for HardFaults and NMIs. -#define M0PLUS_MPU_CTRL_OFFSET 0x0000ed94 -#define M0PLUS_MPU_CTRL_BITS 0x00000007 -#define M0PLUS_MPU_CTRL_RESET 0x00000000 +#define M0PLUS_MPU_CTRL_OFFSET _u(0x0000ed94) +#define M0PLUS_MPU_CTRL_BITS _u(0x00000007) +#define M0PLUS_MPU_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_CTRL_PRIVDEFENA // Description : Controls whether the default memory map is enabled as a @@ -998,10 +998,10 @@ // When enabled, the background region acts as if it is region // number -1. Any region that is defined and enabled has priority // over this default map. -#define M0PLUS_MPU_CTRL_PRIVDEFENA_RESET 0x0 -#define M0PLUS_MPU_CTRL_PRIVDEFENA_BITS 0x00000004 -#define M0PLUS_MPU_CTRL_PRIVDEFENA_MSB 2 -#define M0PLUS_MPU_CTRL_PRIVDEFENA_LSB 2 +#define M0PLUS_MPU_CTRL_PRIVDEFENA_RESET _u(0x0) +#define M0PLUS_MPU_CTRL_PRIVDEFENA_BITS _u(0x00000004) +#define M0PLUS_MPU_CTRL_PRIVDEFENA_MSB _u(2) +#define M0PLUS_MPU_CTRL_PRIVDEFENA_LSB _u(2) #define M0PLUS_MPU_CTRL_PRIVDEFENA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_CTRL_HFNMIENA @@ -1012,10 +1012,10 @@ // 0 = MPU is disabled during HardFault and NMI handlers, // regardless of the value of the ENABLE bit. // 1 = the MPU is enabled during HardFault and NMI handlers. -#define M0PLUS_MPU_CTRL_HFNMIENA_RESET 0x0 -#define M0PLUS_MPU_CTRL_HFNMIENA_BITS 0x00000002 -#define M0PLUS_MPU_CTRL_HFNMIENA_MSB 1 -#define M0PLUS_MPU_CTRL_HFNMIENA_LSB 1 +#define M0PLUS_MPU_CTRL_HFNMIENA_RESET _u(0x0) +#define M0PLUS_MPU_CTRL_HFNMIENA_BITS _u(0x00000002) +#define M0PLUS_MPU_CTRL_HFNMIENA_MSB _u(1) +#define M0PLUS_MPU_CTRL_HFNMIENA_LSB _u(1) #define M0PLUS_MPU_CTRL_HFNMIENA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_CTRL_ENABLE @@ -1023,28 +1023,28 @@ // unprivileged accesses use the default memory map. // 0 = MPU disabled. // 1 = MPU enabled. -#define M0PLUS_MPU_CTRL_ENABLE_RESET 0x0 -#define M0PLUS_MPU_CTRL_ENABLE_BITS 0x00000001 -#define M0PLUS_MPU_CTRL_ENABLE_MSB 0 -#define M0PLUS_MPU_CTRL_ENABLE_LSB 0 +#define M0PLUS_MPU_CTRL_ENABLE_RESET _u(0x0) +#define M0PLUS_MPU_CTRL_ENABLE_BITS _u(0x00000001) +#define M0PLUS_MPU_CTRL_ENABLE_MSB _u(0) +#define M0PLUS_MPU_CTRL_ENABLE_LSB _u(0) #define M0PLUS_MPU_CTRL_ENABLE_ACCESS "RW" // ============================================================================= // Register : M0PLUS_MPU_RNR // Description : Use the MPU Region Number Register to select the region // currently accessed by MPU_RBAR and MPU_RASR. -#define M0PLUS_MPU_RNR_OFFSET 0x0000ed98 -#define M0PLUS_MPU_RNR_BITS 0x0000000f -#define M0PLUS_MPU_RNR_RESET 0x00000000 +#define M0PLUS_MPU_RNR_OFFSET _u(0x0000ed98) +#define M0PLUS_MPU_RNR_BITS _u(0x0000000f) +#define M0PLUS_MPU_RNR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_RNR_REGION // Description : Indicates the MPU region referenced by the MPU_RBAR and // MPU_RASR registers. // The MPU supports 8 memory regions, so the permitted values of // this field are 0-7. -#define M0PLUS_MPU_RNR_REGION_RESET 0x0 -#define M0PLUS_MPU_RNR_REGION_BITS 0x0000000f -#define M0PLUS_MPU_RNR_REGION_MSB 3 -#define M0PLUS_MPU_RNR_REGION_LSB 0 +#define M0PLUS_MPU_RNR_REGION_RESET _u(0x0) +#define M0PLUS_MPU_RNR_REGION_BITS _u(0x0000000f) +#define M0PLUS_MPU_RNR_REGION_MSB _u(3) +#define M0PLUS_MPU_RNR_REGION_LSB _u(0) #define M0PLUS_MPU_RNR_REGION_ACCESS "RW" // ============================================================================= // Register : M0PLUS_MPU_RBAR @@ -1052,16 +1052,16 @@ // address of the region identified by MPU_RNR. Write to update // the base address of said region or that of a specified region, // with whose number MPU_RNR will also be updated. -#define M0PLUS_MPU_RBAR_OFFSET 0x0000ed9c -#define M0PLUS_MPU_RBAR_BITS 0xffffff1f -#define M0PLUS_MPU_RBAR_RESET 0x00000000 +#define M0PLUS_MPU_RBAR_OFFSET _u(0x0000ed9c) +#define M0PLUS_MPU_RBAR_BITS _u(0xffffff1f) +#define M0PLUS_MPU_RBAR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_RBAR_ADDR // Description : Base address of the region. -#define M0PLUS_MPU_RBAR_ADDR_RESET 0x000000 -#define M0PLUS_MPU_RBAR_ADDR_BITS 0xffffff00 -#define M0PLUS_MPU_RBAR_ADDR_MSB 31 -#define M0PLUS_MPU_RBAR_ADDR_LSB 8 +#define M0PLUS_MPU_RBAR_ADDR_RESET _u(0x000000) +#define M0PLUS_MPU_RBAR_ADDR_BITS _u(0xffffff00) +#define M0PLUS_MPU_RBAR_ADDR_MSB _u(31) +#define M0PLUS_MPU_RBAR_ADDR_LSB _u(8) #define M0PLUS_MPU_RBAR_ADDR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_RBAR_VALID @@ -1079,29 +1079,29 @@ // Updates the base address for the region specified in the REGION // field. // Always reads as zero. -#define M0PLUS_MPU_RBAR_VALID_RESET 0x0 -#define M0PLUS_MPU_RBAR_VALID_BITS 0x00000010 -#define M0PLUS_MPU_RBAR_VALID_MSB 4 -#define M0PLUS_MPU_RBAR_VALID_LSB 4 +#define M0PLUS_MPU_RBAR_VALID_RESET _u(0x0) +#define M0PLUS_MPU_RBAR_VALID_BITS _u(0x00000010) +#define M0PLUS_MPU_RBAR_VALID_MSB _u(4) +#define M0PLUS_MPU_RBAR_VALID_LSB _u(4) #define M0PLUS_MPU_RBAR_VALID_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_RBAR_REGION // Description : On writes, specifies the number of the region whose base // address to update provided VALID is set written as 1. On reads, // returns bits [3:0] of MPU_RNR. -#define M0PLUS_MPU_RBAR_REGION_RESET 0x0 -#define M0PLUS_MPU_RBAR_REGION_BITS 0x0000000f -#define M0PLUS_MPU_RBAR_REGION_MSB 3 -#define M0PLUS_MPU_RBAR_REGION_LSB 0 +#define M0PLUS_MPU_RBAR_REGION_RESET _u(0x0) +#define M0PLUS_MPU_RBAR_REGION_BITS _u(0x0000000f) +#define M0PLUS_MPU_RBAR_REGION_MSB _u(3) +#define M0PLUS_MPU_RBAR_REGION_LSB _u(0) #define M0PLUS_MPU_RBAR_REGION_ACCESS "RW" // ============================================================================= // Register : M0PLUS_MPU_RASR // Description : Use the MPU Region Attribute and Size Register to define the // size, access behaviour and memory type of the region identified // by MPU_RNR, and enable that region. -#define M0PLUS_MPU_RASR_OFFSET 0x0000eda0 -#define M0PLUS_MPU_RASR_BITS 0xffffff3f -#define M0PLUS_MPU_RASR_RESET 0x00000000 +#define M0PLUS_MPU_RASR_OFFSET _u(0x0000eda0) +#define M0PLUS_MPU_RASR_BITS _u(0xffffff3f) +#define M0PLUS_MPU_RASR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_RASR_ATTRS // Description : The MPU Region Attribute field. Use to define the region @@ -1113,37 +1113,37 @@ // 18 = S: Shareable bit // 17 = C: Cacheable bit // 16 = B: Bufferable bit -#define M0PLUS_MPU_RASR_ATTRS_RESET 0x0000 -#define M0PLUS_MPU_RASR_ATTRS_BITS 0xffff0000 -#define M0PLUS_MPU_RASR_ATTRS_MSB 31 -#define M0PLUS_MPU_RASR_ATTRS_LSB 16 +#define M0PLUS_MPU_RASR_ATTRS_RESET _u(0x0000) +#define M0PLUS_MPU_RASR_ATTRS_BITS _u(0xffff0000) +#define M0PLUS_MPU_RASR_ATTRS_MSB _u(31) +#define M0PLUS_MPU_RASR_ATTRS_LSB _u(16) #define M0PLUS_MPU_RASR_ATTRS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_RASR_SRD // Description : Subregion Disable. For regions of 256 bytes or larger, each bit // of this field controls whether one of the eight equal // subregions is enabled. -#define M0PLUS_MPU_RASR_SRD_RESET 0x00 -#define M0PLUS_MPU_RASR_SRD_BITS 0x0000ff00 -#define M0PLUS_MPU_RASR_SRD_MSB 15 -#define M0PLUS_MPU_RASR_SRD_LSB 8 +#define M0PLUS_MPU_RASR_SRD_RESET _u(0x00) +#define M0PLUS_MPU_RASR_SRD_BITS _u(0x0000ff00) +#define M0PLUS_MPU_RASR_SRD_MSB _u(15) +#define M0PLUS_MPU_RASR_SRD_LSB _u(8) #define M0PLUS_MPU_RASR_SRD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_RASR_SIZE // Description : Indicates the region size. Region size in bytes = 2^(SIZE+1). // The minimum permitted value is 7 (b00111) = 256Bytes -#define M0PLUS_MPU_RASR_SIZE_RESET 0x00 -#define M0PLUS_MPU_RASR_SIZE_BITS 0x0000003e -#define M0PLUS_MPU_RASR_SIZE_MSB 5 -#define M0PLUS_MPU_RASR_SIZE_LSB 1 +#define M0PLUS_MPU_RASR_SIZE_RESET _u(0x00) +#define M0PLUS_MPU_RASR_SIZE_BITS _u(0x0000003e) +#define M0PLUS_MPU_RASR_SIZE_MSB _u(5) +#define M0PLUS_MPU_RASR_SIZE_LSB _u(1) #define M0PLUS_MPU_RASR_SIZE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : M0PLUS_MPU_RASR_ENABLE // Description : Enables the region. -#define M0PLUS_MPU_RASR_ENABLE_RESET 0x0 -#define M0PLUS_MPU_RASR_ENABLE_BITS 0x00000001 -#define M0PLUS_MPU_RASR_ENABLE_MSB 0 -#define M0PLUS_MPU_RASR_ENABLE_LSB 0 +#define M0PLUS_MPU_RASR_ENABLE_RESET _u(0x0) +#define M0PLUS_MPU_RASR_ENABLE_BITS _u(0x00000001) +#define M0PLUS_MPU_RASR_ENABLE_MSB _u(0) +#define M0PLUS_MPU_RASR_ENABLE_LSB _u(0) #define M0PLUS_MPU_RASR_ENABLE_ACCESS "RW" // ============================================================================= #endif // HARDWARE_REGS_M0PLUS_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h index 92242bd44..06102ac97 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h @@ -16,36 +16,36 @@ // Description : Voltage select. Per bank control // 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) // 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) -#define PADS_BANK0_VOLTAGE_SELECT_OFFSET 0x00000000 -#define PADS_BANK0_VOLTAGE_SELECT_BITS 0x00000001 -#define PADS_BANK0_VOLTAGE_SELECT_RESET 0x00000000 -#define PADS_BANK0_VOLTAGE_SELECT_MSB 0 -#define PADS_BANK0_VOLTAGE_SELECT_LSB 0 +#define PADS_BANK0_VOLTAGE_SELECT_OFFSET _u(0x00000000) +#define PADS_BANK0_VOLTAGE_SELECT_BITS _u(0x00000001) +#define PADS_BANK0_VOLTAGE_SELECT_RESET _u(0x00000000) +#define PADS_BANK0_VOLTAGE_SELECT_MSB _u(0) +#define PADS_BANK0_VOLTAGE_SELECT_LSB _u(0) #define PADS_BANK0_VOLTAGE_SELECT_ACCESS "RW" -#define PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3 0x0 -#define PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8 0x1 +#define PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3 _u(0x0) +#define PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8 _u(0x1) // ============================================================================= // Register : PADS_BANK0_GPIO0 // Description : Pad control register -#define PADS_BANK0_GPIO0_OFFSET 0x00000004 -#define PADS_BANK0_GPIO0_BITS 0x000000ff -#define PADS_BANK0_GPIO0_RESET 0x00000056 +#define PADS_BANK0_GPIO0_OFFSET _u(0x00000004) +#define PADS_BANK0_GPIO0_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO0_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO0_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO0_OD_RESET 0x0 -#define PADS_BANK0_GPIO0_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO0_OD_MSB 7 -#define PADS_BANK0_GPIO0_OD_LSB 7 +#define PADS_BANK0_GPIO0_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO0_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO0_OD_MSB _u(7) +#define PADS_BANK0_GPIO0_OD_LSB _u(7) #define PADS_BANK0_GPIO0_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO0_IE // Description : Input enable -#define PADS_BANK0_GPIO0_IE_RESET 0x1 -#define PADS_BANK0_GPIO0_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO0_IE_MSB 6 -#define PADS_BANK0_GPIO0_IE_LSB 6 +#define PADS_BANK0_GPIO0_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO0_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO0_IE_MSB _u(6) +#define PADS_BANK0_GPIO0_IE_LSB _u(6) #define PADS_BANK0_GPIO0_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO0_DRIVE @@ -54,69 +54,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO0_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO0_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO0_DRIVE_MSB 5 -#define PADS_BANK0_GPIO0_DRIVE_LSB 4 +#define PADS_BANK0_GPIO0_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO0_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO0_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO0_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO0_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO0_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO0_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO0_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO0_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO0_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO0_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO0_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO0_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO0_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO0_PUE_RESET 0x0 -#define PADS_BANK0_GPIO0_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO0_PUE_MSB 3 -#define PADS_BANK0_GPIO0_PUE_LSB 3 +#define PADS_BANK0_GPIO0_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO0_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO0_PUE_MSB _u(3) +#define PADS_BANK0_GPIO0_PUE_LSB _u(3) #define PADS_BANK0_GPIO0_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO0_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO0_PDE_RESET 0x1 -#define PADS_BANK0_GPIO0_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO0_PDE_MSB 2 -#define PADS_BANK0_GPIO0_PDE_LSB 2 +#define PADS_BANK0_GPIO0_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO0_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO0_PDE_MSB _u(2) +#define PADS_BANK0_GPIO0_PDE_LSB _u(2) #define PADS_BANK0_GPIO0_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO0_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO0_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO0_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO0_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO0_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO0_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO0_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO0_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO0_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO0_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO0_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO0_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO0_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO0_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO0_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO0_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO0_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO0_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO0_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO0_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO1 // Description : Pad control register -#define PADS_BANK0_GPIO1_OFFSET 0x00000008 -#define PADS_BANK0_GPIO1_BITS 0x000000ff -#define PADS_BANK0_GPIO1_RESET 0x00000056 +#define PADS_BANK0_GPIO1_OFFSET _u(0x00000008) +#define PADS_BANK0_GPIO1_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO1_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO1_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO1_OD_RESET 0x0 -#define PADS_BANK0_GPIO1_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO1_OD_MSB 7 -#define PADS_BANK0_GPIO1_OD_LSB 7 +#define PADS_BANK0_GPIO1_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO1_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO1_OD_MSB _u(7) +#define PADS_BANK0_GPIO1_OD_LSB _u(7) #define PADS_BANK0_GPIO1_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO1_IE // Description : Input enable -#define PADS_BANK0_GPIO1_IE_RESET 0x1 -#define PADS_BANK0_GPIO1_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO1_IE_MSB 6 -#define PADS_BANK0_GPIO1_IE_LSB 6 +#define PADS_BANK0_GPIO1_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO1_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO1_IE_MSB _u(6) +#define PADS_BANK0_GPIO1_IE_LSB _u(6) #define PADS_BANK0_GPIO1_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO1_DRIVE @@ -125,69 +125,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO1_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO1_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO1_DRIVE_MSB 5 -#define PADS_BANK0_GPIO1_DRIVE_LSB 4 +#define PADS_BANK0_GPIO1_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO1_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO1_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO1_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO1_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO1_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO1_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO1_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO1_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO1_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO1_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO1_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO1_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO1_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO1_PUE_RESET 0x0 -#define PADS_BANK0_GPIO1_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO1_PUE_MSB 3 -#define PADS_BANK0_GPIO1_PUE_LSB 3 +#define PADS_BANK0_GPIO1_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO1_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO1_PUE_MSB _u(3) +#define PADS_BANK0_GPIO1_PUE_LSB _u(3) #define PADS_BANK0_GPIO1_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO1_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO1_PDE_RESET 0x1 -#define PADS_BANK0_GPIO1_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO1_PDE_MSB 2 -#define PADS_BANK0_GPIO1_PDE_LSB 2 +#define PADS_BANK0_GPIO1_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO1_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO1_PDE_MSB _u(2) +#define PADS_BANK0_GPIO1_PDE_LSB _u(2) #define PADS_BANK0_GPIO1_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO1_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO1_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO1_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO1_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO1_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO1_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO1_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO1_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO1_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO1_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO1_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO1_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO1_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO1_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO1_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO1_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO1_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO1_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO1_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO1_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO2 // Description : Pad control register -#define PADS_BANK0_GPIO2_OFFSET 0x0000000c -#define PADS_BANK0_GPIO2_BITS 0x000000ff -#define PADS_BANK0_GPIO2_RESET 0x00000056 +#define PADS_BANK0_GPIO2_OFFSET _u(0x0000000c) +#define PADS_BANK0_GPIO2_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO2_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO2_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO2_OD_RESET 0x0 -#define PADS_BANK0_GPIO2_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO2_OD_MSB 7 -#define PADS_BANK0_GPIO2_OD_LSB 7 +#define PADS_BANK0_GPIO2_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO2_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO2_OD_MSB _u(7) +#define PADS_BANK0_GPIO2_OD_LSB _u(7) #define PADS_BANK0_GPIO2_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO2_IE // Description : Input enable -#define PADS_BANK0_GPIO2_IE_RESET 0x1 -#define PADS_BANK0_GPIO2_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO2_IE_MSB 6 -#define PADS_BANK0_GPIO2_IE_LSB 6 +#define PADS_BANK0_GPIO2_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO2_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO2_IE_MSB _u(6) +#define PADS_BANK0_GPIO2_IE_LSB _u(6) #define PADS_BANK0_GPIO2_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO2_DRIVE @@ -196,69 +196,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO2_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO2_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO2_DRIVE_MSB 5 -#define PADS_BANK0_GPIO2_DRIVE_LSB 4 +#define PADS_BANK0_GPIO2_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO2_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO2_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO2_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO2_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO2_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO2_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO2_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO2_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO2_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO2_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO2_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO2_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO2_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO2_PUE_RESET 0x0 -#define PADS_BANK0_GPIO2_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO2_PUE_MSB 3 -#define PADS_BANK0_GPIO2_PUE_LSB 3 +#define PADS_BANK0_GPIO2_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO2_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO2_PUE_MSB _u(3) +#define PADS_BANK0_GPIO2_PUE_LSB _u(3) #define PADS_BANK0_GPIO2_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO2_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO2_PDE_RESET 0x1 -#define PADS_BANK0_GPIO2_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO2_PDE_MSB 2 -#define PADS_BANK0_GPIO2_PDE_LSB 2 +#define PADS_BANK0_GPIO2_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO2_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO2_PDE_MSB _u(2) +#define PADS_BANK0_GPIO2_PDE_LSB _u(2) #define PADS_BANK0_GPIO2_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO2_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO2_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO2_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO2_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO2_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO2_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO2_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO2_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO2_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO2_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO2_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO2_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO2_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO2_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO2_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO2_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO2_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO2_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO2_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO2_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO3 // Description : Pad control register -#define PADS_BANK0_GPIO3_OFFSET 0x00000010 -#define PADS_BANK0_GPIO3_BITS 0x000000ff -#define PADS_BANK0_GPIO3_RESET 0x00000056 +#define PADS_BANK0_GPIO3_OFFSET _u(0x00000010) +#define PADS_BANK0_GPIO3_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO3_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO3_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO3_OD_RESET 0x0 -#define PADS_BANK0_GPIO3_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO3_OD_MSB 7 -#define PADS_BANK0_GPIO3_OD_LSB 7 +#define PADS_BANK0_GPIO3_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO3_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO3_OD_MSB _u(7) +#define PADS_BANK0_GPIO3_OD_LSB _u(7) #define PADS_BANK0_GPIO3_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO3_IE // Description : Input enable -#define PADS_BANK0_GPIO3_IE_RESET 0x1 -#define PADS_BANK0_GPIO3_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO3_IE_MSB 6 -#define PADS_BANK0_GPIO3_IE_LSB 6 +#define PADS_BANK0_GPIO3_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO3_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO3_IE_MSB _u(6) +#define PADS_BANK0_GPIO3_IE_LSB _u(6) #define PADS_BANK0_GPIO3_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO3_DRIVE @@ -267,69 +267,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO3_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO3_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO3_DRIVE_MSB 5 -#define PADS_BANK0_GPIO3_DRIVE_LSB 4 +#define PADS_BANK0_GPIO3_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO3_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO3_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO3_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO3_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO3_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO3_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO3_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO3_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO3_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO3_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO3_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO3_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO3_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO3_PUE_RESET 0x0 -#define PADS_BANK0_GPIO3_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO3_PUE_MSB 3 -#define PADS_BANK0_GPIO3_PUE_LSB 3 +#define PADS_BANK0_GPIO3_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO3_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO3_PUE_MSB _u(3) +#define PADS_BANK0_GPIO3_PUE_LSB _u(3) #define PADS_BANK0_GPIO3_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO3_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO3_PDE_RESET 0x1 -#define PADS_BANK0_GPIO3_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO3_PDE_MSB 2 -#define PADS_BANK0_GPIO3_PDE_LSB 2 +#define PADS_BANK0_GPIO3_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO3_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO3_PDE_MSB _u(2) +#define PADS_BANK0_GPIO3_PDE_LSB _u(2) #define PADS_BANK0_GPIO3_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO3_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO3_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO3_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO3_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO3_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO3_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO3_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO3_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO3_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO3_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO3_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO3_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO3_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO3_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO3_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO3_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO3_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO3_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO3_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO3_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO4 // Description : Pad control register -#define PADS_BANK0_GPIO4_OFFSET 0x00000014 -#define PADS_BANK0_GPIO4_BITS 0x000000ff -#define PADS_BANK0_GPIO4_RESET 0x00000056 +#define PADS_BANK0_GPIO4_OFFSET _u(0x00000014) +#define PADS_BANK0_GPIO4_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO4_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO4_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO4_OD_RESET 0x0 -#define PADS_BANK0_GPIO4_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO4_OD_MSB 7 -#define PADS_BANK0_GPIO4_OD_LSB 7 +#define PADS_BANK0_GPIO4_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO4_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO4_OD_MSB _u(7) +#define PADS_BANK0_GPIO4_OD_LSB _u(7) #define PADS_BANK0_GPIO4_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO4_IE // Description : Input enable -#define PADS_BANK0_GPIO4_IE_RESET 0x1 -#define PADS_BANK0_GPIO4_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO4_IE_MSB 6 -#define PADS_BANK0_GPIO4_IE_LSB 6 +#define PADS_BANK0_GPIO4_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO4_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO4_IE_MSB _u(6) +#define PADS_BANK0_GPIO4_IE_LSB _u(6) #define PADS_BANK0_GPIO4_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO4_DRIVE @@ -338,69 +338,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO4_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO4_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO4_DRIVE_MSB 5 -#define PADS_BANK0_GPIO4_DRIVE_LSB 4 +#define PADS_BANK0_GPIO4_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO4_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO4_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO4_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO4_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO4_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO4_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO4_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO4_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO4_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO4_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO4_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO4_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO4_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO4_PUE_RESET 0x0 -#define PADS_BANK0_GPIO4_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO4_PUE_MSB 3 -#define PADS_BANK0_GPIO4_PUE_LSB 3 +#define PADS_BANK0_GPIO4_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO4_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO4_PUE_MSB _u(3) +#define PADS_BANK0_GPIO4_PUE_LSB _u(3) #define PADS_BANK0_GPIO4_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO4_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO4_PDE_RESET 0x1 -#define PADS_BANK0_GPIO4_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO4_PDE_MSB 2 -#define PADS_BANK0_GPIO4_PDE_LSB 2 +#define PADS_BANK0_GPIO4_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO4_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO4_PDE_MSB _u(2) +#define PADS_BANK0_GPIO4_PDE_LSB _u(2) #define PADS_BANK0_GPIO4_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO4_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO4_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO4_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO4_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO4_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO4_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO4_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO4_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO4_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO4_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO4_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO4_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO4_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO4_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO4_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO4_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO4_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO4_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO4_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO4_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO5 // Description : Pad control register -#define PADS_BANK0_GPIO5_OFFSET 0x00000018 -#define PADS_BANK0_GPIO5_BITS 0x000000ff -#define PADS_BANK0_GPIO5_RESET 0x00000056 +#define PADS_BANK0_GPIO5_OFFSET _u(0x00000018) +#define PADS_BANK0_GPIO5_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO5_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO5_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO5_OD_RESET 0x0 -#define PADS_BANK0_GPIO5_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO5_OD_MSB 7 -#define PADS_BANK0_GPIO5_OD_LSB 7 +#define PADS_BANK0_GPIO5_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO5_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO5_OD_MSB _u(7) +#define PADS_BANK0_GPIO5_OD_LSB _u(7) #define PADS_BANK0_GPIO5_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO5_IE // Description : Input enable -#define PADS_BANK0_GPIO5_IE_RESET 0x1 -#define PADS_BANK0_GPIO5_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO5_IE_MSB 6 -#define PADS_BANK0_GPIO5_IE_LSB 6 +#define PADS_BANK0_GPIO5_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO5_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO5_IE_MSB _u(6) +#define PADS_BANK0_GPIO5_IE_LSB _u(6) #define PADS_BANK0_GPIO5_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO5_DRIVE @@ -409,69 +409,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO5_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO5_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO5_DRIVE_MSB 5 -#define PADS_BANK0_GPIO5_DRIVE_LSB 4 +#define PADS_BANK0_GPIO5_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO5_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO5_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO5_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO5_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO5_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO5_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO5_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO5_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO5_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO5_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO5_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO5_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO5_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO5_PUE_RESET 0x0 -#define PADS_BANK0_GPIO5_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO5_PUE_MSB 3 -#define PADS_BANK0_GPIO5_PUE_LSB 3 +#define PADS_BANK0_GPIO5_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO5_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO5_PUE_MSB _u(3) +#define PADS_BANK0_GPIO5_PUE_LSB _u(3) #define PADS_BANK0_GPIO5_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO5_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO5_PDE_RESET 0x1 -#define PADS_BANK0_GPIO5_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO5_PDE_MSB 2 -#define PADS_BANK0_GPIO5_PDE_LSB 2 +#define PADS_BANK0_GPIO5_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO5_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO5_PDE_MSB _u(2) +#define PADS_BANK0_GPIO5_PDE_LSB _u(2) #define PADS_BANK0_GPIO5_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO5_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO5_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO5_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO5_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO5_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO5_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO5_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO5_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO5_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO5_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO5_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO5_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO5_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO5_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO5_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO5_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO5_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO5_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO5_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO5_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO6 // Description : Pad control register -#define PADS_BANK0_GPIO6_OFFSET 0x0000001c -#define PADS_BANK0_GPIO6_BITS 0x000000ff -#define PADS_BANK0_GPIO6_RESET 0x00000056 +#define PADS_BANK0_GPIO6_OFFSET _u(0x0000001c) +#define PADS_BANK0_GPIO6_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO6_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO6_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO6_OD_RESET 0x0 -#define PADS_BANK0_GPIO6_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO6_OD_MSB 7 -#define PADS_BANK0_GPIO6_OD_LSB 7 +#define PADS_BANK0_GPIO6_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO6_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO6_OD_MSB _u(7) +#define PADS_BANK0_GPIO6_OD_LSB _u(7) #define PADS_BANK0_GPIO6_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO6_IE // Description : Input enable -#define PADS_BANK0_GPIO6_IE_RESET 0x1 -#define PADS_BANK0_GPIO6_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO6_IE_MSB 6 -#define PADS_BANK0_GPIO6_IE_LSB 6 +#define PADS_BANK0_GPIO6_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO6_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO6_IE_MSB _u(6) +#define PADS_BANK0_GPIO6_IE_LSB _u(6) #define PADS_BANK0_GPIO6_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO6_DRIVE @@ -480,69 +480,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO6_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO6_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO6_DRIVE_MSB 5 -#define PADS_BANK0_GPIO6_DRIVE_LSB 4 +#define PADS_BANK0_GPIO6_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO6_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO6_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO6_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO6_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO6_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO6_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO6_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO6_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO6_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO6_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO6_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO6_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO6_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO6_PUE_RESET 0x0 -#define PADS_BANK0_GPIO6_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO6_PUE_MSB 3 -#define PADS_BANK0_GPIO6_PUE_LSB 3 +#define PADS_BANK0_GPIO6_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO6_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO6_PUE_MSB _u(3) +#define PADS_BANK0_GPIO6_PUE_LSB _u(3) #define PADS_BANK0_GPIO6_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO6_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO6_PDE_RESET 0x1 -#define PADS_BANK0_GPIO6_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO6_PDE_MSB 2 -#define PADS_BANK0_GPIO6_PDE_LSB 2 +#define PADS_BANK0_GPIO6_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO6_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO6_PDE_MSB _u(2) +#define PADS_BANK0_GPIO6_PDE_LSB _u(2) #define PADS_BANK0_GPIO6_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO6_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO6_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO6_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO6_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO6_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO6_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO6_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO6_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO6_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO6_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO6_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO6_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO6_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO6_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO6_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO6_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO6_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO6_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO6_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO6_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO7 // Description : Pad control register -#define PADS_BANK0_GPIO7_OFFSET 0x00000020 -#define PADS_BANK0_GPIO7_BITS 0x000000ff -#define PADS_BANK0_GPIO7_RESET 0x00000056 +#define PADS_BANK0_GPIO7_OFFSET _u(0x00000020) +#define PADS_BANK0_GPIO7_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO7_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO7_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO7_OD_RESET 0x0 -#define PADS_BANK0_GPIO7_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO7_OD_MSB 7 -#define PADS_BANK0_GPIO7_OD_LSB 7 +#define PADS_BANK0_GPIO7_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO7_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO7_OD_MSB _u(7) +#define PADS_BANK0_GPIO7_OD_LSB _u(7) #define PADS_BANK0_GPIO7_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO7_IE // Description : Input enable -#define PADS_BANK0_GPIO7_IE_RESET 0x1 -#define PADS_BANK0_GPIO7_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO7_IE_MSB 6 -#define PADS_BANK0_GPIO7_IE_LSB 6 +#define PADS_BANK0_GPIO7_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO7_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO7_IE_MSB _u(6) +#define PADS_BANK0_GPIO7_IE_LSB _u(6) #define PADS_BANK0_GPIO7_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO7_DRIVE @@ -551,69 +551,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO7_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO7_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO7_DRIVE_MSB 5 -#define PADS_BANK0_GPIO7_DRIVE_LSB 4 +#define PADS_BANK0_GPIO7_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO7_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO7_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO7_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO7_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO7_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO7_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO7_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO7_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO7_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO7_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO7_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO7_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO7_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO7_PUE_RESET 0x0 -#define PADS_BANK0_GPIO7_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO7_PUE_MSB 3 -#define PADS_BANK0_GPIO7_PUE_LSB 3 +#define PADS_BANK0_GPIO7_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO7_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO7_PUE_MSB _u(3) +#define PADS_BANK0_GPIO7_PUE_LSB _u(3) #define PADS_BANK0_GPIO7_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO7_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO7_PDE_RESET 0x1 -#define PADS_BANK0_GPIO7_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO7_PDE_MSB 2 -#define PADS_BANK0_GPIO7_PDE_LSB 2 +#define PADS_BANK0_GPIO7_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO7_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO7_PDE_MSB _u(2) +#define PADS_BANK0_GPIO7_PDE_LSB _u(2) #define PADS_BANK0_GPIO7_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO7_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO7_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO7_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO7_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO7_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO7_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO7_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO7_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO7_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO7_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO7_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO7_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO7_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO7_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO7_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO7_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO7_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO7_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO7_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO7_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO8 // Description : Pad control register -#define PADS_BANK0_GPIO8_OFFSET 0x00000024 -#define PADS_BANK0_GPIO8_BITS 0x000000ff -#define PADS_BANK0_GPIO8_RESET 0x00000056 +#define PADS_BANK0_GPIO8_OFFSET _u(0x00000024) +#define PADS_BANK0_GPIO8_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO8_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO8_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO8_OD_RESET 0x0 -#define PADS_BANK0_GPIO8_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO8_OD_MSB 7 -#define PADS_BANK0_GPIO8_OD_LSB 7 +#define PADS_BANK0_GPIO8_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO8_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO8_OD_MSB _u(7) +#define PADS_BANK0_GPIO8_OD_LSB _u(7) #define PADS_BANK0_GPIO8_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO8_IE // Description : Input enable -#define PADS_BANK0_GPIO8_IE_RESET 0x1 -#define PADS_BANK0_GPIO8_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO8_IE_MSB 6 -#define PADS_BANK0_GPIO8_IE_LSB 6 +#define PADS_BANK0_GPIO8_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO8_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO8_IE_MSB _u(6) +#define PADS_BANK0_GPIO8_IE_LSB _u(6) #define PADS_BANK0_GPIO8_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO8_DRIVE @@ -622,69 +622,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO8_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO8_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO8_DRIVE_MSB 5 -#define PADS_BANK0_GPIO8_DRIVE_LSB 4 +#define PADS_BANK0_GPIO8_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO8_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO8_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO8_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO8_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO8_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO8_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO8_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO8_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO8_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO8_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO8_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO8_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO8_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO8_PUE_RESET 0x0 -#define PADS_BANK0_GPIO8_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO8_PUE_MSB 3 -#define PADS_BANK0_GPIO8_PUE_LSB 3 +#define PADS_BANK0_GPIO8_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO8_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO8_PUE_MSB _u(3) +#define PADS_BANK0_GPIO8_PUE_LSB _u(3) #define PADS_BANK0_GPIO8_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO8_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO8_PDE_RESET 0x1 -#define PADS_BANK0_GPIO8_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO8_PDE_MSB 2 -#define PADS_BANK0_GPIO8_PDE_LSB 2 +#define PADS_BANK0_GPIO8_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO8_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO8_PDE_MSB _u(2) +#define PADS_BANK0_GPIO8_PDE_LSB _u(2) #define PADS_BANK0_GPIO8_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO8_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO8_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO8_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO8_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO8_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO8_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO8_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO8_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO8_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO8_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO8_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO8_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO8_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO8_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO8_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO8_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO8_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO8_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO8_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO8_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO9 // Description : Pad control register -#define PADS_BANK0_GPIO9_OFFSET 0x00000028 -#define PADS_BANK0_GPIO9_BITS 0x000000ff -#define PADS_BANK0_GPIO9_RESET 0x00000056 +#define PADS_BANK0_GPIO9_OFFSET _u(0x00000028) +#define PADS_BANK0_GPIO9_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO9_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO9_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO9_OD_RESET 0x0 -#define PADS_BANK0_GPIO9_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO9_OD_MSB 7 -#define PADS_BANK0_GPIO9_OD_LSB 7 +#define PADS_BANK0_GPIO9_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO9_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO9_OD_MSB _u(7) +#define PADS_BANK0_GPIO9_OD_LSB _u(7) #define PADS_BANK0_GPIO9_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO9_IE // Description : Input enable -#define PADS_BANK0_GPIO9_IE_RESET 0x1 -#define PADS_BANK0_GPIO9_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO9_IE_MSB 6 -#define PADS_BANK0_GPIO9_IE_LSB 6 +#define PADS_BANK0_GPIO9_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO9_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO9_IE_MSB _u(6) +#define PADS_BANK0_GPIO9_IE_LSB _u(6) #define PADS_BANK0_GPIO9_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO9_DRIVE @@ -693,69 +693,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO9_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO9_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO9_DRIVE_MSB 5 -#define PADS_BANK0_GPIO9_DRIVE_LSB 4 +#define PADS_BANK0_GPIO9_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO9_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO9_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO9_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO9_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO9_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO9_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO9_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO9_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO9_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO9_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO9_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO9_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO9_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO9_PUE_RESET 0x0 -#define PADS_BANK0_GPIO9_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO9_PUE_MSB 3 -#define PADS_BANK0_GPIO9_PUE_LSB 3 +#define PADS_BANK0_GPIO9_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO9_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO9_PUE_MSB _u(3) +#define PADS_BANK0_GPIO9_PUE_LSB _u(3) #define PADS_BANK0_GPIO9_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO9_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO9_PDE_RESET 0x1 -#define PADS_BANK0_GPIO9_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO9_PDE_MSB 2 -#define PADS_BANK0_GPIO9_PDE_LSB 2 +#define PADS_BANK0_GPIO9_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO9_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO9_PDE_MSB _u(2) +#define PADS_BANK0_GPIO9_PDE_LSB _u(2) #define PADS_BANK0_GPIO9_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO9_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO9_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO9_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO9_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO9_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO9_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO9_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO9_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO9_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO9_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO9_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO9_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO9_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO9_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO9_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO9_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO9_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO9_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO9_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO9_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO10 // Description : Pad control register -#define PADS_BANK0_GPIO10_OFFSET 0x0000002c -#define PADS_BANK0_GPIO10_BITS 0x000000ff -#define PADS_BANK0_GPIO10_RESET 0x00000056 +#define PADS_BANK0_GPIO10_OFFSET _u(0x0000002c) +#define PADS_BANK0_GPIO10_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO10_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO10_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO10_OD_RESET 0x0 -#define PADS_BANK0_GPIO10_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO10_OD_MSB 7 -#define PADS_BANK0_GPIO10_OD_LSB 7 +#define PADS_BANK0_GPIO10_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO10_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO10_OD_MSB _u(7) +#define PADS_BANK0_GPIO10_OD_LSB _u(7) #define PADS_BANK0_GPIO10_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO10_IE // Description : Input enable -#define PADS_BANK0_GPIO10_IE_RESET 0x1 -#define PADS_BANK0_GPIO10_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO10_IE_MSB 6 -#define PADS_BANK0_GPIO10_IE_LSB 6 +#define PADS_BANK0_GPIO10_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO10_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO10_IE_MSB _u(6) +#define PADS_BANK0_GPIO10_IE_LSB _u(6) #define PADS_BANK0_GPIO10_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO10_DRIVE @@ -764,69 +764,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO10_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO10_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO10_DRIVE_MSB 5 -#define PADS_BANK0_GPIO10_DRIVE_LSB 4 +#define PADS_BANK0_GPIO10_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO10_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO10_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO10_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO10_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO10_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO10_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO10_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO10_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO10_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO10_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO10_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO10_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO10_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO10_PUE_RESET 0x0 -#define PADS_BANK0_GPIO10_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO10_PUE_MSB 3 -#define PADS_BANK0_GPIO10_PUE_LSB 3 +#define PADS_BANK0_GPIO10_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO10_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO10_PUE_MSB _u(3) +#define PADS_BANK0_GPIO10_PUE_LSB _u(3) #define PADS_BANK0_GPIO10_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO10_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO10_PDE_RESET 0x1 -#define PADS_BANK0_GPIO10_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO10_PDE_MSB 2 -#define PADS_BANK0_GPIO10_PDE_LSB 2 +#define PADS_BANK0_GPIO10_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO10_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO10_PDE_MSB _u(2) +#define PADS_BANK0_GPIO10_PDE_LSB _u(2) #define PADS_BANK0_GPIO10_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO10_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO10_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO10_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO10_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO10_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO10_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO10_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO10_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO10_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO10_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO10_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO10_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO10_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO10_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO10_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO10_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO10_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO10_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO10_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO10_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO11 // Description : Pad control register -#define PADS_BANK0_GPIO11_OFFSET 0x00000030 -#define PADS_BANK0_GPIO11_BITS 0x000000ff -#define PADS_BANK0_GPIO11_RESET 0x00000056 +#define PADS_BANK0_GPIO11_OFFSET _u(0x00000030) +#define PADS_BANK0_GPIO11_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO11_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO11_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO11_OD_RESET 0x0 -#define PADS_BANK0_GPIO11_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO11_OD_MSB 7 -#define PADS_BANK0_GPIO11_OD_LSB 7 +#define PADS_BANK0_GPIO11_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO11_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO11_OD_MSB _u(7) +#define PADS_BANK0_GPIO11_OD_LSB _u(7) #define PADS_BANK0_GPIO11_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO11_IE // Description : Input enable -#define PADS_BANK0_GPIO11_IE_RESET 0x1 -#define PADS_BANK0_GPIO11_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO11_IE_MSB 6 -#define PADS_BANK0_GPIO11_IE_LSB 6 +#define PADS_BANK0_GPIO11_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO11_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO11_IE_MSB _u(6) +#define PADS_BANK0_GPIO11_IE_LSB _u(6) #define PADS_BANK0_GPIO11_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO11_DRIVE @@ -835,69 +835,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO11_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO11_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO11_DRIVE_MSB 5 -#define PADS_BANK0_GPIO11_DRIVE_LSB 4 +#define PADS_BANK0_GPIO11_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO11_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO11_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO11_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO11_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO11_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO11_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO11_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO11_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO11_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO11_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO11_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO11_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO11_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO11_PUE_RESET 0x0 -#define PADS_BANK0_GPIO11_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO11_PUE_MSB 3 -#define PADS_BANK0_GPIO11_PUE_LSB 3 +#define PADS_BANK0_GPIO11_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO11_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO11_PUE_MSB _u(3) +#define PADS_BANK0_GPIO11_PUE_LSB _u(3) #define PADS_BANK0_GPIO11_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO11_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO11_PDE_RESET 0x1 -#define PADS_BANK0_GPIO11_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO11_PDE_MSB 2 -#define PADS_BANK0_GPIO11_PDE_LSB 2 +#define PADS_BANK0_GPIO11_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO11_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO11_PDE_MSB _u(2) +#define PADS_BANK0_GPIO11_PDE_LSB _u(2) #define PADS_BANK0_GPIO11_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO11_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO11_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO11_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO11_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO11_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO11_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO11_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO11_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO11_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO11_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO11_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO11_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO11_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO11_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO11_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO11_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO11_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO11_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO11_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO11_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO12 // Description : Pad control register -#define PADS_BANK0_GPIO12_OFFSET 0x00000034 -#define PADS_BANK0_GPIO12_BITS 0x000000ff -#define PADS_BANK0_GPIO12_RESET 0x00000056 +#define PADS_BANK0_GPIO12_OFFSET _u(0x00000034) +#define PADS_BANK0_GPIO12_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO12_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO12_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO12_OD_RESET 0x0 -#define PADS_BANK0_GPIO12_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO12_OD_MSB 7 -#define PADS_BANK0_GPIO12_OD_LSB 7 +#define PADS_BANK0_GPIO12_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO12_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO12_OD_MSB _u(7) +#define PADS_BANK0_GPIO12_OD_LSB _u(7) #define PADS_BANK0_GPIO12_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO12_IE // Description : Input enable -#define PADS_BANK0_GPIO12_IE_RESET 0x1 -#define PADS_BANK0_GPIO12_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO12_IE_MSB 6 -#define PADS_BANK0_GPIO12_IE_LSB 6 +#define PADS_BANK0_GPIO12_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO12_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO12_IE_MSB _u(6) +#define PADS_BANK0_GPIO12_IE_LSB _u(6) #define PADS_BANK0_GPIO12_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO12_DRIVE @@ -906,69 +906,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO12_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO12_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO12_DRIVE_MSB 5 -#define PADS_BANK0_GPIO12_DRIVE_LSB 4 +#define PADS_BANK0_GPIO12_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO12_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO12_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO12_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO12_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO12_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO12_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO12_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO12_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO12_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO12_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO12_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO12_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO12_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO12_PUE_RESET 0x0 -#define PADS_BANK0_GPIO12_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO12_PUE_MSB 3 -#define PADS_BANK0_GPIO12_PUE_LSB 3 +#define PADS_BANK0_GPIO12_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO12_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO12_PUE_MSB _u(3) +#define PADS_BANK0_GPIO12_PUE_LSB _u(3) #define PADS_BANK0_GPIO12_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO12_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO12_PDE_RESET 0x1 -#define PADS_BANK0_GPIO12_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO12_PDE_MSB 2 -#define PADS_BANK0_GPIO12_PDE_LSB 2 +#define PADS_BANK0_GPIO12_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO12_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO12_PDE_MSB _u(2) +#define PADS_BANK0_GPIO12_PDE_LSB _u(2) #define PADS_BANK0_GPIO12_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO12_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO12_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO12_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO12_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO12_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO12_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO12_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO12_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO12_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO12_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO12_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO12_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO12_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO12_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO12_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO12_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO12_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO12_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO12_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO12_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO13 // Description : Pad control register -#define PADS_BANK0_GPIO13_OFFSET 0x00000038 -#define PADS_BANK0_GPIO13_BITS 0x000000ff -#define PADS_BANK0_GPIO13_RESET 0x00000056 +#define PADS_BANK0_GPIO13_OFFSET _u(0x00000038) +#define PADS_BANK0_GPIO13_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO13_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO13_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO13_OD_RESET 0x0 -#define PADS_BANK0_GPIO13_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO13_OD_MSB 7 -#define PADS_BANK0_GPIO13_OD_LSB 7 +#define PADS_BANK0_GPIO13_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO13_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO13_OD_MSB _u(7) +#define PADS_BANK0_GPIO13_OD_LSB _u(7) #define PADS_BANK0_GPIO13_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO13_IE // Description : Input enable -#define PADS_BANK0_GPIO13_IE_RESET 0x1 -#define PADS_BANK0_GPIO13_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO13_IE_MSB 6 -#define PADS_BANK0_GPIO13_IE_LSB 6 +#define PADS_BANK0_GPIO13_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO13_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO13_IE_MSB _u(6) +#define PADS_BANK0_GPIO13_IE_LSB _u(6) #define PADS_BANK0_GPIO13_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO13_DRIVE @@ -977,69 +977,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO13_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO13_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO13_DRIVE_MSB 5 -#define PADS_BANK0_GPIO13_DRIVE_LSB 4 +#define PADS_BANK0_GPIO13_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO13_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO13_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO13_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO13_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO13_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO13_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO13_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO13_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO13_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO13_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO13_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO13_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO13_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO13_PUE_RESET 0x0 -#define PADS_BANK0_GPIO13_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO13_PUE_MSB 3 -#define PADS_BANK0_GPIO13_PUE_LSB 3 +#define PADS_BANK0_GPIO13_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO13_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO13_PUE_MSB _u(3) +#define PADS_BANK0_GPIO13_PUE_LSB _u(3) #define PADS_BANK0_GPIO13_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO13_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO13_PDE_RESET 0x1 -#define PADS_BANK0_GPIO13_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO13_PDE_MSB 2 -#define PADS_BANK0_GPIO13_PDE_LSB 2 +#define PADS_BANK0_GPIO13_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO13_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO13_PDE_MSB _u(2) +#define PADS_BANK0_GPIO13_PDE_LSB _u(2) #define PADS_BANK0_GPIO13_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO13_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO13_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO13_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO13_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO13_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO13_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO13_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO13_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO13_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO13_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO13_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO13_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO13_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO13_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO13_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO13_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO13_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO13_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO13_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO13_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO14 // Description : Pad control register -#define PADS_BANK0_GPIO14_OFFSET 0x0000003c -#define PADS_BANK0_GPIO14_BITS 0x000000ff -#define PADS_BANK0_GPIO14_RESET 0x00000056 +#define PADS_BANK0_GPIO14_OFFSET _u(0x0000003c) +#define PADS_BANK0_GPIO14_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO14_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO14_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO14_OD_RESET 0x0 -#define PADS_BANK0_GPIO14_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO14_OD_MSB 7 -#define PADS_BANK0_GPIO14_OD_LSB 7 +#define PADS_BANK0_GPIO14_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO14_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO14_OD_MSB _u(7) +#define PADS_BANK0_GPIO14_OD_LSB _u(7) #define PADS_BANK0_GPIO14_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO14_IE // Description : Input enable -#define PADS_BANK0_GPIO14_IE_RESET 0x1 -#define PADS_BANK0_GPIO14_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO14_IE_MSB 6 -#define PADS_BANK0_GPIO14_IE_LSB 6 +#define PADS_BANK0_GPIO14_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO14_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO14_IE_MSB _u(6) +#define PADS_BANK0_GPIO14_IE_LSB _u(6) #define PADS_BANK0_GPIO14_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO14_DRIVE @@ -1048,69 +1048,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO14_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO14_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO14_DRIVE_MSB 5 -#define PADS_BANK0_GPIO14_DRIVE_LSB 4 +#define PADS_BANK0_GPIO14_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO14_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO14_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO14_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO14_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO14_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO14_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO14_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO14_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO14_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO14_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO14_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO14_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO14_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO14_PUE_RESET 0x0 -#define PADS_BANK0_GPIO14_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO14_PUE_MSB 3 -#define PADS_BANK0_GPIO14_PUE_LSB 3 +#define PADS_BANK0_GPIO14_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO14_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO14_PUE_MSB _u(3) +#define PADS_BANK0_GPIO14_PUE_LSB _u(3) #define PADS_BANK0_GPIO14_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO14_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO14_PDE_RESET 0x1 -#define PADS_BANK0_GPIO14_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO14_PDE_MSB 2 -#define PADS_BANK0_GPIO14_PDE_LSB 2 +#define PADS_BANK0_GPIO14_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO14_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO14_PDE_MSB _u(2) +#define PADS_BANK0_GPIO14_PDE_LSB _u(2) #define PADS_BANK0_GPIO14_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO14_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO14_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO14_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO14_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO14_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO14_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO14_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO14_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO14_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO14_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO14_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO14_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO14_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO14_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO14_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO14_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO14_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO14_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO14_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO14_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO15 // Description : Pad control register -#define PADS_BANK0_GPIO15_OFFSET 0x00000040 -#define PADS_BANK0_GPIO15_BITS 0x000000ff -#define PADS_BANK0_GPIO15_RESET 0x00000056 +#define PADS_BANK0_GPIO15_OFFSET _u(0x00000040) +#define PADS_BANK0_GPIO15_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO15_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO15_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO15_OD_RESET 0x0 -#define PADS_BANK0_GPIO15_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO15_OD_MSB 7 -#define PADS_BANK0_GPIO15_OD_LSB 7 +#define PADS_BANK0_GPIO15_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO15_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO15_OD_MSB _u(7) +#define PADS_BANK0_GPIO15_OD_LSB _u(7) #define PADS_BANK0_GPIO15_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO15_IE // Description : Input enable -#define PADS_BANK0_GPIO15_IE_RESET 0x1 -#define PADS_BANK0_GPIO15_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO15_IE_MSB 6 -#define PADS_BANK0_GPIO15_IE_LSB 6 +#define PADS_BANK0_GPIO15_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO15_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO15_IE_MSB _u(6) +#define PADS_BANK0_GPIO15_IE_LSB _u(6) #define PADS_BANK0_GPIO15_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO15_DRIVE @@ -1119,69 +1119,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO15_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO15_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO15_DRIVE_MSB 5 -#define PADS_BANK0_GPIO15_DRIVE_LSB 4 +#define PADS_BANK0_GPIO15_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO15_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO15_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO15_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO15_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO15_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO15_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO15_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO15_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO15_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO15_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO15_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO15_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO15_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO15_PUE_RESET 0x0 -#define PADS_BANK0_GPIO15_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO15_PUE_MSB 3 -#define PADS_BANK0_GPIO15_PUE_LSB 3 +#define PADS_BANK0_GPIO15_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO15_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO15_PUE_MSB _u(3) +#define PADS_BANK0_GPIO15_PUE_LSB _u(3) #define PADS_BANK0_GPIO15_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO15_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO15_PDE_RESET 0x1 -#define PADS_BANK0_GPIO15_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO15_PDE_MSB 2 -#define PADS_BANK0_GPIO15_PDE_LSB 2 +#define PADS_BANK0_GPIO15_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO15_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO15_PDE_MSB _u(2) +#define PADS_BANK0_GPIO15_PDE_LSB _u(2) #define PADS_BANK0_GPIO15_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO15_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO15_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO15_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO15_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO15_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO15_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO15_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO15_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO15_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO15_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO15_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO15_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO15_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO15_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO15_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO15_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO15_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO15_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO15_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO15_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO16 // Description : Pad control register -#define PADS_BANK0_GPIO16_OFFSET 0x00000044 -#define PADS_BANK0_GPIO16_BITS 0x000000ff -#define PADS_BANK0_GPIO16_RESET 0x00000056 +#define PADS_BANK0_GPIO16_OFFSET _u(0x00000044) +#define PADS_BANK0_GPIO16_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO16_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO16_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO16_OD_RESET 0x0 -#define PADS_BANK0_GPIO16_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO16_OD_MSB 7 -#define PADS_BANK0_GPIO16_OD_LSB 7 +#define PADS_BANK0_GPIO16_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO16_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO16_OD_MSB _u(7) +#define PADS_BANK0_GPIO16_OD_LSB _u(7) #define PADS_BANK0_GPIO16_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO16_IE // Description : Input enable -#define PADS_BANK0_GPIO16_IE_RESET 0x1 -#define PADS_BANK0_GPIO16_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO16_IE_MSB 6 -#define PADS_BANK0_GPIO16_IE_LSB 6 +#define PADS_BANK0_GPIO16_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO16_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO16_IE_MSB _u(6) +#define PADS_BANK0_GPIO16_IE_LSB _u(6) #define PADS_BANK0_GPIO16_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO16_DRIVE @@ -1190,69 +1190,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO16_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO16_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO16_DRIVE_MSB 5 -#define PADS_BANK0_GPIO16_DRIVE_LSB 4 +#define PADS_BANK0_GPIO16_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO16_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO16_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO16_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO16_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO16_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO16_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO16_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO16_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO16_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO16_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO16_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO16_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO16_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO16_PUE_RESET 0x0 -#define PADS_BANK0_GPIO16_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO16_PUE_MSB 3 -#define PADS_BANK0_GPIO16_PUE_LSB 3 +#define PADS_BANK0_GPIO16_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO16_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO16_PUE_MSB _u(3) +#define PADS_BANK0_GPIO16_PUE_LSB _u(3) #define PADS_BANK0_GPIO16_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO16_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO16_PDE_RESET 0x1 -#define PADS_BANK0_GPIO16_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO16_PDE_MSB 2 -#define PADS_BANK0_GPIO16_PDE_LSB 2 +#define PADS_BANK0_GPIO16_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO16_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO16_PDE_MSB _u(2) +#define PADS_BANK0_GPIO16_PDE_LSB _u(2) #define PADS_BANK0_GPIO16_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO16_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO16_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO16_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO16_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO16_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO16_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO16_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO16_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO16_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO16_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO16_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO16_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO16_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO16_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO16_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO16_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO16_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO16_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO16_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO16_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO17 // Description : Pad control register -#define PADS_BANK0_GPIO17_OFFSET 0x00000048 -#define PADS_BANK0_GPIO17_BITS 0x000000ff -#define PADS_BANK0_GPIO17_RESET 0x00000056 +#define PADS_BANK0_GPIO17_OFFSET _u(0x00000048) +#define PADS_BANK0_GPIO17_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO17_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO17_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO17_OD_RESET 0x0 -#define PADS_BANK0_GPIO17_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO17_OD_MSB 7 -#define PADS_BANK0_GPIO17_OD_LSB 7 +#define PADS_BANK0_GPIO17_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO17_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO17_OD_MSB _u(7) +#define PADS_BANK0_GPIO17_OD_LSB _u(7) #define PADS_BANK0_GPIO17_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO17_IE // Description : Input enable -#define PADS_BANK0_GPIO17_IE_RESET 0x1 -#define PADS_BANK0_GPIO17_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO17_IE_MSB 6 -#define PADS_BANK0_GPIO17_IE_LSB 6 +#define PADS_BANK0_GPIO17_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO17_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO17_IE_MSB _u(6) +#define PADS_BANK0_GPIO17_IE_LSB _u(6) #define PADS_BANK0_GPIO17_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO17_DRIVE @@ -1261,69 +1261,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO17_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO17_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO17_DRIVE_MSB 5 -#define PADS_BANK0_GPIO17_DRIVE_LSB 4 +#define PADS_BANK0_GPIO17_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO17_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO17_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO17_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO17_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO17_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO17_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO17_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO17_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO17_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO17_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO17_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO17_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO17_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO17_PUE_RESET 0x0 -#define PADS_BANK0_GPIO17_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO17_PUE_MSB 3 -#define PADS_BANK0_GPIO17_PUE_LSB 3 +#define PADS_BANK0_GPIO17_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO17_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO17_PUE_MSB _u(3) +#define PADS_BANK0_GPIO17_PUE_LSB _u(3) #define PADS_BANK0_GPIO17_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO17_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO17_PDE_RESET 0x1 -#define PADS_BANK0_GPIO17_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO17_PDE_MSB 2 -#define PADS_BANK0_GPIO17_PDE_LSB 2 +#define PADS_BANK0_GPIO17_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO17_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO17_PDE_MSB _u(2) +#define PADS_BANK0_GPIO17_PDE_LSB _u(2) #define PADS_BANK0_GPIO17_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO17_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO17_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO17_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO17_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO17_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO17_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO17_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO17_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO17_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO17_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO17_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO17_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO17_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO17_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO17_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO17_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO17_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO17_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO17_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO17_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO18 // Description : Pad control register -#define PADS_BANK0_GPIO18_OFFSET 0x0000004c -#define PADS_BANK0_GPIO18_BITS 0x000000ff -#define PADS_BANK0_GPIO18_RESET 0x00000056 +#define PADS_BANK0_GPIO18_OFFSET _u(0x0000004c) +#define PADS_BANK0_GPIO18_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO18_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO18_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO18_OD_RESET 0x0 -#define PADS_BANK0_GPIO18_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO18_OD_MSB 7 -#define PADS_BANK0_GPIO18_OD_LSB 7 +#define PADS_BANK0_GPIO18_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO18_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO18_OD_MSB _u(7) +#define PADS_BANK0_GPIO18_OD_LSB _u(7) #define PADS_BANK0_GPIO18_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO18_IE // Description : Input enable -#define PADS_BANK0_GPIO18_IE_RESET 0x1 -#define PADS_BANK0_GPIO18_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO18_IE_MSB 6 -#define PADS_BANK0_GPIO18_IE_LSB 6 +#define PADS_BANK0_GPIO18_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO18_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO18_IE_MSB _u(6) +#define PADS_BANK0_GPIO18_IE_LSB _u(6) #define PADS_BANK0_GPIO18_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO18_DRIVE @@ -1332,69 +1332,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO18_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO18_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO18_DRIVE_MSB 5 -#define PADS_BANK0_GPIO18_DRIVE_LSB 4 +#define PADS_BANK0_GPIO18_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO18_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO18_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO18_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO18_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO18_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO18_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO18_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO18_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO18_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO18_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO18_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO18_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO18_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO18_PUE_RESET 0x0 -#define PADS_BANK0_GPIO18_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO18_PUE_MSB 3 -#define PADS_BANK0_GPIO18_PUE_LSB 3 +#define PADS_BANK0_GPIO18_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO18_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO18_PUE_MSB _u(3) +#define PADS_BANK0_GPIO18_PUE_LSB _u(3) #define PADS_BANK0_GPIO18_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO18_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO18_PDE_RESET 0x1 -#define PADS_BANK0_GPIO18_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO18_PDE_MSB 2 -#define PADS_BANK0_GPIO18_PDE_LSB 2 +#define PADS_BANK0_GPIO18_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO18_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO18_PDE_MSB _u(2) +#define PADS_BANK0_GPIO18_PDE_LSB _u(2) #define PADS_BANK0_GPIO18_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO18_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO18_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO18_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO18_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO18_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO18_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO18_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO18_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO18_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO18_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO18_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO18_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO18_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO18_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO18_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO18_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO18_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO18_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO18_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO18_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO19 // Description : Pad control register -#define PADS_BANK0_GPIO19_OFFSET 0x00000050 -#define PADS_BANK0_GPIO19_BITS 0x000000ff -#define PADS_BANK0_GPIO19_RESET 0x00000056 +#define PADS_BANK0_GPIO19_OFFSET _u(0x00000050) +#define PADS_BANK0_GPIO19_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO19_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO19_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO19_OD_RESET 0x0 -#define PADS_BANK0_GPIO19_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO19_OD_MSB 7 -#define PADS_BANK0_GPIO19_OD_LSB 7 +#define PADS_BANK0_GPIO19_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO19_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO19_OD_MSB _u(7) +#define PADS_BANK0_GPIO19_OD_LSB _u(7) #define PADS_BANK0_GPIO19_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO19_IE // Description : Input enable -#define PADS_BANK0_GPIO19_IE_RESET 0x1 -#define PADS_BANK0_GPIO19_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO19_IE_MSB 6 -#define PADS_BANK0_GPIO19_IE_LSB 6 +#define PADS_BANK0_GPIO19_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO19_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO19_IE_MSB _u(6) +#define PADS_BANK0_GPIO19_IE_LSB _u(6) #define PADS_BANK0_GPIO19_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO19_DRIVE @@ -1403,69 +1403,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO19_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO19_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO19_DRIVE_MSB 5 -#define PADS_BANK0_GPIO19_DRIVE_LSB 4 +#define PADS_BANK0_GPIO19_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO19_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO19_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO19_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO19_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO19_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO19_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO19_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO19_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO19_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO19_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO19_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO19_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO19_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO19_PUE_RESET 0x0 -#define PADS_BANK0_GPIO19_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO19_PUE_MSB 3 -#define PADS_BANK0_GPIO19_PUE_LSB 3 +#define PADS_BANK0_GPIO19_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO19_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO19_PUE_MSB _u(3) +#define PADS_BANK0_GPIO19_PUE_LSB _u(3) #define PADS_BANK0_GPIO19_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO19_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO19_PDE_RESET 0x1 -#define PADS_BANK0_GPIO19_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO19_PDE_MSB 2 -#define PADS_BANK0_GPIO19_PDE_LSB 2 +#define PADS_BANK0_GPIO19_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO19_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO19_PDE_MSB _u(2) +#define PADS_BANK0_GPIO19_PDE_LSB _u(2) #define PADS_BANK0_GPIO19_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO19_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO19_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO19_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO19_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO19_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO19_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO19_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO19_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO19_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO19_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO19_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO19_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO19_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO19_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO19_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO19_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO19_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO19_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO19_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO19_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO20 // Description : Pad control register -#define PADS_BANK0_GPIO20_OFFSET 0x00000054 -#define PADS_BANK0_GPIO20_BITS 0x000000ff -#define PADS_BANK0_GPIO20_RESET 0x00000056 +#define PADS_BANK0_GPIO20_OFFSET _u(0x00000054) +#define PADS_BANK0_GPIO20_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO20_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO20_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO20_OD_RESET 0x0 -#define PADS_BANK0_GPIO20_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO20_OD_MSB 7 -#define PADS_BANK0_GPIO20_OD_LSB 7 +#define PADS_BANK0_GPIO20_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO20_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO20_OD_MSB _u(7) +#define PADS_BANK0_GPIO20_OD_LSB _u(7) #define PADS_BANK0_GPIO20_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO20_IE // Description : Input enable -#define PADS_BANK0_GPIO20_IE_RESET 0x1 -#define PADS_BANK0_GPIO20_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO20_IE_MSB 6 -#define PADS_BANK0_GPIO20_IE_LSB 6 +#define PADS_BANK0_GPIO20_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO20_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO20_IE_MSB _u(6) +#define PADS_BANK0_GPIO20_IE_LSB _u(6) #define PADS_BANK0_GPIO20_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO20_DRIVE @@ -1474,69 +1474,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO20_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO20_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO20_DRIVE_MSB 5 -#define PADS_BANK0_GPIO20_DRIVE_LSB 4 +#define PADS_BANK0_GPIO20_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO20_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO20_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO20_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO20_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO20_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO20_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO20_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO20_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO20_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO20_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO20_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO20_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO20_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO20_PUE_RESET 0x0 -#define PADS_BANK0_GPIO20_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO20_PUE_MSB 3 -#define PADS_BANK0_GPIO20_PUE_LSB 3 +#define PADS_BANK0_GPIO20_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO20_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO20_PUE_MSB _u(3) +#define PADS_BANK0_GPIO20_PUE_LSB _u(3) #define PADS_BANK0_GPIO20_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO20_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO20_PDE_RESET 0x1 -#define PADS_BANK0_GPIO20_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO20_PDE_MSB 2 -#define PADS_BANK0_GPIO20_PDE_LSB 2 +#define PADS_BANK0_GPIO20_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO20_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO20_PDE_MSB _u(2) +#define PADS_BANK0_GPIO20_PDE_LSB _u(2) #define PADS_BANK0_GPIO20_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO20_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO20_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO20_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO20_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO20_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO20_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO20_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO20_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO20_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO20_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO20_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO20_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO20_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO20_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO20_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO20_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO20_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO20_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO20_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO20_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO21 // Description : Pad control register -#define PADS_BANK0_GPIO21_OFFSET 0x00000058 -#define PADS_BANK0_GPIO21_BITS 0x000000ff -#define PADS_BANK0_GPIO21_RESET 0x00000056 +#define PADS_BANK0_GPIO21_OFFSET _u(0x00000058) +#define PADS_BANK0_GPIO21_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO21_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO21_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO21_OD_RESET 0x0 -#define PADS_BANK0_GPIO21_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO21_OD_MSB 7 -#define PADS_BANK0_GPIO21_OD_LSB 7 +#define PADS_BANK0_GPIO21_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO21_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO21_OD_MSB _u(7) +#define PADS_BANK0_GPIO21_OD_LSB _u(7) #define PADS_BANK0_GPIO21_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO21_IE // Description : Input enable -#define PADS_BANK0_GPIO21_IE_RESET 0x1 -#define PADS_BANK0_GPIO21_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO21_IE_MSB 6 -#define PADS_BANK0_GPIO21_IE_LSB 6 +#define PADS_BANK0_GPIO21_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO21_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO21_IE_MSB _u(6) +#define PADS_BANK0_GPIO21_IE_LSB _u(6) #define PADS_BANK0_GPIO21_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO21_DRIVE @@ -1545,69 +1545,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO21_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO21_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO21_DRIVE_MSB 5 -#define PADS_BANK0_GPIO21_DRIVE_LSB 4 +#define PADS_BANK0_GPIO21_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO21_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO21_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO21_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO21_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO21_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO21_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO21_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO21_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO21_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO21_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO21_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO21_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO21_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO21_PUE_RESET 0x0 -#define PADS_BANK0_GPIO21_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO21_PUE_MSB 3 -#define PADS_BANK0_GPIO21_PUE_LSB 3 +#define PADS_BANK0_GPIO21_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO21_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO21_PUE_MSB _u(3) +#define PADS_BANK0_GPIO21_PUE_LSB _u(3) #define PADS_BANK0_GPIO21_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO21_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO21_PDE_RESET 0x1 -#define PADS_BANK0_GPIO21_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO21_PDE_MSB 2 -#define PADS_BANK0_GPIO21_PDE_LSB 2 +#define PADS_BANK0_GPIO21_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO21_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO21_PDE_MSB _u(2) +#define PADS_BANK0_GPIO21_PDE_LSB _u(2) #define PADS_BANK0_GPIO21_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO21_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO21_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO21_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO21_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO21_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO21_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO21_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO21_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO21_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO21_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO21_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO21_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO21_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO21_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO21_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO21_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO21_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO21_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO21_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO21_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO22 // Description : Pad control register -#define PADS_BANK0_GPIO22_OFFSET 0x0000005c -#define PADS_BANK0_GPIO22_BITS 0x000000ff -#define PADS_BANK0_GPIO22_RESET 0x00000056 +#define PADS_BANK0_GPIO22_OFFSET _u(0x0000005c) +#define PADS_BANK0_GPIO22_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO22_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO22_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO22_OD_RESET 0x0 -#define PADS_BANK0_GPIO22_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO22_OD_MSB 7 -#define PADS_BANK0_GPIO22_OD_LSB 7 +#define PADS_BANK0_GPIO22_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO22_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO22_OD_MSB _u(7) +#define PADS_BANK0_GPIO22_OD_LSB _u(7) #define PADS_BANK0_GPIO22_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO22_IE // Description : Input enable -#define PADS_BANK0_GPIO22_IE_RESET 0x1 -#define PADS_BANK0_GPIO22_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO22_IE_MSB 6 -#define PADS_BANK0_GPIO22_IE_LSB 6 +#define PADS_BANK0_GPIO22_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO22_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO22_IE_MSB _u(6) +#define PADS_BANK0_GPIO22_IE_LSB _u(6) #define PADS_BANK0_GPIO22_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO22_DRIVE @@ -1616,69 +1616,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO22_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO22_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO22_DRIVE_MSB 5 -#define PADS_BANK0_GPIO22_DRIVE_LSB 4 +#define PADS_BANK0_GPIO22_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO22_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO22_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO22_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO22_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO22_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO22_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO22_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO22_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO22_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO22_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO22_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO22_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO22_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO22_PUE_RESET 0x0 -#define PADS_BANK0_GPIO22_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO22_PUE_MSB 3 -#define PADS_BANK0_GPIO22_PUE_LSB 3 +#define PADS_BANK0_GPIO22_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO22_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO22_PUE_MSB _u(3) +#define PADS_BANK0_GPIO22_PUE_LSB _u(3) #define PADS_BANK0_GPIO22_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO22_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO22_PDE_RESET 0x1 -#define PADS_BANK0_GPIO22_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO22_PDE_MSB 2 -#define PADS_BANK0_GPIO22_PDE_LSB 2 +#define PADS_BANK0_GPIO22_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO22_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO22_PDE_MSB _u(2) +#define PADS_BANK0_GPIO22_PDE_LSB _u(2) #define PADS_BANK0_GPIO22_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO22_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO22_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO22_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO22_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO22_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO22_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO22_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO22_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO22_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO22_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO22_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO22_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO22_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO22_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO22_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO22_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO22_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO22_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO22_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO22_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO23 // Description : Pad control register -#define PADS_BANK0_GPIO23_OFFSET 0x00000060 -#define PADS_BANK0_GPIO23_BITS 0x000000ff -#define PADS_BANK0_GPIO23_RESET 0x00000056 +#define PADS_BANK0_GPIO23_OFFSET _u(0x00000060) +#define PADS_BANK0_GPIO23_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO23_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO23_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO23_OD_RESET 0x0 -#define PADS_BANK0_GPIO23_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO23_OD_MSB 7 -#define PADS_BANK0_GPIO23_OD_LSB 7 +#define PADS_BANK0_GPIO23_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO23_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO23_OD_MSB _u(7) +#define PADS_BANK0_GPIO23_OD_LSB _u(7) #define PADS_BANK0_GPIO23_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO23_IE // Description : Input enable -#define PADS_BANK0_GPIO23_IE_RESET 0x1 -#define PADS_BANK0_GPIO23_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO23_IE_MSB 6 -#define PADS_BANK0_GPIO23_IE_LSB 6 +#define PADS_BANK0_GPIO23_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO23_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO23_IE_MSB _u(6) +#define PADS_BANK0_GPIO23_IE_LSB _u(6) #define PADS_BANK0_GPIO23_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO23_DRIVE @@ -1687,69 +1687,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO23_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO23_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO23_DRIVE_MSB 5 -#define PADS_BANK0_GPIO23_DRIVE_LSB 4 +#define PADS_BANK0_GPIO23_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO23_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO23_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO23_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO23_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO23_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO23_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO23_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO23_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO23_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO23_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO23_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO23_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO23_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO23_PUE_RESET 0x0 -#define PADS_BANK0_GPIO23_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO23_PUE_MSB 3 -#define PADS_BANK0_GPIO23_PUE_LSB 3 +#define PADS_BANK0_GPIO23_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO23_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO23_PUE_MSB _u(3) +#define PADS_BANK0_GPIO23_PUE_LSB _u(3) #define PADS_BANK0_GPIO23_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO23_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO23_PDE_RESET 0x1 -#define PADS_BANK0_GPIO23_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO23_PDE_MSB 2 -#define PADS_BANK0_GPIO23_PDE_LSB 2 +#define PADS_BANK0_GPIO23_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO23_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO23_PDE_MSB _u(2) +#define PADS_BANK0_GPIO23_PDE_LSB _u(2) #define PADS_BANK0_GPIO23_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO23_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO23_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO23_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO23_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO23_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO23_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO23_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO23_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO23_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO23_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO23_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO23_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO23_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO23_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO23_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO23_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO23_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO23_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO23_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO23_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO24 // Description : Pad control register -#define PADS_BANK0_GPIO24_OFFSET 0x00000064 -#define PADS_BANK0_GPIO24_BITS 0x000000ff -#define PADS_BANK0_GPIO24_RESET 0x00000056 +#define PADS_BANK0_GPIO24_OFFSET _u(0x00000064) +#define PADS_BANK0_GPIO24_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO24_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO24_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO24_OD_RESET 0x0 -#define PADS_BANK0_GPIO24_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO24_OD_MSB 7 -#define PADS_BANK0_GPIO24_OD_LSB 7 +#define PADS_BANK0_GPIO24_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO24_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO24_OD_MSB _u(7) +#define PADS_BANK0_GPIO24_OD_LSB _u(7) #define PADS_BANK0_GPIO24_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO24_IE // Description : Input enable -#define PADS_BANK0_GPIO24_IE_RESET 0x1 -#define PADS_BANK0_GPIO24_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO24_IE_MSB 6 -#define PADS_BANK0_GPIO24_IE_LSB 6 +#define PADS_BANK0_GPIO24_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO24_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO24_IE_MSB _u(6) +#define PADS_BANK0_GPIO24_IE_LSB _u(6) #define PADS_BANK0_GPIO24_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO24_DRIVE @@ -1758,69 +1758,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO24_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO24_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO24_DRIVE_MSB 5 -#define PADS_BANK0_GPIO24_DRIVE_LSB 4 +#define PADS_BANK0_GPIO24_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO24_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO24_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO24_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO24_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO24_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO24_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO24_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO24_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO24_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO24_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO24_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO24_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO24_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO24_PUE_RESET 0x0 -#define PADS_BANK0_GPIO24_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO24_PUE_MSB 3 -#define PADS_BANK0_GPIO24_PUE_LSB 3 +#define PADS_BANK0_GPIO24_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO24_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO24_PUE_MSB _u(3) +#define PADS_BANK0_GPIO24_PUE_LSB _u(3) #define PADS_BANK0_GPIO24_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO24_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO24_PDE_RESET 0x1 -#define PADS_BANK0_GPIO24_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO24_PDE_MSB 2 -#define PADS_BANK0_GPIO24_PDE_LSB 2 +#define PADS_BANK0_GPIO24_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO24_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO24_PDE_MSB _u(2) +#define PADS_BANK0_GPIO24_PDE_LSB _u(2) #define PADS_BANK0_GPIO24_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO24_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO24_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO24_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO24_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO24_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO24_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO24_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO24_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO24_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO24_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO24_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO24_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO24_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO24_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO24_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO24_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO24_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO24_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO24_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO24_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO25 // Description : Pad control register -#define PADS_BANK0_GPIO25_OFFSET 0x00000068 -#define PADS_BANK0_GPIO25_BITS 0x000000ff -#define PADS_BANK0_GPIO25_RESET 0x00000056 +#define PADS_BANK0_GPIO25_OFFSET _u(0x00000068) +#define PADS_BANK0_GPIO25_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO25_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO25_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO25_OD_RESET 0x0 -#define PADS_BANK0_GPIO25_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO25_OD_MSB 7 -#define PADS_BANK0_GPIO25_OD_LSB 7 +#define PADS_BANK0_GPIO25_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO25_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO25_OD_MSB _u(7) +#define PADS_BANK0_GPIO25_OD_LSB _u(7) #define PADS_BANK0_GPIO25_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO25_IE // Description : Input enable -#define PADS_BANK0_GPIO25_IE_RESET 0x1 -#define PADS_BANK0_GPIO25_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO25_IE_MSB 6 -#define PADS_BANK0_GPIO25_IE_LSB 6 +#define PADS_BANK0_GPIO25_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO25_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO25_IE_MSB _u(6) +#define PADS_BANK0_GPIO25_IE_LSB _u(6) #define PADS_BANK0_GPIO25_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO25_DRIVE @@ -1829,69 +1829,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO25_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO25_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO25_DRIVE_MSB 5 -#define PADS_BANK0_GPIO25_DRIVE_LSB 4 +#define PADS_BANK0_GPIO25_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO25_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO25_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO25_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO25_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO25_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO25_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO25_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO25_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO25_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO25_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO25_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO25_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO25_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO25_PUE_RESET 0x0 -#define PADS_BANK0_GPIO25_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO25_PUE_MSB 3 -#define PADS_BANK0_GPIO25_PUE_LSB 3 +#define PADS_BANK0_GPIO25_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO25_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO25_PUE_MSB _u(3) +#define PADS_BANK0_GPIO25_PUE_LSB _u(3) #define PADS_BANK0_GPIO25_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO25_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO25_PDE_RESET 0x1 -#define PADS_BANK0_GPIO25_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO25_PDE_MSB 2 -#define PADS_BANK0_GPIO25_PDE_LSB 2 +#define PADS_BANK0_GPIO25_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO25_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO25_PDE_MSB _u(2) +#define PADS_BANK0_GPIO25_PDE_LSB _u(2) #define PADS_BANK0_GPIO25_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO25_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO25_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO25_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO25_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO25_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO25_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO25_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO25_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO25_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO25_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO25_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO25_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO25_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO25_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO25_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO25_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO25_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO25_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO25_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO25_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO26 // Description : Pad control register -#define PADS_BANK0_GPIO26_OFFSET 0x0000006c -#define PADS_BANK0_GPIO26_BITS 0x000000ff -#define PADS_BANK0_GPIO26_RESET 0x00000056 +#define PADS_BANK0_GPIO26_OFFSET _u(0x0000006c) +#define PADS_BANK0_GPIO26_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO26_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO26_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO26_OD_RESET 0x0 -#define PADS_BANK0_GPIO26_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO26_OD_MSB 7 -#define PADS_BANK0_GPIO26_OD_LSB 7 +#define PADS_BANK0_GPIO26_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO26_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO26_OD_MSB _u(7) +#define PADS_BANK0_GPIO26_OD_LSB _u(7) #define PADS_BANK0_GPIO26_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO26_IE // Description : Input enable -#define PADS_BANK0_GPIO26_IE_RESET 0x1 -#define PADS_BANK0_GPIO26_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO26_IE_MSB 6 -#define PADS_BANK0_GPIO26_IE_LSB 6 +#define PADS_BANK0_GPIO26_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO26_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO26_IE_MSB _u(6) +#define PADS_BANK0_GPIO26_IE_LSB _u(6) #define PADS_BANK0_GPIO26_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO26_DRIVE @@ -1900,69 +1900,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO26_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO26_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO26_DRIVE_MSB 5 -#define PADS_BANK0_GPIO26_DRIVE_LSB 4 +#define PADS_BANK0_GPIO26_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO26_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO26_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO26_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO26_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO26_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO26_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO26_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO26_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO26_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO26_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO26_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO26_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO26_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO26_PUE_RESET 0x0 -#define PADS_BANK0_GPIO26_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO26_PUE_MSB 3 -#define PADS_BANK0_GPIO26_PUE_LSB 3 +#define PADS_BANK0_GPIO26_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO26_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO26_PUE_MSB _u(3) +#define PADS_BANK0_GPIO26_PUE_LSB _u(3) #define PADS_BANK0_GPIO26_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO26_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO26_PDE_RESET 0x1 -#define PADS_BANK0_GPIO26_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO26_PDE_MSB 2 -#define PADS_BANK0_GPIO26_PDE_LSB 2 +#define PADS_BANK0_GPIO26_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO26_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO26_PDE_MSB _u(2) +#define PADS_BANK0_GPIO26_PDE_LSB _u(2) #define PADS_BANK0_GPIO26_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO26_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO26_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO26_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO26_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO26_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO26_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO26_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO26_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO26_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO26_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO26_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO26_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO26_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO26_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO26_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO26_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO26_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO26_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO26_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO26_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO27 // Description : Pad control register -#define PADS_BANK0_GPIO27_OFFSET 0x00000070 -#define PADS_BANK0_GPIO27_BITS 0x000000ff -#define PADS_BANK0_GPIO27_RESET 0x00000056 +#define PADS_BANK0_GPIO27_OFFSET _u(0x00000070) +#define PADS_BANK0_GPIO27_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO27_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO27_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO27_OD_RESET 0x0 -#define PADS_BANK0_GPIO27_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO27_OD_MSB 7 -#define PADS_BANK0_GPIO27_OD_LSB 7 +#define PADS_BANK0_GPIO27_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO27_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO27_OD_MSB _u(7) +#define PADS_BANK0_GPIO27_OD_LSB _u(7) #define PADS_BANK0_GPIO27_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO27_IE // Description : Input enable -#define PADS_BANK0_GPIO27_IE_RESET 0x1 -#define PADS_BANK0_GPIO27_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO27_IE_MSB 6 -#define PADS_BANK0_GPIO27_IE_LSB 6 +#define PADS_BANK0_GPIO27_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO27_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO27_IE_MSB _u(6) +#define PADS_BANK0_GPIO27_IE_LSB _u(6) #define PADS_BANK0_GPIO27_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO27_DRIVE @@ -1971,69 +1971,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO27_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO27_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO27_DRIVE_MSB 5 -#define PADS_BANK0_GPIO27_DRIVE_LSB 4 +#define PADS_BANK0_GPIO27_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO27_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO27_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO27_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO27_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO27_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO27_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO27_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO27_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO27_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO27_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO27_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO27_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO27_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO27_PUE_RESET 0x0 -#define PADS_BANK0_GPIO27_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO27_PUE_MSB 3 -#define PADS_BANK0_GPIO27_PUE_LSB 3 +#define PADS_BANK0_GPIO27_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO27_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO27_PUE_MSB _u(3) +#define PADS_BANK0_GPIO27_PUE_LSB _u(3) #define PADS_BANK0_GPIO27_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO27_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO27_PDE_RESET 0x1 -#define PADS_BANK0_GPIO27_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO27_PDE_MSB 2 -#define PADS_BANK0_GPIO27_PDE_LSB 2 +#define PADS_BANK0_GPIO27_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO27_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO27_PDE_MSB _u(2) +#define PADS_BANK0_GPIO27_PDE_LSB _u(2) #define PADS_BANK0_GPIO27_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO27_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO27_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO27_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO27_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO27_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO27_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO27_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO27_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO27_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO27_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO27_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO27_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO27_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO27_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO27_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO27_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO27_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO27_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO27_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO27_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO28 // Description : Pad control register -#define PADS_BANK0_GPIO28_OFFSET 0x00000074 -#define PADS_BANK0_GPIO28_BITS 0x000000ff -#define PADS_BANK0_GPIO28_RESET 0x00000056 +#define PADS_BANK0_GPIO28_OFFSET _u(0x00000074) +#define PADS_BANK0_GPIO28_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO28_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO28_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO28_OD_RESET 0x0 -#define PADS_BANK0_GPIO28_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO28_OD_MSB 7 -#define PADS_BANK0_GPIO28_OD_LSB 7 +#define PADS_BANK0_GPIO28_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO28_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO28_OD_MSB _u(7) +#define PADS_BANK0_GPIO28_OD_LSB _u(7) #define PADS_BANK0_GPIO28_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO28_IE // Description : Input enable -#define PADS_BANK0_GPIO28_IE_RESET 0x1 -#define PADS_BANK0_GPIO28_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO28_IE_MSB 6 -#define PADS_BANK0_GPIO28_IE_LSB 6 +#define PADS_BANK0_GPIO28_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO28_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO28_IE_MSB _u(6) +#define PADS_BANK0_GPIO28_IE_LSB _u(6) #define PADS_BANK0_GPIO28_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO28_DRIVE @@ -2042,69 +2042,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO28_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO28_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO28_DRIVE_MSB 5 -#define PADS_BANK0_GPIO28_DRIVE_LSB 4 +#define PADS_BANK0_GPIO28_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO28_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO28_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO28_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO28_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO28_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO28_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO28_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO28_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO28_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO28_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO28_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO28_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO28_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO28_PUE_RESET 0x0 -#define PADS_BANK0_GPIO28_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO28_PUE_MSB 3 -#define PADS_BANK0_GPIO28_PUE_LSB 3 +#define PADS_BANK0_GPIO28_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO28_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO28_PUE_MSB _u(3) +#define PADS_BANK0_GPIO28_PUE_LSB _u(3) #define PADS_BANK0_GPIO28_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO28_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO28_PDE_RESET 0x1 -#define PADS_BANK0_GPIO28_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO28_PDE_MSB 2 -#define PADS_BANK0_GPIO28_PDE_LSB 2 +#define PADS_BANK0_GPIO28_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO28_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO28_PDE_MSB _u(2) +#define PADS_BANK0_GPIO28_PDE_LSB _u(2) #define PADS_BANK0_GPIO28_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO28_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO28_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO28_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO28_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO28_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO28_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO28_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO28_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO28_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO28_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO28_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO28_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO28_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO28_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO28_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO28_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO28_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO28_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO28_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO28_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_GPIO29 // Description : Pad control register -#define PADS_BANK0_GPIO29_OFFSET 0x00000078 -#define PADS_BANK0_GPIO29_BITS 0x000000ff -#define PADS_BANK0_GPIO29_RESET 0x00000056 +#define PADS_BANK0_GPIO29_OFFSET _u(0x00000078) +#define PADS_BANK0_GPIO29_BITS _u(0x000000ff) +#define PADS_BANK0_GPIO29_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO29_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_GPIO29_OD_RESET 0x0 -#define PADS_BANK0_GPIO29_OD_BITS 0x00000080 -#define PADS_BANK0_GPIO29_OD_MSB 7 -#define PADS_BANK0_GPIO29_OD_LSB 7 +#define PADS_BANK0_GPIO29_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO29_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO29_OD_MSB _u(7) +#define PADS_BANK0_GPIO29_OD_LSB _u(7) #define PADS_BANK0_GPIO29_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO29_IE // Description : Input enable -#define PADS_BANK0_GPIO29_IE_RESET 0x1 -#define PADS_BANK0_GPIO29_IE_BITS 0x00000040 -#define PADS_BANK0_GPIO29_IE_MSB 6 -#define PADS_BANK0_GPIO29_IE_LSB 6 +#define PADS_BANK0_GPIO29_IE_RESET _u(0x1) +#define PADS_BANK0_GPIO29_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO29_IE_MSB _u(6) +#define PADS_BANK0_GPIO29_IE_LSB _u(6) #define PADS_BANK0_GPIO29_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO29_DRIVE @@ -2113,69 +2113,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO29_DRIVE_RESET 0x1 -#define PADS_BANK0_GPIO29_DRIVE_BITS 0x00000030 -#define PADS_BANK0_GPIO29_DRIVE_MSB 5 -#define PADS_BANK0_GPIO29_DRIVE_LSB 4 +#define PADS_BANK0_GPIO29_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO29_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO29_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO29_DRIVE_LSB _u(4) #define PADS_BANK0_GPIO29_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO29_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_GPIO29_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_GPIO29_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_GPIO29_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_GPIO29_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO29_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO29_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO29_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO29_PUE // Description : Pull up enable -#define PADS_BANK0_GPIO29_PUE_RESET 0x0 -#define PADS_BANK0_GPIO29_PUE_BITS 0x00000008 -#define PADS_BANK0_GPIO29_PUE_MSB 3 -#define PADS_BANK0_GPIO29_PUE_LSB 3 +#define PADS_BANK0_GPIO29_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO29_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO29_PUE_MSB _u(3) +#define PADS_BANK0_GPIO29_PUE_LSB _u(3) #define PADS_BANK0_GPIO29_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO29_PDE // Description : Pull down enable -#define PADS_BANK0_GPIO29_PDE_RESET 0x1 -#define PADS_BANK0_GPIO29_PDE_BITS 0x00000004 -#define PADS_BANK0_GPIO29_PDE_MSB 2 -#define PADS_BANK0_GPIO29_PDE_LSB 2 +#define PADS_BANK0_GPIO29_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO29_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO29_PDE_MSB _u(2) +#define PADS_BANK0_GPIO29_PDE_LSB _u(2) #define PADS_BANK0_GPIO29_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO29_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_GPIO29_SCHMITT_RESET 0x1 -#define PADS_BANK0_GPIO29_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_GPIO29_SCHMITT_MSB 1 -#define PADS_BANK0_GPIO29_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO29_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO29_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO29_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO29_SCHMITT_LSB _u(1) #define PADS_BANK0_GPIO29_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO29_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_GPIO29_SLEWFAST_RESET 0x0 -#define PADS_BANK0_GPIO29_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_GPIO29_SLEWFAST_MSB 0 -#define PADS_BANK0_GPIO29_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO29_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO29_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO29_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO29_SLEWFAST_LSB _u(0) #define PADS_BANK0_GPIO29_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_SWCLK // Description : Pad control register -#define PADS_BANK0_SWCLK_OFFSET 0x0000007c -#define PADS_BANK0_SWCLK_BITS 0x000000ff -#define PADS_BANK0_SWCLK_RESET 0x000000da +#define PADS_BANK0_SWCLK_OFFSET _u(0x0000007c) +#define PADS_BANK0_SWCLK_BITS _u(0x000000ff) +#define PADS_BANK0_SWCLK_RESET _u(0x000000da) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWCLK_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_SWCLK_OD_RESET 0x1 -#define PADS_BANK0_SWCLK_OD_BITS 0x00000080 -#define PADS_BANK0_SWCLK_OD_MSB 7 -#define PADS_BANK0_SWCLK_OD_LSB 7 +#define PADS_BANK0_SWCLK_OD_RESET _u(0x1) +#define PADS_BANK0_SWCLK_OD_BITS _u(0x00000080) +#define PADS_BANK0_SWCLK_OD_MSB _u(7) +#define PADS_BANK0_SWCLK_OD_LSB _u(7) #define PADS_BANK0_SWCLK_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWCLK_IE // Description : Input enable -#define PADS_BANK0_SWCLK_IE_RESET 0x1 -#define PADS_BANK0_SWCLK_IE_BITS 0x00000040 -#define PADS_BANK0_SWCLK_IE_MSB 6 -#define PADS_BANK0_SWCLK_IE_LSB 6 +#define PADS_BANK0_SWCLK_IE_RESET _u(0x1) +#define PADS_BANK0_SWCLK_IE_BITS _u(0x00000040) +#define PADS_BANK0_SWCLK_IE_MSB _u(6) +#define PADS_BANK0_SWCLK_IE_LSB _u(6) #define PADS_BANK0_SWCLK_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWCLK_DRIVE @@ -2184,69 +2184,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_SWCLK_DRIVE_RESET 0x1 -#define PADS_BANK0_SWCLK_DRIVE_BITS 0x00000030 -#define PADS_BANK0_SWCLK_DRIVE_MSB 5 -#define PADS_BANK0_SWCLK_DRIVE_LSB 4 +#define PADS_BANK0_SWCLK_DRIVE_RESET _u(0x1) +#define PADS_BANK0_SWCLK_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_SWCLK_DRIVE_MSB _u(5) +#define PADS_BANK0_SWCLK_DRIVE_LSB _u(4) #define PADS_BANK0_SWCLK_DRIVE_ACCESS "RW" -#define PADS_BANK0_SWCLK_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_SWCLK_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_SWCLK_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_SWCLK_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_SWCLK_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_SWCLK_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_SWCLK_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_SWCLK_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWCLK_PUE // Description : Pull up enable -#define PADS_BANK0_SWCLK_PUE_RESET 0x1 -#define PADS_BANK0_SWCLK_PUE_BITS 0x00000008 -#define PADS_BANK0_SWCLK_PUE_MSB 3 -#define PADS_BANK0_SWCLK_PUE_LSB 3 +#define PADS_BANK0_SWCLK_PUE_RESET _u(0x1) +#define PADS_BANK0_SWCLK_PUE_BITS _u(0x00000008) +#define PADS_BANK0_SWCLK_PUE_MSB _u(3) +#define PADS_BANK0_SWCLK_PUE_LSB _u(3) #define PADS_BANK0_SWCLK_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWCLK_PDE // Description : Pull down enable -#define PADS_BANK0_SWCLK_PDE_RESET 0x0 -#define PADS_BANK0_SWCLK_PDE_BITS 0x00000004 -#define PADS_BANK0_SWCLK_PDE_MSB 2 -#define PADS_BANK0_SWCLK_PDE_LSB 2 +#define PADS_BANK0_SWCLK_PDE_RESET _u(0x0) +#define PADS_BANK0_SWCLK_PDE_BITS _u(0x00000004) +#define PADS_BANK0_SWCLK_PDE_MSB _u(2) +#define PADS_BANK0_SWCLK_PDE_LSB _u(2) #define PADS_BANK0_SWCLK_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWCLK_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_SWCLK_SCHMITT_RESET 0x1 -#define PADS_BANK0_SWCLK_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_SWCLK_SCHMITT_MSB 1 -#define PADS_BANK0_SWCLK_SCHMITT_LSB 1 +#define PADS_BANK0_SWCLK_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_SWCLK_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_SWCLK_SCHMITT_MSB _u(1) +#define PADS_BANK0_SWCLK_SCHMITT_LSB _u(1) #define PADS_BANK0_SWCLK_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWCLK_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_SWCLK_SLEWFAST_RESET 0x0 -#define PADS_BANK0_SWCLK_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_SWCLK_SLEWFAST_MSB 0 -#define PADS_BANK0_SWCLK_SLEWFAST_LSB 0 +#define PADS_BANK0_SWCLK_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_SWCLK_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_SWCLK_SLEWFAST_MSB _u(0) +#define PADS_BANK0_SWCLK_SLEWFAST_LSB _u(0) #define PADS_BANK0_SWCLK_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_BANK0_SWD // Description : Pad control register -#define PADS_BANK0_SWD_OFFSET 0x00000080 -#define PADS_BANK0_SWD_BITS 0x000000ff -#define PADS_BANK0_SWD_RESET 0x0000005a +#define PADS_BANK0_SWD_OFFSET _u(0x00000080) +#define PADS_BANK0_SWD_BITS _u(0x000000ff) +#define PADS_BANK0_SWD_RESET _u(0x0000005a) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWD_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_BANK0_SWD_OD_RESET 0x0 -#define PADS_BANK0_SWD_OD_BITS 0x00000080 -#define PADS_BANK0_SWD_OD_MSB 7 -#define PADS_BANK0_SWD_OD_LSB 7 +#define PADS_BANK0_SWD_OD_RESET _u(0x0) +#define PADS_BANK0_SWD_OD_BITS _u(0x00000080) +#define PADS_BANK0_SWD_OD_MSB _u(7) +#define PADS_BANK0_SWD_OD_LSB _u(7) #define PADS_BANK0_SWD_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWD_IE // Description : Input enable -#define PADS_BANK0_SWD_IE_RESET 0x1 -#define PADS_BANK0_SWD_IE_BITS 0x00000040 -#define PADS_BANK0_SWD_IE_MSB 6 -#define PADS_BANK0_SWD_IE_LSB 6 +#define PADS_BANK0_SWD_IE_RESET _u(0x1) +#define PADS_BANK0_SWD_IE_BITS _u(0x00000040) +#define PADS_BANK0_SWD_IE_MSB _u(6) +#define PADS_BANK0_SWD_IE_LSB _u(6) #define PADS_BANK0_SWD_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWD_DRIVE @@ -2255,46 +2255,46 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_SWD_DRIVE_RESET 0x1 -#define PADS_BANK0_SWD_DRIVE_BITS 0x00000030 -#define PADS_BANK0_SWD_DRIVE_MSB 5 -#define PADS_BANK0_SWD_DRIVE_LSB 4 +#define PADS_BANK0_SWD_DRIVE_RESET _u(0x1) +#define PADS_BANK0_SWD_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_SWD_DRIVE_MSB _u(5) +#define PADS_BANK0_SWD_DRIVE_LSB _u(4) #define PADS_BANK0_SWD_DRIVE_ACCESS "RW" -#define PADS_BANK0_SWD_DRIVE_VALUE_2MA 0x0 -#define PADS_BANK0_SWD_DRIVE_VALUE_4MA 0x1 -#define PADS_BANK0_SWD_DRIVE_VALUE_8MA 0x2 -#define PADS_BANK0_SWD_DRIVE_VALUE_12MA 0x3 +#define PADS_BANK0_SWD_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_SWD_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_SWD_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_SWD_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWD_PUE // Description : Pull up enable -#define PADS_BANK0_SWD_PUE_RESET 0x1 -#define PADS_BANK0_SWD_PUE_BITS 0x00000008 -#define PADS_BANK0_SWD_PUE_MSB 3 -#define PADS_BANK0_SWD_PUE_LSB 3 +#define PADS_BANK0_SWD_PUE_RESET _u(0x1) +#define PADS_BANK0_SWD_PUE_BITS _u(0x00000008) +#define PADS_BANK0_SWD_PUE_MSB _u(3) +#define PADS_BANK0_SWD_PUE_LSB _u(3) #define PADS_BANK0_SWD_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWD_PDE // Description : Pull down enable -#define PADS_BANK0_SWD_PDE_RESET 0x0 -#define PADS_BANK0_SWD_PDE_BITS 0x00000004 -#define PADS_BANK0_SWD_PDE_MSB 2 -#define PADS_BANK0_SWD_PDE_LSB 2 +#define PADS_BANK0_SWD_PDE_RESET _u(0x0) +#define PADS_BANK0_SWD_PDE_BITS _u(0x00000004) +#define PADS_BANK0_SWD_PDE_MSB _u(2) +#define PADS_BANK0_SWD_PDE_LSB _u(2) #define PADS_BANK0_SWD_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWD_SCHMITT // Description : Enable schmitt trigger -#define PADS_BANK0_SWD_SCHMITT_RESET 0x1 -#define PADS_BANK0_SWD_SCHMITT_BITS 0x00000002 -#define PADS_BANK0_SWD_SCHMITT_MSB 1 -#define PADS_BANK0_SWD_SCHMITT_LSB 1 +#define PADS_BANK0_SWD_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_SWD_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_SWD_SCHMITT_MSB _u(1) +#define PADS_BANK0_SWD_SCHMITT_LSB _u(1) #define PADS_BANK0_SWD_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWD_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_BANK0_SWD_SLEWFAST_RESET 0x0 -#define PADS_BANK0_SWD_SLEWFAST_BITS 0x00000001 -#define PADS_BANK0_SWD_SLEWFAST_MSB 0 -#define PADS_BANK0_SWD_SLEWFAST_LSB 0 +#define PADS_BANK0_SWD_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_SWD_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_SWD_SLEWFAST_MSB _u(0) +#define PADS_BANK0_SWD_SLEWFAST_LSB _u(0) #define PADS_BANK0_SWD_SLEWFAST_ACCESS "RW" // ============================================================================= #endif // HARDWARE_REGS_PADS_BANK0_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h index 7aba5e856..b3a09e900 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h @@ -16,36 +16,36 @@ // Description : Voltage select. Per bank control // 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) // 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) -#define PADS_QSPI_VOLTAGE_SELECT_OFFSET 0x00000000 -#define PADS_QSPI_VOLTAGE_SELECT_BITS 0x00000001 -#define PADS_QSPI_VOLTAGE_SELECT_RESET 0x00000000 -#define PADS_QSPI_VOLTAGE_SELECT_MSB 0 -#define PADS_QSPI_VOLTAGE_SELECT_LSB 0 +#define PADS_QSPI_VOLTAGE_SELECT_OFFSET _u(0x00000000) +#define PADS_QSPI_VOLTAGE_SELECT_BITS _u(0x00000001) +#define PADS_QSPI_VOLTAGE_SELECT_RESET _u(0x00000000) +#define PADS_QSPI_VOLTAGE_SELECT_MSB _u(0) +#define PADS_QSPI_VOLTAGE_SELECT_LSB _u(0) #define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW" -#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 0x0 -#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 0x1 +#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _u(0x0) +#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _u(0x1) // ============================================================================= // Register : PADS_QSPI_GPIO_QSPI_SCLK // Description : Pad control register -#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET 0x00000004 -#define PADS_QSPI_GPIO_QSPI_SCLK_BITS 0x000000ff -#define PADS_QSPI_GPIO_QSPI_SCLK_RESET 0x00000056 +#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SCLK_BITS _u(0x000000ff) +#define PADS_QSPI_GPIO_QSPI_SCLK_RESET _u(0x00000056) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SCLK_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS 0x00000080 -#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB 7 -#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB _u(7) #define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SCLK_IE // Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS 0x00000040 -#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB 6 -#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB _u(6) #define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE @@ -54,69 +54,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS 0x00000030 -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB 5 -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB _u(4) #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA 0x0 -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA 0x1 -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA 0x2 -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA 0x3 +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SCLK_PUE // Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS 0x00000008 -#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB 3 -#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB _u(3) #define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SCLK_PDE // Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS 0x00000004 -#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB 2 -#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB _u(2) #define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT // Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS 0x00000002 -#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB 1 -#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB _u(1) #define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS 0x00000001 -#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB 0 -#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB _u(0) #define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_QSPI_GPIO_QSPI_SD0 // Description : Pad control register -#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET 0x00000008 -#define PADS_QSPI_GPIO_QSPI_SD0_BITS 0x000000ff -#define PADS_QSPI_GPIO_QSPI_SD0_RESET 0x00000052 +#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SD0_BITS _u(0x000000ff) +#define PADS_QSPI_GPIO_QSPI_SD0_RESET _u(0x00000052) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD0_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS 0x00000080 -#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB 7 -#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB _u(7) #define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD0_IE // Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS 0x00000040 -#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB 6 -#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB _u(6) #define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD0_DRIVE @@ -125,69 +125,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS 0x00000030 -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB 5 -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB _u(4) #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA 0x0 -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA 0x1 -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA 0x2 -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA 0x3 +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD0_PUE // Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS 0x00000008 -#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB 3 -#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB _u(3) #define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD0_PDE // Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS 0x00000004 -#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB 2 -#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB _u(2) #define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT // Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS 0x00000002 -#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB 1 -#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB _u(1) #define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS 0x00000001 -#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB 0 -#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB _u(0) #define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_QSPI_GPIO_QSPI_SD1 // Description : Pad control register -#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET 0x0000000c -#define PADS_QSPI_GPIO_QSPI_SD1_BITS 0x000000ff -#define PADS_QSPI_GPIO_QSPI_SD1_RESET 0x00000052 +#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET _u(0x0000000c) +#define PADS_QSPI_GPIO_QSPI_SD1_BITS _u(0x000000ff) +#define PADS_QSPI_GPIO_QSPI_SD1_RESET _u(0x00000052) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD1_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS 0x00000080 -#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB 7 -#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB _u(7) #define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD1_IE // Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS 0x00000040 -#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB 6 -#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB _u(6) #define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD1_DRIVE @@ -196,69 +196,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS 0x00000030 -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB 5 -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB _u(4) #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA 0x0 -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA 0x1 -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA 0x2 -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA 0x3 +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD1_PUE // Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS 0x00000008 -#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB 3 -#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB _u(3) #define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD1_PDE // Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS 0x00000004 -#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB 2 -#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB _u(2) #define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT // Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS 0x00000002 -#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB 1 -#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB _u(1) #define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS 0x00000001 -#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB 0 -#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB _u(0) #define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_QSPI_GPIO_QSPI_SD2 // Description : Pad control register -#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET 0x00000010 -#define PADS_QSPI_GPIO_QSPI_SD2_BITS 0x000000ff -#define PADS_QSPI_GPIO_QSPI_SD2_RESET 0x00000052 +#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET _u(0x00000010) +#define PADS_QSPI_GPIO_QSPI_SD2_BITS _u(0x000000ff) +#define PADS_QSPI_GPIO_QSPI_SD2_RESET _u(0x00000052) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD2_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS 0x00000080 -#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB 7 -#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB _u(7) #define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD2_IE // Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS 0x00000040 -#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB 6 -#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB _u(6) #define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD2_DRIVE @@ -267,69 +267,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS 0x00000030 -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB 5 -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB _u(4) #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA 0x0 -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA 0x1 -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA 0x2 -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA 0x3 +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD2_PUE // Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS 0x00000008 -#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB 3 -#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB _u(3) #define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD2_PDE // Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS 0x00000004 -#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB 2 -#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB _u(2) #define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT // Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS 0x00000002 -#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB 1 -#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB _u(1) #define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS 0x00000001 -#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB 0 -#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB _u(0) #define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_QSPI_GPIO_QSPI_SD3 // Description : Pad control register -#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET 0x00000014 -#define PADS_QSPI_GPIO_QSPI_SD3_BITS 0x000000ff -#define PADS_QSPI_GPIO_QSPI_SD3_RESET 0x00000052 +#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET _u(0x00000014) +#define PADS_QSPI_GPIO_QSPI_SD3_BITS _u(0x000000ff) +#define PADS_QSPI_GPIO_QSPI_SD3_RESET _u(0x00000052) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD3_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS 0x00000080 -#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB 7 -#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB _u(7) #define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD3_IE // Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS 0x00000040 -#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB 6 -#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB _u(6) #define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD3_DRIVE @@ -338,69 +338,69 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS 0x00000030 -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB 5 -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB _u(4) #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA 0x0 -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA 0x1 -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA 0x2 -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA 0x3 +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD3_PUE // Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS 0x00000008 -#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB 3 -#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB _u(3) #define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD3_PDE // Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS 0x00000004 -#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB 2 -#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB _u(2) #define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT // Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS 0x00000002 -#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB 1 -#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB _u(1) #define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS 0x00000001 -#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB 0 -#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB _u(0) #define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW" // ============================================================================= // Register : PADS_QSPI_GPIO_QSPI_SS // Description : Pad control register -#define PADS_QSPI_GPIO_QSPI_SS_OFFSET 0x00000018 -#define PADS_QSPI_GPIO_QSPI_SS_BITS 0x000000ff -#define PADS_QSPI_GPIO_QSPI_SS_RESET 0x0000005a +#define PADS_QSPI_GPIO_QSPI_SS_OFFSET _u(0x00000018) +#define PADS_QSPI_GPIO_QSPI_SS_BITS _u(0x000000ff) +#define PADS_QSPI_GPIO_QSPI_SS_RESET _u(0x0000005a) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SS_OD // Description : Output disable. Has priority over output enable from // peripherals -#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS 0x00000080 -#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB 7 -#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB _u(7) #define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SS_IE // Description : Input enable -#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS 0x00000040 -#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB 6 -#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB _u(6) #define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SS_DRIVE @@ -409,46 +409,46 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS 0x00000030 -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB 5 -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB _u(4) #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA 0x0 -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA 0x1 -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA 0x2 -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA 0x3 +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SS_PUE // Description : Pull up enable -#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS 0x00000008 -#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB 3 -#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB _u(3) #define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SS_PDE // Description : Pull down enable -#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS 0x00000004 -#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB 2 -#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB _u(2) #define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SS_SCHMITT // Description : Enable schmitt trigger -#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET 0x1 -#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS 0x00000002 -#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB 1 -#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB _u(1) #define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST // Description : Slew rate control. 1 = Fast, 0 = Slow -#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET 0x0 -#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS 0x00000001 -#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB 0 -#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB _u(0) #define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW" // ============================================================================= #endif // HARDWARE_REGS_PADS_QSPI_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pio.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pio.h index 503aa0940..b231882ac 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pio.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pio.h @@ -14,323 +14,388 @@ // ============================================================================= // Register : PIO_CTRL // Description : PIO control register -#define PIO_CTRL_OFFSET 0x00000000 -#define PIO_CTRL_BITS 0x00000fff -#define PIO_CTRL_RESET 0x00000000 +#define PIO_CTRL_OFFSET _u(0x00000000) +#define PIO_CTRL_BITS _u(0x00000fff) +#define PIO_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_CTRL_CLKDIV_RESTART -// Description : Force clock dividers to restart their count and clear -// fractional -// accumulators. Restart multiple dividers to synchronise them. -#define PIO_CTRL_CLKDIV_RESTART_RESET 0x0 -#define PIO_CTRL_CLKDIV_RESTART_BITS 0x00000f00 -#define PIO_CTRL_CLKDIV_RESTART_MSB 11 -#define PIO_CTRL_CLKDIV_RESTART_LSB 8 +// Description : Restart a state machine's clock divider from an initial phase +// of 0. Clock dividers are free-running, so once started, their +// output (including fractional jitter) is completely determined +// by the integer/fractional divisor configured in SMx_CLKDIV. +// This means that, if multiple clock dividers with the same +// divisor are restarted simultaneously, by writing multiple 1 +// bits to this field, the execution clocks of those state +// machines will run in precise lockstep. +// +// Note that setting/clearing SM_ENABLE does not stop the clock +// divider from running, so once multiple state machines' clocks +// are synchronised, it is safe to disable/reenable a state +// machine, whilst keeping the clock dividers in sync. +// +// Note also that CLKDIV_RESTART can be written to whilst the +// state machine is running, and this is useful to resynchronise +// clock dividers after the divisors (SMx_CLKDIV) have been +// changed on-the-fly. +#define PIO_CTRL_CLKDIV_RESTART_RESET _u(0x0) +#define PIO_CTRL_CLKDIV_RESTART_BITS _u(0x00000f00) +#define PIO_CTRL_CLKDIV_RESTART_MSB _u(11) +#define PIO_CTRL_CLKDIV_RESTART_LSB _u(8) #define PIO_CTRL_CLKDIV_RESTART_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PIO_CTRL_SM_RESTART -// Description : Clear internal SM state which is otherwise difficult to access -// (e.g. shift counters). Self-clearing. -#define PIO_CTRL_SM_RESTART_RESET 0x0 -#define PIO_CTRL_SM_RESTART_BITS 0x000000f0 -#define PIO_CTRL_SM_RESTART_MSB 7 -#define PIO_CTRL_SM_RESTART_LSB 4 +// Description : Write 1 to instantly clear internal SM state which may be +// otherwise difficult to access and will affect future execution. +// +// Specifically, the following are cleared: input and output shift +// counters; the contents of the input shift register; the delay +// counter; the waiting-on-IRQ state; any stalled instruction +// written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left +// asserted due to OUT_STICKY. +#define PIO_CTRL_SM_RESTART_RESET _u(0x0) +#define PIO_CTRL_SM_RESTART_BITS _u(0x000000f0) +#define PIO_CTRL_SM_RESTART_MSB _u(7) +#define PIO_CTRL_SM_RESTART_LSB _u(4) #define PIO_CTRL_SM_RESTART_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PIO_CTRL_SM_ENABLE -// Description : Enable state machine -#define PIO_CTRL_SM_ENABLE_RESET 0x0 -#define PIO_CTRL_SM_ENABLE_BITS 0x0000000f -#define PIO_CTRL_SM_ENABLE_MSB 3 -#define PIO_CTRL_SM_ENABLE_LSB 0 +// Description : Enable/disable each of the four state machines by writing 1/0 +// to each of these four bits. When disabled, a state machine will +// cease executing instructions, except those written directly to +// SMx_INSTR by the system. Multiple bits can be set/cleared at +// once to run/halt multiple state machines simultaneously. +#define PIO_CTRL_SM_ENABLE_RESET _u(0x0) +#define PIO_CTRL_SM_ENABLE_BITS _u(0x0000000f) +#define PIO_CTRL_SM_ENABLE_MSB _u(3) +#define PIO_CTRL_SM_ENABLE_LSB _u(0) #define PIO_CTRL_SM_ENABLE_ACCESS "RW" // ============================================================================= // Register : PIO_FSTAT // Description : FIFO status register -#define PIO_FSTAT_OFFSET 0x00000004 -#define PIO_FSTAT_BITS 0x0f0f0f0f -#define PIO_FSTAT_RESET 0x0f000f00 +#define PIO_FSTAT_OFFSET _u(0x00000004) +#define PIO_FSTAT_BITS _u(0x0f0f0f0f) +#define PIO_FSTAT_RESET _u(0x0f000f00) // ----------------------------------------------------------------------------- // Field : PIO_FSTAT_TXEMPTY // Description : State machine TX FIFO is empty -#define PIO_FSTAT_TXEMPTY_RESET 0xf -#define PIO_FSTAT_TXEMPTY_BITS 0x0f000000 -#define PIO_FSTAT_TXEMPTY_MSB 27 -#define PIO_FSTAT_TXEMPTY_LSB 24 +#define PIO_FSTAT_TXEMPTY_RESET _u(0xf) +#define PIO_FSTAT_TXEMPTY_BITS _u(0x0f000000) +#define PIO_FSTAT_TXEMPTY_MSB _u(27) +#define PIO_FSTAT_TXEMPTY_LSB _u(24) #define PIO_FSTAT_TXEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FSTAT_TXFULL // Description : State machine TX FIFO is full -#define PIO_FSTAT_TXFULL_RESET 0x0 -#define PIO_FSTAT_TXFULL_BITS 0x000f0000 -#define PIO_FSTAT_TXFULL_MSB 19 -#define PIO_FSTAT_TXFULL_LSB 16 +#define PIO_FSTAT_TXFULL_RESET _u(0x0) +#define PIO_FSTAT_TXFULL_BITS _u(0x000f0000) +#define PIO_FSTAT_TXFULL_MSB _u(19) +#define PIO_FSTAT_TXFULL_LSB _u(16) #define PIO_FSTAT_TXFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FSTAT_RXEMPTY // Description : State machine RX FIFO is empty -#define PIO_FSTAT_RXEMPTY_RESET 0xf -#define PIO_FSTAT_RXEMPTY_BITS 0x00000f00 -#define PIO_FSTAT_RXEMPTY_MSB 11 -#define PIO_FSTAT_RXEMPTY_LSB 8 +#define PIO_FSTAT_RXEMPTY_RESET _u(0xf) +#define PIO_FSTAT_RXEMPTY_BITS _u(0x00000f00) +#define PIO_FSTAT_RXEMPTY_MSB _u(11) +#define PIO_FSTAT_RXEMPTY_LSB _u(8) #define PIO_FSTAT_RXEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FSTAT_RXFULL // Description : State machine RX FIFO is full -#define PIO_FSTAT_RXFULL_RESET 0x0 -#define PIO_FSTAT_RXFULL_BITS 0x0000000f -#define PIO_FSTAT_RXFULL_MSB 3 -#define PIO_FSTAT_RXFULL_LSB 0 +#define PIO_FSTAT_RXFULL_RESET _u(0x0) +#define PIO_FSTAT_RXFULL_BITS _u(0x0000000f) +#define PIO_FSTAT_RXFULL_MSB _u(3) +#define PIO_FSTAT_RXFULL_LSB _u(0) #define PIO_FSTAT_RXFULL_ACCESS "RO" // ============================================================================= // Register : PIO_FDEBUG // Description : FIFO debug register -#define PIO_FDEBUG_OFFSET 0x00000008 -#define PIO_FDEBUG_BITS 0x0f0f0f0f -#define PIO_FDEBUG_RESET 0x00000000 +#define PIO_FDEBUG_OFFSET _u(0x00000008) +#define PIO_FDEBUG_BITS _u(0x0f0f0f0f) +#define PIO_FDEBUG_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_FDEBUG_TXSTALL -// Description : State machine has stalled on empty TX FIFO. Write 1 to clear. -#define PIO_FDEBUG_TXSTALL_RESET 0x0 -#define PIO_FDEBUG_TXSTALL_BITS 0x0f000000 -#define PIO_FDEBUG_TXSTALL_MSB 27 -#define PIO_FDEBUG_TXSTALL_LSB 24 +// Description : State machine has stalled on empty TX FIFO during a blocking +// PULL, or an OUT with autopull enabled. Write 1 to clear. +#define PIO_FDEBUG_TXSTALL_RESET _u(0x0) +#define PIO_FDEBUG_TXSTALL_BITS _u(0x0f000000) +#define PIO_FDEBUG_TXSTALL_MSB _u(27) +#define PIO_FDEBUG_TXSTALL_LSB _u(24) #define PIO_FDEBUG_TXSTALL_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PIO_FDEBUG_TXOVER -// Description : TX FIFO overflow has occurred. Write 1 to clear. -#define PIO_FDEBUG_TXOVER_RESET 0x0 -#define PIO_FDEBUG_TXOVER_BITS 0x000f0000 -#define PIO_FDEBUG_TXOVER_MSB 19 -#define PIO_FDEBUG_TXOVER_LSB 16 +// Description : TX FIFO overflow (i.e. write-on-full by the system) has +// occurred. Write 1 to clear. Note that write-on-full does not +// alter the state or contents of the FIFO in any way, but the +// data that the system attempted to write is dropped, so if this +// flag is set, your software has quite likely dropped some data +// on the floor. +#define PIO_FDEBUG_TXOVER_RESET _u(0x0) +#define PIO_FDEBUG_TXOVER_BITS _u(0x000f0000) +#define PIO_FDEBUG_TXOVER_MSB _u(19) +#define PIO_FDEBUG_TXOVER_LSB _u(16) #define PIO_FDEBUG_TXOVER_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PIO_FDEBUG_RXUNDER -// Description : RX FIFO underflow has occurred. Write 1 to clear. -#define PIO_FDEBUG_RXUNDER_RESET 0x0 -#define PIO_FDEBUG_RXUNDER_BITS 0x00000f00 -#define PIO_FDEBUG_RXUNDER_MSB 11 -#define PIO_FDEBUG_RXUNDER_LSB 8 +// Description : RX FIFO underflow (i.e. read-on-empty by the system) has +// occurred. Write 1 to clear. Note that read-on-empty does not +// perturb the state of the FIFO in any way, but the data returned +// by reading from an empty FIFO is undefined, so this flag +// generally only becomes set due to some kind of software error. +#define PIO_FDEBUG_RXUNDER_RESET _u(0x0) +#define PIO_FDEBUG_RXUNDER_BITS _u(0x00000f00) +#define PIO_FDEBUG_RXUNDER_MSB _u(11) +#define PIO_FDEBUG_RXUNDER_LSB _u(8) #define PIO_FDEBUG_RXUNDER_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PIO_FDEBUG_RXSTALL -// Description : State machine has stalled on full RX FIFO. Write 1 to clear. -#define PIO_FDEBUG_RXSTALL_RESET 0x0 -#define PIO_FDEBUG_RXSTALL_BITS 0x0000000f -#define PIO_FDEBUG_RXSTALL_MSB 3 -#define PIO_FDEBUG_RXSTALL_LSB 0 +// Description : State machine has stalled on full RX FIFO during a blocking +// PUSH, or an IN with autopush enabled. This flag is also set +// when a nonblocking PUSH to a full FIFO took place, in which +// case the state machine has dropped data. Write 1 to clear. +#define PIO_FDEBUG_RXSTALL_RESET _u(0x0) +#define PIO_FDEBUG_RXSTALL_BITS _u(0x0000000f) +#define PIO_FDEBUG_RXSTALL_MSB _u(3) +#define PIO_FDEBUG_RXSTALL_LSB _u(0) #define PIO_FDEBUG_RXSTALL_ACCESS "WC" // ============================================================================= // Register : PIO_FLEVEL // Description : FIFO levels -#define PIO_FLEVEL_OFFSET 0x0000000c -#define PIO_FLEVEL_BITS 0xffffffff -#define PIO_FLEVEL_RESET 0x00000000 +#define PIO_FLEVEL_OFFSET _u(0x0000000c) +#define PIO_FLEVEL_BITS _u(0xffffffff) +#define PIO_FLEVEL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_RX3 // Description : None -#define PIO_FLEVEL_RX3_RESET 0x0 -#define PIO_FLEVEL_RX3_BITS 0xf0000000 -#define PIO_FLEVEL_RX3_MSB 31 -#define PIO_FLEVEL_RX3_LSB 28 +#define PIO_FLEVEL_RX3_RESET _u(0x0) +#define PIO_FLEVEL_RX3_BITS _u(0xf0000000) +#define PIO_FLEVEL_RX3_MSB _u(31) +#define PIO_FLEVEL_RX3_LSB _u(28) #define PIO_FLEVEL_RX3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_TX3 // Description : None -#define PIO_FLEVEL_TX3_RESET 0x0 -#define PIO_FLEVEL_TX3_BITS 0x0f000000 -#define PIO_FLEVEL_TX3_MSB 27 -#define PIO_FLEVEL_TX3_LSB 24 +#define PIO_FLEVEL_TX3_RESET _u(0x0) +#define PIO_FLEVEL_TX3_BITS _u(0x0f000000) +#define PIO_FLEVEL_TX3_MSB _u(27) +#define PIO_FLEVEL_TX3_LSB _u(24) #define PIO_FLEVEL_TX3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_RX2 // Description : None -#define PIO_FLEVEL_RX2_RESET 0x0 -#define PIO_FLEVEL_RX2_BITS 0x00f00000 -#define PIO_FLEVEL_RX2_MSB 23 -#define PIO_FLEVEL_RX2_LSB 20 +#define PIO_FLEVEL_RX2_RESET _u(0x0) +#define PIO_FLEVEL_RX2_BITS _u(0x00f00000) +#define PIO_FLEVEL_RX2_MSB _u(23) +#define PIO_FLEVEL_RX2_LSB _u(20) #define PIO_FLEVEL_RX2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_TX2 // Description : None -#define PIO_FLEVEL_TX2_RESET 0x0 -#define PIO_FLEVEL_TX2_BITS 0x000f0000 -#define PIO_FLEVEL_TX2_MSB 19 -#define PIO_FLEVEL_TX2_LSB 16 +#define PIO_FLEVEL_TX2_RESET _u(0x0) +#define PIO_FLEVEL_TX2_BITS _u(0x000f0000) +#define PIO_FLEVEL_TX2_MSB _u(19) +#define PIO_FLEVEL_TX2_LSB _u(16) #define PIO_FLEVEL_TX2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_RX1 // Description : None -#define PIO_FLEVEL_RX1_RESET 0x0 -#define PIO_FLEVEL_RX1_BITS 0x0000f000 -#define PIO_FLEVEL_RX1_MSB 15 -#define PIO_FLEVEL_RX1_LSB 12 +#define PIO_FLEVEL_RX1_RESET _u(0x0) +#define PIO_FLEVEL_RX1_BITS _u(0x0000f000) +#define PIO_FLEVEL_RX1_MSB _u(15) +#define PIO_FLEVEL_RX1_LSB _u(12) #define PIO_FLEVEL_RX1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_TX1 // Description : None -#define PIO_FLEVEL_TX1_RESET 0x0 -#define PIO_FLEVEL_TX1_BITS 0x00000f00 -#define PIO_FLEVEL_TX1_MSB 11 -#define PIO_FLEVEL_TX1_LSB 8 +#define PIO_FLEVEL_TX1_RESET _u(0x0) +#define PIO_FLEVEL_TX1_BITS _u(0x00000f00) +#define PIO_FLEVEL_TX1_MSB _u(11) +#define PIO_FLEVEL_TX1_LSB _u(8) #define PIO_FLEVEL_TX1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_RX0 // Description : None -#define PIO_FLEVEL_RX0_RESET 0x0 -#define PIO_FLEVEL_RX0_BITS 0x000000f0 -#define PIO_FLEVEL_RX0_MSB 7 -#define PIO_FLEVEL_RX0_LSB 4 +#define PIO_FLEVEL_RX0_RESET _u(0x0) +#define PIO_FLEVEL_RX0_BITS _u(0x000000f0) +#define PIO_FLEVEL_RX0_MSB _u(7) +#define PIO_FLEVEL_RX0_LSB _u(4) #define PIO_FLEVEL_RX0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_TX0 // Description : None -#define PIO_FLEVEL_TX0_RESET 0x0 -#define PIO_FLEVEL_TX0_BITS 0x0000000f -#define PIO_FLEVEL_TX0_MSB 3 -#define PIO_FLEVEL_TX0_LSB 0 +#define PIO_FLEVEL_TX0_RESET _u(0x0) +#define PIO_FLEVEL_TX0_BITS _u(0x0000000f) +#define PIO_FLEVEL_TX0_MSB _u(3) +#define PIO_FLEVEL_TX0_LSB _u(0) #define PIO_FLEVEL_TX0_ACCESS "RO" // ============================================================================= // Register : PIO_TXF0 // Description : Direct write access to the TX FIFO for this state machine. Each -// write pushes one word to the FIFO. -#define PIO_TXF0_OFFSET 0x00000010 -#define PIO_TXF0_BITS 0xffffffff -#define PIO_TXF0_RESET 0x00000000 -#define PIO_TXF0_MSB 31 -#define PIO_TXF0_LSB 0 +// write pushes one word to the FIFO. Attempting to write to a +// full FIFO has no effect on the FIFO state or contents, and sets +// the sticky FDEBUG_TXOVER error flag for this FIFO. +#define PIO_TXF0_OFFSET _u(0x00000010) +#define PIO_TXF0_BITS _u(0xffffffff) +#define PIO_TXF0_RESET _u(0x00000000) +#define PIO_TXF0_MSB _u(31) +#define PIO_TXF0_LSB _u(0) #define PIO_TXF0_ACCESS "WF" // ============================================================================= // Register : PIO_TXF1 // Description : Direct write access to the TX FIFO for this state machine. Each -// write pushes one word to the FIFO. -#define PIO_TXF1_OFFSET 0x00000014 -#define PIO_TXF1_BITS 0xffffffff -#define PIO_TXF1_RESET 0x00000000 -#define PIO_TXF1_MSB 31 -#define PIO_TXF1_LSB 0 +// write pushes one word to the FIFO. Attempting to write to a +// full FIFO has no effect on the FIFO state or contents, and sets +// the sticky FDEBUG_TXOVER error flag for this FIFO. +#define PIO_TXF1_OFFSET _u(0x00000014) +#define PIO_TXF1_BITS _u(0xffffffff) +#define PIO_TXF1_RESET _u(0x00000000) +#define PIO_TXF1_MSB _u(31) +#define PIO_TXF1_LSB _u(0) #define PIO_TXF1_ACCESS "WF" // ============================================================================= // Register : PIO_TXF2 // Description : Direct write access to the TX FIFO for this state machine. Each -// write pushes one word to the FIFO. -#define PIO_TXF2_OFFSET 0x00000018 -#define PIO_TXF2_BITS 0xffffffff -#define PIO_TXF2_RESET 0x00000000 -#define PIO_TXF2_MSB 31 -#define PIO_TXF2_LSB 0 +// write pushes one word to the FIFO. Attempting to write to a +// full FIFO has no effect on the FIFO state or contents, and sets +// the sticky FDEBUG_TXOVER error flag for this FIFO. +#define PIO_TXF2_OFFSET _u(0x00000018) +#define PIO_TXF2_BITS _u(0xffffffff) +#define PIO_TXF2_RESET _u(0x00000000) +#define PIO_TXF2_MSB _u(31) +#define PIO_TXF2_LSB _u(0) #define PIO_TXF2_ACCESS "WF" // ============================================================================= // Register : PIO_TXF3 // Description : Direct write access to the TX FIFO for this state machine. Each -// write pushes one word to the FIFO. -#define PIO_TXF3_OFFSET 0x0000001c -#define PIO_TXF3_BITS 0xffffffff -#define PIO_TXF3_RESET 0x00000000 -#define PIO_TXF3_MSB 31 -#define PIO_TXF3_LSB 0 +// write pushes one word to the FIFO. Attempting to write to a +// full FIFO has no effect on the FIFO state or contents, and sets +// the sticky FDEBUG_TXOVER error flag for this FIFO. +#define PIO_TXF3_OFFSET _u(0x0000001c) +#define PIO_TXF3_BITS _u(0xffffffff) +#define PIO_TXF3_RESET _u(0x00000000) +#define PIO_TXF3_MSB _u(31) +#define PIO_TXF3_LSB _u(0) #define PIO_TXF3_ACCESS "WF" // ============================================================================= // Register : PIO_RXF0 // Description : Direct read access to the RX FIFO for this state machine. Each -// read pops one word from the FIFO. -#define PIO_RXF0_OFFSET 0x00000020 -#define PIO_RXF0_BITS 0xffffffff +// read pops one word from the FIFO. Attempting to read from an +// empty FIFO has no effect on the FIFO state, and sets the sticky +// FDEBUG_RXUNDER error flag for this FIFO. The data returned to +// the system on a read from an empty FIFO is undefined. +#define PIO_RXF0_OFFSET _u(0x00000020) +#define PIO_RXF0_BITS _u(0xffffffff) #define PIO_RXF0_RESET "-" -#define PIO_RXF0_MSB 31 -#define PIO_RXF0_LSB 0 +#define PIO_RXF0_MSB _u(31) +#define PIO_RXF0_LSB _u(0) #define PIO_RXF0_ACCESS "RF" // ============================================================================= // Register : PIO_RXF1 // Description : Direct read access to the RX FIFO for this state machine. Each -// read pops one word from the FIFO. -#define PIO_RXF1_OFFSET 0x00000024 -#define PIO_RXF1_BITS 0xffffffff +// read pops one word from the FIFO. Attempting to read from an +// empty FIFO has no effect on the FIFO state, and sets the sticky +// FDEBUG_RXUNDER error flag for this FIFO. The data returned to +// the system on a read from an empty FIFO is undefined. +#define PIO_RXF1_OFFSET _u(0x00000024) +#define PIO_RXF1_BITS _u(0xffffffff) #define PIO_RXF1_RESET "-" -#define PIO_RXF1_MSB 31 -#define PIO_RXF1_LSB 0 +#define PIO_RXF1_MSB _u(31) +#define PIO_RXF1_LSB _u(0) #define PIO_RXF1_ACCESS "RF" // ============================================================================= // Register : PIO_RXF2 // Description : Direct read access to the RX FIFO for this state machine. Each -// read pops one word from the FIFO. -#define PIO_RXF2_OFFSET 0x00000028 -#define PIO_RXF2_BITS 0xffffffff +// read pops one word from the FIFO. Attempting to read from an +// empty FIFO has no effect on the FIFO state, and sets the sticky +// FDEBUG_RXUNDER error flag for this FIFO. The data returned to +// the system on a read from an empty FIFO is undefined. +#define PIO_RXF2_OFFSET _u(0x00000028) +#define PIO_RXF2_BITS _u(0xffffffff) #define PIO_RXF2_RESET "-" -#define PIO_RXF2_MSB 31 -#define PIO_RXF2_LSB 0 +#define PIO_RXF2_MSB _u(31) +#define PIO_RXF2_LSB _u(0) #define PIO_RXF2_ACCESS "RF" // ============================================================================= // Register : PIO_RXF3 // Description : Direct read access to the RX FIFO for this state machine. Each -// read pops one word from the FIFO. -#define PIO_RXF3_OFFSET 0x0000002c -#define PIO_RXF3_BITS 0xffffffff +// read pops one word from the FIFO. Attempting to read from an +// empty FIFO has no effect on the FIFO state, and sets the sticky +// FDEBUG_RXUNDER error flag for this FIFO. The data returned to +// the system on a read from an empty FIFO is undefined. +#define PIO_RXF3_OFFSET _u(0x0000002c) +#define PIO_RXF3_BITS _u(0xffffffff) #define PIO_RXF3_RESET "-" -#define PIO_RXF3_MSB 31 -#define PIO_RXF3_LSB 0 +#define PIO_RXF3_MSB _u(31) +#define PIO_RXF3_LSB _u(0) #define PIO_RXF3_ACCESS "RF" // ============================================================================= // Register : PIO_IRQ -// Description : Interrupt request register. Write 1 to clear -#define PIO_IRQ_OFFSET 0x00000030 -#define PIO_IRQ_BITS 0x000000ff -#define PIO_IRQ_RESET 0x00000000 -#define PIO_IRQ_MSB 7 -#define PIO_IRQ_LSB 0 +// Description : State machine IRQ flags register. Write 1 to clear. There are 8 +// state machine IRQ flags, which can be set, cleared, and waited +// on by the state machines. There's no fixed association between +// flags and state machines -- any state machine can use any flag. +// +// Any of the 8 flags can be used for timing synchronisation +// between state machines, using IRQ and WAIT instructions. The +// lower four of these flags are also routed out to system-level +// interrupt requests, alongside FIFO status interrupts -- see +// e.g. IRQ0_INTE. +#define PIO_IRQ_OFFSET _u(0x00000030) +#define PIO_IRQ_BITS _u(0x000000ff) +#define PIO_IRQ_RESET _u(0x00000000) +#define PIO_IRQ_MSB _u(7) +#define PIO_IRQ_LSB _u(0) #define PIO_IRQ_ACCESS "WC" // ============================================================================= // Register : PIO_IRQ_FORCE // Description : Writing a 1 to each of these bits will forcibly assert the -// corresponding IRQ. -// Note this is different to the INTF register: writing here -// affects PIO internal -// state. INTF just asserts the processor-facing IRQ signal for -// testing ISRs, -// and is not visible to the state machines. -#define PIO_IRQ_FORCE_OFFSET 0x00000034 -#define PIO_IRQ_FORCE_BITS 0x000000ff -#define PIO_IRQ_FORCE_RESET 0x00000000 -#define PIO_IRQ_FORCE_MSB 7 -#define PIO_IRQ_FORCE_LSB 0 +// corresponding IRQ. Note this is different to the INTF register: +// writing here affects PIO internal state. INTF just asserts the +// processor-facing IRQ signal for testing ISRs, and is not +// visible to the state machines. +#define PIO_IRQ_FORCE_OFFSET _u(0x00000034) +#define PIO_IRQ_FORCE_BITS _u(0x000000ff) +#define PIO_IRQ_FORCE_RESET _u(0x00000000) +#define PIO_IRQ_FORCE_MSB _u(7) +#define PIO_IRQ_FORCE_LSB _u(0) #define PIO_IRQ_FORCE_ACCESS "WF" // ============================================================================= // Register : PIO_INPUT_SYNC_BYPASS // Description : There is a 2-flipflop synchronizer on each GPIO input, which -// protects -// PIO logic from metastabilities. This increases input delay, and -// for fast -// synchronous IO (e.g. SPI) these synchronizers may need to be -// bypassed. -// Each bit in this register corresponds to one GPIO. +// protects PIO logic from metastabilities. This increases input +// delay, and for fast synchronous IO (e.g. SPI) these +// synchronizers may need to be bypassed. Each bit in this +// register corresponds to one GPIO. // 0 -> input is synchronized (default) // 1 -> synchronizer is bypassed // If in doubt, leave this register as all zeroes. -#define PIO_INPUT_SYNC_BYPASS_OFFSET 0x00000038 -#define PIO_INPUT_SYNC_BYPASS_BITS 0xffffffff -#define PIO_INPUT_SYNC_BYPASS_RESET 0x00000000 -#define PIO_INPUT_SYNC_BYPASS_MSB 31 -#define PIO_INPUT_SYNC_BYPASS_LSB 0 +#define PIO_INPUT_SYNC_BYPASS_OFFSET _u(0x00000038) +#define PIO_INPUT_SYNC_BYPASS_BITS _u(0xffffffff) +#define PIO_INPUT_SYNC_BYPASS_RESET _u(0x00000000) +#define PIO_INPUT_SYNC_BYPASS_MSB _u(31) +#define PIO_INPUT_SYNC_BYPASS_LSB _u(0) #define PIO_INPUT_SYNC_BYPASS_ACCESS "RW" // ============================================================================= // Register : PIO_DBG_PADOUT // Description : Read to sample the pad output values PIO is currently driving -// to the GPIOs. -#define PIO_DBG_PADOUT_OFFSET 0x0000003c -#define PIO_DBG_PADOUT_BITS 0xffffffff -#define PIO_DBG_PADOUT_RESET 0x00000000 -#define PIO_DBG_PADOUT_MSB 31 -#define PIO_DBG_PADOUT_LSB 0 +// to the GPIOs. On RP2040 there are 30 GPIOs, so the two most +// significant bits are hardwired to 0. +#define PIO_DBG_PADOUT_OFFSET _u(0x0000003c) +#define PIO_DBG_PADOUT_BITS _u(0xffffffff) +#define PIO_DBG_PADOUT_RESET _u(0x00000000) +#define PIO_DBG_PADOUT_MSB _u(31) +#define PIO_DBG_PADOUT_LSB _u(0) #define PIO_DBG_PADOUT_ACCESS "RO" // ============================================================================= // Register : PIO_DBG_PADOE // Description : Read to sample the pad output enables (direction) PIO is -// currently driving to the GPIOs. -#define PIO_DBG_PADOE_OFFSET 0x00000040 -#define PIO_DBG_PADOE_BITS 0xffffffff -#define PIO_DBG_PADOE_RESET 0x00000000 -#define PIO_DBG_PADOE_MSB 31 -#define PIO_DBG_PADOE_LSB 0 +// currently driving to the GPIOs. On RP2040 there are 30 GPIOs, +// so the two most significant bits are hardwired to 0. +#define PIO_DBG_PADOE_OFFSET _u(0x00000040) +#define PIO_DBG_PADOE_BITS _u(0xffffffff) +#define PIO_DBG_PADOE_RESET _u(0x00000000) +#define PIO_DBG_PADOE_MSB _u(31) +#define PIO_DBG_PADOE_LSB _u(0) #define PIO_DBG_PADOE_ACCESS "RO" // ============================================================================= // Register : PIO_DBG_CFGINFO @@ -338,26 +403,26 @@ // chip products. // These should be provided in the chip datasheet, but are also // exposed here. -#define PIO_DBG_CFGINFO_OFFSET 0x00000044 -#define PIO_DBG_CFGINFO_BITS 0x003f0f3f -#define PIO_DBG_CFGINFO_RESET 0x00000000 +#define PIO_DBG_CFGINFO_OFFSET _u(0x00000044) +#define PIO_DBG_CFGINFO_BITS _u(0x003f0f3f) +#define PIO_DBG_CFGINFO_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_DBG_CFGINFO_IMEM_SIZE // Description : The size of the instruction memory, measured in units of one // instruction #define PIO_DBG_CFGINFO_IMEM_SIZE_RESET "-" -#define PIO_DBG_CFGINFO_IMEM_SIZE_BITS 0x003f0000 -#define PIO_DBG_CFGINFO_IMEM_SIZE_MSB 21 -#define PIO_DBG_CFGINFO_IMEM_SIZE_LSB 16 +#define PIO_DBG_CFGINFO_IMEM_SIZE_BITS _u(0x003f0000) +#define PIO_DBG_CFGINFO_IMEM_SIZE_MSB _u(21) +#define PIO_DBG_CFGINFO_IMEM_SIZE_LSB _u(16) #define PIO_DBG_CFGINFO_IMEM_SIZE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_DBG_CFGINFO_SM_COUNT // Description : The number of state machines this PIO instance is equipped // with. #define PIO_DBG_CFGINFO_SM_COUNT_RESET "-" -#define PIO_DBG_CFGINFO_SM_COUNT_BITS 0x00000f00 -#define PIO_DBG_CFGINFO_SM_COUNT_MSB 11 -#define PIO_DBG_CFGINFO_SM_COUNT_LSB 8 +#define PIO_DBG_CFGINFO_SM_COUNT_BITS _u(0x00000f00) +#define PIO_DBG_CFGINFO_SM_COUNT_MSB _u(11) +#define PIO_DBG_CFGINFO_SM_COUNT_LSB _u(8) #define PIO_DBG_CFGINFO_SM_COUNT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_DBG_CFGINFO_FIFO_DEPTH @@ -365,373 +430,377 @@ // Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double // this depth. #define PIO_DBG_CFGINFO_FIFO_DEPTH_RESET "-" -#define PIO_DBG_CFGINFO_FIFO_DEPTH_BITS 0x0000003f -#define PIO_DBG_CFGINFO_FIFO_DEPTH_MSB 5 -#define PIO_DBG_CFGINFO_FIFO_DEPTH_LSB 0 +#define PIO_DBG_CFGINFO_FIFO_DEPTH_BITS _u(0x0000003f) +#define PIO_DBG_CFGINFO_FIFO_DEPTH_MSB _u(5) +#define PIO_DBG_CFGINFO_FIFO_DEPTH_LSB _u(0) #define PIO_DBG_CFGINFO_FIFO_DEPTH_ACCESS "RO" // ============================================================================= // Register : PIO_INSTR_MEM0 // Description : Write-only access to instruction memory location 0 -#define PIO_INSTR_MEM0_OFFSET 0x00000048 -#define PIO_INSTR_MEM0_BITS 0x0000ffff -#define PIO_INSTR_MEM0_RESET 0x00000000 -#define PIO_INSTR_MEM0_MSB 15 -#define PIO_INSTR_MEM0_LSB 0 +#define PIO_INSTR_MEM0_OFFSET _u(0x00000048) +#define PIO_INSTR_MEM0_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM0_RESET _u(0x00000000) +#define PIO_INSTR_MEM0_MSB _u(15) +#define PIO_INSTR_MEM0_LSB _u(0) #define PIO_INSTR_MEM0_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM1 // Description : Write-only access to instruction memory location 1 -#define PIO_INSTR_MEM1_OFFSET 0x0000004c -#define PIO_INSTR_MEM1_BITS 0x0000ffff -#define PIO_INSTR_MEM1_RESET 0x00000000 -#define PIO_INSTR_MEM1_MSB 15 -#define PIO_INSTR_MEM1_LSB 0 +#define PIO_INSTR_MEM1_OFFSET _u(0x0000004c) +#define PIO_INSTR_MEM1_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM1_RESET _u(0x00000000) +#define PIO_INSTR_MEM1_MSB _u(15) +#define PIO_INSTR_MEM1_LSB _u(0) #define PIO_INSTR_MEM1_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM2 // Description : Write-only access to instruction memory location 2 -#define PIO_INSTR_MEM2_OFFSET 0x00000050 -#define PIO_INSTR_MEM2_BITS 0x0000ffff -#define PIO_INSTR_MEM2_RESET 0x00000000 -#define PIO_INSTR_MEM2_MSB 15 -#define PIO_INSTR_MEM2_LSB 0 +#define PIO_INSTR_MEM2_OFFSET _u(0x00000050) +#define PIO_INSTR_MEM2_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM2_RESET _u(0x00000000) +#define PIO_INSTR_MEM2_MSB _u(15) +#define PIO_INSTR_MEM2_LSB _u(0) #define PIO_INSTR_MEM2_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM3 // Description : Write-only access to instruction memory location 3 -#define PIO_INSTR_MEM3_OFFSET 0x00000054 -#define PIO_INSTR_MEM3_BITS 0x0000ffff -#define PIO_INSTR_MEM3_RESET 0x00000000 -#define PIO_INSTR_MEM3_MSB 15 -#define PIO_INSTR_MEM3_LSB 0 +#define PIO_INSTR_MEM3_OFFSET _u(0x00000054) +#define PIO_INSTR_MEM3_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM3_RESET _u(0x00000000) +#define PIO_INSTR_MEM3_MSB _u(15) +#define PIO_INSTR_MEM3_LSB _u(0) #define PIO_INSTR_MEM3_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM4 // Description : Write-only access to instruction memory location 4 -#define PIO_INSTR_MEM4_OFFSET 0x00000058 -#define PIO_INSTR_MEM4_BITS 0x0000ffff -#define PIO_INSTR_MEM4_RESET 0x00000000 -#define PIO_INSTR_MEM4_MSB 15 -#define PIO_INSTR_MEM4_LSB 0 +#define PIO_INSTR_MEM4_OFFSET _u(0x00000058) +#define PIO_INSTR_MEM4_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM4_RESET _u(0x00000000) +#define PIO_INSTR_MEM4_MSB _u(15) +#define PIO_INSTR_MEM4_LSB _u(0) #define PIO_INSTR_MEM4_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM5 // Description : Write-only access to instruction memory location 5 -#define PIO_INSTR_MEM5_OFFSET 0x0000005c -#define PIO_INSTR_MEM5_BITS 0x0000ffff -#define PIO_INSTR_MEM5_RESET 0x00000000 -#define PIO_INSTR_MEM5_MSB 15 -#define PIO_INSTR_MEM5_LSB 0 +#define PIO_INSTR_MEM5_OFFSET _u(0x0000005c) +#define PIO_INSTR_MEM5_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM5_RESET _u(0x00000000) +#define PIO_INSTR_MEM5_MSB _u(15) +#define PIO_INSTR_MEM5_LSB _u(0) #define PIO_INSTR_MEM5_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM6 // Description : Write-only access to instruction memory location 6 -#define PIO_INSTR_MEM6_OFFSET 0x00000060 -#define PIO_INSTR_MEM6_BITS 0x0000ffff -#define PIO_INSTR_MEM6_RESET 0x00000000 -#define PIO_INSTR_MEM6_MSB 15 -#define PIO_INSTR_MEM6_LSB 0 +#define PIO_INSTR_MEM6_OFFSET _u(0x00000060) +#define PIO_INSTR_MEM6_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM6_RESET _u(0x00000000) +#define PIO_INSTR_MEM6_MSB _u(15) +#define PIO_INSTR_MEM6_LSB _u(0) #define PIO_INSTR_MEM6_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM7 // Description : Write-only access to instruction memory location 7 -#define PIO_INSTR_MEM7_OFFSET 0x00000064 -#define PIO_INSTR_MEM7_BITS 0x0000ffff -#define PIO_INSTR_MEM7_RESET 0x00000000 -#define PIO_INSTR_MEM7_MSB 15 -#define PIO_INSTR_MEM7_LSB 0 +#define PIO_INSTR_MEM7_OFFSET _u(0x00000064) +#define PIO_INSTR_MEM7_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM7_RESET _u(0x00000000) +#define PIO_INSTR_MEM7_MSB _u(15) +#define PIO_INSTR_MEM7_LSB _u(0) #define PIO_INSTR_MEM7_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM8 // Description : Write-only access to instruction memory location 8 -#define PIO_INSTR_MEM8_OFFSET 0x00000068 -#define PIO_INSTR_MEM8_BITS 0x0000ffff -#define PIO_INSTR_MEM8_RESET 0x00000000 -#define PIO_INSTR_MEM8_MSB 15 -#define PIO_INSTR_MEM8_LSB 0 +#define PIO_INSTR_MEM8_OFFSET _u(0x00000068) +#define PIO_INSTR_MEM8_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM8_RESET _u(0x00000000) +#define PIO_INSTR_MEM8_MSB _u(15) +#define PIO_INSTR_MEM8_LSB _u(0) #define PIO_INSTR_MEM8_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM9 // Description : Write-only access to instruction memory location 9 -#define PIO_INSTR_MEM9_OFFSET 0x0000006c -#define PIO_INSTR_MEM9_BITS 0x0000ffff -#define PIO_INSTR_MEM9_RESET 0x00000000 -#define PIO_INSTR_MEM9_MSB 15 -#define PIO_INSTR_MEM9_LSB 0 +#define PIO_INSTR_MEM9_OFFSET _u(0x0000006c) +#define PIO_INSTR_MEM9_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM9_RESET _u(0x00000000) +#define PIO_INSTR_MEM9_MSB _u(15) +#define PIO_INSTR_MEM9_LSB _u(0) #define PIO_INSTR_MEM9_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM10 // Description : Write-only access to instruction memory location 10 -#define PIO_INSTR_MEM10_OFFSET 0x00000070 -#define PIO_INSTR_MEM10_BITS 0x0000ffff -#define PIO_INSTR_MEM10_RESET 0x00000000 -#define PIO_INSTR_MEM10_MSB 15 -#define PIO_INSTR_MEM10_LSB 0 +#define PIO_INSTR_MEM10_OFFSET _u(0x00000070) +#define PIO_INSTR_MEM10_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM10_RESET _u(0x00000000) +#define PIO_INSTR_MEM10_MSB _u(15) +#define PIO_INSTR_MEM10_LSB _u(0) #define PIO_INSTR_MEM10_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM11 // Description : Write-only access to instruction memory location 11 -#define PIO_INSTR_MEM11_OFFSET 0x00000074 -#define PIO_INSTR_MEM11_BITS 0x0000ffff -#define PIO_INSTR_MEM11_RESET 0x00000000 -#define PIO_INSTR_MEM11_MSB 15 -#define PIO_INSTR_MEM11_LSB 0 +#define PIO_INSTR_MEM11_OFFSET _u(0x00000074) +#define PIO_INSTR_MEM11_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM11_RESET _u(0x00000000) +#define PIO_INSTR_MEM11_MSB _u(15) +#define PIO_INSTR_MEM11_LSB _u(0) #define PIO_INSTR_MEM11_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM12 // Description : Write-only access to instruction memory location 12 -#define PIO_INSTR_MEM12_OFFSET 0x00000078 -#define PIO_INSTR_MEM12_BITS 0x0000ffff -#define PIO_INSTR_MEM12_RESET 0x00000000 -#define PIO_INSTR_MEM12_MSB 15 -#define PIO_INSTR_MEM12_LSB 0 +#define PIO_INSTR_MEM12_OFFSET _u(0x00000078) +#define PIO_INSTR_MEM12_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM12_RESET _u(0x00000000) +#define PIO_INSTR_MEM12_MSB _u(15) +#define PIO_INSTR_MEM12_LSB _u(0) #define PIO_INSTR_MEM12_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM13 // Description : Write-only access to instruction memory location 13 -#define PIO_INSTR_MEM13_OFFSET 0x0000007c -#define PIO_INSTR_MEM13_BITS 0x0000ffff -#define PIO_INSTR_MEM13_RESET 0x00000000 -#define PIO_INSTR_MEM13_MSB 15 -#define PIO_INSTR_MEM13_LSB 0 +#define PIO_INSTR_MEM13_OFFSET _u(0x0000007c) +#define PIO_INSTR_MEM13_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM13_RESET _u(0x00000000) +#define PIO_INSTR_MEM13_MSB _u(15) +#define PIO_INSTR_MEM13_LSB _u(0) #define PIO_INSTR_MEM13_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM14 // Description : Write-only access to instruction memory location 14 -#define PIO_INSTR_MEM14_OFFSET 0x00000080 -#define PIO_INSTR_MEM14_BITS 0x0000ffff -#define PIO_INSTR_MEM14_RESET 0x00000000 -#define PIO_INSTR_MEM14_MSB 15 -#define PIO_INSTR_MEM14_LSB 0 +#define PIO_INSTR_MEM14_OFFSET _u(0x00000080) +#define PIO_INSTR_MEM14_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM14_RESET _u(0x00000000) +#define PIO_INSTR_MEM14_MSB _u(15) +#define PIO_INSTR_MEM14_LSB _u(0) #define PIO_INSTR_MEM14_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM15 // Description : Write-only access to instruction memory location 15 -#define PIO_INSTR_MEM15_OFFSET 0x00000084 -#define PIO_INSTR_MEM15_BITS 0x0000ffff -#define PIO_INSTR_MEM15_RESET 0x00000000 -#define PIO_INSTR_MEM15_MSB 15 -#define PIO_INSTR_MEM15_LSB 0 +#define PIO_INSTR_MEM15_OFFSET _u(0x00000084) +#define PIO_INSTR_MEM15_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM15_RESET _u(0x00000000) +#define PIO_INSTR_MEM15_MSB _u(15) +#define PIO_INSTR_MEM15_LSB _u(0) #define PIO_INSTR_MEM15_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM16 // Description : Write-only access to instruction memory location 16 -#define PIO_INSTR_MEM16_OFFSET 0x00000088 -#define PIO_INSTR_MEM16_BITS 0x0000ffff -#define PIO_INSTR_MEM16_RESET 0x00000000 -#define PIO_INSTR_MEM16_MSB 15 -#define PIO_INSTR_MEM16_LSB 0 +#define PIO_INSTR_MEM16_OFFSET _u(0x00000088) +#define PIO_INSTR_MEM16_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM16_RESET _u(0x00000000) +#define PIO_INSTR_MEM16_MSB _u(15) +#define PIO_INSTR_MEM16_LSB _u(0) #define PIO_INSTR_MEM16_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM17 // Description : Write-only access to instruction memory location 17 -#define PIO_INSTR_MEM17_OFFSET 0x0000008c -#define PIO_INSTR_MEM17_BITS 0x0000ffff -#define PIO_INSTR_MEM17_RESET 0x00000000 -#define PIO_INSTR_MEM17_MSB 15 -#define PIO_INSTR_MEM17_LSB 0 +#define PIO_INSTR_MEM17_OFFSET _u(0x0000008c) +#define PIO_INSTR_MEM17_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM17_RESET _u(0x00000000) +#define PIO_INSTR_MEM17_MSB _u(15) +#define PIO_INSTR_MEM17_LSB _u(0) #define PIO_INSTR_MEM17_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM18 // Description : Write-only access to instruction memory location 18 -#define PIO_INSTR_MEM18_OFFSET 0x00000090 -#define PIO_INSTR_MEM18_BITS 0x0000ffff -#define PIO_INSTR_MEM18_RESET 0x00000000 -#define PIO_INSTR_MEM18_MSB 15 -#define PIO_INSTR_MEM18_LSB 0 +#define PIO_INSTR_MEM18_OFFSET _u(0x00000090) +#define PIO_INSTR_MEM18_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM18_RESET _u(0x00000000) +#define PIO_INSTR_MEM18_MSB _u(15) +#define PIO_INSTR_MEM18_LSB _u(0) #define PIO_INSTR_MEM18_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM19 // Description : Write-only access to instruction memory location 19 -#define PIO_INSTR_MEM19_OFFSET 0x00000094 -#define PIO_INSTR_MEM19_BITS 0x0000ffff -#define PIO_INSTR_MEM19_RESET 0x00000000 -#define PIO_INSTR_MEM19_MSB 15 -#define PIO_INSTR_MEM19_LSB 0 +#define PIO_INSTR_MEM19_OFFSET _u(0x00000094) +#define PIO_INSTR_MEM19_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM19_RESET _u(0x00000000) +#define PIO_INSTR_MEM19_MSB _u(15) +#define PIO_INSTR_MEM19_LSB _u(0) #define PIO_INSTR_MEM19_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM20 // Description : Write-only access to instruction memory location 20 -#define PIO_INSTR_MEM20_OFFSET 0x00000098 -#define PIO_INSTR_MEM20_BITS 0x0000ffff -#define PIO_INSTR_MEM20_RESET 0x00000000 -#define PIO_INSTR_MEM20_MSB 15 -#define PIO_INSTR_MEM20_LSB 0 +#define PIO_INSTR_MEM20_OFFSET _u(0x00000098) +#define PIO_INSTR_MEM20_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM20_RESET _u(0x00000000) +#define PIO_INSTR_MEM20_MSB _u(15) +#define PIO_INSTR_MEM20_LSB _u(0) #define PIO_INSTR_MEM20_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM21 // Description : Write-only access to instruction memory location 21 -#define PIO_INSTR_MEM21_OFFSET 0x0000009c -#define PIO_INSTR_MEM21_BITS 0x0000ffff -#define PIO_INSTR_MEM21_RESET 0x00000000 -#define PIO_INSTR_MEM21_MSB 15 -#define PIO_INSTR_MEM21_LSB 0 +#define PIO_INSTR_MEM21_OFFSET _u(0x0000009c) +#define PIO_INSTR_MEM21_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM21_RESET _u(0x00000000) +#define PIO_INSTR_MEM21_MSB _u(15) +#define PIO_INSTR_MEM21_LSB _u(0) #define PIO_INSTR_MEM21_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM22 // Description : Write-only access to instruction memory location 22 -#define PIO_INSTR_MEM22_OFFSET 0x000000a0 -#define PIO_INSTR_MEM22_BITS 0x0000ffff -#define PIO_INSTR_MEM22_RESET 0x00000000 -#define PIO_INSTR_MEM22_MSB 15 -#define PIO_INSTR_MEM22_LSB 0 +#define PIO_INSTR_MEM22_OFFSET _u(0x000000a0) +#define PIO_INSTR_MEM22_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM22_RESET _u(0x00000000) +#define PIO_INSTR_MEM22_MSB _u(15) +#define PIO_INSTR_MEM22_LSB _u(0) #define PIO_INSTR_MEM22_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM23 // Description : Write-only access to instruction memory location 23 -#define PIO_INSTR_MEM23_OFFSET 0x000000a4 -#define PIO_INSTR_MEM23_BITS 0x0000ffff -#define PIO_INSTR_MEM23_RESET 0x00000000 -#define PIO_INSTR_MEM23_MSB 15 -#define PIO_INSTR_MEM23_LSB 0 +#define PIO_INSTR_MEM23_OFFSET _u(0x000000a4) +#define PIO_INSTR_MEM23_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM23_RESET _u(0x00000000) +#define PIO_INSTR_MEM23_MSB _u(15) +#define PIO_INSTR_MEM23_LSB _u(0) #define PIO_INSTR_MEM23_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM24 // Description : Write-only access to instruction memory location 24 -#define PIO_INSTR_MEM24_OFFSET 0x000000a8 -#define PIO_INSTR_MEM24_BITS 0x0000ffff -#define PIO_INSTR_MEM24_RESET 0x00000000 -#define PIO_INSTR_MEM24_MSB 15 -#define PIO_INSTR_MEM24_LSB 0 +#define PIO_INSTR_MEM24_OFFSET _u(0x000000a8) +#define PIO_INSTR_MEM24_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM24_RESET _u(0x00000000) +#define PIO_INSTR_MEM24_MSB _u(15) +#define PIO_INSTR_MEM24_LSB _u(0) #define PIO_INSTR_MEM24_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM25 // Description : Write-only access to instruction memory location 25 -#define PIO_INSTR_MEM25_OFFSET 0x000000ac -#define PIO_INSTR_MEM25_BITS 0x0000ffff -#define PIO_INSTR_MEM25_RESET 0x00000000 -#define PIO_INSTR_MEM25_MSB 15 -#define PIO_INSTR_MEM25_LSB 0 +#define PIO_INSTR_MEM25_OFFSET _u(0x000000ac) +#define PIO_INSTR_MEM25_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM25_RESET _u(0x00000000) +#define PIO_INSTR_MEM25_MSB _u(15) +#define PIO_INSTR_MEM25_LSB _u(0) #define PIO_INSTR_MEM25_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM26 // Description : Write-only access to instruction memory location 26 -#define PIO_INSTR_MEM26_OFFSET 0x000000b0 -#define PIO_INSTR_MEM26_BITS 0x0000ffff -#define PIO_INSTR_MEM26_RESET 0x00000000 -#define PIO_INSTR_MEM26_MSB 15 -#define PIO_INSTR_MEM26_LSB 0 +#define PIO_INSTR_MEM26_OFFSET _u(0x000000b0) +#define PIO_INSTR_MEM26_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM26_RESET _u(0x00000000) +#define PIO_INSTR_MEM26_MSB _u(15) +#define PIO_INSTR_MEM26_LSB _u(0) #define PIO_INSTR_MEM26_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM27 // Description : Write-only access to instruction memory location 27 -#define PIO_INSTR_MEM27_OFFSET 0x000000b4 -#define PIO_INSTR_MEM27_BITS 0x0000ffff -#define PIO_INSTR_MEM27_RESET 0x00000000 -#define PIO_INSTR_MEM27_MSB 15 -#define PIO_INSTR_MEM27_LSB 0 +#define PIO_INSTR_MEM27_OFFSET _u(0x000000b4) +#define PIO_INSTR_MEM27_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM27_RESET _u(0x00000000) +#define PIO_INSTR_MEM27_MSB _u(15) +#define PIO_INSTR_MEM27_LSB _u(0) #define PIO_INSTR_MEM27_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM28 // Description : Write-only access to instruction memory location 28 -#define PIO_INSTR_MEM28_OFFSET 0x000000b8 -#define PIO_INSTR_MEM28_BITS 0x0000ffff -#define PIO_INSTR_MEM28_RESET 0x00000000 -#define PIO_INSTR_MEM28_MSB 15 -#define PIO_INSTR_MEM28_LSB 0 +#define PIO_INSTR_MEM28_OFFSET _u(0x000000b8) +#define PIO_INSTR_MEM28_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM28_RESET _u(0x00000000) +#define PIO_INSTR_MEM28_MSB _u(15) +#define PIO_INSTR_MEM28_LSB _u(0) #define PIO_INSTR_MEM28_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM29 // Description : Write-only access to instruction memory location 29 -#define PIO_INSTR_MEM29_OFFSET 0x000000bc -#define PIO_INSTR_MEM29_BITS 0x0000ffff -#define PIO_INSTR_MEM29_RESET 0x00000000 -#define PIO_INSTR_MEM29_MSB 15 -#define PIO_INSTR_MEM29_LSB 0 +#define PIO_INSTR_MEM29_OFFSET _u(0x000000bc) +#define PIO_INSTR_MEM29_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM29_RESET _u(0x00000000) +#define PIO_INSTR_MEM29_MSB _u(15) +#define PIO_INSTR_MEM29_LSB _u(0) #define PIO_INSTR_MEM29_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM30 // Description : Write-only access to instruction memory location 30 -#define PIO_INSTR_MEM30_OFFSET 0x000000c0 -#define PIO_INSTR_MEM30_BITS 0x0000ffff -#define PIO_INSTR_MEM30_RESET 0x00000000 -#define PIO_INSTR_MEM30_MSB 15 -#define PIO_INSTR_MEM30_LSB 0 +#define PIO_INSTR_MEM30_OFFSET _u(0x000000c0) +#define PIO_INSTR_MEM30_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM30_RESET _u(0x00000000) +#define PIO_INSTR_MEM30_MSB _u(15) +#define PIO_INSTR_MEM30_LSB _u(0) #define PIO_INSTR_MEM30_ACCESS "WO" // ============================================================================= // Register : PIO_INSTR_MEM31 // Description : Write-only access to instruction memory location 31 -#define PIO_INSTR_MEM31_OFFSET 0x000000c4 -#define PIO_INSTR_MEM31_BITS 0x0000ffff -#define PIO_INSTR_MEM31_RESET 0x00000000 -#define PIO_INSTR_MEM31_MSB 15 -#define PIO_INSTR_MEM31_LSB 0 +#define PIO_INSTR_MEM31_OFFSET _u(0x000000c4) +#define PIO_INSTR_MEM31_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM31_RESET _u(0x00000000) +#define PIO_INSTR_MEM31_MSB _u(15) +#define PIO_INSTR_MEM31_LSB _u(0) #define PIO_INSTR_MEM31_ACCESS "WO" // ============================================================================= // Register : PIO_SM0_CLKDIV -// Description : Clock divider register for state machine 0 +// Description : Clock divisor register for state machine 0 // Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) -#define PIO_SM0_CLKDIV_OFFSET 0x000000c8 -#define PIO_SM0_CLKDIV_BITS 0xffffff00 -#define PIO_SM0_CLKDIV_RESET 0x00010000 +#define PIO_SM0_CLKDIV_OFFSET _u(0x000000c8) +#define PIO_SM0_CLKDIV_BITS _u(0xffffff00) +#define PIO_SM0_CLKDIV_RESET _u(0x00010000) // ----------------------------------------------------------------------------- // Field : PIO_SM0_CLKDIV_INT -// Description : Effective frequency is sysclk/int. -// Value of 0 is interpreted as max possible value -#define PIO_SM0_CLKDIV_INT_RESET 0x0001 -#define PIO_SM0_CLKDIV_INT_BITS 0xffff0000 -#define PIO_SM0_CLKDIV_INT_MSB 31 -#define PIO_SM0_CLKDIV_INT_LSB 16 +// Description : Effective frequency is sysclk/(int + frac/256). +// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also +// be 0. +#define PIO_SM0_CLKDIV_INT_RESET _u(0x0001) +#define PIO_SM0_CLKDIV_INT_BITS _u(0xffff0000) +#define PIO_SM0_CLKDIV_INT_MSB _u(31) +#define PIO_SM0_CLKDIV_INT_LSB _u(16) #define PIO_SM0_CLKDIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_CLKDIV_FRAC -// Description : Fractional part of clock divider -#define PIO_SM0_CLKDIV_FRAC_RESET 0x00 -#define PIO_SM0_CLKDIV_FRAC_BITS 0x0000ff00 -#define PIO_SM0_CLKDIV_FRAC_MSB 15 -#define PIO_SM0_CLKDIV_FRAC_LSB 8 +// Description : Fractional part of clock divisor +#define PIO_SM0_CLKDIV_FRAC_RESET _u(0x00) +#define PIO_SM0_CLKDIV_FRAC_BITS _u(0x0000ff00) +#define PIO_SM0_CLKDIV_FRAC_MSB _u(15) +#define PIO_SM0_CLKDIV_FRAC_LSB _u(8) #define PIO_SM0_CLKDIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PIO_SM0_EXECCTRL // Description : Execution/behavioural settings for state machine 0 -#define PIO_SM0_EXECCTRL_OFFSET 0x000000cc -#define PIO_SM0_EXECCTRL_BITS 0xffffff9f -#define PIO_SM0_EXECCTRL_RESET 0x0001f000 +#define PIO_SM0_EXECCTRL_OFFSET _u(0x000000cc) +#define PIO_SM0_EXECCTRL_BITS _u(0xffffff9f) +#define PIO_SM0_EXECCTRL_RESET _u(0x0001f000) // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_EXEC_STALLED -// Description : An instruction written to SMx_INSTR is stalled, and latched by -// the -// state machine. Will clear once the instruction completes. -#define PIO_SM0_EXECCTRL_EXEC_STALLED_RESET 0x0 -#define PIO_SM0_EXECCTRL_EXEC_STALLED_BITS 0x80000000 -#define PIO_SM0_EXECCTRL_EXEC_STALLED_MSB 31 -#define PIO_SM0_EXECCTRL_EXEC_STALLED_LSB 31 +// Description : If 1, an instruction written to SMx_INSTR is stalled, and +// latched by the state machine. Will clear to 0 once this +// instruction completes. +#define PIO_SM0_EXECCTRL_EXEC_STALLED_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) +#define PIO_SM0_EXECCTRL_EXEC_STALLED_MSB _u(31) +#define PIO_SM0_EXECCTRL_EXEC_STALLED_LSB _u(31) #define PIO_SM0_EXECCTRL_EXEC_STALLED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_SIDE_EN -// Description : If 1, the delay MSB is used as side-set enable, rather than a -// side-set data bit. This allows instructions to perform side-set -// optionally, -// rather than on every instruction. -#define PIO_SM0_EXECCTRL_SIDE_EN_RESET 0x0 -#define PIO_SM0_EXECCTRL_SIDE_EN_BITS 0x40000000 -#define PIO_SM0_EXECCTRL_SIDE_EN_MSB 30 -#define PIO_SM0_EXECCTRL_SIDE_EN_LSB 30 +// Description : If 1, the MSB of the Delay/Side-set instruction field is used +// as side-set enable, rather than a side-set data bit. This +// allows instructions to perform side-set optionally, rather than +// on every instruction, but the maximum possible side-set width +// is reduced from 5 to 4. Note that the value of +// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. +#define PIO_SM0_EXECCTRL_SIDE_EN_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_SIDE_EN_BITS _u(0x40000000) +#define PIO_SM0_EXECCTRL_SIDE_EN_MSB _u(30) +#define PIO_SM0_EXECCTRL_SIDE_EN_LSB _u(30) #define PIO_SM0_EXECCTRL_SIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_SIDE_PINDIR -// Description : Side-set data is asserted to pin OEs instead of pin values -#define PIO_SM0_EXECCTRL_SIDE_PINDIR_RESET 0x0 -#define PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS 0x20000000 -#define PIO_SM0_EXECCTRL_SIDE_PINDIR_MSB 29 -#define PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB 29 +// Description : If 1, side-set data is asserted to pin directions, instead of +// pin values +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_MSB _u(29) +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB _u(29) #define PIO_SM0_EXECCTRL_SIDE_PINDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_JMP_PIN // Description : The GPIO number to use as condition for JMP PIN. Unaffected by // input mapping. -#define PIO_SM0_EXECCTRL_JMP_PIN_RESET 0x00 -#define PIO_SM0_EXECCTRL_JMP_PIN_BITS 0x1f000000 -#define PIO_SM0_EXECCTRL_JMP_PIN_MSB 28 -#define PIO_SM0_EXECCTRL_JMP_PIN_LSB 24 +#define PIO_SM0_EXECCTRL_JMP_PIN_RESET _u(0x00) +#define PIO_SM0_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) +#define PIO_SM0_EXECCTRL_JMP_PIN_MSB _u(28) +#define PIO_SM0_EXECCTRL_JMP_PIN_LSB _u(24) #define PIO_SM0_EXECCTRL_JMP_PIN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_OUT_EN_SEL // Description : Which data bit to use for inline OUT enable -#define PIO_SM0_EXECCTRL_OUT_EN_SEL_RESET 0x00 -#define PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS 0x00f80000 -#define PIO_SM0_EXECCTRL_OUT_EN_SEL_MSB 23 -#define PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB 19 +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_MSB _u(23) +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB _u(19) #define PIO_SM0_EXECCTRL_OUT_EN_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_INLINE_OUT_EN @@ -742,18 +811,18 @@ // masking/override behaviour // due to the priority ordering of state machine pin writes (SM0 < // SM1 < ...) -#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_RESET 0x0 -#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS 0x00040000 -#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_MSB 18 -#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB 18 +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_MSB _u(18) +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB _u(18) #define PIO_SM0_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_OUT_STICKY // Description : Continuously assert the most recent OUT/SET to the pins -#define PIO_SM0_EXECCTRL_OUT_STICKY_RESET 0x0 -#define PIO_SM0_EXECCTRL_OUT_STICKY_BITS 0x00020000 -#define PIO_SM0_EXECCTRL_OUT_STICKY_MSB 17 -#define PIO_SM0_EXECCTRL_OUT_STICKY_LSB 17 +#define PIO_SM0_EXECCTRL_OUT_STICKY_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) +#define PIO_SM0_EXECCTRL_OUT_STICKY_MSB _u(17) +#define PIO_SM0_EXECCTRL_OUT_STICKY_LSB _u(17) #define PIO_SM0_EXECCTRL_OUT_STICKY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_WRAP_TOP @@ -761,46 +830,46 @@ // wrap_bottom. // If the instruction is a jump, and the jump condition is true, // the jump takes priority. -#define PIO_SM0_EXECCTRL_WRAP_TOP_RESET 0x1f -#define PIO_SM0_EXECCTRL_WRAP_TOP_BITS 0x0001f000 -#define PIO_SM0_EXECCTRL_WRAP_TOP_MSB 16 -#define PIO_SM0_EXECCTRL_WRAP_TOP_LSB 12 +#define PIO_SM0_EXECCTRL_WRAP_TOP_RESET _u(0x1f) +#define PIO_SM0_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) +#define PIO_SM0_EXECCTRL_WRAP_TOP_MSB _u(16) +#define PIO_SM0_EXECCTRL_WRAP_TOP_LSB _u(12) #define PIO_SM0_EXECCTRL_WRAP_TOP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_WRAP_BOTTOM // Description : After reaching wrap_top, execution is wrapped to this address. -#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_RESET 0x00 -#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS 0x00000f80 -#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_MSB 11 -#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB 7 +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_MSB _u(11) +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB _u(7) #define PIO_SM0_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_STATUS_SEL // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PIO_SM0_EXECCTRL_STATUS_SEL_RESET 0x0 -#define PIO_SM0_EXECCTRL_STATUS_SEL_BITS 0x00000010 -#define PIO_SM0_EXECCTRL_STATUS_SEL_MSB 4 -#define PIO_SM0_EXECCTRL_STATUS_SEL_LSB 4 +#define PIO_SM0_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) +#define PIO_SM0_EXECCTRL_STATUS_SEL_MSB _u(4) +#define PIO_SM0_EXECCTRL_STATUS_SEL_LSB _u(4) #define PIO_SM0_EXECCTRL_STATUS_SEL_ACCESS "RW" -#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL 0x0 -#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL 0x1 +#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) +#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) // ----------------------------------------------------------------------------- // Field : PIO_SM0_EXECCTRL_STATUS_N // Description : Comparison level for the MOV x, STATUS instruction -#define PIO_SM0_EXECCTRL_STATUS_N_RESET 0x0 -#define PIO_SM0_EXECCTRL_STATUS_N_BITS 0x0000000f -#define PIO_SM0_EXECCTRL_STATUS_N_MSB 3 -#define PIO_SM0_EXECCTRL_STATUS_N_LSB 0 +#define PIO_SM0_EXECCTRL_STATUS_N_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_STATUS_N_BITS _u(0x0000000f) +#define PIO_SM0_EXECCTRL_STATUS_N_MSB _u(3) +#define PIO_SM0_EXECCTRL_STATUS_N_LSB _u(0) #define PIO_SM0_EXECCTRL_STATUS_N_ACCESS "RW" // ============================================================================= // Register : PIO_SM0_SHIFTCTRL // Description : Control behaviour of the input/output shift registers for state // machine 0 -#define PIO_SM0_SHIFTCTRL_OFFSET 0x000000d0 -#define PIO_SM0_SHIFTCTRL_BITS 0xffff0000 -#define PIO_SM0_SHIFTCTRL_RESET 0x000c0000 +#define PIO_SM0_SHIFTCTRL_OFFSET _u(0x000000d0) +#define PIO_SM0_SHIFTCTRL_BITS _u(0xffff0000) +#define PIO_SM0_SHIFTCTRL_RESET _u(0x000c0000) // ----------------------------------------------------------------------------- // Field : PIO_SM0_SHIFTCTRL_FJOIN_RX // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice @@ -808,10 +877,10 @@ // TX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_RESET 0x0 -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS 0x80000000 -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_MSB 31 -#define PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB 31 +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_MSB _u(31) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB _u(31) #define PIO_SM0_SHIFTCTRL_FJOIN_RX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_SHIFTCTRL_FJOIN_TX @@ -820,222 +889,249 @@ // RX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PIO_SM0_SHIFTCTRL_FJOIN_TX_RESET 0x0 -#define PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS 0x40000000 -#define PIO_SM0_SHIFTCTRL_FJOIN_TX_MSB 30 -#define PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB 30 +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_MSB _u(30) +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB _u(30) #define PIO_SM0_SHIFTCTRL_FJOIN_TX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_SHIFTCTRL_PULL_THRESH -// Description : Number of bits shifted out of TXSR before autopull or -// conditional pull. +// Description : Number of bits shifted out of OSR before autopull, or +// conditional pull (PULL IFEMPTY), will take place. // Write 0 for value of 32. -#define PIO_SM0_SHIFTCTRL_PULL_THRESH_RESET 0x00 -#define PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS 0x3e000000 -#define PIO_SM0_SHIFTCTRL_PULL_THRESH_MSB 29 -#define PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB 25 +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_MSB _u(29) +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB _u(25) #define PIO_SM0_SHIFTCTRL_PULL_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_SHIFTCTRL_PUSH_THRESH -// Description : Number of bits shifted into RXSR before autopush or conditional -// push. +// Description : Number of bits shifted into ISR before autopush, or conditional +// push (PUSH IFFULL), will take place. // Write 0 for value of 32. -#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_RESET 0x00 -#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS 0x01f00000 -#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_MSB 24 -#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB 20 +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_MSB _u(24) +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB _u(20) #define PIO_SM0_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR // Description : 1 = shift out of output shift register to right. 0 = to left. -#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_RESET 0x1 -#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS 0x00080000 -#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_MSB 19 -#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB 19 +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) #define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_SHIFTCTRL_IN_SHIFTDIR // Description : 1 = shift input shift register to right (data enters from // left). 0 = to left. -#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_RESET 0x1 -#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS 0x00040000 -#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_MSB 18 -#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB 18 +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) #define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_SHIFTCTRL_AUTOPULL -// Description : Pull automatically when the output shift register is emptied -#define PIO_SM0_SHIFTCTRL_AUTOPULL_RESET 0x0 -#define PIO_SM0_SHIFTCTRL_AUTOPULL_BITS 0x00020000 -#define PIO_SM0_SHIFTCTRL_AUTOPULL_MSB 17 -#define PIO_SM0_SHIFTCTRL_AUTOPULL_LSB 17 +// Description : Pull automatically when the output shift register is emptied, +// i.e. on or following an OUT instruction which causes the output +// shift counter to reach or exceed PULL_THRESH. +#define PIO_SM0_SHIFTCTRL_AUTOPULL_RESET _u(0x0) +#define PIO_SM0_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) +#define PIO_SM0_SHIFTCTRL_AUTOPULL_MSB _u(17) +#define PIO_SM0_SHIFTCTRL_AUTOPULL_LSB _u(17) #define PIO_SM0_SHIFTCTRL_AUTOPULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_SHIFTCTRL_AUTOPUSH -// Description : Push automatically when the input shift register is filled -#define PIO_SM0_SHIFTCTRL_AUTOPUSH_RESET 0x0 -#define PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS 0x00010000 -#define PIO_SM0_SHIFTCTRL_AUTOPUSH_MSB 16 -#define PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB 16 +// Description : Push automatically when the input shift register is filled, +// i.e. on an IN instruction which causes the input shift counter +// to reach or exceed PUSH_THRESH. +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_MSB _u(16) +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB _u(16) #define PIO_SM0_SHIFTCTRL_AUTOPUSH_ACCESS "RW" // ============================================================================= // Register : PIO_SM0_ADDR // Description : Current instruction address of state machine 0 -#define PIO_SM0_ADDR_OFFSET 0x000000d4 -#define PIO_SM0_ADDR_BITS 0x0000001f -#define PIO_SM0_ADDR_RESET 0x00000000 -#define PIO_SM0_ADDR_MSB 4 -#define PIO_SM0_ADDR_LSB 0 +#define PIO_SM0_ADDR_OFFSET _u(0x000000d4) +#define PIO_SM0_ADDR_BITS _u(0x0000001f) +#define PIO_SM0_ADDR_RESET _u(0x00000000) +#define PIO_SM0_ADDR_MSB _u(4) +#define PIO_SM0_ADDR_LSB _u(0) #define PIO_SM0_ADDR_ACCESS "RO" // ============================================================================= // Register : PIO_SM0_INSTR -// Description : Instruction currently being executed by state machine 0 +// Description : Read to see the instruction currently addressed by state +// machine 0's program counter // Write to execute an instruction immediately (including jumps) // and then resume execution. -#define PIO_SM0_INSTR_OFFSET 0x000000d8 -#define PIO_SM0_INSTR_BITS 0x0000ffff +#define PIO_SM0_INSTR_OFFSET _u(0x000000d8) +#define PIO_SM0_INSTR_BITS _u(0x0000ffff) #define PIO_SM0_INSTR_RESET "-" -#define PIO_SM0_INSTR_MSB 15 -#define PIO_SM0_INSTR_LSB 0 +#define PIO_SM0_INSTR_MSB _u(15) +#define PIO_SM0_INSTR_LSB _u(0) #define PIO_SM0_INSTR_ACCESS "RW" // ============================================================================= // Register : PIO_SM0_PINCTRL // Description : State machine pin control -#define PIO_SM0_PINCTRL_OFFSET 0x000000dc -#define PIO_SM0_PINCTRL_BITS 0xffffffff -#define PIO_SM0_PINCTRL_RESET 0x14000000 +#define PIO_SM0_PINCTRL_OFFSET _u(0x000000dc) +#define PIO_SM0_PINCTRL_BITS _u(0xffffffff) +#define PIO_SM0_PINCTRL_RESET _u(0x14000000) // ----------------------------------------------------------------------------- // Field : PIO_SM0_PINCTRL_SIDESET_COUNT -// Description : The number of delay bits co-opted for side-set. Inclusive of -// the enable bit, if present. -#define PIO_SM0_PINCTRL_SIDESET_COUNT_RESET 0x0 -#define PIO_SM0_PINCTRL_SIDESET_COUNT_BITS 0xe0000000 -#define PIO_SM0_PINCTRL_SIDESET_COUNT_MSB 31 -#define PIO_SM0_PINCTRL_SIDESET_COUNT_LSB 29 +// Description : The number of MSBs of the Delay/Side-set instruction field +// which are used for side-set. Inclusive of the enable bit, if +// present. Minimum of 0 (all delay bits, no side-set) and maximum +// of 5 (all side-set, no delay). +#define PIO_SM0_PINCTRL_SIDESET_COUNT_RESET _u(0x0) +#define PIO_SM0_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) +#define PIO_SM0_PINCTRL_SIDESET_COUNT_MSB _u(31) +#define PIO_SM0_PINCTRL_SIDESET_COUNT_LSB _u(29) #define PIO_SM0_PINCTRL_SIDESET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_PINCTRL_SET_COUNT -// Description : The number of pins asserted by a SET. Max of 5 -#define PIO_SM0_PINCTRL_SET_COUNT_RESET 0x5 -#define PIO_SM0_PINCTRL_SET_COUNT_BITS 0x1c000000 -#define PIO_SM0_PINCTRL_SET_COUNT_MSB 28 -#define PIO_SM0_PINCTRL_SET_COUNT_LSB 26 +// Description : The number of pins asserted by a SET. In the range 0 to 5 +// inclusive. +#define PIO_SM0_PINCTRL_SET_COUNT_RESET _u(0x5) +#define PIO_SM0_PINCTRL_SET_COUNT_BITS _u(0x1c000000) +#define PIO_SM0_PINCTRL_SET_COUNT_MSB _u(28) +#define PIO_SM0_PINCTRL_SET_COUNT_LSB _u(26) #define PIO_SM0_PINCTRL_SET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_PINCTRL_OUT_COUNT -// Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins -#define PIO_SM0_PINCTRL_OUT_COUNT_RESET 0x00 -#define PIO_SM0_PINCTRL_OUT_COUNT_BITS 0x03f00000 -#define PIO_SM0_PINCTRL_OUT_COUNT_MSB 25 -#define PIO_SM0_PINCTRL_OUT_COUNT_LSB 20 +// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV +// PINS instruction. In the range 0 to 32 inclusive. +#define PIO_SM0_PINCTRL_OUT_COUNT_RESET _u(0x00) +#define PIO_SM0_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) +#define PIO_SM0_PINCTRL_OUT_COUNT_MSB _u(25) +#define PIO_SM0_PINCTRL_OUT_COUNT_LSB _u(20) #define PIO_SM0_PINCTRL_OUT_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_PINCTRL_IN_BASE -// Description : The virtual pin corresponding to IN bit 0 -#define PIO_SM0_PINCTRL_IN_BASE_RESET 0x00 -#define PIO_SM0_PINCTRL_IN_BASE_BITS 0x000f8000 -#define PIO_SM0_PINCTRL_IN_BASE_MSB 19 -#define PIO_SM0_PINCTRL_IN_BASE_LSB 15 +// Description : The pin which is mapped to the least-significant bit of a state +// machine's IN data bus. Higher-numbered pins are mapped to +// consecutively more-significant data bits, with a modulo of 32 +// applied to pin number. +#define PIO_SM0_PINCTRL_IN_BASE_RESET _u(0x00) +#define PIO_SM0_PINCTRL_IN_BASE_BITS _u(0x000f8000) +#define PIO_SM0_PINCTRL_IN_BASE_MSB _u(19) +#define PIO_SM0_PINCTRL_IN_BASE_LSB _u(15) #define PIO_SM0_PINCTRL_IN_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_PINCTRL_SIDESET_BASE -// Description : The virtual pin corresponding to delay field bit 0 -#define PIO_SM0_PINCTRL_SIDESET_BASE_RESET 0x00 -#define PIO_SM0_PINCTRL_SIDESET_BASE_BITS 0x00007c00 -#define PIO_SM0_PINCTRL_SIDESET_BASE_MSB 14 -#define PIO_SM0_PINCTRL_SIDESET_BASE_LSB 10 +// Description : The lowest-numbered pin that will be affected by a side-set +// operation. The MSBs of an instruction's side-set/delay field +// (up to 5, determined by SIDESET_COUNT) are used for side-set +// data, with the remaining LSBs used for delay. The +// least-significant bit of the side-set portion is the bit +// written to this pin, with more-significant bits written to +// higher-numbered pins. +#define PIO_SM0_PINCTRL_SIDESET_BASE_RESET _u(0x00) +#define PIO_SM0_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) +#define PIO_SM0_PINCTRL_SIDESET_BASE_MSB _u(14) +#define PIO_SM0_PINCTRL_SIDESET_BASE_LSB _u(10) #define PIO_SM0_PINCTRL_SIDESET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_PINCTRL_SET_BASE -// Description : The virtual pin corresponding to SET bit 0 -#define PIO_SM0_PINCTRL_SET_BASE_RESET 0x00 -#define PIO_SM0_PINCTRL_SET_BASE_BITS 0x000003e0 -#define PIO_SM0_PINCTRL_SET_BASE_MSB 9 -#define PIO_SM0_PINCTRL_SET_BASE_LSB 5 +// Description : The lowest-numbered pin that will be affected by a SET PINS or +// SET PINDIRS instruction. The data written to this pin is the +// least-significant bit of the SET data. +#define PIO_SM0_PINCTRL_SET_BASE_RESET _u(0x00) +#define PIO_SM0_PINCTRL_SET_BASE_BITS _u(0x000003e0) +#define PIO_SM0_PINCTRL_SET_BASE_MSB _u(9) +#define PIO_SM0_PINCTRL_SET_BASE_LSB _u(5) #define PIO_SM0_PINCTRL_SET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM0_PINCTRL_OUT_BASE -// Description : The virtual pin corresponding to OUT bit 0 -#define PIO_SM0_PINCTRL_OUT_BASE_RESET 0x00 -#define PIO_SM0_PINCTRL_OUT_BASE_BITS 0x0000001f -#define PIO_SM0_PINCTRL_OUT_BASE_MSB 4 -#define PIO_SM0_PINCTRL_OUT_BASE_LSB 0 +// Description : The lowest-numbered pin that will be affected by an OUT PINS, +// OUT PINDIRS or MOV PINS instruction. The data written to this +// pin will always be the least-significant bit of the OUT or MOV +// data. +#define PIO_SM0_PINCTRL_OUT_BASE_RESET _u(0x00) +#define PIO_SM0_PINCTRL_OUT_BASE_BITS _u(0x0000001f) +#define PIO_SM0_PINCTRL_OUT_BASE_MSB _u(4) +#define PIO_SM0_PINCTRL_OUT_BASE_LSB _u(0) #define PIO_SM0_PINCTRL_OUT_BASE_ACCESS "RW" // ============================================================================= // Register : PIO_SM1_CLKDIV -// Description : Clock divider register for state machine 1 +// Description : Clock divisor register for state machine 1 // Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) -#define PIO_SM1_CLKDIV_OFFSET 0x000000e0 -#define PIO_SM1_CLKDIV_BITS 0xffffff00 -#define PIO_SM1_CLKDIV_RESET 0x00010000 +#define PIO_SM1_CLKDIV_OFFSET _u(0x000000e0) +#define PIO_SM1_CLKDIV_BITS _u(0xffffff00) +#define PIO_SM1_CLKDIV_RESET _u(0x00010000) // ----------------------------------------------------------------------------- // Field : PIO_SM1_CLKDIV_INT -// Description : Effective frequency is sysclk/int. -// Value of 0 is interpreted as max possible value -#define PIO_SM1_CLKDIV_INT_RESET 0x0001 -#define PIO_SM1_CLKDIV_INT_BITS 0xffff0000 -#define PIO_SM1_CLKDIV_INT_MSB 31 -#define PIO_SM1_CLKDIV_INT_LSB 16 +// Description : Effective frequency is sysclk/(int + frac/256). +// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also +// be 0. +#define PIO_SM1_CLKDIV_INT_RESET _u(0x0001) +#define PIO_SM1_CLKDIV_INT_BITS _u(0xffff0000) +#define PIO_SM1_CLKDIV_INT_MSB _u(31) +#define PIO_SM1_CLKDIV_INT_LSB _u(16) #define PIO_SM1_CLKDIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_CLKDIV_FRAC -// Description : Fractional part of clock divider -#define PIO_SM1_CLKDIV_FRAC_RESET 0x00 -#define PIO_SM1_CLKDIV_FRAC_BITS 0x0000ff00 -#define PIO_SM1_CLKDIV_FRAC_MSB 15 -#define PIO_SM1_CLKDIV_FRAC_LSB 8 +// Description : Fractional part of clock divisor +#define PIO_SM1_CLKDIV_FRAC_RESET _u(0x00) +#define PIO_SM1_CLKDIV_FRAC_BITS _u(0x0000ff00) +#define PIO_SM1_CLKDIV_FRAC_MSB _u(15) +#define PIO_SM1_CLKDIV_FRAC_LSB _u(8) #define PIO_SM1_CLKDIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PIO_SM1_EXECCTRL // Description : Execution/behavioural settings for state machine 1 -#define PIO_SM1_EXECCTRL_OFFSET 0x000000e4 -#define PIO_SM1_EXECCTRL_BITS 0xffffff9f -#define PIO_SM1_EXECCTRL_RESET 0x0001f000 +#define PIO_SM1_EXECCTRL_OFFSET _u(0x000000e4) +#define PIO_SM1_EXECCTRL_BITS _u(0xffffff9f) +#define PIO_SM1_EXECCTRL_RESET _u(0x0001f000) // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_EXEC_STALLED -// Description : An instruction written to SMx_INSTR is stalled, and latched by -// the -// state machine. Will clear once the instruction completes. -#define PIO_SM1_EXECCTRL_EXEC_STALLED_RESET 0x0 -#define PIO_SM1_EXECCTRL_EXEC_STALLED_BITS 0x80000000 -#define PIO_SM1_EXECCTRL_EXEC_STALLED_MSB 31 -#define PIO_SM1_EXECCTRL_EXEC_STALLED_LSB 31 +// Description : If 1, an instruction written to SMx_INSTR is stalled, and +// latched by the state machine. Will clear to 0 once this +// instruction completes. +#define PIO_SM1_EXECCTRL_EXEC_STALLED_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) +#define PIO_SM1_EXECCTRL_EXEC_STALLED_MSB _u(31) +#define PIO_SM1_EXECCTRL_EXEC_STALLED_LSB _u(31) #define PIO_SM1_EXECCTRL_EXEC_STALLED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_SIDE_EN -// Description : If 1, the delay MSB is used as side-set enable, rather than a -// side-set data bit. This allows instructions to perform side-set -// optionally, -// rather than on every instruction. -#define PIO_SM1_EXECCTRL_SIDE_EN_RESET 0x0 -#define PIO_SM1_EXECCTRL_SIDE_EN_BITS 0x40000000 -#define PIO_SM1_EXECCTRL_SIDE_EN_MSB 30 -#define PIO_SM1_EXECCTRL_SIDE_EN_LSB 30 +// Description : If 1, the MSB of the Delay/Side-set instruction field is used +// as side-set enable, rather than a side-set data bit. This +// allows instructions to perform side-set optionally, rather than +// on every instruction, but the maximum possible side-set width +// is reduced from 5 to 4. Note that the value of +// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. +#define PIO_SM1_EXECCTRL_SIDE_EN_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_SIDE_EN_BITS _u(0x40000000) +#define PIO_SM1_EXECCTRL_SIDE_EN_MSB _u(30) +#define PIO_SM1_EXECCTRL_SIDE_EN_LSB _u(30) #define PIO_SM1_EXECCTRL_SIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_SIDE_PINDIR -// Description : Side-set data is asserted to pin OEs instead of pin values -#define PIO_SM1_EXECCTRL_SIDE_PINDIR_RESET 0x0 -#define PIO_SM1_EXECCTRL_SIDE_PINDIR_BITS 0x20000000 -#define PIO_SM1_EXECCTRL_SIDE_PINDIR_MSB 29 -#define PIO_SM1_EXECCTRL_SIDE_PINDIR_LSB 29 +// Description : If 1, side-set data is asserted to pin directions, instead of +// pin values +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_MSB _u(29) +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_LSB _u(29) #define PIO_SM1_EXECCTRL_SIDE_PINDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_JMP_PIN // Description : The GPIO number to use as condition for JMP PIN. Unaffected by // input mapping. -#define PIO_SM1_EXECCTRL_JMP_PIN_RESET 0x00 -#define PIO_SM1_EXECCTRL_JMP_PIN_BITS 0x1f000000 -#define PIO_SM1_EXECCTRL_JMP_PIN_MSB 28 -#define PIO_SM1_EXECCTRL_JMP_PIN_LSB 24 +#define PIO_SM1_EXECCTRL_JMP_PIN_RESET _u(0x00) +#define PIO_SM1_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) +#define PIO_SM1_EXECCTRL_JMP_PIN_MSB _u(28) +#define PIO_SM1_EXECCTRL_JMP_PIN_LSB _u(24) #define PIO_SM1_EXECCTRL_JMP_PIN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_OUT_EN_SEL // Description : Which data bit to use for inline OUT enable -#define PIO_SM1_EXECCTRL_OUT_EN_SEL_RESET 0x00 -#define PIO_SM1_EXECCTRL_OUT_EN_SEL_BITS 0x00f80000 -#define PIO_SM1_EXECCTRL_OUT_EN_SEL_MSB 23 -#define PIO_SM1_EXECCTRL_OUT_EN_SEL_LSB 19 +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_MSB _u(23) +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_LSB _u(19) #define PIO_SM1_EXECCTRL_OUT_EN_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_INLINE_OUT_EN @@ -1046,18 +1142,18 @@ // masking/override behaviour // due to the priority ordering of state machine pin writes (SM0 < // SM1 < ...) -#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_RESET 0x0 -#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_BITS 0x00040000 -#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_MSB 18 -#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_LSB 18 +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_MSB _u(18) +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_LSB _u(18) #define PIO_SM1_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_OUT_STICKY // Description : Continuously assert the most recent OUT/SET to the pins -#define PIO_SM1_EXECCTRL_OUT_STICKY_RESET 0x0 -#define PIO_SM1_EXECCTRL_OUT_STICKY_BITS 0x00020000 -#define PIO_SM1_EXECCTRL_OUT_STICKY_MSB 17 -#define PIO_SM1_EXECCTRL_OUT_STICKY_LSB 17 +#define PIO_SM1_EXECCTRL_OUT_STICKY_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) +#define PIO_SM1_EXECCTRL_OUT_STICKY_MSB _u(17) +#define PIO_SM1_EXECCTRL_OUT_STICKY_LSB _u(17) #define PIO_SM1_EXECCTRL_OUT_STICKY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_WRAP_TOP @@ -1065,46 +1161,46 @@ // wrap_bottom. // If the instruction is a jump, and the jump condition is true, // the jump takes priority. -#define PIO_SM1_EXECCTRL_WRAP_TOP_RESET 0x1f -#define PIO_SM1_EXECCTRL_WRAP_TOP_BITS 0x0001f000 -#define PIO_SM1_EXECCTRL_WRAP_TOP_MSB 16 -#define PIO_SM1_EXECCTRL_WRAP_TOP_LSB 12 +#define PIO_SM1_EXECCTRL_WRAP_TOP_RESET _u(0x1f) +#define PIO_SM1_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) +#define PIO_SM1_EXECCTRL_WRAP_TOP_MSB _u(16) +#define PIO_SM1_EXECCTRL_WRAP_TOP_LSB _u(12) #define PIO_SM1_EXECCTRL_WRAP_TOP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_WRAP_BOTTOM // Description : After reaching wrap_top, execution is wrapped to this address. -#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_RESET 0x00 -#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_BITS 0x00000f80 -#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_MSB 11 -#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_LSB 7 +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_MSB _u(11) +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_LSB _u(7) #define PIO_SM1_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_STATUS_SEL // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PIO_SM1_EXECCTRL_STATUS_SEL_RESET 0x0 -#define PIO_SM1_EXECCTRL_STATUS_SEL_BITS 0x00000010 -#define PIO_SM1_EXECCTRL_STATUS_SEL_MSB 4 -#define PIO_SM1_EXECCTRL_STATUS_SEL_LSB 4 +#define PIO_SM1_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) +#define PIO_SM1_EXECCTRL_STATUS_SEL_MSB _u(4) +#define PIO_SM1_EXECCTRL_STATUS_SEL_LSB _u(4) #define PIO_SM1_EXECCTRL_STATUS_SEL_ACCESS "RW" -#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL 0x0 -#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL 0x1 +#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) +#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) // ----------------------------------------------------------------------------- // Field : PIO_SM1_EXECCTRL_STATUS_N // Description : Comparison level for the MOV x, STATUS instruction -#define PIO_SM1_EXECCTRL_STATUS_N_RESET 0x0 -#define PIO_SM1_EXECCTRL_STATUS_N_BITS 0x0000000f -#define PIO_SM1_EXECCTRL_STATUS_N_MSB 3 -#define PIO_SM1_EXECCTRL_STATUS_N_LSB 0 +#define PIO_SM1_EXECCTRL_STATUS_N_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_STATUS_N_BITS _u(0x0000000f) +#define PIO_SM1_EXECCTRL_STATUS_N_MSB _u(3) +#define PIO_SM1_EXECCTRL_STATUS_N_LSB _u(0) #define PIO_SM1_EXECCTRL_STATUS_N_ACCESS "RW" // ============================================================================= // Register : PIO_SM1_SHIFTCTRL // Description : Control behaviour of the input/output shift registers for state // machine 1 -#define PIO_SM1_SHIFTCTRL_OFFSET 0x000000e8 -#define PIO_SM1_SHIFTCTRL_BITS 0xffff0000 -#define PIO_SM1_SHIFTCTRL_RESET 0x000c0000 +#define PIO_SM1_SHIFTCTRL_OFFSET _u(0x000000e8) +#define PIO_SM1_SHIFTCTRL_BITS _u(0xffff0000) +#define PIO_SM1_SHIFTCTRL_RESET _u(0x000c0000) // ----------------------------------------------------------------------------- // Field : PIO_SM1_SHIFTCTRL_FJOIN_RX // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice @@ -1112,10 +1208,10 @@ // TX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_RESET 0x0 -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_BITS 0x80000000 -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_MSB 31 -#define PIO_SM1_SHIFTCTRL_FJOIN_RX_LSB 31 +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_MSB _u(31) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_LSB _u(31) #define PIO_SM1_SHIFTCTRL_FJOIN_RX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_SHIFTCTRL_FJOIN_TX @@ -1124,222 +1220,249 @@ // RX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PIO_SM1_SHIFTCTRL_FJOIN_TX_RESET 0x0 -#define PIO_SM1_SHIFTCTRL_FJOIN_TX_BITS 0x40000000 -#define PIO_SM1_SHIFTCTRL_FJOIN_TX_MSB 30 -#define PIO_SM1_SHIFTCTRL_FJOIN_TX_LSB 30 +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_MSB _u(30) +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_LSB _u(30) #define PIO_SM1_SHIFTCTRL_FJOIN_TX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_SHIFTCTRL_PULL_THRESH -// Description : Number of bits shifted out of TXSR before autopull or -// conditional pull. +// Description : Number of bits shifted out of OSR before autopull, or +// conditional pull (PULL IFEMPTY), will take place. // Write 0 for value of 32. -#define PIO_SM1_SHIFTCTRL_PULL_THRESH_RESET 0x00 -#define PIO_SM1_SHIFTCTRL_PULL_THRESH_BITS 0x3e000000 -#define PIO_SM1_SHIFTCTRL_PULL_THRESH_MSB 29 -#define PIO_SM1_SHIFTCTRL_PULL_THRESH_LSB 25 +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_MSB _u(29) +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_LSB _u(25) #define PIO_SM1_SHIFTCTRL_PULL_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_SHIFTCTRL_PUSH_THRESH -// Description : Number of bits shifted into RXSR before autopush or conditional -// push. +// Description : Number of bits shifted into ISR before autopush, or conditional +// push (PUSH IFFULL), will take place. // Write 0 for value of 32. -#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_RESET 0x00 -#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_BITS 0x01f00000 -#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_MSB 24 -#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_LSB 20 +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_MSB _u(24) +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_LSB _u(20) #define PIO_SM1_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR // Description : 1 = shift out of output shift register to right. 0 = to left. -#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_RESET 0x1 -#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_BITS 0x00080000 -#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_MSB 19 -#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_LSB 19 +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) #define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_SHIFTCTRL_IN_SHIFTDIR // Description : 1 = shift input shift register to right (data enters from // left). 0 = to left. -#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_RESET 0x1 -#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_BITS 0x00040000 -#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_MSB 18 -#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_LSB 18 +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) #define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_SHIFTCTRL_AUTOPULL -// Description : Pull automatically when the output shift register is emptied -#define PIO_SM1_SHIFTCTRL_AUTOPULL_RESET 0x0 -#define PIO_SM1_SHIFTCTRL_AUTOPULL_BITS 0x00020000 -#define PIO_SM1_SHIFTCTRL_AUTOPULL_MSB 17 -#define PIO_SM1_SHIFTCTRL_AUTOPULL_LSB 17 +// Description : Pull automatically when the output shift register is emptied, +// i.e. on or following an OUT instruction which causes the output +// shift counter to reach or exceed PULL_THRESH. +#define PIO_SM1_SHIFTCTRL_AUTOPULL_RESET _u(0x0) +#define PIO_SM1_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) +#define PIO_SM1_SHIFTCTRL_AUTOPULL_MSB _u(17) +#define PIO_SM1_SHIFTCTRL_AUTOPULL_LSB _u(17) #define PIO_SM1_SHIFTCTRL_AUTOPULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_SHIFTCTRL_AUTOPUSH -// Description : Push automatically when the input shift register is filled -#define PIO_SM1_SHIFTCTRL_AUTOPUSH_RESET 0x0 -#define PIO_SM1_SHIFTCTRL_AUTOPUSH_BITS 0x00010000 -#define PIO_SM1_SHIFTCTRL_AUTOPUSH_MSB 16 -#define PIO_SM1_SHIFTCTRL_AUTOPUSH_LSB 16 +// Description : Push automatically when the input shift register is filled, +// i.e. on an IN instruction which causes the input shift counter +// to reach or exceed PUSH_THRESH. +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_MSB _u(16) +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_LSB _u(16) #define PIO_SM1_SHIFTCTRL_AUTOPUSH_ACCESS "RW" // ============================================================================= // Register : PIO_SM1_ADDR // Description : Current instruction address of state machine 1 -#define PIO_SM1_ADDR_OFFSET 0x000000ec -#define PIO_SM1_ADDR_BITS 0x0000001f -#define PIO_SM1_ADDR_RESET 0x00000000 -#define PIO_SM1_ADDR_MSB 4 -#define PIO_SM1_ADDR_LSB 0 +#define PIO_SM1_ADDR_OFFSET _u(0x000000ec) +#define PIO_SM1_ADDR_BITS _u(0x0000001f) +#define PIO_SM1_ADDR_RESET _u(0x00000000) +#define PIO_SM1_ADDR_MSB _u(4) +#define PIO_SM1_ADDR_LSB _u(0) #define PIO_SM1_ADDR_ACCESS "RO" // ============================================================================= // Register : PIO_SM1_INSTR -// Description : Instruction currently being executed by state machine 1 +// Description : Read to see the instruction currently addressed by state +// machine 1's program counter // Write to execute an instruction immediately (including jumps) // and then resume execution. -#define PIO_SM1_INSTR_OFFSET 0x000000f0 -#define PIO_SM1_INSTR_BITS 0x0000ffff +#define PIO_SM1_INSTR_OFFSET _u(0x000000f0) +#define PIO_SM1_INSTR_BITS _u(0x0000ffff) #define PIO_SM1_INSTR_RESET "-" -#define PIO_SM1_INSTR_MSB 15 -#define PIO_SM1_INSTR_LSB 0 +#define PIO_SM1_INSTR_MSB _u(15) +#define PIO_SM1_INSTR_LSB _u(0) #define PIO_SM1_INSTR_ACCESS "RW" // ============================================================================= // Register : PIO_SM1_PINCTRL // Description : State machine pin control -#define PIO_SM1_PINCTRL_OFFSET 0x000000f4 -#define PIO_SM1_PINCTRL_BITS 0xffffffff -#define PIO_SM1_PINCTRL_RESET 0x14000000 +#define PIO_SM1_PINCTRL_OFFSET _u(0x000000f4) +#define PIO_SM1_PINCTRL_BITS _u(0xffffffff) +#define PIO_SM1_PINCTRL_RESET _u(0x14000000) // ----------------------------------------------------------------------------- // Field : PIO_SM1_PINCTRL_SIDESET_COUNT -// Description : The number of delay bits co-opted for side-set. Inclusive of -// the enable bit, if present. -#define PIO_SM1_PINCTRL_SIDESET_COUNT_RESET 0x0 -#define PIO_SM1_PINCTRL_SIDESET_COUNT_BITS 0xe0000000 -#define PIO_SM1_PINCTRL_SIDESET_COUNT_MSB 31 -#define PIO_SM1_PINCTRL_SIDESET_COUNT_LSB 29 +// Description : The number of MSBs of the Delay/Side-set instruction field +// which are used for side-set. Inclusive of the enable bit, if +// present. Minimum of 0 (all delay bits, no side-set) and maximum +// of 5 (all side-set, no delay). +#define PIO_SM1_PINCTRL_SIDESET_COUNT_RESET _u(0x0) +#define PIO_SM1_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) +#define PIO_SM1_PINCTRL_SIDESET_COUNT_MSB _u(31) +#define PIO_SM1_PINCTRL_SIDESET_COUNT_LSB _u(29) #define PIO_SM1_PINCTRL_SIDESET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_PINCTRL_SET_COUNT -// Description : The number of pins asserted by a SET. Max of 5 -#define PIO_SM1_PINCTRL_SET_COUNT_RESET 0x5 -#define PIO_SM1_PINCTRL_SET_COUNT_BITS 0x1c000000 -#define PIO_SM1_PINCTRL_SET_COUNT_MSB 28 -#define PIO_SM1_PINCTRL_SET_COUNT_LSB 26 +// Description : The number of pins asserted by a SET. In the range 0 to 5 +// inclusive. +#define PIO_SM1_PINCTRL_SET_COUNT_RESET _u(0x5) +#define PIO_SM1_PINCTRL_SET_COUNT_BITS _u(0x1c000000) +#define PIO_SM1_PINCTRL_SET_COUNT_MSB _u(28) +#define PIO_SM1_PINCTRL_SET_COUNT_LSB _u(26) #define PIO_SM1_PINCTRL_SET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_PINCTRL_OUT_COUNT -// Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins -#define PIO_SM1_PINCTRL_OUT_COUNT_RESET 0x00 -#define PIO_SM1_PINCTRL_OUT_COUNT_BITS 0x03f00000 -#define PIO_SM1_PINCTRL_OUT_COUNT_MSB 25 -#define PIO_SM1_PINCTRL_OUT_COUNT_LSB 20 +// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV +// PINS instruction. In the range 0 to 32 inclusive. +#define PIO_SM1_PINCTRL_OUT_COUNT_RESET _u(0x00) +#define PIO_SM1_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) +#define PIO_SM1_PINCTRL_OUT_COUNT_MSB _u(25) +#define PIO_SM1_PINCTRL_OUT_COUNT_LSB _u(20) #define PIO_SM1_PINCTRL_OUT_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_PINCTRL_IN_BASE -// Description : The virtual pin corresponding to IN bit 0 -#define PIO_SM1_PINCTRL_IN_BASE_RESET 0x00 -#define PIO_SM1_PINCTRL_IN_BASE_BITS 0x000f8000 -#define PIO_SM1_PINCTRL_IN_BASE_MSB 19 -#define PIO_SM1_PINCTRL_IN_BASE_LSB 15 +// Description : The pin which is mapped to the least-significant bit of a state +// machine's IN data bus. Higher-numbered pins are mapped to +// consecutively more-significant data bits, with a modulo of 32 +// applied to pin number. +#define PIO_SM1_PINCTRL_IN_BASE_RESET _u(0x00) +#define PIO_SM1_PINCTRL_IN_BASE_BITS _u(0x000f8000) +#define PIO_SM1_PINCTRL_IN_BASE_MSB _u(19) +#define PIO_SM1_PINCTRL_IN_BASE_LSB _u(15) #define PIO_SM1_PINCTRL_IN_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_PINCTRL_SIDESET_BASE -// Description : The virtual pin corresponding to delay field bit 0 -#define PIO_SM1_PINCTRL_SIDESET_BASE_RESET 0x00 -#define PIO_SM1_PINCTRL_SIDESET_BASE_BITS 0x00007c00 -#define PIO_SM1_PINCTRL_SIDESET_BASE_MSB 14 -#define PIO_SM1_PINCTRL_SIDESET_BASE_LSB 10 +// Description : The lowest-numbered pin that will be affected by a side-set +// operation. The MSBs of an instruction's side-set/delay field +// (up to 5, determined by SIDESET_COUNT) are used for side-set +// data, with the remaining LSBs used for delay. The +// least-significant bit of the side-set portion is the bit +// written to this pin, with more-significant bits written to +// higher-numbered pins. +#define PIO_SM1_PINCTRL_SIDESET_BASE_RESET _u(0x00) +#define PIO_SM1_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) +#define PIO_SM1_PINCTRL_SIDESET_BASE_MSB _u(14) +#define PIO_SM1_PINCTRL_SIDESET_BASE_LSB _u(10) #define PIO_SM1_PINCTRL_SIDESET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_PINCTRL_SET_BASE -// Description : The virtual pin corresponding to SET bit 0 -#define PIO_SM1_PINCTRL_SET_BASE_RESET 0x00 -#define PIO_SM1_PINCTRL_SET_BASE_BITS 0x000003e0 -#define PIO_SM1_PINCTRL_SET_BASE_MSB 9 -#define PIO_SM1_PINCTRL_SET_BASE_LSB 5 +// Description : The lowest-numbered pin that will be affected by a SET PINS or +// SET PINDIRS instruction. The data written to this pin is the +// least-significant bit of the SET data. +#define PIO_SM1_PINCTRL_SET_BASE_RESET _u(0x00) +#define PIO_SM1_PINCTRL_SET_BASE_BITS _u(0x000003e0) +#define PIO_SM1_PINCTRL_SET_BASE_MSB _u(9) +#define PIO_SM1_PINCTRL_SET_BASE_LSB _u(5) #define PIO_SM1_PINCTRL_SET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM1_PINCTRL_OUT_BASE -// Description : The virtual pin corresponding to OUT bit 0 -#define PIO_SM1_PINCTRL_OUT_BASE_RESET 0x00 -#define PIO_SM1_PINCTRL_OUT_BASE_BITS 0x0000001f -#define PIO_SM1_PINCTRL_OUT_BASE_MSB 4 -#define PIO_SM1_PINCTRL_OUT_BASE_LSB 0 +// Description : The lowest-numbered pin that will be affected by an OUT PINS, +// OUT PINDIRS or MOV PINS instruction. The data written to this +// pin will always be the least-significant bit of the OUT or MOV +// data. +#define PIO_SM1_PINCTRL_OUT_BASE_RESET _u(0x00) +#define PIO_SM1_PINCTRL_OUT_BASE_BITS _u(0x0000001f) +#define PIO_SM1_PINCTRL_OUT_BASE_MSB _u(4) +#define PIO_SM1_PINCTRL_OUT_BASE_LSB _u(0) #define PIO_SM1_PINCTRL_OUT_BASE_ACCESS "RW" // ============================================================================= // Register : PIO_SM2_CLKDIV -// Description : Clock divider register for state machine 2 +// Description : Clock divisor register for state machine 2 // Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) -#define PIO_SM2_CLKDIV_OFFSET 0x000000f8 -#define PIO_SM2_CLKDIV_BITS 0xffffff00 -#define PIO_SM2_CLKDIV_RESET 0x00010000 +#define PIO_SM2_CLKDIV_OFFSET _u(0x000000f8) +#define PIO_SM2_CLKDIV_BITS _u(0xffffff00) +#define PIO_SM2_CLKDIV_RESET _u(0x00010000) // ----------------------------------------------------------------------------- // Field : PIO_SM2_CLKDIV_INT -// Description : Effective frequency is sysclk/int. -// Value of 0 is interpreted as max possible value -#define PIO_SM2_CLKDIV_INT_RESET 0x0001 -#define PIO_SM2_CLKDIV_INT_BITS 0xffff0000 -#define PIO_SM2_CLKDIV_INT_MSB 31 -#define PIO_SM2_CLKDIV_INT_LSB 16 +// Description : Effective frequency is sysclk/(int + frac/256). +// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also +// be 0. +#define PIO_SM2_CLKDIV_INT_RESET _u(0x0001) +#define PIO_SM2_CLKDIV_INT_BITS _u(0xffff0000) +#define PIO_SM2_CLKDIV_INT_MSB _u(31) +#define PIO_SM2_CLKDIV_INT_LSB _u(16) #define PIO_SM2_CLKDIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_CLKDIV_FRAC -// Description : Fractional part of clock divider -#define PIO_SM2_CLKDIV_FRAC_RESET 0x00 -#define PIO_SM2_CLKDIV_FRAC_BITS 0x0000ff00 -#define PIO_SM2_CLKDIV_FRAC_MSB 15 -#define PIO_SM2_CLKDIV_FRAC_LSB 8 +// Description : Fractional part of clock divisor +#define PIO_SM2_CLKDIV_FRAC_RESET _u(0x00) +#define PIO_SM2_CLKDIV_FRAC_BITS _u(0x0000ff00) +#define PIO_SM2_CLKDIV_FRAC_MSB _u(15) +#define PIO_SM2_CLKDIV_FRAC_LSB _u(8) #define PIO_SM2_CLKDIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PIO_SM2_EXECCTRL // Description : Execution/behavioural settings for state machine 2 -#define PIO_SM2_EXECCTRL_OFFSET 0x000000fc -#define PIO_SM2_EXECCTRL_BITS 0xffffff9f -#define PIO_SM2_EXECCTRL_RESET 0x0001f000 +#define PIO_SM2_EXECCTRL_OFFSET _u(0x000000fc) +#define PIO_SM2_EXECCTRL_BITS _u(0xffffff9f) +#define PIO_SM2_EXECCTRL_RESET _u(0x0001f000) // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_EXEC_STALLED -// Description : An instruction written to SMx_INSTR is stalled, and latched by -// the -// state machine. Will clear once the instruction completes. -#define PIO_SM2_EXECCTRL_EXEC_STALLED_RESET 0x0 -#define PIO_SM2_EXECCTRL_EXEC_STALLED_BITS 0x80000000 -#define PIO_SM2_EXECCTRL_EXEC_STALLED_MSB 31 -#define PIO_SM2_EXECCTRL_EXEC_STALLED_LSB 31 +// Description : If 1, an instruction written to SMx_INSTR is stalled, and +// latched by the state machine. Will clear to 0 once this +// instruction completes. +#define PIO_SM2_EXECCTRL_EXEC_STALLED_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) +#define PIO_SM2_EXECCTRL_EXEC_STALLED_MSB _u(31) +#define PIO_SM2_EXECCTRL_EXEC_STALLED_LSB _u(31) #define PIO_SM2_EXECCTRL_EXEC_STALLED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_SIDE_EN -// Description : If 1, the delay MSB is used as side-set enable, rather than a -// side-set data bit. This allows instructions to perform side-set -// optionally, -// rather than on every instruction. -#define PIO_SM2_EXECCTRL_SIDE_EN_RESET 0x0 -#define PIO_SM2_EXECCTRL_SIDE_EN_BITS 0x40000000 -#define PIO_SM2_EXECCTRL_SIDE_EN_MSB 30 -#define PIO_SM2_EXECCTRL_SIDE_EN_LSB 30 +// Description : If 1, the MSB of the Delay/Side-set instruction field is used +// as side-set enable, rather than a side-set data bit. This +// allows instructions to perform side-set optionally, rather than +// on every instruction, but the maximum possible side-set width +// is reduced from 5 to 4. Note that the value of +// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. +#define PIO_SM2_EXECCTRL_SIDE_EN_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_SIDE_EN_BITS _u(0x40000000) +#define PIO_SM2_EXECCTRL_SIDE_EN_MSB _u(30) +#define PIO_SM2_EXECCTRL_SIDE_EN_LSB _u(30) #define PIO_SM2_EXECCTRL_SIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_SIDE_PINDIR -// Description : Side-set data is asserted to pin OEs instead of pin values -#define PIO_SM2_EXECCTRL_SIDE_PINDIR_RESET 0x0 -#define PIO_SM2_EXECCTRL_SIDE_PINDIR_BITS 0x20000000 -#define PIO_SM2_EXECCTRL_SIDE_PINDIR_MSB 29 -#define PIO_SM2_EXECCTRL_SIDE_PINDIR_LSB 29 +// Description : If 1, side-set data is asserted to pin directions, instead of +// pin values +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_MSB _u(29) +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_LSB _u(29) #define PIO_SM2_EXECCTRL_SIDE_PINDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_JMP_PIN // Description : The GPIO number to use as condition for JMP PIN. Unaffected by // input mapping. -#define PIO_SM2_EXECCTRL_JMP_PIN_RESET 0x00 -#define PIO_SM2_EXECCTRL_JMP_PIN_BITS 0x1f000000 -#define PIO_SM2_EXECCTRL_JMP_PIN_MSB 28 -#define PIO_SM2_EXECCTRL_JMP_PIN_LSB 24 +#define PIO_SM2_EXECCTRL_JMP_PIN_RESET _u(0x00) +#define PIO_SM2_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) +#define PIO_SM2_EXECCTRL_JMP_PIN_MSB _u(28) +#define PIO_SM2_EXECCTRL_JMP_PIN_LSB _u(24) #define PIO_SM2_EXECCTRL_JMP_PIN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_OUT_EN_SEL // Description : Which data bit to use for inline OUT enable -#define PIO_SM2_EXECCTRL_OUT_EN_SEL_RESET 0x00 -#define PIO_SM2_EXECCTRL_OUT_EN_SEL_BITS 0x00f80000 -#define PIO_SM2_EXECCTRL_OUT_EN_SEL_MSB 23 -#define PIO_SM2_EXECCTRL_OUT_EN_SEL_LSB 19 +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_MSB _u(23) +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_LSB _u(19) #define PIO_SM2_EXECCTRL_OUT_EN_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_INLINE_OUT_EN @@ -1350,18 +1473,18 @@ // masking/override behaviour // due to the priority ordering of state machine pin writes (SM0 < // SM1 < ...) -#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_RESET 0x0 -#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_BITS 0x00040000 -#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_MSB 18 -#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_LSB 18 +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_MSB _u(18) +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_LSB _u(18) #define PIO_SM2_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_OUT_STICKY // Description : Continuously assert the most recent OUT/SET to the pins -#define PIO_SM2_EXECCTRL_OUT_STICKY_RESET 0x0 -#define PIO_SM2_EXECCTRL_OUT_STICKY_BITS 0x00020000 -#define PIO_SM2_EXECCTRL_OUT_STICKY_MSB 17 -#define PIO_SM2_EXECCTRL_OUT_STICKY_LSB 17 +#define PIO_SM2_EXECCTRL_OUT_STICKY_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) +#define PIO_SM2_EXECCTRL_OUT_STICKY_MSB _u(17) +#define PIO_SM2_EXECCTRL_OUT_STICKY_LSB _u(17) #define PIO_SM2_EXECCTRL_OUT_STICKY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_WRAP_TOP @@ -1369,46 +1492,46 @@ // wrap_bottom. // If the instruction is a jump, and the jump condition is true, // the jump takes priority. -#define PIO_SM2_EXECCTRL_WRAP_TOP_RESET 0x1f -#define PIO_SM2_EXECCTRL_WRAP_TOP_BITS 0x0001f000 -#define PIO_SM2_EXECCTRL_WRAP_TOP_MSB 16 -#define PIO_SM2_EXECCTRL_WRAP_TOP_LSB 12 +#define PIO_SM2_EXECCTRL_WRAP_TOP_RESET _u(0x1f) +#define PIO_SM2_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) +#define PIO_SM2_EXECCTRL_WRAP_TOP_MSB _u(16) +#define PIO_SM2_EXECCTRL_WRAP_TOP_LSB _u(12) #define PIO_SM2_EXECCTRL_WRAP_TOP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_WRAP_BOTTOM // Description : After reaching wrap_top, execution is wrapped to this address. -#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_RESET 0x00 -#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_BITS 0x00000f80 -#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_MSB 11 -#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_LSB 7 +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_MSB _u(11) +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_LSB _u(7) #define PIO_SM2_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_STATUS_SEL // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PIO_SM2_EXECCTRL_STATUS_SEL_RESET 0x0 -#define PIO_SM2_EXECCTRL_STATUS_SEL_BITS 0x00000010 -#define PIO_SM2_EXECCTRL_STATUS_SEL_MSB 4 -#define PIO_SM2_EXECCTRL_STATUS_SEL_LSB 4 +#define PIO_SM2_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) +#define PIO_SM2_EXECCTRL_STATUS_SEL_MSB _u(4) +#define PIO_SM2_EXECCTRL_STATUS_SEL_LSB _u(4) #define PIO_SM2_EXECCTRL_STATUS_SEL_ACCESS "RW" -#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL 0x0 -#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL 0x1 +#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) +#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) // ----------------------------------------------------------------------------- // Field : PIO_SM2_EXECCTRL_STATUS_N // Description : Comparison level for the MOV x, STATUS instruction -#define PIO_SM2_EXECCTRL_STATUS_N_RESET 0x0 -#define PIO_SM2_EXECCTRL_STATUS_N_BITS 0x0000000f -#define PIO_SM2_EXECCTRL_STATUS_N_MSB 3 -#define PIO_SM2_EXECCTRL_STATUS_N_LSB 0 +#define PIO_SM2_EXECCTRL_STATUS_N_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_STATUS_N_BITS _u(0x0000000f) +#define PIO_SM2_EXECCTRL_STATUS_N_MSB _u(3) +#define PIO_SM2_EXECCTRL_STATUS_N_LSB _u(0) #define PIO_SM2_EXECCTRL_STATUS_N_ACCESS "RW" // ============================================================================= // Register : PIO_SM2_SHIFTCTRL // Description : Control behaviour of the input/output shift registers for state // machine 2 -#define PIO_SM2_SHIFTCTRL_OFFSET 0x00000100 -#define PIO_SM2_SHIFTCTRL_BITS 0xffff0000 -#define PIO_SM2_SHIFTCTRL_RESET 0x000c0000 +#define PIO_SM2_SHIFTCTRL_OFFSET _u(0x00000100) +#define PIO_SM2_SHIFTCTRL_BITS _u(0xffff0000) +#define PIO_SM2_SHIFTCTRL_RESET _u(0x000c0000) // ----------------------------------------------------------------------------- // Field : PIO_SM2_SHIFTCTRL_FJOIN_RX // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice @@ -1416,10 +1539,10 @@ // TX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_RESET 0x0 -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_BITS 0x80000000 -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_MSB 31 -#define PIO_SM2_SHIFTCTRL_FJOIN_RX_LSB 31 +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_MSB _u(31) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_LSB _u(31) #define PIO_SM2_SHIFTCTRL_FJOIN_RX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_SHIFTCTRL_FJOIN_TX @@ -1428,222 +1551,249 @@ // RX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PIO_SM2_SHIFTCTRL_FJOIN_TX_RESET 0x0 -#define PIO_SM2_SHIFTCTRL_FJOIN_TX_BITS 0x40000000 -#define PIO_SM2_SHIFTCTRL_FJOIN_TX_MSB 30 -#define PIO_SM2_SHIFTCTRL_FJOIN_TX_LSB 30 +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_MSB _u(30) +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_LSB _u(30) #define PIO_SM2_SHIFTCTRL_FJOIN_TX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_SHIFTCTRL_PULL_THRESH -// Description : Number of bits shifted out of TXSR before autopull or -// conditional pull. +// Description : Number of bits shifted out of OSR before autopull, or +// conditional pull (PULL IFEMPTY), will take place. // Write 0 for value of 32. -#define PIO_SM2_SHIFTCTRL_PULL_THRESH_RESET 0x00 -#define PIO_SM2_SHIFTCTRL_PULL_THRESH_BITS 0x3e000000 -#define PIO_SM2_SHIFTCTRL_PULL_THRESH_MSB 29 -#define PIO_SM2_SHIFTCTRL_PULL_THRESH_LSB 25 +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_MSB _u(29) +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_LSB _u(25) #define PIO_SM2_SHIFTCTRL_PULL_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_SHIFTCTRL_PUSH_THRESH -// Description : Number of bits shifted into RXSR before autopush or conditional -// push. +// Description : Number of bits shifted into ISR before autopush, or conditional +// push (PUSH IFFULL), will take place. // Write 0 for value of 32. -#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_RESET 0x00 -#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_BITS 0x01f00000 -#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_MSB 24 -#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_LSB 20 +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_MSB _u(24) +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_LSB _u(20) #define PIO_SM2_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR // Description : 1 = shift out of output shift register to right. 0 = to left. -#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_RESET 0x1 -#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_BITS 0x00080000 -#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_MSB 19 -#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_LSB 19 +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) #define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_SHIFTCTRL_IN_SHIFTDIR // Description : 1 = shift input shift register to right (data enters from // left). 0 = to left. -#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_RESET 0x1 -#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_BITS 0x00040000 -#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_MSB 18 -#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_LSB 18 +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) #define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_SHIFTCTRL_AUTOPULL -// Description : Pull automatically when the output shift register is emptied -#define PIO_SM2_SHIFTCTRL_AUTOPULL_RESET 0x0 -#define PIO_SM2_SHIFTCTRL_AUTOPULL_BITS 0x00020000 -#define PIO_SM2_SHIFTCTRL_AUTOPULL_MSB 17 -#define PIO_SM2_SHIFTCTRL_AUTOPULL_LSB 17 +// Description : Pull automatically when the output shift register is emptied, +// i.e. on or following an OUT instruction which causes the output +// shift counter to reach or exceed PULL_THRESH. +#define PIO_SM2_SHIFTCTRL_AUTOPULL_RESET _u(0x0) +#define PIO_SM2_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) +#define PIO_SM2_SHIFTCTRL_AUTOPULL_MSB _u(17) +#define PIO_SM2_SHIFTCTRL_AUTOPULL_LSB _u(17) #define PIO_SM2_SHIFTCTRL_AUTOPULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_SHIFTCTRL_AUTOPUSH -// Description : Push automatically when the input shift register is filled -#define PIO_SM2_SHIFTCTRL_AUTOPUSH_RESET 0x0 -#define PIO_SM2_SHIFTCTRL_AUTOPUSH_BITS 0x00010000 -#define PIO_SM2_SHIFTCTRL_AUTOPUSH_MSB 16 -#define PIO_SM2_SHIFTCTRL_AUTOPUSH_LSB 16 +// Description : Push automatically when the input shift register is filled, +// i.e. on an IN instruction which causes the input shift counter +// to reach or exceed PUSH_THRESH. +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_MSB _u(16) +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_LSB _u(16) #define PIO_SM2_SHIFTCTRL_AUTOPUSH_ACCESS "RW" // ============================================================================= // Register : PIO_SM2_ADDR // Description : Current instruction address of state machine 2 -#define PIO_SM2_ADDR_OFFSET 0x00000104 -#define PIO_SM2_ADDR_BITS 0x0000001f -#define PIO_SM2_ADDR_RESET 0x00000000 -#define PIO_SM2_ADDR_MSB 4 -#define PIO_SM2_ADDR_LSB 0 +#define PIO_SM2_ADDR_OFFSET _u(0x00000104) +#define PIO_SM2_ADDR_BITS _u(0x0000001f) +#define PIO_SM2_ADDR_RESET _u(0x00000000) +#define PIO_SM2_ADDR_MSB _u(4) +#define PIO_SM2_ADDR_LSB _u(0) #define PIO_SM2_ADDR_ACCESS "RO" // ============================================================================= // Register : PIO_SM2_INSTR -// Description : Instruction currently being executed by state machine 2 +// Description : Read to see the instruction currently addressed by state +// machine 2's program counter // Write to execute an instruction immediately (including jumps) // and then resume execution. -#define PIO_SM2_INSTR_OFFSET 0x00000108 -#define PIO_SM2_INSTR_BITS 0x0000ffff +#define PIO_SM2_INSTR_OFFSET _u(0x00000108) +#define PIO_SM2_INSTR_BITS _u(0x0000ffff) #define PIO_SM2_INSTR_RESET "-" -#define PIO_SM2_INSTR_MSB 15 -#define PIO_SM2_INSTR_LSB 0 +#define PIO_SM2_INSTR_MSB _u(15) +#define PIO_SM2_INSTR_LSB _u(0) #define PIO_SM2_INSTR_ACCESS "RW" // ============================================================================= // Register : PIO_SM2_PINCTRL // Description : State machine pin control -#define PIO_SM2_PINCTRL_OFFSET 0x0000010c -#define PIO_SM2_PINCTRL_BITS 0xffffffff -#define PIO_SM2_PINCTRL_RESET 0x14000000 +#define PIO_SM2_PINCTRL_OFFSET _u(0x0000010c) +#define PIO_SM2_PINCTRL_BITS _u(0xffffffff) +#define PIO_SM2_PINCTRL_RESET _u(0x14000000) // ----------------------------------------------------------------------------- // Field : PIO_SM2_PINCTRL_SIDESET_COUNT -// Description : The number of delay bits co-opted for side-set. Inclusive of -// the enable bit, if present. -#define PIO_SM2_PINCTRL_SIDESET_COUNT_RESET 0x0 -#define PIO_SM2_PINCTRL_SIDESET_COUNT_BITS 0xe0000000 -#define PIO_SM2_PINCTRL_SIDESET_COUNT_MSB 31 -#define PIO_SM2_PINCTRL_SIDESET_COUNT_LSB 29 +// Description : The number of MSBs of the Delay/Side-set instruction field +// which are used for side-set. Inclusive of the enable bit, if +// present. Minimum of 0 (all delay bits, no side-set) and maximum +// of 5 (all side-set, no delay). +#define PIO_SM2_PINCTRL_SIDESET_COUNT_RESET _u(0x0) +#define PIO_SM2_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) +#define PIO_SM2_PINCTRL_SIDESET_COUNT_MSB _u(31) +#define PIO_SM2_PINCTRL_SIDESET_COUNT_LSB _u(29) #define PIO_SM2_PINCTRL_SIDESET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_PINCTRL_SET_COUNT -// Description : The number of pins asserted by a SET. Max of 5 -#define PIO_SM2_PINCTRL_SET_COUNT_RESET 0x5 -#define PIO_SM2_PINCTRL_SET_COUNT_BITS 0x1c000000 -#define PIO_SM2_PINCTRL_SET_COUNT_MSB 28 -#define PIO_SM2_PINCTRL_SET_COUNT_LSB 26 +// Description : The number of pins asserted by a SET. In the range 0 to 5 +// inclusive. +#define PIO_SM2_PINCTRL_SET_COUNT_RESET _u(0x5) +#define PIO_SM2_PINCTRL_SET_COUNT_BITS _u(0x1c000000) +#define PIO_SM2_PINCTRL_SET_COUNT_MSB _u(28) +#define PIO_SM2_PINCTRL_SET_COUNT_LSB _u(26) #define PIO_SM2_PINCTRL_SET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_PINCTRL_OUT_COUNT -// Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins -#define PIO_SM2_PINCTRL_OUT_COUNT_RESET 0x00 -#define PIO_SM2_PINCTRL_OUT_COUNT_BITS 0x03f00000 -#define PIO_SM2_PINCTRL_OUT_COUNT_MSB 25 -#define PIO_SM2_PINCTRL_OUT_COUNT_LSB 20 +// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV +// PINS instruction. In the range 0 to 32 inclusive. +#define PIO_SM2_PINCTRL_OUT_COUNT_RESET _u(0x00) +#define PIO_SM2_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) +#define PIO_SM2_PINCTRL_OUT_COUNT_MSB _u(25) +#define PIO_SM2_PINCTRL_OUT_COUNT_LSB _u(20) #define PIO_SM2_PINCTRL_OUT_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_PINCTRL_IN_BASE -// Description : The virtual pin corresponding to IN bit 0 -#define PIO_SM2_PINCTRL_IN_BASE_RESET 0x00 -#define PIO_SM2_PINCTRL_IN_BASE_BITS 0x000f8000 -#define PIO_SM2_PINCTRL_IN_BASE_MSB 19 -#define PIO_SM2_PINCTRL_IN_BASE_LSB 15 +// Description : The pin which is mapped to the least-significant bit of a state +// machine's IN data bus. Higher-numbered pins are mapped to +// consecutively more-significant data bits, with a modulo of 32 +// applied to pin number. +#define PIO_SM2_PINCTRL_IN_BASE_RESET _u(0x00) +#define PIO_SM2_PINCTRL_IN_BASE_BITS _u(0x000f8000) +#define PIO_SM2_PINCTRL_IN_BASE_MSB _u(19) +#define PIO_SM2_PINCTRL_IN_BASE_LSB _u(15) #define PIO_SM2_PINCTRL_IN_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_PINCTRL_SIDESET_BASE -// Description : The virtual pin corresponding to delay field bit 0 -#define PIO_SM2_PINCTRL_SIDESET_BASE_RESET 0x00 -#define PIO_SM2_PINCTRL_SIDESET_BASE_BITS 0x00007c00 -#define PIO_SM2_PINCTRL_SIDESET_BASE_MSB 14 -#define PIO_SM2_PINCTRL_SIDESET_BASE_LSB 10 +// Description : The lowest-numbered pin that will be affected by a side-set +// operation. The MSBs of an instruction's side-set/delay field +// (up to 5, determined by SIDESET_COUNT) are used for side-set +// data, with the remaining LSBs used for delay. The +// least-significant bit of the side-set portion is the bit +// written to this pin, with more-significant bits written to +// higher-numbered pins. +#define PIO_SM2_PINCTRL_SIDESET_BASE_RESET _u(0x00) +#define PIO_SM2_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) +#define PIO_SM2_PINCTRL_SIDESET_BASE_MSB _u(14) +#define PIO_SM2_PINCTRL_SIDESET_BASE_LSB _u(10) #define PIO_SM2_PINCTRL_SIDESET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_PINCTRL_SET_BASE -// Description : The virtual pin corresponding to SET bit 0 -#define PIO_SM2_PINCTRL_SET_BASE_RESET 0x00 -#define PIO_SM2_PINCTRL_SET_BASE_BITS 0x000003e0 -#define PIO_SM2_PINCTRL_SET_BASE_MSB 9 -#define PIO_SM2_PINCTRL_SET_BASE_LSB 5 +// Description : The lowest-numbered pin that will be affected by a SET PINS or +// SET PINDIRS instruction. The data written to this pin is the +// least-significant bit of the SET data. +#define PIO_SM2_PINCTRL_SET_BASE_RESET _u(0x00) +#define PIO_SM2_PINCTRL_SET_BASE_BITS _u(0x000003e0) +#define PIO_SM2_PINCTRL_SET_BASE_MSB _u(9) +#define PIO_SM2_PINCTRL_SET_BASE_LSB _u(5) #define PIO_SM2_PINCTRL_SET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM2_PINCTRL_OUT_BASE -// Description : The virtual pin corresponding to OUT bit 0 -#define PIO_SM2_PINCTRL_OUT_BASE_RESET 0x00 -#define PIO_SM2_PINCTRL_OUT_BASE_BITS 0x0000001f -#define PIO_SM2_PINCTRL_OUT_BASE_MSB 4 -#define PIO_SM2_PINCTRL_OUT_BASE_LSB 0 +// Description : The lowest-numbered pin that will be affected by an OUT PINS, +// OUT PINDIRS or MOV PINS instruction. The data written to this +// pin will always be the least-significant bit of the OUT or MOV +// data. +#define PIO_SM2_PINCTRL_OUT_BASE_RESET _u(0x00) +#define PIO_SM2_PINCTRL_OUT_BASE_BITS _u(0x0000001f) +#define PIO_SM2_PINCTRL_OUT_BASE_MSB _u(4) +#define PIO_SM2_PINCTRL_OUT_BASE_LSB _u(0) #define PIO_SM2_PINCTRL_OUT_BASE_ACCESS "RW" // ============================================================================= // Register : PIO_SM3_CLKDIV -// Description : Clock divider register for state machine 3 +// Description : Clock divisor register for state machine 3 // Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) -#define PIO_SM3_CLKDIV_OFFSET 0x00000110 -#define PIO_SM3_CLKDIV_BITS 0xffffff00 -#define PIO_SM3_CLKDIV_RESET 0x00010000 +#define PIO_SM3_CLKDIV_OFFSET _u(0x00000110) +#define PIO_SM3_CLKDIV_BITS _u(0xffffff00) +#define PIO_SM3_CLKDIV_RESET _u(0x00010000) // ----------------------------------------------------------------------------- // Field : PIO_SM3_CLKDIV_INT -// Description : Effective frequency is sysclk/int. -// Value of 0 is interpreted as max possible value -#define PIO_SM3_CLKDIV_INT_RESET 0x0001 -#define PIO_SM3_CLKDIV_INT_BITS 0xffff0000 -#define PIO_SM3_CLKDIV_INT_MSB 31 -#define PIO_SM3_CLKDIV_INT_LSB 16 +// Description : Effective frequency is sysclk/(int + frac/256). +// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also +// be 0. +#define PIO_SM3_CLKDIV_INT_RESET _u(0x0001) +#define PIO_SM3_CLKDIV_INT_BITS _u(0xffff0000) +#define PIO_SM3_CLKDIV_INT_MSB _u(31) +#define PIO_SM3_CLKDIV_INT_LSB _u(16) #define PIO_SM3_CLKDIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_CLKDIV_FRAC -// Description : Fractional part of clock divider -#define PIO_SM3_CLKDIV_FRAC_RESET 0x00 -#define PIO_SM3_CLKDIV_FRAC_BITS 0x0000ff00 -#define PIO_SM3_CLKDIV_FRAC_MSB 15 -#define PIO_SM3_CLKDIV_FRAC_LSB 8 +// Description : Fractional part of clock divisor +#define PIO_SM3_CLKDIV_FRAC_RESET _u(0x00) +#define PIO_SM3_CLKDIV_FRAC_BITS _u(0x0000ff00) +#define PIO_SM3_CLKDIV_FRAC_MSB _u(15) +#define PIO_SM3_CLKDIV_FRAC_LSB _u(8) #define PIO_SM3_CLKDIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PIO_SM3_EXECCTRL // Description : Execution/behavioural settings for state machine 3 -#define PIO_SM3_EXECCTRL_OFFSET 0x00000114 -#define PIO_SM3_EXECCTRL_BITS 0xffffff9f -#define PIO_SM3_EXECCTRL_RESET 0x0001f000 +#define PIO_SM3_EXECCTRL_OFFSET _u(0x00000114) +#define PIO_SM3_EXECCTRL_BITS _u(0xffffff9f) +#define PIO_SM3_EXECCTRL_RESET _u(0x0001f000) // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_EXEC_STALLED -// Description : An instruction written to SMx_INSTR is stalled, and latched by -// the -// state machine. Will clear once the instruction completes. -#define PIO_SM3_EXECCTRL_EXEC_STALLED_RESET 0x0 -#define PIO_SM3_EXECCTRL_EXEC_STALLED_BITS 0x80000000 -#define PIO_SM3_EXECCTRL_EXEC_STALLED_MSB 31 -#define PIO_SM3_EXECCTRL_EXEC_STALLED_LSB 31 +// Description : If 1, an instruction written to SMx_INSTR is stalled, and +// latched by the state machine. Will clear to 0 once this +// instruction completes. +#define PIO_SM3_EXECCTRL_EXEC_STALLED_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) +#define PIO_SM3_EXECCTRL_EXEC_STALLED_MSB _u(31) +#define PIO_SM3_EXECCTRL_EXEC_STALLED_LSB _u(31) #define PIO_SM3_EXECCTRL_EXEC_STALLED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_SIDE_EN -// Description : If 1, the delay MSB is used as side-set enable, rather than a -// side-set data bit. This allows instructions to perform side-set -// optionally, -// rather than on every instruction. -#define PIO_SM3_EXECCTRL_SIDE_EN_RESET 0x0 -#define PIO_SM3_EXECCTRL_SIDE_EN_BITS 0x40000000 -#define PIO_SM3_EXECCTRL_SIDE_EN_MSB 30 -#define PIO_SM3_EXECCTRL_SIDE_EN_LSB 30 +// Description : If 1, the MSB of the Delay/Side-set instruction field is used +// as side-set enable, rather than a side-set data bit. This +// allows instructions to perform side-set optionally, rather than +// on every instruction, but the maximum possible side-set width +// is reduced from 5 to 4. Note that the value of +// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. +#define PIO_SM3_EXECCTRL_SIDE_EN_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_SIDE_EN_BITS _u(0x40000000) +#define PIO_SM3_EXECCTRL_SIDE_EN_MSB _u(30) +#define PIO_SM3_EXECCTRL_SIDE_EN_LSB _u(30) #define PIO_SM3_EXECCTRL_SIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_SIDE_PINDIR -// Description : Side-set data is asserted to pin OEs instead of pin values -#define PIO_SM3_EXECCTRL_SIDE_PINDIR_RESET 0x0 -#define PIO_SM3_EXECCTRL_SIDE_PINDIR_BITS 0x20000000 -#define PIO_SM3_EXECCTRL_SIDE_PINDIR_MSB 29 -#define PIO_SM3_EXECCTRL_SIDE_PINDIR_LSB 29 +// Description : If 1, side-set data is asserted to pin directions, instead of +// pin values +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_MSB _u(29) +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_LSB _u(29) #define PIO_SM3_EXECCTRL_SIDE_PINDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_JMP_PIN // Description : The GPIO number to use as condition for JMP PIN. Unaffected by // input mapping. -#define PIO_SM3_EXECCTRL_JMP_PIN_RESET 0x00 -#define PIO_SM3_EXECCTRL_JMP_PIN_BITS 0x1f000000 -#define PIO_SM3_EXECCTRL_JMP_PIN_MSB 28 -#define PIO_SM3_EXECCTRL_JMP_PIN_LSB 24 +#define PIO_SM3_EXECCTRL_JMP_PIN_RESET _u(0x00) +#define PIO_SM3_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) +#define PIO_SM3_EXECCTRL_JMP_PIN_MSB _u(28) +#define PIO_SM3_EXECCTRL_JMP_PIN_LSB _u(24) #define PIO_SM3_EXECCTRL_JMP_PIN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_OUT_EN_SEL // Description : Which data bit to use for inline OUT enable -#define PIO_SM3_EXECCTRL_OUT_EN_SEL_RESET 0x00 -#define PIO_SM3_EXECCTRL_OUT_EN_SEL_BITS 0x00f80000 -#define PIO_SM3_EXECCTRL_OUT_EN_SEL_MSB 23 -#define PIO_SM3_EXECCTRL_OUT_EN_SEL_LSB 19 +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_MSB _u(23) +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_LSB _u(19) #define PIO_SM3_EXECCTRL_OUT_EN_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_INLINE_OUT_EN @@ -1654,18 +1804,18 @@ // masking/override behaviour // due to the priority ordering of state machine pin writes (SM0 < // SM1 < ...) -#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_RESET 0x0 -#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_BITS 0x00040000 -#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_MSB 18 -#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_LSB 18 +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_MSB _u(18) +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_LSB _u(18) #define PIO_SM3_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_OUT_STICKY // Description : Continuously assert the most recent OUT/SET to the pins -#define PIO_SM3_EXECCTRL_OUT_STICKY_RESET 0x0 -#define PIO_SM3_EXECCTRL_OUT_STICKY_BITS 0x00020000 -#define PIO_SM3_EXECCTRL_OUT_STICKY_MSB 17 -#define PIO_SM3_EXECCTRL_OUT_STICKY_LSB 17 +#define PIO_SM3_EXECCTRL_OUT_STICKY_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) +#define PIO_SM3_EXECCTRL_OUT_STICKY_MSB _u(17) +#define PIO_SM3_EXECCTRL_OUT_STICKY_LSB _u(17) #define PIO_SM3_EXECCTRL_OUT_STICKY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_WRAP_TOP @@ -1673,46 +1823,46 @@ // wrap_bottom. // If the instruction is a jump, and the jump condition is true, // the jump takes priority. -#define PIO_SM3_EXECCTRL_WRAP_TOP_RESET 0x1f -#define PIO_SM3_EXECCTRL_WRAP_TOP_BITS 0x0001f000 -#define PIO_SM3_EXECCTRL_WRAP_TOP_MSB 16 -#define PIO_SM3_EXECCTRL_WRAP_TOP_LSB 12 +#define PIO_SM3_EXECCTRL_WRAP_TOP_RESET _u(0x1f) +#define PIO_SM3_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) +#define PIO_SM3_EXECCTRL_WRAP_TOP_MSB _u(16) +#define PIO_SM3_EXECCTRL_WRAP_TOP_LSB _u(12) #define PIO_SM3_EXECCTRL_WRAP_TOP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_WRAP_BOTTOM // Description : After reaching wrap_top, execution is wrapped to this address. -#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_RESET 0x00 -#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_BITS 0x00000f80 -#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_MSB 11 -#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_LSB 7 +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_MSB _u(11) +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_LSB _u(7) #define PIO_SM3_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_STATUS_SEL // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PIO_SM3_EXECCTRL_STATUS_SEL_RESET 0x0 -#define PIO_SM3_EXECCTRL_STATUS_SEL_BITS 0x00000010 -#define PIO_SM3_EXECCTRL_STATUS_SEL_MSB 4 -#define PIO_SM3_EXECCTRL_STATUS_SEL_LSB 4 +#define PIO_SM3_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) +#define PIO_SM3_EXECCTRL_STATUS_SEL_MSB _u(4) +#define PIO_SM3_EXECCTRL_STATUS_SEL_LSB _u(4) #define PIO_SM3_EXECCTRL_STATUS_SEL_ACCESS "RW" -#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL 0x0 -#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL 0x1 +#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) +#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) // ----------------------------------------------------------------------------- // Field : PIO_SM3_EXECCTRL_STATUS_N // Description : Comparison level for the MOV x, STATUS instruction -#define PIO_SM3_EXECCTRL_STATUS_N_RESET 0x0 -#define PIO_SM3_EXECCTRL_STATUS_N_BITS 0x0000000f -#define PIO_SM3_EXECCTRL_STATUS_N_MSB 3 -#define PIO_SM3_EXECCTRL_STATUS_N_LSB 0 +#define PIO_SM3_EXECCTRL_STATUS_N_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_STATUS_N_BITS _u(0x0000000f) +#define PIO_SM3_EXECCTRL_STATUS_N_MSB _u(3) +#define PIO_SM3_EXECCTRL_STATUS_N_LSB _u(0) #define PIO_SM3_EXECCTRL_STATUS_N_ACCESS "RW" // ============================================================================= // Register : PIO_SM3_SHIFTCTRL // Description : Control behaviour of the input/output shift registers for state // machine 3 -#define PIO_SM3_SHIFTCTRL_OFFSET 0x00000118 -#define PIO_SM3_SHIFTCTRL_BITS 0xffff0000 -#define PIO_SM3_SHIFTCTRL_RESET 0x000c0000 +#define PIO_SM3_SHIFTCTRL_OFFSET _u(0x00000118) +#define PIO_SM3_SHIFTCTRL_BITS _u(0xffff0000) +#define PIO_SM3_SHIFTCTRL_RESET _u(0x000c0000) // ----------------------------------------------------------------------------- // Field : PIO_SM3_SHIFTCTRL_FJOIN_RX // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice @@ -1720,10 +1870,10 @@ // TX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_RESET 0x0 -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_BITS 0x80000000 -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_MSB 31 -#define PIO_SM3_SHIFTCTRL_FJOIN_RX_LSB 31 +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_MSB _u(31) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_LSB _u(31) #define PIO_SM3_SHIFTCTRL_FJOIN_RX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_SHIFTCTRL_FJOIN_TX @@ -1732,860 +1882,883 @@ // RX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PIO_SM3_SHIFTCTRL_FJOIN_TX_RESET 0x0 -#define PIO_SM3_SHIFTCTRL_FJOIN_TX_BITS 0x40000000 -#define PIO_SM3_SHIFTCTRL_FJOIN_TX_MSB 30 -#define PIO_SM3_SHIFTCTRL_FJOIN_TX_LSB 30 +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_MSB _u(30) +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_LSB _u(30) #define PIO_SM3_SHIFTCTRL_FJOIN_TX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_SHIFTCTRL_PULL_THRESH -// Description : Number of bits shifted out of TXSR before autopull or -// conditional pull. +// Description : Number of bits shifted out of OSR before autopull, or +// conditional pull (PULL IFEMPTY), will take place. // Write 0 for value of 32. -#define PIO_SM3_SHIFTCTRL_PULL_THRESH_RESET 0x00 -#define PIO_SM3_SHIFTCTRL_PULL_THRESH_BITS 0x3e000000 -#define PIO_SM3_SHIFTCTRL_PULL_THRESH_MSB 29 -#define PIO_SM3_SHIFTCTRL_PULL_THRESH_LSB 25 +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_MSB _u(29) +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_LSB _u(25) #define PIO_SM3_SHIFTCTRL_PULL_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_SHIFTCTRL_PUSH_THRESH -// Description : Number of bits shifted into RXSR before autopush or conditional -// push. +// Description : Number of bits shifted into ISR before autopush, or conditional +// push (PUSH IFFULL), will take place. // Write 0 for value of 32. -#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_RESET 0x00 -#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_BITS 0x01f00000 -#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_MSB 24 -#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_LSB 20 +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_MSB _u(24) +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_LSB _u(20) #define PIO_SM3_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR // Description : 1 = shift out of output shift register to right. 0 = to left. -#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_RESET 0x1 -#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_BITS 0x00080000 -#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_MSB 19 -#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_LSB 19 +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) #define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_SHIFTCTRL_IN_SHIFTDIR // Description : 1 = shift input shift register to right (data enters from // left). 0 = to left. -#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_RESET 0x1 -#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_BITS 0x00040000 -#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_MSB 18 -#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_LSB 18 +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) #define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_SHIFTCTRL_AUTOPULL -// Description : Pull automatically when the output shift register is emptied -#define PIO_SM3_SHIFTCTRL_AUTOPULL_RESET 0x0 -#define PIO_SM3_SHIFTCTRL_AUTOPULL_BITS 0x00020000 -#define PIO_SM3_SHIFTCTRL_AUTOPULL_MSB 17 -#define PIO_SM3_SHIFTCTRL_AUTOPULL_LSB 17 +// Description : Pull automatically when the output shift register is emptied, +// i.e. on or following an OUT instruction which causes the output +// shift counter to reach or exceed PULL_THRESH. +#define PIO_SM3_SHIFTCTRL_AUTOPULL_RESET _u(0x0) +#define PIO_SM3_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) +#define PIO_SM3_SHIFTCTRL_AUTOPULL_MSB _u(17) +#define PIO_SM3_SHIFTCTRL_AUTOPULL_LSB _u(17) #define PIO_SM3_SHIFTCTRL_AUTOPULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_SHIFTCTRL_AUTOPUSH -// Description : Push automatically when the input shift register is filled -#define PIO_SM3_SHIFTCTRL_AUTOPUSH_RESET 0x0 -#define PIO_SM3_SHIFTCTRL_AUTOPUSH_BITS 0x00010000 -#define PIO_SM3_SHIFTCTRL_AUTOPUSH_MSB 16 -#define PIO_SM3_SHIFTCTRL_AUTOPUSH_LSB 16 +// Description : Push automatically when the input shift register is filled, +// i.e. on an IN instruction which causes the input shift counter +// to reach or exceed PUSH_THRESH. +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_MSB _u(16) +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_LSB _u(16) #define PIO_SM3_SHIFTCTRL_AUTOPUSH_ACCESS "RW" // ============================================================================= // Register : PIO_SM3_ADDR // Description : Current instruction address of state machine 3 -#define PIO_SM3_ADDR_OFFSET 0x0000011c -#define PIO_SM3_ADDR_BITS 0x0000001f -#define PIO_SM3_ADDR_RESET 0x00000000 -#define PIO_SM3_ADDR_MSB 4 -#define PIO_SM3_ADDR_LSB 0 +#define PIO_SM3_ADDR_OFFSET _u(0x0000011c) +#define PIO_SM3_ADDR_BITS _u(0x0000001f) +#define PIO_SM3_ADDR_RESET _u(0x00000000) +#define PIO_SM3_ADDR_MSB _u(4) +#define PIO_SM3_ADDR_LSB _u(0) #define PIO_SM3_ADDR_ACCESS "RO" // ============================================================================= // Register : PIO_SM3_INSTR -// Description : Instruction currently being executed by state machine 3 +// Description : Read to see the instruction currently addressed by state +// machine 3's program counter // Write to execute an instruction immediately (including jumps) // and then resume execution. -#define PIO_SM3_INSTR_OFFSET 0x00000120 -#define PIO_SM3_INSTR_BITS 0x0000ffff +#define PIO_SM3_INSTR_OFFSET _u(0x00000120) +#define PIO_SM3_INSTR_BITS _u(0x0000ffff) #define PIO_SM3_INSTR_RESET "-" -#define PIO_SM3_INSTR_MSB 15 -#define PIO_SM3_INSTR_LSB 0 +#define PIO_SM3_INSTR_MSB _u(15) +#define PIO_SM3_INSTR_LSB _u(0) #define PIO_SM3_INSTR_ACCESS "RW" // ============================================================================= // Register : PIO_SM3_PINCTRL // Description : State machine pin control -#define PIO_SM3_PINCTRL_OFFSET 0x00000124 -#define PIO_SM3_PINCTRL_BITS 0xffffffff -#define PIO_SM3_PINCTRL_RESET 0x14000000 +#define PIO_SM3_PINCTRL_OFFSET _u(0x00000124) +#define PIO_SM3_PINCTRL_BITS _u(0xffffffff) +#define PIO_SM3_PINCTRL_RESET _u(0x14000000) // ----------------------------------------------------------------------------- // Field : PIO_SM3_PINCTRL_SIDESET_COUNT -// Description : The number of delay bits co-opted for side-set. Inclusive of -// the enable bit, if present. -#define PIO_SM3_PINCTRL_SIDESET_COUNT_RESET 0x0 -#define PIO_SM3_PINCTRL_SIDESET_COUNT_BITS 0xe0000000 -#define PIO_SM3_PINCTRL_SIDESET_COUNT_MSB 31 -#define PIO_SM3_PINCTRL_SIDESET_COUNT_LSB 29 +// Description : The number of MSBs of the Delay/Side-set instruction field +// which are used for side-set. Inclusive of the enable bit, if +// present. Minimum of 0 (all delay bits, no side-set) and maximum +// of 5 (all side-set, no delay). +#define PIO_SM3_PINCTRL_SIDESET_COUNT_RESET _u(0x0) +#define PIO_SM3_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) +#define PIO_SM3_PINCTRL_SIDESET_COUNT_MSB _u(31) +#define PIO_SM3_PINCTRL_SIDESET_COUNT_LSB _u(29) #define PIO_SM3_PINCTRL_SIDESET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_PINCTRL_SET_COUNT -// Description : The number of pins asserted by a SET. Max of 5 -#define PIO_SM3_PINCTRL_SET_COUNT_RESET 0x5 -#define PIO_SM3_PINCTRL_SET_COUNT_BITS 0x1c000000 -#define PIO_SM3_PINCTRL_SET_COUNT_MSB 28 -#define PIO_SM3_PINCTRL_SET_COUNT_LSB 26 +// Description : The number of pins asserted by a SET. In the range 0 to 5 +// inclusive. +#define PIO_SM3_PINCTRL_SET_COUNT_RESET _u(0x5) +#define PIO_SM3_PINCTRL_SET_COUNT_BITS _u(0x1c000000) +#define PIO_SM3_PINCTRL_SET_COUNT_MSB _u(28) +#define PIO_SM3_PINCTRL_SET_COUNT_LSB _u(26) #define PIO_SM3_PINCTRL_SET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_PINCTRL_OUT_COUNT -// Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins -#define PIO_SM3_PINCTRL_OUT_COUNT_RESET 0x00 -#define PIO_SM3_PINCTRL_OUT_COUNT_BITS 0x03f00000 -#define PIO_SM3_PINCTRL_OUT_COUNT_MSB 25 -#define PIO_SM3_PINCTRL_OUT_COUNT_LSB 20 +// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV +// PINS instruction. In the range 0 to 32 inclusive. +#define PIO_SM3_PINCTRL_OUT_COUNT_RESET _u(0x00) +#define PIO_SM3_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) +#define PIO_SM3_PINCTRL_OUT_COUNT_MSB _u(25) +#define PIO_SM3_PINCTRL_OUT_COUNT_LSB _u(20) #define PIO_SM3_PINCTRL_OUT_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_PINCTRL_IN_BASE -// Description : The virtual pin corresponding to IN bit 0 -#define PIO_SM3_PINCTRL_IN_BASE_RESET 0x00 -#define PIO_SM3_PINCTRL_IN_BASE_BITS 0x000f8000 -#define PIO_SM3_PINCTRL_IN_BASE_MSB 19 -#define PIO_SM3_PINCTRL_IN_BASE_LSB 15 +// Description : The pin which is mapped to the least-significant bit of a state +// machine's IN data bus. Higher-numbered pins are mapped to +// consecutively more-significant data bits, with a modulo of 32 +// applied to pin number. +#define PIO_SM3_PINCTRL_IN_BASE_RESET _u(0x00) +#define PIO_SM3_PINCTRL_IN_BASE_BITS _u(0x000f8000) +#define PIO_SM3_PINCTRL_IN_BASE_MSB _u(19) +#define PIO_SM3_PINCTRL_IN_BASE_LSB _u(15) #define PIO_SM3_PINCTRL_IN_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_PINCTRL_SIDESET_BASE -// Description : The virtual pin corresponding to delay field bit 0 -#define PIO_SM3_PINCTRL_SIDESET_BASE_RESET 0x00 -#define PIO_SM3_PINCTRL_SIDESET_BASE_BITS 0x00007c00 -#define PIO_SM3_PINCTRL_SIDESET_BASE_MSB 14 -#define PIO_SM3_PINCTRL_SIDESET_BASE_LSB 10 +// Description : The lowest-numbered pin that will be affected by a side-set +// operation. The MSBs of an instruction's side-set/delay field +// (up to 5, determined by SIDESET_COUNT) are used for side-set +// data, with the remaining LSBs used for delay. The +// least-significant bit of the side-set portion is the bit +// written to this pin, with more-significant bits written to +// higher-numbered pins. +#define PIO_SM3_PINCTRL_SIDESET_BASE_RESET _u(0x00) +#define PIO_SM3_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) +#define PIO_SM3_PINCTRL_SIDESET_BASE_MSB _u(14) +#define PIO_SM3_PINCTRL_SIDESET_BASE_LSB _u(10) #define PIO_SM3_PINCTRL_SIDESET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_PINCTRL_SET_BASE -// Description : The virtual pin corresponding to SET bit 0 -#define PIO_SM3_PINCTRL_SET_BASE_RESET 0x00 -#define PIO_SM3_PINCTRL_SET_BASE_BITS 0x000003e0 -#define PIO_SM3_PINCTRL_SET_BASE_MSB 9 -#define PIO_SM3_PINCTRL_SET_BASE_LSB 5 +// Description : The lowest-numbered pin that will be affected by a SET PINS or +// SET PINDIRS instruction. The data written to this pin is the +// least-significant bit of the SET data. +#define PIO_SM3_PINCTRL_SET_BASE_RESET _u(0x00) +#define PIO_SM3_PINCTRL_SET_BASE_BITS _u(0x000003e0) +#define PIO_SM3_PINCTRL_SET_BASE_MSB _u(9) +#define PIO_SM3_PINCTRL_SET_BASE_LSB _u(5) #define PIO_SM3_PINCTRL_SET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_SM3_PINCTRL_OUT_BASE -// Description : The virtual pin corresponding to OUT bit 0 -#define PIO_SM3_PINCTRL_OUT_BASE_RESET 0x00 -#define PIO_SM3_PINCTRL_OUT_BASE_BITS 0x0000001f -#define PIO_SM3_PINCTRL_OUT_BASE_MSB 4 -#define PIO_SM3_PINCTRL_OUT_BASE_LSB 0 +// Description : The lowest-numbered pin that will be affected by an OUT PINS, +// OUT PINDIRS or MOV PINS instruction. The data written to this +// pin will always be the least-significant bit of the OUT or MOV +// data. +#define PIO_SM3_PINCTRL_OUT_BASE_RESET _u(0x00) +#define PIO_SM3_PINCTRL_OUT_BASE_BITS _u(0x0000001f) +#define PIO_SM3_PINCTRL_OUT_BASE_MSB _u(4) +#define PIO_SM3_PINCTRL_OUT_BASE_LSB _u(0) #define PIO_SM3_PINCTRL_OUT_BASE_ACCESS "RW" // ============================================================================= // Register : PIO_INTR // Description : Raw Interrupts -#define PIO_INTR_OFFSET 0x00000128 -#define PIO_INTR_BITS 0x00000fff -#define PIO_INTR_RESET 0x00000000 +#define PIO_INTR_OFFSET _u(0x00000128) +#define PIO_INTR_BITS _u(0x00000fff) +#define PIO_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM3 // Description : None -#define PIO_INTR_SM3_RESET 0x0 -#define PIO_INTR_SM3_BITS 0x00000800 -#define PIO_INTR_SM3_MSB 11 -#define PIO_INTR_SM3_LSB 11 +#define PIO_INTR_SM3_RESET _u(0x0) +#define PIO_INTR_SM3_BITS _u(0x00000800) +#define PIO_INTR_SM3_MSB _u(11) +#define PIO_INTR_SM3_LSB _u(11) #define PIO_INTR_SM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM2 // Description : None -#define PIO_INTR_SM2_RESET 0x0 -#define PIO_INTR_SM2_BITS 0x00000400 -#define PIO_INTR_SM2_MSB 10 -#define PIO_INTR_SM2_LSB 10 +#define PIO_INTR_SM2_RESET _u(0x0) +#define PIO_INTR_SM2_BITS _u(0x00000400) +#define PIO_INTR_SM2_MSB _u(10) +#define PIO_INTR_SM2_LSB _u(10) #define PIO_INTR_SM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM1 // Description : None -#define PIO_INTR_SM1_RESET 0x0 -#define PIO_INTR_SM1_BITS 0x00000200 -#define PIO_INTR_SM1_MSB 9 -#define PIO_INTR_SM1_LSB 9 +#define PIO_INTR_SM1_RESET _u(0x0) +#define PIO_INTR_SM1_BITS _u(0x00000200) +#define PIO_INTR_SM1_MSB _u(9) +#define PIO_INTR_SM1_LSB _u(9) #define PIO_INTR_SM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM0 // Description : None -#define PIO_INTR_SM0_RESET 0x0 -#define PIO_INTR_SM0_BITS 0x00000100 -#define PIO_INTR_SM0_MSB 8 -#define PIO_INTR_SM0_LSB 8 +#define PIO_INTR_SM0_RESET _u(0x0) +#define PIO_INTR_SM0_BITS _u(0x00000100) +#define PIO_INTR_SM0_MSB _u(8) +#define PIO_INTR_SM0_LSB _u(8) #define PIO_INTR_SM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM3_TXNFULL // Description : None -#define PIO_INTR_SM3_TXNFULL_RESET 0x0 -#define PIO_INTR_SM3_TXNFULL_BITS 0x00000080 -#define PIO_INTR_SM3_TXNFULL_MSB 7 -#define PIO_INTR_SM3_TXNFULL_LSB 7 +#define PIO_INTR_SM3_TXNFULL_RESET _u(0x0) +#define PIO_INTR_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_INTR_SM3_TXNFULL_MSB _u(7) +#define PIO_INTR_SM3_TXNFULL_LSB _u(7) #define PIO_INTR_SM3_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM2_TXNFULL // Description : None -#define PIO_INTR_SM2_TXNFULL_RESET 0x0 -#define PIO_INTR_SM2_TXNFULL_BITS 0x00000040 -#define PIO_INTR_SM2_TXNFULL_MSB 6 -#define PIO_INTR_SM2_TXNFULL_LSB 6 +#define PIO_INTR_SM2_TXNFULL_RESET _u(0x0) +#define PIO_INTR_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_INTR_SM2_TXNFULL_MSB _u(6) +#define PIO_INTR_SM2_TXNFULL_LSB _u(6) #define PIO_INTR_SM2_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM1_TXNFULL // Description : None -#define PIO_INTR_SM1_TXNFULL_RESET 0x0 -#define PIO_INTR_SM1_TXNFULL_BITS 0x00000020 -#define PIO_INTR_SM1_TXNFULL_MSB 5 -#define PIO_INTR_SM1_TXNFULL_LSB 5 +#define PIO_INTR_SM1_TXNFULL_RESET _u(0x0) +#define PIO_INTR_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_INTR_SM1_TXNFULL_MSB _u(5) +#define PIO_INTR_SM1_TXNFULL_LSB _u(5) #define PIO_INTR_SM1_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM0_TXNFULL // Description : None -#define PIO_INTR_SM0_TXNFULL_RESET 0x0 -#define PIO_INTR_SM0_TXNFULL_BITS 0x00000010 -#define PIO_INTR_SM0_TXNFULL_MSB 4 -#define PIO_INTR_SM0_TXNFULL_LSB 4 +#define PIO_INTR_SM0_TXNFULL_RESET _u(0x0) +#define PIO_INTR_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_INTR_SM0_TXNFULL_MSB _u(4) +#define PIO_INTR_SM0_TXNFULL_LSB _u(4) #define PIO_INTR_SM0_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM3_RXNEMPTY // Description : None -#define PIO_INTR_SM3_RXNEMPTY_RESET 0x0 -#define PIO_INTR_SM3_RXNEMPTY_BITS 0x00000008 -#define PIO_INTR_SM3_RXNEMPTY_MSB 3 -#define PIO_INTR_SM3_RXNEMPTY_LSB 3 +#define PIO_INTR_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_INTR_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_INTR_SM3_RXNEMPTY_MSB _u(3) +#define PIO_INTR_SM3_RXNEMPTY_LSB _u(3) #define PIO_INTR_SM3_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM2_RXNEMPTY // Description : None -#define PIO_INTR_SM2_RXNEMPTY_RESET 0x0 -#define PIO_INTR_SM2_RXNEMPTY_BITS 0x00000004 -#define PIO_INTR_SM2_RXNEMPTY_MSB 2 -#define PIO_INTR_SM2_RXNEMPTY_LSB 2 +#define PIO_INTR_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_INTR_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_INTR_SM2_RXNEMPTY_MSB _u(2) +#define PIO_INTR_SM2_RXNEMPTY_LSB _u(2) #define PIO_INTR_SM2_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM1_RXNEMPTY // Description : None -#define PIO_INTR_SM1_RXNEMPTY_RESET 0x0 -#define PIO_INTR_SM1_RXNEMPTY_BITS 0x00000002 -#define PIO_INTR_SM1_RXNEMPTY_MSB 1 -#define PIO_INTR_SM1_RXNEMPTY_LSB 1 +#define PIO_INTR_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_INTR_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_INTR_SM1_RXNEMPTY_MSB _u(1) +#define PIO_INTR_SM1_RXNEMPTY_LSB _u(1) #define PIO_INTR_SM1_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM0_RXNEMPTY // Description : None -#define PIO_INTR_SM0_RXNEMPTY_RESET 0x0 -#define PIO_INTR_SM0_RXNEMPTY_BITS 0x00000001 -#define PIO_INTR_SM0_RXNEMPTY_MSB 0 -#define PIO_INTR_SM0_RXNEMPTY_LSB 0 +#define PIO_INTR_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_INTR_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_INTR_SM0_RXNEMPTY_MSB _u(0) +#define PIO_INTR_SM0_RXNEMPTY_LSB _u(0) #define PIO_INTR_SM0_RXNEMPTY_ACCESS "RO" // ============================================================================= // Register : PIO_IRQ0_INTE // Description : Interrupt Enable for irq0 -#define PIO_IRQ0_INTE_OFFSET 0x0000012c -#define PIO_IRQ0_INTE_BITS 0x00000fff -#define PIO_IRQ0_INTE_RESET 0x00000000 +#define PIO_IRQ0_INTE_OFFSET _u(0x0000012c) +#define PIO_IRQ0_INTE_BITS _u(0x00000fff) +#define PIO_IRQ0_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM3 // Description : None -#define PIO_IRQ0_INTE_SM3_RESET 0x0 -#define PIO_IRQ0_INTE_SM3_BITS 0x00000800 -#define PIO_IRQ0_INTE_SM3_MSB 11 -#define PIO_IRQ0_INTE_SM3_LSB 11 +#define PIO_IRQ0_INTE_SM3_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM3_BITS _u(0x00000800) +#define PIO_IRQ0_INTE_SM3_MSB _u(11) +#define PIO_IRQ0_INTE_SM3_LSB _u(11) #define PIO_IRQ0_INTE_SM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM2 // Description : None -#define PIO_IRQ0_INTE_SM2_RESET 0x0 -#define PIO_IRQ0_INTE_SM2_BITS 0x00000400 -#define PIO_IRQ0_INTE_SM2_MSB 10 -#define PIO_IRQ0_INTE_SM2_LSB 10 +#define PIO_IRQ0_INTE_SM2_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM2_BITS _u(0x00000400) +#define PIO_IRQ0_INTE_SM2_MSB _u(10) +#define PIO_IRQ0_INTE_SM2_LSB _u(10) #define PIO_IRQ0_INTE_SM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM1 // Description : None -#define PIO_IRQ0_INTE_SM1_RESET 0x0 -#define PIO_IRQ0_INTE_SM1_BITS 0x00000200 -#define PIO_IRQ0_INTE_SM1_MSB 9 -#define PIO_IRQ0_INTE_SM1_LSB 9 +#define PIO_IRQ0_INTE_SM1_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM1_BITS _u(0x00000200) +#define PIO_IRQ0_INTE_SM1_MSB _u(9) +#define PIO_IRQ0_INTE_SM1_LSB _u(9) #define PIO_IRQ0_INTE_SM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM0 // Description : None -#define PIO_IRQ0_INTE_SM0_RESET 0x0 -#define PIO_IRQ0_INTE_SM0_BITS 0x00000100 -#define PIO_IRQ0_INTE_SM0_MSB 8 -#define PIO_IRQ0_INTE_SM0_LSB 8 +#define PIO_IRQ0_INTE_SM0_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM0_BITS _u(0x00000100) +#define PIO_IRQ0_INTE_SM0_MSB _u(8) +#define PIO_IRQ0_INTE_SM0_LSB _u(8) #define PIO_IRQ0_INTE_SM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM3_TXNFULL // Description : None -#define PIO_IRQ0_INTE_SM3_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTE_SM3_TXNFULL_BITS 0x00000080 -#define PIO_IRQ0_INTE_SM3_TXNFULL_MSB 7 -#define PIO_IRQ0_INTE_SM3_TXNFULL_LSB 7 +#define PIO_IRQ0_INTE_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ0_INTE_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ0_INTE_SM3_TXNFULL_LSB _u(7) #define PIO_IRQ0_INTE_SM3_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM2_TXNFULL // Description : None -#define PIO_IRQ0_INTE_SM2_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTE_SM2_TXNFULL_BITS 0x00000040 -#define PIO_IRQ0_INTE_SM2_TXNFULL_MSB 6 -#define PIO_IRQ0_INTE_SM2_TXNFULL_LSB 6 +#define PIO_IRQ0_INTE_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ0_INTE_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ0_INTE_SM2_TXNFULL_LSB _u(6) #define PIO_IRQ0_INTE_SM2_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM1_TXNFULL // Description : None -#define PIO_IRQ0_INTE_SM1_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTE_SM1_TXNFULL_BITS 0x00000020 -#define PIO_IRQ0_INTE_SM1_TXNFULL_MSB 5 -#define PIO_IRQ0_INTE_SM1_TXNFULL_LSB 5 +#define PIO_IRQ0_INTE_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ0_INTE_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ0_INTE_SM1_TXNFULL_LSB _u(5) #define PIO_IRQ0_INTE_SM1_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM0_TXNFULL // Description : None -#define PIO_IRQ0_INTE_SM0_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTE_SM0_TXNFULL_BITS 0x00000010 -#define PIO_IRQ0_INTE_SM0_TXNFULL_MSB 4 -#define PIO_IRQ0_INTE_SM0_TXNFULL_LSB 4 +#define PIO_IRQ0_INTE_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ0_INTE_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ0_INTE_SM0_TXNFULL_LSB _u(4) #define PIO_IRQ0_INTE_SM0_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM3_RXNEMPTY // Description : None -#define PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS 0x00000008 -#define PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB 3 -#define PIO_IRQ0_INTE_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_LSB _u(3) #define PIO_IRQ0_INTE_SM3_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM2_RXNEMPTY // Description : None -#define PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS 0x00000004 -#define PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB 2 -#define PIO_IRQ0_INTE_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_LSB _u(2) #define PIO_IRQ0_INTE_SM2_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM1_RXNEMPTY // Description : None -#define PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS 0x00000002 -#define PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB 1 -#define PIO_IRQ0_INTE_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_LSB _u(1) #define PIO_IRQ0_INTE_SM1_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM0_RXNEMPTY // Description : None -#define PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS 0x00000001 -#define PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB 0 -#define PIO_IRQ0_INTE_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_LSB _u(0) #define PIO_IRQ0_INTE_SM0_RXNEMPTY_ACCESS "RW" // ============================================================================= // Register : PIO_IRQ0_INTF // Description : Interrupt Force for irq0 -#define PIO_IRQ0_INTF_OFFSET 0x00000130 -#define PIO_IRQ0_INTF_BITS 0x00000fff -#define PIO_IRQ0_INTF_RESET 0x00000000 +#define PIO_IRQ0_INTF_OFFSET _u(0x00000130) +#define PIO_IRQ0_INTF_BITS _u(0x00000fff) +#define PIO_IRQ0_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM3 // Description : None -#define PIO_IRQ0_INTF_SM3_RESET 0x0 -#define PIO_IRQ0_INTF_SM3_BITS 0x00000800 -#define PIO_IRQ0_INTF_SM3_MSB 11 -#define PIO_IRQ0_INTF_SM3_LSB 11 +#define PIO_IRQ0_INTF_SM3_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM3_BITS _u(0x00000800) +#define PIO_IRQ0_INTF_SM3_MSB _u(11) +#define PIO_IRQ0_INTF_SM3_LSB _u(11) #define PIO_IRQ0_INTF_SM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM2 // Description : None -#define PIO_IRQ0_INTF_SM2_RESET 0x0 -#define PIO_IRQ0_INTF_SM2_BITS 0x00000400 -#define PIO_IRQ0_INTF_SM2_MSB 10 -#define PIO_IRQ0_INTF_SM2_LSB 10 +#define PIO_IRQ0_INTF_SM2_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM2_BITS _u(0x00000400) +#define PIO_IRQ0_INTF_SM2_MSB _u(10) +#define PIO_IRQ0_INTF_SM2_LSB _u(10) #define PIO_IRQ0_INTF_SM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM1 // Description : None -#define PIO_IRQ0_INTF_SM1_RESET 0x0 -#define PIO_IRQ0_INTF_SM1_BITS 0x00000200 -#define PIO_IRQ0_INTF_SM1_MSB 9 -#define PIO_IRQ0_INTF_SM1_LSB 9 +#define PIO_IRQ0_INTF_SM1_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM1_BITS _u(0x00000200) +#define PIO_IRQ0_INTF_SM1_MSB _u(9) +#define PIO_IRQ0_INTF_SM1_LSB _u(9) #define PIO_IRQ0_INTF_SM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM0 // Description : None -#define PIO_IRQ0_INTF_SM0_RESET 0x0 -#define PIO_IRQ0_INTF_SM0_BITS 0x00000100 -#define PIO_IRQ0_INTF_SM0_MSB 8 -#define PIO_IRQ0_INTF_SM0_LSB 8 +#define PIO_IRQ0_INTF_SM0_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM0_BITS _u(0x00000100) +#define PIO_IRQ0_INTF_SM0_MSB _u(8) +#define PIO_IRQ0_INTF_SM0_LSB _u(8) #define PIO_IRQ0_INTF_SM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM3_TXNFULL // Description : None -#define PIO_IRQ0_INTF_SM3_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTF_SM3_TXNFULL_BITS 0x00000080 -#define PIO_IRQ0_INTF_SM3_TXNFULL_MSB 7 -#define PIO_IRQ0_INTF_SM3_TXNFULL_LSB 7 +#define PIO_IRQ0_INTF_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ0_INTF_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ0_INTF_SM3_TXNFULL_LSB _u(7) #define PIO_IRQ0_INTF_SM3_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM2_TXNFULL // Description : None -#define PIO_IRQ0_INTF_SM2_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTF_SM2_TXNFULL_BITS 0x00000040 -#define PIO_IRQ0_INTF_SM2_TXNFULL_MSB 6 -#define PIO_IRQ0_INTF_SM2_TXNFULL_LSB 6 +#define PIO_IRQ0_INTF_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ0_INTF_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ0_INTF_SM2_TXNFULL_LSB _u(6) #define PIO_IRQ0_INTF_SM2_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM1_TXNFULL // Description : None -#define PIO_IRQ0_INTF_SM1_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTF_SM1_TXNFULL_BITS 0x00000020 -#define PIO_IRQ0_INTF_SM1_TXNFULL_MSB 5 -#define PIO_IRQ0_INTF_SM1_TXNFULL_LSB 5 +#define PIO_IRQ0_INTF_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ0_INTF_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ0_INTF_SM1_TXNFULL_LSB _u(5) #define PIO_IRQ0_INTF_SM1_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM0_TXNFULL // Description : None -#define PIO_IRQ0_INTF_SM0_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTF_SM0_TXNFULL_BITS 0x00000010 -#define PIO_IRQ0_INTF_SM0_TXNFULL_MSB 4 -#define PIO_IRQ0_INTF_SM0_TXNFULL_LSB 4 +#define PIO_IRQ0_INTF_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ0_INTF_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ0_INTF_SM0_TXNFULL_LSB _u(4) #define PIO_IRQ0_INTF_SM0_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM3_RXNEMPTY // Description : None -#define PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS 0x00000008 -#define PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB 3 -#define PIO_IRQ0_INTF_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_LSB _u(3) #define PIO_IRQ0_INTF_SM3_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM2_RXNEMPTY // Description : None -#define PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS 0x00000004 -#define PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB 2 -#define PIO_IRQ0_INTF_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_LSB _u(2) #define PIO_IRQ0_INTF_SM2_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM1_RXNEMPTY // Description : None -#define PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS 0x00000002 -#define PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB 1 -#define PIO_IRQ0_INTF_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_LSB _u(1) #define PIO_IRQ0_INTF_SM1_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM0_RXNEMPTY // Description : None -#define PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS 0x00000001 -#define PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB 0 -#define PIO_IRQ0_INTF_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_LSB _u(0) #define PIO_IRQ0_INTF_SM0_RXNEMPTY_ACCESS "RW" // ============================================================================= // Register : PIO_IRQ0_INTS // Description : Interrupt status after masking & forcing for irq0 -#define PIO_IRQ0_INTS_OFFSET 0x00000134 -#define PIO_IRQ0_INTS_BITS 0x00000fff -#define PIO_IRQ0_INTS_RESET 0x00000000 +#define PIO_IRQ0_INTS_OFFSET _u(0x00000134) +#define PIO_IRQ0_INTS_BITS _u(0x00000fff) +#define PIO_IRQ0_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM3 // Description : None -#define PIO_IRQ0_INTS_SM3_RESET 0x0 -#define PIO_IRQ0_INTS_SM3_BITS 0x00000800 -#define PIO_IRQ0_INTS_SM3_MSB 11 -#define PIO_IRQ0_INTS_SM3_LSB 11 +#define PIO_IRQ0_INTS_SM3_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM3_BITS _u(0x00000800) +#define PIO_IRQ0_INTS_SM3_MSB _u(11) +#define PIO_IRQ0_INTS_SM3_LSB _u(11) #define PIO_IRQ0_INTS_SM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM2 // Description : None -#define PIO_IRQ0_INTS_SM2_RESET 0x0 -#define PIO_IRQ0_INTS_SM2_BITS 0x00000400 -#define PIO_IRQ0_INTS_SM2_MSB 10 -#define PIO_IRQ0_INTS_SM2_LSB 10 +#define PIO_IRQ0_INTS_SM2_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM2_BITS _u(0x00000400) +#define PIO_IRQ0_INTS_SM2_MSB _u(10) +#define PIO_IRQ0_INTS_SM2_LSB _u(10) #define PIO_IRQ0_INTS_SM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM1 // Description : None -#define PIO_IRQ0_INTS_SM1_RESET 0x0 -#define PIO_IRQ0_INTS_SM1_BITS 0x00000200 -#define PIO_IRQ0_INTS_SM1_MSB 9 -#define PIO_IRQ0_INTS_SM1_LSB 9 +#define PIO_IRQ0_INTS_SM1_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM1_BITS _u(0x00000200) +#define PIO_IRQ0_INTS_SM1_MSB _u(9) +#define PIO_IRQ0_INTS_SM1_LSB _u(9) #define PIO_IRQ0_INTS_SM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM0 // Description : None -#define PIO_IRQ0_INTS_SM0_RESET 0x0 -#define PIO_IRQ0_INTS_SM0_BITS 0x00000100 -#define PIO_IRQ0_INTS_SM0_MSB 8 -#define PIO_IRQ0_INTS_SM0_LSB 8 +#define PIO_IRQ0_INTS_SM0_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM0_BITS _u(0x00000100) +#define PIO_IRQ0_INTS_SM0_MSB _u(8) +#define PIO_IRQ0_INTS_SM0_LSB _u(8) #define PIO_IRQ0_INTS_SM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM3_TXNFULL // Description : None -#define PIO_IRQ0_INTS_SM3_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTS_SM3_TXNFULL_BITS 0x00000080 -#define PIO_IRQ0_INTS_SM3_TXNFULL_MSB 7 -#define PIO_IRQ0_INTS_SM3_TXNFULL_LSB 7 +#define PIO_IRQ0_INTS_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ0_INTS_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ0_INTS_SM3_TXNFULL_LSB _u(7) #define PIO_IRQ0_INTS_SM3_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM2_TXNFULL // Description : None -#define PIO_IRQ0_INTS_SM2_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTS_SM2_TXNFULL_BITS 0x00000040 -#define PIO_IRQ0_INTS_SM2_TXNFULL_MSB 6 -#define PIO_IRQ0_INTS_SM2_TXNFULL_LSB 6 +#define PIO_IRQ0_INTS_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ0_INTS_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ0_INTS_SM2_TXNFULL_LSB _u(6) #define PIO_IRQ0_INTS_SM2_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM1_TXNFULL // Description : None -#define PIO_IRQ0_INTS_SM1_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTS_SM1_TXNFULL_BITS 0x00000020 -#define PIO_IRQ0_INTS_SM1_TXNFULL_MSB 5 -#define PIO_IRQ0_INTS_SM1_TXNFULL_LSB 5 +#define PIO_IRQ0_INTS_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ0_INTS_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ0_INTS_SM1_TXNFULL_LSB _u(5) #define PIO_IRQ0_INTS_SM1_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM0_TXNFULL // Description : None -#define PIO_IRQ0_INTS_SM0_TXNFULL_RESET 0x0 -#define PIO_IRQ0_INTS_SM0_TXNFULL_BITS 0x00000010 -#define PIO_IRQ0_INTS_SM0_TXNFULL_MSB 4 -#define PIO_IRQ0_INTS_SM0_TXNFULL_LSB 4 +#define PIO_IRQ0_INTS_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ0_INTS_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ0_INTS_SM0_TXNFULL_LSB _u(4) #define PIO_IRQ0_INTS_SM0_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM3_RXNEMPTY // Description : None -#define PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS 0x00000008 -#define PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB 3 -#define PIO_IRQ0_INTS_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_LSB _u(3) #define PIO_IRQ0_INTS_SM3_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM2_RXNEMPTY // Description : None -#define PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS 0x00000004 -#define PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB 2 -#define PIO_IRQ0_INTS_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_LSB _u(2) #define PIO_IRQ0_INTS_SM2_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM1_RXNEMPTY // Description : None -#define PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS 0x00000002 -#define PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB 1 -#define PIO_IRQ0_INTS_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_LSB _u(1) #define PIO_IRQ0_INTS_SM1_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM0_RXNEMPTY // Description : None -#define PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET 0x0 -#define PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS 0x00000001 -#define PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB 0 -#define PIO_IRQ0_INTS_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_LSB _u(0) #define PIO_IRQ0_INTS_SM0_RXNEMPTY_ACCESS "RO" // ============================================================================= // Register : PIO_IRQ1_INTE // Description : Interrupt Enable for irq1 -#define PIO_IRQ1_INTE_OFFSET 0x00000138 -#define PIO_IRQ1_INTE_BITS 0x00000fff -#define PIO_IRQ1_INTE_RESET 0x00000000 +#define PIO_IRQ1_INTE_OFFSET _u(0x00000138) +#define PIO_IRQ1_INTE_BITS _u(0x00000fff) +#define PIO_IRQ1_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM3 // Description : None -#define PIO_IRQ1_INTE_SM3_RESET 0x0 -#define PIO_IRQ1_INTE_SM3_BITS 0x00000800 -#define PIO_IRQ1_INTE_SM3_MSB 11 -#define PIO_IRQ1_INTE_SM3_LSB 11 +#define PIO_IRQ1_INTE_SM3_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM3_BITS _u(0x00000800) +#define PIO_IRQ1_INTE_SM3_MSB _u(11) +#define PIO_IRQ1_INTE_SM3_LSB _u(11) #define PIO_IRQ1_INTE_SM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM2 // Description : None -#define PIO_IRQ1_INTE_SM2_RESET 0x0 -#define PIO_IRQ1_INTE_SM2_BITS 0x00000400 -#define PIO_IRQ1_INTE_SM2_MSB 10 -#define PIO_IRQ1_INTE_SM2_LSB 10 +#define PIO_IRQ1_INTE_SM2_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM2_BITS _u(0x00000400) +#define PIO_IRQ1_INTE_SM2_MSB _u(10) +#define PIO_IRQ1_INTE_SM2_LSB _u(10) #define PIO_IRQ1_INTE_SM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM1 // Description : None -#define PIO_IRQ1_INTE_SM1_RESET 0x0 -#define PIO_IRQ1_INTE_SM1_BITS 0x00000200 -#define PIO_IRQ1_INTE_SM1_MSB 9 -#define PIO_IRQ1_INTE_SM1_LSB 9 +#define PIO_IRQ1_INTE_SM1_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM1_BITS _u(0x00000200) +#define PIO_IRQ1_INTE_SM1_MSB _u(9) +#define PIO_IRQ1_INTE_SM1_LSB _u(9) #define PIO_IRQ1_INTE_SM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM0 // Description : None -#define PIO_IRQ1_INTE_SM0_RESET 0x0 -#define PIO_IRQ1_INTE_SM0_BITS 0x00000100 -#define PIO_IRQ1_INTE_SM0_MSB 8 -#define PIO_IRQ1_INTE_SM0_LSB 8 +#define PIO_IRQ1_INTE_SM0_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM0_BITS _u(0x00000100) +#define PIO_IRQ1_INTE_SM0_MSB _u(8) +#define PIO_IRQ1_INTE_SM0_LSB _u(8) #define PIO_IRQ1_INTE_SM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM3_TXNFULL // Description : None -#define PIO_IRQ1_INTE_SM3_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTE_SM3_TXNFULL_BITS 0x00000080 -#define PIO_IRQ1_INTE_SM3_TXNFULL_MSB 7 -#define PIO_IRQ1_INTE_SM3_TXNFULL_LSB 7 +#define PIO_IRQ1_INTE_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ1_INTE_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ1_INTE_SM3_TXNFULL_LSB _u(7) #define PIO_IRQ1_INTE_SM3_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM2_TXNFULL // Description : None -#define PIO_IRQ1_INTE_SM2_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTE_SM2_TXNFULL_BITS 0x00000040 -#define PIO_IRQ1_INTE_SM2_TXNFULL_MSB 6 -#define PIO_IRQ1_INTE_SM2_TXNFULL_LSB 6 +#define PIO_IRQ1_INTE_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ1_INTE_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ1_INTE_SM2_TXNFULL_LSB _u(6) #define PIO_IRQ1_INTE_SM2_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM1_TXNFULL // Description : None -#define PIO_IRQ1_INTE_SM1_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTE_SM1_TXNFULL_BITS 0x00000020 -#define PIO_IRQ1_INTE_SM1_TXNFULL_MSB 5 -#define PIO_IRQ1_INTE_SM1_TXNFULL_LSB 5 +#define PIO_IRQ1_INTE_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ1_INTE_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ1_INTE_SM1_TXNFULL_LSB _u(5) #define PIO_IRQ1_INTE_SM1_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM0_TXNFULL // Description : None -#define PIO_IRQ1_INTE_SM0_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTE_SM0_TXNFULL_BITS 0x00000010 -#define PIO_IRQ1_INTE_SM0_TXNFULL_MSB 4 -#define PIO_IRQ1_INTE_SM0_TXNFULL_LSB 4 +#define PIO_IRQ1_INTE_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ1_INTE_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ1_INTE_SM0_TXNFULL_LSB _u(4) #define PIO_IRQ1_INTE_SM0_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM3_RXNEMPTY // Description : None -#define PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS 0x00000008 -#define PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB 3 -#define PIO_IRQ1_INTE_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_LSB _u(3) #define PIO_IRQ1_INTE_SM3_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM2_RXNEMPTY // Description : None -#define PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS 0x00000004 -#define PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB 2 -#define PIO_IRQ1_INTE_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_LSB _u(2) #define PIO_IRQ1_INTE_SM2_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM1_RXNEMPTY // Description : None -#define PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS 0x00000002 -#define PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB 1 -#define PIO_IRQ1_INTE_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_LSB _u(1) #define PIO_IRQ1_INTE_SM1_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM0_RXNEMPTY // Description : None -#define PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS 0x00000001 -#define PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB 0 -#define PIO_IRQ1_INTE_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_LSB _u(0) #define PIO_IRQ1_INTE_SM0_RXNEMPTY_ACCESS "RW" // ============================================================================= // Register : PIO_IRQ1_INTF // Description : Interrupt Force for irq1 -#define PIO_IRQ1_INTF_OFFSET 0x0000013c -#define PIO_IRQ1_INTF_BITS 0x00000fff -#define PIO_IRQ1_INTF_RESET 0x00000000 +#define PIO_IRQ1_INTF_OFFSET _u(0x0000013c) +#define PIO_IRQ1_INTF_BITS _u(0x00000fff) +#define PIO_IRQ1_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM3 // Description : None -#define PIO_IRQ1_INTF_SM3_RESET 0x0 -#define PIO_IRQ1_INTF_SM3_BITS 0x00000800 -#define PIO_IRQ1_INTF_SM3_MSB 11 -#define PIO_IRQ1_INTF_SM3_LSB 11 +#define PIO_IRQ1_INTF_SM3_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM3_BITS _u(0x00000800) +#define PIO_IRQ1_INTF_SM3_MSB _u(11) +#define PIO_IRQ1_INTF_SM3_LSB _u(11) #define PIO_IRQ1_INTF_SM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM2 // Description : None -#define PIO_IRQ1_INTF_SM2_RESET 0x0 -#define PIO_IRQ1_INTF_SM2_BITS 0x00000400 -#define PIO_IRQ1_INTF_SM2_MSB 10 -#define PIO_IRQ1_INTF_SM2_LSB 10 +#define PIO_IRQ1_INTF_SM2_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM2_BITS _u(0x00000400) +#define PIO_IRQ1_INTF_SM2_MSB _u(10) +#define PIO_IRQ1_INTF_SM2_LSB _u(10) #define PIO_IRQ1_INTF_SM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM1 // Description : None -#define PIO_IRQ1_INTF_SM1_RESET 0x0 -#define PIO_IRQ1_INTF_SM1_BITS 0x00000200 -#define PIO_IRQ1_INTF_SM1_MSB 9 -#define PIO_IRQ1_INTF_SM1_LSB 9 +#define PIO_IRQ1_INTF_SM1_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM1_BITS _u(0x00000200) +#define PIO_IRQ1_INTF_SM1_MSB _u(9) +#define PIO_IRQ1_INTF_SM1_LSB _u(9) #define PIO_IRQ1_INTF_SM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM0 // Description : None -#define PIO_IRQ1_INTF_SM0_RESET 0x0 -#define PIO_IRQ1_INTF_SM0_BITS 0x00000100 -#define PIO_IRQ1_INTF_SM0_MSB 8 -#define PIO_IRQ1_INTF_SM0_LSB 8 +#define PIO_IRQ1_INTF_SM0_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM0_BITS _u(0x00000100) +#define PIO_IRQ1_INTF_SM0_MSB _u(8) +#define PIO_IRQ1_INTF_SM0_LSB _u(8) #define PIO_IRQ1_INTF_SM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM3_TXNFULL // Description : None -#define PIO_IRQ1_INTF_SM3_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTF_SM3_TXNFULL_BITS 0x00000080 -#define PIO_IRQ1_INTF_SM3_TXNFULL_MSB 7 -#define PIO_IRQ1_INTF_SM3_TXNFULL_LSB 7 +#define PIO_IRQ1_INTF_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ1_INTF_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ1_INTF_SM3_TXNFULL_LSB _u(7) #define PIO_IRQ1_INTF_SM3_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM2_TXNFULL // Description : None -#define PIO_IRQ1_INTF_SM2_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTF_SM2_TXNFULL_BITS 0x00000040 -#define PIO_IRQ1_INTF_SM2_TXNFULL_MSB 6 -#define PIO_IRQ1_INTF_SM2_TXNFULL_LSB 6 +#define PIO_IRQ1_INTF_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ1_INTF_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ1_INTF_SM2_TXNFULL_LSB _u(6) #define PIO_IRQ1_INTF_SM2_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM1_TXNFULL // Description : None -#define PIO_IRQ1_INTF_SM1_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTF_SM1_TXNFULL_BITS 0x00000020 -#define PIO_IRQ1_INTF_SM1_TXNFULL_MSB 5 -#define PIO_IRQ1_INTF_SM1_TXNFULL_LSB 5 +#define PIO_IRQ1_INTF_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ1_INTF_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ1_INTF_SM1_TXNFULL_LSB _u(5) #define PIO_IRQ1_INTF_SM1_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM0_TXNFULL // Description : None -#define PIO_IRQ1_INTF_SM0_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTF_SM0_TXNFULL_BITS 0x00000010 -#define PIO_IRQ1_INTF_SM0_TXNFULL_MSB 4 -#define PIO_IRQ1_INTF_SM0_TXNFULL_LSB 4 +#define PIO_IRQ1_INTF_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ1_INTF_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ1_INTF_SM0_TXNFULL_LSB _u(4) #define PIO_IRQ1_INTF_SM0_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM3_RXNEMPTY // Description : None -#define PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS 0x00000008 -#define PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB 3 -#define PIO_IRQ1_INTF_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_LSB _u(3) #define PIO_IRQ1_INTF_SM3_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM2_RXNEMPTY // Description : None -#define PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS 0x00000004 -#define PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB 2 -#define PIO_IRQ1_INTF_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_LSB _u(2) #define PIO_IRQ1_INTF_SM2_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM1_RXNEMPTY // Description : None -#define PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS 0x00000002 -#define PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB 1 -#define PIO_IRQ1_INTF_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_LSB _u(1) #define PIO_IRQ1_INTF_SM1_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM0_RXNEMPTY // Description : None -#define PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS 0x00000001 -#define PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB 0 -#define PIO_IRQ1_INTF_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_LSB _u(0) #define PIO_IRQ1_INTF_SM0_RXNEMPTY_ACCESS "RW" // ============================================================================= // Register : PIO_IRQ1_INTS // Description : Interrupt status after masking & forcing for irq1 -#define PIO_IRQ1_INTS_OFFSET 0x00000140 -#define PIO_IRQ1_INTS_BITS 0x00000fff -#define PIO_IRQ1_INTS_RESET 0x00000000 +#define PIO_IRQ1_INTS_OFFSET _u(0x00000140) +#define PIO_IRQ1_INTS_BITS _u(0x00000fff) +#define PIO_IRQ1_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM3 // Description : None -#define PIO_IRQ1_INTS_SM3_RESET 0x0 -#define PIO_IRQ1_INTS_SM3_BITS 0x00000800 -#define PIO_IRQ1_INTS_SM3_MSB 11 -#define PIO_IRQ1_INTS_SM3_LSB 11 +#define PIO_IRQ1_INTS_SM3_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM3_BITS _u(0x00000800) +#define PIO_IRQ1_INTS_SM3_MSB _u(11) +#define PIO_IRQ1_INTS_SM3_LSB _u(11) #define PIO_IRQ1_INTS_SM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM2 // Description : None -#define PIO_IRQ1_INTS_SM2_RESET 0x0 -#define PIO_IRQ1_INTS_SM2_BITS 0x00000400 -#define PIO_IRQ1_INTS_SM2_MSB 10 -#define PIO_IRQ1_INTS_SM2_LSB 10 +#define PIO_IRQ1_INTS_SM2_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM2_BITS _u(0x00000400) +#define PIO_IRQ1_INTS_SM2_MSB _u(10) +#define PIO_IRQ1_INTS_SM2_LSB _u(10) #define PIO_IRQ1_INTS_SM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM1 // Description : None -#define PIO_IRQ1_INTS_SM1_RESET 0x0 -#define PIO_IRQ1_INTS_SM1_BITS 0x00000200 -#define PIO_IRQ1_INTS_SM1_MSB 9 -#define PIO_IRQ1_INTS_SM1_LSB 9 +#define PIO_IRQ1_INTS_SM1_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM1_BITS _u(0x00000200) +#define PIO_IRQ1_INTS_SM1_MSB _u(9) +#define PIO_IRQ1_INTS_SM1_LSB _u(9) #define PIO_IRQ1_INTS_SM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM0 // Description : None -#define PIO_IRQ1_INTS_SM0_RESET 0x0 -#define PIO_IRQ1_INTS_SM0_BITS 0x00000100 -#define PIO_IRQ1_INTS_SM0_MSB 8 -#define PIO_IRQ1_INTS_SM0_LSB 8 +#define PIO_IRQ1_INTS_SM0_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM0_BITS _u(0x00000100) +#define PIO_IRQ1_INTS_SM0_MSB _u(8) +#define PIO_IRQ1_INTS_SM0_LSB _u(8) #define PIO_IRQ1_INTS_SM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM3_TXNFULL // Description : None -#define PIO_IRQ1_INTS_SM3_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTS_SM3_TXNFULL_BITS 0x00000080 -#define PIO_IRQ1_INTS_SM3_TXNFULL_MSB 7 -#define PIO_IRQ1_INTS_SM3_TXNFULL_LSB 7 +#define PIO_IRQ1_INTS_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ1_INTS_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ1_INTS_SM3_TXNFULL_LSB _u(7) #define PIO_IRQ1_INTS_SM3_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM2_TXNFULL // Description : None -#define PIO_IRQ1_INTS_SM2_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTS_SM2_TXNFULL_BITS 0x00000040 -#define PIO_IRQ1_INTS_SM2_TXNFULL_MSB 6 -#define PIO_IRQ1_INTS_SM2_TXNFULL_LSB 6 +#define PIO_IRQ1_INTS_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ1_INTS_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ1_INTS_SM2_TXNFULL_LSB _u(6) #define PIO_IRQ1_INTS_SM2_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM1_TXNFULL // Description : None -#define PIO_IRQ1_INTS_SM1_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTS_SM1_TXNFULL_BITS 0x00000020 -#define PIO_IRQ1_INTS_SM1_TXNFULL_MSB 5 -#define PIO_IRQ1_INTS_SM1_TXNFULL_LSB 5 +#define PIO_IRQ1_INTS_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ1_INTS_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ1_INTS_SM1_TXNFULL_LSB _u(5) #define PIO_IRQ1_INTS_SM1_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM0_TXNFULL // Description : None -#define PIO_IRQ1_INTS_SM0_TXNFULL_RESET 0x0 -#define PIO_IRQ1_INTS_SM0_TXNFULL_BITS 0x00000010 -#define PIO_IRQ1_INTS_SM0_TXNFULL_MSB 4 -#define PIO_IRQ1_INTS_SM0_TXNFULL_LSB 4 +#define PIO_IRQ1_INTS_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ1_INTS_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ1_INTS_SM0_TXNFULL_LSB _u(4) #define PIO_IRQ1_INTS_SM0_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM3_RXNEMPTY // Description : None -#define PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS 0x00000008 -#define PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB 3 -#define PIO_IRQ1_INTS_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_LSB _u(3) #define PIO_IRQ1_INTS_SM3_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM2_RXNEMPTY // Description : None -#define PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS 0x00000004 -#define PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB 2 -#define PIO_IRQ1_INTS_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_LSB _u(2) #define PIO_IRQ1_INTS_SM2_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM1_RXNEMPTY // Description : None -#define PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS 0x00000002 -#define PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB 1 -#define PIO_IRQ1_INTS_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_LSB _u(1) #define PIO_IRQ1_INTS_SM1_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM0_RXNEMPTY // Description : None -#define PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET 0x0 -#define PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS 0x00000001 -#define PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB 0 -#define PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB _u(0) #define PIO_IRQ1_INTS_SM0_RXNEMPTY_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_PIO_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pll.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pll.h index 6a21d5603..a0f5ad0ef 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pll.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pll.h @@ -18,16 +18,16 @@ // Reference clock frequency min=5MHz, max=800MHz // Feedback divider min=16, max=320 // VCO frequency min=400MHz, max=1600MHz -#define PLL_CS_OFFSET 0x00000000 -#define PLL_CS_BITS 0x8000013f -#define PLL_CS_RESET 0x00000001 +#define PLL_CS_OFFSET _u(0x00000000) +#define PLL_CS_BITS _u(0x8000013f) +#define PLL_CS_RESET _u(0x00000001) // ----------------------------------------------------------------------------- // Field : PLL_CS_LOCK // Description : PLL is locked -#define PLL_CS_LOCK_RESET 0x0 -#define PLL_CS_LOCK_BITS 0x80000000 -#define PLL_CS_LOCK_MSB 31 -#define PLL_CS_LOCK_LSB 31 +#define PLL_CS_LOCK_RESET _u(0x0) +#define PLL_CS_LOCK_BITS _u(0x80000000) +#define PLL_CS_LOCK_MSB _u(31) +#define PLL_CS_LOCK_LSB _u(31) #define PLL_CS_LOCK_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PLL_CS_BYPASS @@ -35,10 +35,10 @@ // VCO. The VCO continues to run so the user can switch between // the reference clock and the divided VCO but the output will // glitch when doing so. -#define PLL_CS_BYPASS_RESET 0x0 -#define PLL_CS_BYPASS_BITS 0x00000100 -#define PLL_CS_BYPASS_MSB 8 -#define PLL_CS_BYPASS_LSB 8 +#define PLL_CS_BYPASS_RESET _u(0x0) +#define PLL_CS_BYPASS_BITS _u(0x00000100) +#define PLL_CS_BYPASS_MSB _u(8) +#define PLL_CS_BYPASS_LSB _u(8) #define PLL_CS_BYPASS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PLL_CS_REFDIV @@ -46,65 +46,65 @@ // Behaviour is undefined for div=0. // PLL output will be unpredictable during refdiv changes, wait // for lock=1 before using it. -#define PLL_CS_REFDIV_RESET 0x01 -#define PLL_CS_REFDIV_BITS 0x0000003f -#define PLL_CS_REFDIV_MSB 5 -#define PLL_CS_REFDIV_LSB 0 +#define PLL_CS_REFDIV_RESET _u(0x01) +#define PLL_CS_REFDIV_BITS _u(0x0000003f) +#define PLL_CS_REFDIV_MSB _u(5) +#define PLL_CS_REFDIV_LSB _u(0) #define PLL_CS_REFDIV_ACCESS "RW" // ============================================================================= // Register : PLL_PWR // Description : Controls the PLL power modes. -#define PLL_PWR_OFFSET 0x00000004 -#define PLL_PWR_BITS 0x0000002d -#define PLL_PWR_RESET 0x0000002d +#define PLL_PWR_OFFSET _u(0x00000004) +#define PLL_PWR_BITS _u(0x0000002d) +#define PLL_PWR_RESET _u(0x0000002d) // ----------------------------------------------------------------------------- // Field : PLL_PWR_VCOPD // Description : PLL VCO powerdown // To save power set high when PLL output not required or // bypass=1. -#define PLL_PWR_VCOPD_RESET 0x1 -#define PLL_PWR_VCOPD_BITS 0x00000020 -#define PLL_PWR_VCOPD_MSB 5 -#define PLL_PWR_VCOPD_LSB 5 +#define PLL_PWR_VCOPD_RESET _u(0x1) +#define PLL_PWR_VCOPD_BITS _u(0x00000020) +#define PLL_PWR_VCOPD_MSB _u(5) +#define PLL_PWR_VCOPD_LSB _u(5) #define PLL_PWR_VCOPD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PLL_PWR_POSTDIVPD // Description : PLL post divider powerdown // To save power set high when PLL output not required or // bypass=1. -#define PLL_PWR_POSTDIVPD_RESET 0x1 -#define PLL_PWR_POSTDIVPD_BITS 0x00000008 -#define PLL_PWR_POSTDIVPD_MSB 3 -#define PLL_PWR_POSTDIVPD_LSB 3 +#define PLL_PWR_POSTDIVPD_RESET _u(0x1) +#define PLL_PWR_POSTDIVPD_BITS _u(0x00000008) +#define PLL_PWR_POSTDIVPD_MSB _u(3) +#define PLL_PWR_POSTDIVPD_LSB _u(3) #define PLL_PWR_POSTDIVPD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PLL_PWR_DSMPD // Description : PLL DSM powerdown // Nothing is achieved by setting this low. -#define PLL_PWR_DSMPD_RESET 0x1 -#define PLL_PWR_DSMPD_BITS 0x00000004 -#define PLL_PWR_DSMPD_MSB 2 -#define PLL_PWR_DSMPD_LSB 2 +#define PLL_PWR_DSMPD_RESET _u(0x1) +#define PLL_PWR_DSMPD_BITS _u(0x00000004) +#define PLL_PWR_DSMPD_MSB _u(2) +#define PLL_PWR_DSMPD_LSB _u(2) #define PLL_PWR_DSMPD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PLL_PWR_PD // Description : PLL powerdown // To save power set high when PLL output not required. -#define PLL_PWR_PD_RESET 0x1 -#define PLL_PWR_PD_BITS 0x00000001 -#define PLL_PWR_PD_MSB 0 -#define PLL_PWR_PD_LSB 0 +#define PLL_PWR_PD_RESET _u(0x1) +#define PLL_PWR_PD_BITS _u(0x00000001) +#define PLL_PWR_PD_MSB _u(0) +#define PLL_PWR_PD_LSB _u(0) #define PLL_PWR_PD_ACCESS "RW" // ============================================================================= // Register : PLL_FBDIV_INT // Description : Feedback divisor // (note: this PLL does not support fractional division) // see ctrl reg description for constraints -#define PLL_FBDIV_INT_OFFSET 0x00000008 -#define PLL_FBDIV_INT_BITS 0x00000fff -#define PLL_FBDIV_INT_RESET 0x00000000 -#define PLL_FBDIV_INT_MSB 11 -#define PLL_FBDIV_INT_LSB 0 +#define PLL_FBDIV_INT_OFFSET _u(0x00000008) +#define PLL_FBDIV_INT_BITS _u(0x00000fff) +#define PLL_FBDIV_INT_RESET _u(0x00000000) +#define PLL_FBDIV_INT_MSB _u(11) +#define PLL_FBDIV_INT_LSB _u(0) #define PLL_FBDIV_INT_ACCESS "RW" // ============================================================================= // Register : PLL_PRIM @@ -112,24 +112,24 @@ // (note: this PLL does not have a secondary output) // the primary output is driven from VCO divided by // postdiv1*postdiv2 -#define PLL_PRIM_OFFSET 0x0000000c -#define PLL_PRIM_BITS 0x00077000 -#define PLL_PRIM_RESET 0x00077000 +#define PLL_PRIM_OFFSET _u(0x0000000c) +#define PLL_PRIM_BITS _u(0x00077000) +#define PLL_PRIM_RESET _u(0x00077000) // ----------------------------------------------------------------------------- // Field : PLL_PRIM_POSTDIV1 // Description : divide by 1-7 -#define PLL_PRIM_POSTDIV1_RESET 0x7 -#define PLL_PRIM_POSTDIV1_BITS 0x00070000 -#define PLL_PRIM_POSTDIV1_MSB 18 -#define PLL_PRIM_POSTDIV1_LSB 16 +#define PLL_PRIM_POSTDIV1_RESET _u(0x7) +#define PLL_PRIM_POSTDIV1_BITS _u(0x00070000) +#define PLL_PRIM_POSTDIV1_MSB _u(18) +#define PLL_PRIM_POSTDIV1_LSB _u(16) #define PLL_PRIM_POSTDIV1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PLL_PRIM_POSTDIV2 // Description : divide by 1-7 -#define PLL_PRIM_POSTDIV2_RESET 0x7 -#define PLL_PRIM_POSTDIV2_BITS 0x00007000 -#define PLL_PRIM_POSTDIV2_MSB 14 -#define PLL_PRIM_POSTDIV2_LSB 12 +#define PLL_PRIM_POSTDIV2_RESET _u(0x7) +#define PLL_PRIM_POSTDIV2_BITS _u(0x00007000) +#define PLL_PRIM_POSTDIV2_MSB _u(14) +#define PLL_PRIM_POSTDIV2_LSB _u(12) #define PLL_PRIM_POSTDIV2_ACCESS "RW" // ============================================================================= #endif // HARDWARE_REGS_PLL_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/psm.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/psm.h index dacf36394..8810ae8bb 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/psm.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/psm.h @@ -14,571 +14,571 @@ // ============================================================================= // Register : PSM_FRCE_ON // Description : Force block out of reset (i.e. power it on) -#define PSM_FRCE_ON_OFFSET 0x00000000 -#define PSM_FRCE_ON_BITS 0x0001ffff -#define PSM_FRCE_ON_RESET 0x00000000 +#define PSM_FRCE_ON_OFFSET _u(0x00000000) +#define PSM_FRCE_ON_BITS _u(0x0001ffff) +#define PSM_FRCE_ON_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_PROC1 // Description : None -#define PSM_FRCE_ON_PROC1_RESET 0x0 -#define PSM_FRCE_ON_PROC1_BITS 0x00010000 -#define PSM_FRCE_ON_PROC1_MSB 16 -#define PSM_FRCE_ON_PROC1_LSB 16 +#define PSM_FRCE_ON_PROC1_RESET _u(0x0) +#define PSM_FRCE_ON_PROC1_BITS _u(0x00010000) +#define PSM_FRCE_ON_PROC1_MSB _u(16) +#define PSM_FRCE_ON_PROC1_LSB _u(16) #define PSM_FRCE_ON_PROC1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_PROC0 // Description : None -#define PSM_FRCE_ON_PROC0_RESET 0x0 -#define PSM_FRCE_ON_PROC0_BITS 0x00008000 -#define PSM_FRCE_ON_PROC0_MSB 15 -#define PSM_FRCE_ON_PROC0_LSB 15 +#define PSM_FRCE_ON_PROC0_RESET _u(0x0) +#define PSM_FRCE_ON_PROC0_BITS _u(0x00008000) +#define PSM_FRCE_ON_PROC0_MSB _u(15) +#define PSM_FRCE_ON_PROC0_LSB _u(15) #define PSM_FRCE_ON_PROC0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SIO // Description : None -#define PSM_FRCE_ON_SIO_RESET 0x0 -#define PSM_FRCE_ON_SIO_BITS 0x00004000 -#define PSM_FRCE_ON_SIO_MSB 14 -#define PSM_FRCE_ON_SIO_LSB 14 +#define PSM_FRCE_ON_SIO_RESET _u(0x0) +#define PSM_FRCE_ON_SIO_BITS _u(0x00004000) +#define PSM_FRCE_ON_SIO_MSB _u(14) +#define PSM_FRCE_ON_SIO_LSB _u(14) #define PSM_FRCE_ON_SIO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_VREG_AND_CHIP_RESET // Description : None -#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET 0x0 -#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS 0x00002000 -#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB 13 -#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_LSB 13 +#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET _u(0x0) +#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS _u(0x00002000) +#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB _u(13) +#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_LSB _u(13) #define PSM_FRCE_ON_VREG_AND_CHIP_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_XIP // Description : None -#define PSM_FRCE_ON_XIP_RESET 0x0 -#define PSM_FRCE_ON_XIP_BITS 0x00001000 -#define PSM_FRCE_ON_XIP_MSB 12 -#define PSM_FRCE_ON_XIP_LSB 12 +#define PSM_FRCE_ON_XIP_RESET _u(0x0) +#define PSM_FRCE_ON_XIP_BITS _u(0x00001000) +#define PSM_FRCE_ON_XIP_MSB _u(12) +#define PSM_FRCE_ON_XIP_LSB _u(12) #define PSM_FRCE_ON_XIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM5 // Description : None -#define PSM_FRCE_ON_SRAM5_RESET 0x0 -#define PSM_FRCE_ON_SRAM5_BITS 0x00000800 -#define PSM_FRCE_ON_SRAM5_MSB 11 -#define PSM_FRCE_ON_SRAM5_LSB 11 +#define PSM_FRCE_ON_SRAM5_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM5_BITS _u(0x00000800) +#define PSM_FRCE_ON_SRAM5_MSB _u(11) +#define PSM_FRCE_ON_SRAM5_LSB _u(11) #define PSM_FRCE_ON_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM4 // Description : None -#define PSM_FRCE_ON_SRAM4_RESET 0x0 -#define PSM_FRCE_ON_SRAM4_BITS 0x00000400 -#define PSM_FRCE_ON_SRAM4_MSB 10 -#define PSM_FRCE_ON_SRAM4_LSB 10 +#define PSM_FRCE_ON_SRAM4_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM4_BITS _u(0x00000400) +#define PSM_FRCE_ON_SRAM4_MSB _u(10) +#define PSM_FRCE_ON_SRAM4_LSB _u(10) #define PSM_FRCE_ON_SRAM4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM3 // Description : None -#define PSM_FRCE_ON_SRAM3_RESET 0x0 -#define PSM_FRCE_ON_SRAM3_BITS 0x00000200 -#define PSM_FRCE_ON_SRAM3_MSB 9 -#define PSM_FRCE_ON_SRAM3_LSB 9 +#define PSM_FRCE_ON_SRAM3_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM3_BITS _u(0x00000200) +#define PSM_FRCE_ON_SRAM3_MSB _u(9) +#define PSM_FRCE_ON_SRAM3_LSB _u(9) #define PSM_FRCE_ON_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM2 // Description : None -#define PSM_FRCE_ON_SRAM2_RESET 0x0 -#define PSM_FRCE_ON_SRAM2_BITS 0x00000100 -#define PSM_FRCE_ON_SRAM2_MSB 8 -#define PSM_FRCE_ON_SRAM2_LSB 8 +#define PSM_FRCE_ON_SRAM2_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM2_BITS _u(0x00000100) +#define PSM_FRCE_ON_SRAM2_MSB _u(8) +#define PSM_FRCE_ON_SRAM2_LSB _u(8) #define PSM_FRCE_ON_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM1 // Description : None -#define PSM_FRCE_ON_SRAM1_RESET 0x0 -#define PSM_FRCE_ON_SRAM1_BITS 0x00000080 -#define PSM_FRCE_ON_SRAM1_MSB 7 -#define PSM_FRCE_ON_SRAM1_LSB 7 +#define PSM_FRCE_ON_SRAM1_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM1_BITS _u(0x00000080) +#define PSM_FRCE_ON_SRAM1_MSB _u(7) +#define PSM_FRCE_ON_SRAM1_LSB _u(7) #define PSM_FRCE_ON_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM0 // Description : None -#define PSM_FRCE_ON_SRAM0_RESET 0x0 -#define PSM_FRCE_ON_SRAM0_BITS 0x00000040 -#define PSM_FRCE_ON_SRAM0_MSB 6 -#define PSM_FRCE_ON_SRAM0_LSB 6 +#define PSM_FRCE_ON_SRAM0_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM0_BITS _u(0x00000040) +#define PSM_FRCE_ON_SRAM0_MSB _u(6) +#define PSM_FRCE_ON_SRAM0_LSB _u(6) #define PSM_FRCE_ON_SRAM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_ROM // Description : None -#define PSM_FRCE_ON_ROM_RESET 0x0 -#define PSM_FRCE_ON_ROM_BITS 0x00000020 -#define PSM_FRCE_ON_ROM_MSB 5 -#define PSM_FRCE_ON_ROM_LSB 5 +#define PSM_FRCE_ON_ROM_RESET _u(0x0) +#define PSM_FRCE_ON_ROM_BITS _u(0x00000020) +#define PSM_FRCE_ON_ROM_MSB _u(5) +#define PSM_FRCE_ON_ROM_LSB _u(5) #define PSM_FRCE_ON_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_BUSFABRIC // Description : None -#define PSM_FRCE_ON_BUSFABRIC_RESET 0x0 -#define PSM_FRCE_ON_BUSFABRIC_BITS 0x00000010 -#define PSM_FRCE_ON_BUSFABRIC_MSB 4 -#define PSM_FRCE_ON_BUSFABRIC_LSB 4 +#define PSM_FRCE_ON_BUSFABRIC_RESET _u(0x0) +#define PSM_FRCE_ON_BUSFABRIC_BITS _u(0x00000010) +#define PSM_FRCE_ON_BUSFABRIC_MSB _u(4) +#define PSM_FRCE_ON_BUSFABRIC_LSB _u(4) #define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_RESETS // Description : None -#define PSM_FRCE_ON_RESETS_RESET 0x0 -#define PSM_FRCE_ON_RESETS_BITS 0x00000008 -#define PSM_FRCE_ON_RESETS_MSB 3 -#define PSM_FRCE_ON_RESETS_LSB 3 +#define PSM_FRCE_ON_RESETS_RESET _u(0x0) +#define PSM_FRCE_ON_RESETS_BITS _u(0x00000008) +#define PSM_FRCE_ON_RESETS_MSB _u(3) +#define PSM_FRCE_ON_RESETS_LSB _u(3) #define PSM_FRCE_ON_RESETS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_CLOCKS // Description : None -#define PSM_FRCE_ON_CLOCKS_RESET 0x0 -#define PSM_FRCE_ON_CLOCKS_BITS 0x00000004 -#define PSM_FRCE_ON_CLOCKS_MSB 2 -#define PSM_FRCE_ON_CLOCKS_LSB 2 +#define PSM_FRCE_ON_CLOCKS_RESET _u(0x0) +#define PSM_FRCE_ON_CLOCKS_BITS _u(0x00000004) +#define PSM_FRCE_ON_CLOCKS_MSB _u(2) +#define PSM_FRCE_ON_CLOCKS_LSB _u(2) #define PSM_FRCE_ON_CLOCKS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_XOSC // Description : None -#define PSM_FRCE_ON_XOSC_RESET 0x0 -#define PSM_FRCE_ON_XOSC_BITS 0x00000002 -#define PSM_FRCE_ON_XOSC_MSB 1 -#define PSM_FRCE_ON_XOSC_LSB 1 +#define PSM_FRCE_ON_XOSC_RESET _u(0x0) +#define PSM_FRCE_ON_XOSC_BITS _u(0x00000002) +#define PSM_FRCE_ON_XOSC_MSB _u(1) +#define PSM_FRCE_ON_XOSC_LSB _u(1) #define PSM_FRCE_ON_XOSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_ROSC // Description : None -#define PSM_FRCE_ON_ROSC_RESET 0x0 -#define PSM_FRCE_ON_ROSC_BITS 0x00000001 -#define PSM_FRCE_ON_ROSC_MSB 0 -#define PSM_FRCE_ON_ROSC_LSB 0 +#define PSM_FRCE_ON_ROSC_RESET _u(0x0) +#define PSM_FRCE_ON_ROSC_BITS _u(0x00000001) +#define PSM_FRCE_ON_ROSC_MSB _u(0) +#define PSM_FRCE_ON_ROSC_LSB _u(0) #define PSM_FRCE_ON_ROSC_ACCESS "RW" // ============================================================================= // Register : PSM_FRCE_OFF // Description : Force into reset (i.e. power it off) -#define PSM_FRCE_OFF_OFFSET 0x00000004 -#define PSM_FRCE_OFF_BITS 0x0001ffff -#define PSM_FRCE_OFF_RESET 0x00000000 +#define PSM_FRCE_OFF_OFFSET _u(0x00000004) +#define PSM_FRCE_OFF_BITS _u(0x0001ffff) +#define PSM_FRCE_OFF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_PROC1 // Description : None -#define PSM_FRCE_OFF_PROC1_RESET 0x0 -#define PSM_FRCE_OFF_PROC1_BITS 0x00010000 -#define PSM_FRCE_OFF_PROC1_MSB 16 -#define PSM_FRCE_OFF_PROC1_LSB 16 +#define PSM_FRCE_OFF_PROC1_RESET _u(0x0) +#define PSM_FRCE_OFF_PROC1_BITS _u(0x00010000) +#define PSM_FRCE_OFF_PROC1_MSB _u(16) +#define PSM_FRCE_OFF_PROC1_LSB _u(16) #define PSM_FRCE_OFF_PROC1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_PROC0 // Description : None -#define PSM_FRCE_OFF_PROC0_RESET 0x0 -#define PSM_FRCE_OFF_PROC0_BITS 0x00008000 -#define PSM_FRCE_OFF_PROC0_MSB 15 -#define PSM_FRCE_OFF_PROC0_LSB 15 +#define PSM_FRCE_OFF_PROC0_RESET _u(0x0) +#define PSM_FRCE_OFF_PROC0_BITS _u(0x00008000) +#define PSM_FRCE_OFF_PROC0_MSB _u(15) +#define PSM_FRCE_OFF_PROC0_LSB _u(15) #define PSM_FRCE_OFF_PROC0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SIO // Description : None -#define PSM_FRCE_OFF_SIO_RESET 0x0 -#define PSM_FRCE_OFF_SIO_BITS 0x00004000 -#define PSM_FRCE_OFF_SIO_MSB 14 -#define PSM_FRCE_OFF_SIO_LSB 14 +#define PSM_FRCE_OFF_SIO_RESET _u(0x0) +#define PSM_FRCE_OFF_SIO_BITS _u(0x00004000) +#define PSM_FRCE_OFF_SIO_MSB _u(14) +#define PSM_FRCE_OFF_SIO_LSB _u(14) #define PSM_FRCE_OFF_SIO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_VREG_AND_CHIP_RESET // Description : None -#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET 0x0 -#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS 0x00002000 -#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB 13 -#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_LSB 13 +#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET _u(0x0) +#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS _u(0x00002000) +#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB _u(13) +#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_LSB _u(13) #define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_XIP // Description : None -#define PSM_FRCE_OFF_XIP_RESET 0x0 -#define PSM_FRCE_OFF_XIP_BITS 0x00001000 -#define PSM_FRCE_OFF_XIP_MSB 12 -#define PSM_FRCE_OFF_XIP_LSB 12 +#define PSM_FRCE_OFF_XIP_RESET _u(0x0) +#define PSM_FRCE_OFF_XIP_BITS _u(0x00001000) +#define PSM_FRCE_OFF_XIP_MSB _u(12) +#define PSM_FRCE_OFF_XIP_LSB _u(12) #define PSM_FRCE_OFF_XIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM5 // Description : None -#define PSM_FRCE_OFF_SRAM5_RESET 0x0 -#define PSM_FRCE_OFF_SRAM5_BITS 0x00000800 -#define PSM_FRCE_OFF_SRAM5_MSB 11 -#define PSM_FRCE_OFF_SRAM5_LSB 11 +#define PSM_FRCE_OFF_SRAM5_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM5_BITS _u(0x00000800) +#define PSM_FRCE_OFF_SRAM5_MSB _u(11) +#define PSM_FRCE_OFF_SRAM5_LSB _u(11) #define PSM_FRCE_OFF_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM4 // Description : None -#define PSM_FRCE_OFF_SRAM4_RESET 0x0 -#define PSM_FRCE_OFF_SRAM4_BITS 0x00000400 -#define PSM_FRCE_OFF_SRAM4_MSB 10 -#define PSM_FRCE_OFF_SRAM4_LSB 10 +#define PSM_FRCE_OFF_SRAM4_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM4_BITS _u(0x00000400) +#define PSM_FRCE_OFF_SRAM4_MSB _u(10) +#define PSM_FRCE_OFF_SRAM4_LSB _u(10) #define PSM_FRCE_OFF_SRAM4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM3 // Description : None -#define PSM_FRCE_OFF_SRAM3_RESET 0x0 -#define PSM_FRCE_OFF_SRAM3_BITS 0x00000200 -#define PSM_FRCE_OFF_SRAM3_MSB 9 -#define PSM_FRCE_OFF_SRAM3_LSB 9 +#define PSM_FRCE_OFF_SRAM3_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM3_BITS _u(0x00000200) +#define PSM_FRCE_OFF_SRAM3_MSB _u(9) +#define PSM_FRCE_OFF_SRAM3_LSB _u(9) #define PSM_FRCE_OFF_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM2 // Description : None -#define PSM_FRCE_OFF_SRAM2_RESET 0x0 -#define PSM_FRCE_OFF_SRAM2_BITS 0x00000100 -#define PSM_FRCE_OFF_SRAM2_MSB 8 -#define PSM_FRCE_OFF_SRAM2_LSB 8 +#define PSM_FRCE_OFF_SRAM2_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM2_BITS _u(0x00000100) +#define PSM_FRCE_OFF_SRAM2_MSB _u(8) +#define PSM_FRCE_OFF_SRAM2_LSB _u(8) #define PSM_FRCE_OFF_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM1 // Description : None -#define PSM_FRCE_OFF_SRAM1_RESET 0x0 -#define PSM_FRCE_OFF_SRAM1_BITS 0x00000080 -#define PSM_FRCE_OFF_SRAM1_MSB 7 -#define PSM_FRCE_OFF_SRAM1_LSB 7 +#define PSM_FRCE_OFF_SRAM1_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM1_BITS _u(0x00000080) +#define PSM_FRCE_OFF_SRAM1_MSB _u(7) +#define PSM_FRCE_OFF_SRAM1_LSB _u(7) #define PSM_FRCE_OFF_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM0 // Description : None -#define PSM_FRCE_OFF_SRAM0_RESET 0x0 -#define PSM_FRCE_OFF_SRAM0_BITS 0x00000040 -#define PSM_FRCE_OFF_SRAM0_MSB 6 -#define PSM_FRCE_OFF_SRAM0_LSB 6 +#define PSM_FRCE_OFF_SRAM0_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM0_BITS _u(0x00000040) +#define PSM_FRCE_OFF_SRAM0_MSB _u(6) +#define PSM_FRCE_OFF_SRAM0_LSB _u(6) #define PSM_FRCE_OFF_SRAM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_ROM // Description : None -#define PSM_FRCE_OFF_ROM_RESET 0x0 -#define PSM_FRCE_OFF_ROM_BITS 0x00000020 -#define PSM_FRCE_OFF_ROM_MSB 5 -#define PSM_FRCE_OFF_ROM_LSB 5 +#define PSM_FRCE_OFF_ROM_RESET _u(0x0) +#define PSM_FRCE_OFF_ROM_BITS _u(0x00000020) +#define PSM_FRCE_OFF_ROM_MSB _u(5) +#define PSM_FRCE_OFF_ROM_LSB _u(5) #define PSM_FRCE_OFF_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_BUSFABRIC // Description : None -#define PSM_FRCE_OFF_BUSFABRIC_RESET 0x0 -#define PSM_FRCE_OFF_BUSFABRIC_BITS 0x00000010 -#define PSM_FRCE_OFF_BUSFABRIC_MSB 4 -#define PSM_FRCE_OFF_BUSFABRIC_LSB 4 +#define PSM_FRCE_OFF_BUSFABRIC_RESET _u(0x0) +#define PSM_FRCE_OFF_BUSFABRIC_BITS _u(0x00000010) +#define PSM_FRCE_OFF_BUSFABRIC_MSB _u(4) +#define PSM_FRCE_OFF_BUSFABRIC_LSB _u(4) #define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_RESETS // Description : None -#define PSM_FRCE_OFF_RESETS_RESET 0x0 -#define PSM_FRCE_OFF_RESETS_BITS 0x00000008 -#define PSM_FRCE_OFF_RESETS_MSB 3 -#define PSM_FRCE_OFF_RESETS_LSB 3 +#define PSM_FRCE_OFF_RESETS_RESET _u(0x0) +#define PSM_FRCE_OFF_RESETS_BITS _u(0x00000008) +#define PSM_FRCE_OFF_RESETS_MSB _u(3) +#define PSM_FRCE_OFF_RESETS_LSB _u(3) #define PSM_FRCE_OFF_RESETS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_CLOCKS // Description : None -#define PSM_FRCE_OFF_CLOCKS_RESET 0x0 -#define PSM_FRCE_OFF_CLOCKS_BITS 0x00000004 -#define PSM_FRCE_OFF_CLOCKS_MSB 2 -#define PSM_FRCE_OFF_CLOCKS_LSB 2 +#define PSM_FRCE_OFF_CLOCKS_RESET _u(0x0) +#define PSM_FRCE_OFF_CLOCKS_BITS _u(0x00000004) +#define PSM_FRCE_OFF_CLOCKS_MSB _u(2) +#define PSM_FRCE_OFF_CLOCKS_LSB _u(2) #define PSM_FRCE_OFF_CLOCKS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_XOSC // Description : None -#define PSM_FRCE_OFF_XOSC_RESET 0x0 -#define PSM_FRCE_OFF_XOSC_BITS 0x00000002 -#define PSM_FRCE_OFF_XOSC_MSB 1 -#define PSM_FRCE_OFF_XOSC_LSB 1 +#define PSM_FRCE_OFF_XOSC_RESET _u(0x0) +#define PSM_FRCE_OFF_XOSC_BITS _u(0x00000002) +#define PSM_FRCE_OFF_XOSC_MSB _u(1) +#define PSM_FRCE_OFF_XOSC_LSB _u(1) #define PSM_FRCE_OFF_XOSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_ROSC // Description : None -#define PSM_FRCE_OFF_ROSC_RESET 0x0 -#define PSM_FRCE_OFF_ROSC_BITS 0x00000001 -#define PSM_FRCE_OFF_ROSC_MSB 0 -#define PSM_FRCE_OFF_ROSC_LSB 0 +#define PSM_FRCE_OFF_ROSC_RESET _u(0x0) +#define PSM_FRCE_OFF_ROSC_BITS _u(0x00000001) +#define PSM_FRCE_OFF_ROSC_MSB _u(0) +#define PSM_FRCE_OFF_ROSC_LSB _u(0) #define PSM_FRCE_OFF_ROSC_ACCESS "RW" // ============================================================================= // Register : PSM_WDSEL // Description : Set to 1 if this peripheral should be reset when the watchdog // fires. -#define PSM_WDSEL_OFFSET 0x00000008 -#define PSM_WDSEL_BITS 0x0001ffff -#define PSM_WDSEL_RESET 0x00000000 +#define PSM_WDSEL_OFFSET _u(0x00000008) +#define PSM_WDSEL_BITS _u(0x0001ffff) +#define PSM_WDSEL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_PROC1 // Description : None -#define PSM_WDSEL_PROC1_RESET 0x0 -#define PSM_WDSEL_PROC1_BITS 0x00010000 -#define PSM_WDSEL_PROC1_MSB 16 -#define PSM_WDSEL_PROC1_LSB 16 +#define PSM_WDSEL_PROC1_RESET _u(0x0) +#define PSM_WDSEL_PROC1_BITS _u(0x00010000) +#define PSM_WDSEL_PROC1_MSB _u(16) +#define PSM_WDSEL_PROC1_LSB _u(16) #define PSM_WDSEL_PROC1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_PROC0 // Description : None -#define PSM_WDSEL_PROC0_RESET 0x0 -#define PSM_WDSEL_PROC0_BITS 0x00008000 -#define PSM_WDSEL_PROC0_MSB 15 -#define PSM_WDSEL_PROC0_LSB 15 +#define PSM_WDSEL_PROC0_RESET _u(0x0) +#define PSM_WDSEL_PROC0_BITS _u(0x00008000) +#define PSM_WDSEL_PROC0_MSB _u(15) +#define PSM_WDSEL_PROC0_LSB _u(15) #define PSM_WDSEL_PROC0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SIO // Description : None -#define PSM_WDSEL_SIO_RESET 0x0 -#define PSM_WDSEL_SIO_BITS 0x00004000 -#define PSM_WDSEL_SIO_MSB 14 -#define PSM_WDSEL_SIO_LSB 14 +#define PSM_WDSEL_SIO_RESET _u(0x0) +#define PSM_WDSEL_SIO_BITS _u(0x00004000) +#define PSM_WDSEL_SIO_MSB _u(14) +#define PSM_WDSEL_SIO_LSB _u(14) #define PSM_WDSEL_SIO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_VREG_AND_CHIP_RESET // Description : None -#define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET 0x0 -#define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS 0x00002000 -#define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB 13 -#define PSM_WDSEL_VREG_AND_CHIP_RESET_LSB 13 +#define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET _u(0x0) +#define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS _u(0x00002000) +#define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB _u(13) +#define PSM_WDSEL_VREG_AND_CHIP_RESET_LSB _u(13) #define PSM_WDSEL_VREG_AND_CHIP_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_XIP // Description : None -#define PSM_WDSEL_XIP_RESET 0x0 -#define PSM_WDSEL_XIP_BITS 0x00001000 -#define PSM_WDSEL_XIP_MSB 12 -#define PSM_WDSEL_XIP_LSB 12 +#define PSM_WDSEL_XIP_RESET _u(0x0) +#define PSM_WDSEL_XIP_BITS _u(0x00001000) +#define PSM_WDSEL_XIP_MSB _u(12) +#define PSM_WDSEL_XIP_LSB _u(12) #define PSM_WDSEL_XIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM5 // Description : None -#define PSM_WDSEL_SRAM5_RESET 0x0 -#define PSM_WDSEL_SRAM5_BITS 0x00000800 -#define PSM_WDSEL_SRAM5_MSB 11 -#define PSM_WDSEL_SRAM5_LSB 11 +#define PSM_WDSEL_SRAM5_RESET _u(0x0) +#define PSM_WDSEL_SRAM5_BITS _u(0x00000800) +#define PSM_WDSEL_SRAM5_MSB _u(11) +#define PSM_WDSEL_SRAM5_LSB _u(11) #define PSM_WDSEL_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM4 // Description : None -#define PSM_WDSEL_SRAM4_RESET 0x0 -#define PSM_WDSEL_SRAM4_BITS 0x00000400 -#define PSM_WDSEL_SRAM4_MSB 10 -#define PSM_WDSEL_SRAM4_LSB 10 +#define PSM_WDSEL_SRAM4_RESET _u(0x0) +#define PSM_WDSEL_SRAM4_BITS _u(0x00000400) +#define PSM_WDSEL_SRAM4_MSB _u(10) +#define PSM_WDSEL_SRAM4_LSB _u(10) #define PSM_WDSEL_SRAM4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM3 // Description : None -#define PSM_WDSEL_SRAM3_RESET 0x0 -#define PSM_WDSEL_SRAM3_BITS 0x00000200 -#define PSM_WDSEL_SRAM3_MSB 9 -#define PSM_WDSEL_SRAM3_LSB 9 +#define PSM_WDSEL_SRAM3_RESET _u(0x0) +#define PSM_WDSEL_SRAM3_BITS _u(0x00000200) +#define PSM_WDSEL_SRAM3_MSB _u(9) +#define PSM_WDSEL_SRAM3_LSB _u(9) #define PSM_WDSEL_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM2 // Description : None -#define PSM_WDSEL_SRAM2_RESET 0x0 -#define PSM_WDSEL_SRAM2_BITS 0x00000100 -#define PSM_WDSEL_SRAM2_MSB 8 -#define PSM_WDSEL_SRAM2_LSB 8 +#define PSM_WDSEL_SRAM2_RESET _u(0x0) +#define PSM_WDSEL_SRAM2_BITS _u(0x00000100) +#define PSM_WDSEL_SRAM2_MSB _u(8) +#define PSM_WDSEL_SRAM2_LSB _u(8) #define PSM_WDSEL_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM1 // Description : None -#define PSM_WDSEL_SRAM1_RESET 0x0 -#define PSM_WDSEL_SRAM1_BITS 0x00000080 -#define PSM_WDSEL_SRAM1_MSB 7 -#define PSM_WDSEL_SRAM1_LSB 7 +#define PSM_WDSEL_SRAM1_RESET _u(0x0) +#define PSM_WDSEL_SRAM1_BITS _u(0x00000080) +#define PSM_WDSEL_SRAM1_MSB _u(7) +#define PSM_WDSEL_SRAM1_LSB _u(7) #define PSM_WDSEL_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM0 // Description : None -#define PSM_WDSEL_SRAM0_RESET 0x0 -#define PSM_WDSEL_SRAM0_BITS 0x00000040 -#define PSM_WDSEL_SRAM0_MSB 6 -#define PSM_WDSEL_SRAM0_LSB 6 +#define PSM_WDSEL_SRAM0_RESET _u(0x0) +#define PSM_WDSEL_SRAM0_BITS _u(0x00000040) +#define PSM_WDSEL_SRAM0_MSB _u(6) +#define PSM_WDSEL_SRAM0_LSB _u(6) #define PSM_WDSEL_SRAM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_ROM // Description : None -#define PSM_WDSEL_ROM_RESET 0x0 -#define PSM_WDSEL_ROM_BITS 0x00000020 -#define PSM_WDSEL_ROM_MSB 5 -#define PSM_WDSEL_ROM_LSB 5 +#define PSM_WDSEL_ROM_RESET _u(0x0) +#define PSM_WDSEL_ROM_BITS _u(0x00000020) +#define PSM_WDSEL_ROM_MSB _u(5) +#define PSM_WDSEL_ROM_LSB _u(5) #define PSM_WDSEL_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_BUSFABRIC // Description : None -#define PSM_WDSEL_BUSFABRIC_RESET 0x0 -#define PSM_WDSEL_BUSFABRIC_BITS 0x00000010 -#define PSM_WDSEL_BUSFABRIC_MSB 4 -#define PSM_WDSEL_BUSFABRIC_LSB 4 +#define PSM_WDSEL_BUSFABRIC_RESET _u(0x0) +#define PSM_WDSEL_BUSFABRIC_BITS _u(0x00000010) +#define PSM_WDSEL_BUSFABRIC_MSB _u(4) +#define PSM_WDSEL_BUSFABRIC_LSB _u(4) #define PSM_WDSEL_BUSFABRIC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_RESETS // Description : None -#define PSM_WDSEL_RESETS_RESET 0x0 -#define PSM_WDSEL_RESETS_BITS 0x00000008 -#define PSM_WDSEL_RESETS_MSB 3 -#define PSM_WDSEL_RESETS_LSB 3 +#define PSM_WDSEL_RESETS_RESET _u(0x0) +#define PSM_WDSEL_RESETS_BITS _u(0x00000008) +#define PSM_WDSEL_RESETS_MSB _u(3) +#define PSM_WDSEL_RESETS_LSB _u(3) #define PSM_WDSEL_RESETS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_CLOCKS // Description : None -#define PSM_WDSEL_CLOCKS_RESET 0x0 -#define PSM_WDSEL_CLOCKS_BITS 0x00000004 -#define PSM_WDSEL_CLOCKS_MSB 2 -#define PSM_WDSEL_CLOCKS_LSB 2 +#define PSM_WDSEL_CLOCKS_RESET _u(0x0) +#define PSM_WDSEL_CLOCKS_BITS _u(0x00000004) +#define PSM_WDSEL_CLOCKS_MSB _u(2) +#define PSM_WDSEL_CLOCKS_LSB _u(2) #define PSM_WDSEL_CLOCKS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_XOSC // Description : None -#define PSM_WDSEL_XOSC_RESET 0x0 -#define PSM_WDSEL_XOSC_BITS 0x00000002 -#define PSM_WDSEL_XOSC_MSB 1 -#define PSM_WDSEL_XOSC_LSB 1 +#define PSM_WDSEL_XOSC_RESET _u(0x0) +#define PSM_WDSEL_XOSC_BITS _u(0x00000002) +#define PSM_WDSEL_XOSC_MSB _u(1) +#define PSM_WDSEL_XOSC_LSB _u(1) #define PSM_WDSEL_XOSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_ROSC // Description : None -#define PSM_WDSEL_ROSC_RESET 0x0 -#define PSM_WDSEL_ROSC_BITS 0x00000001 -#define PSM_WDSEL_ROSC_MSB 0 -#define PSM_WDSEL_ROSC_LSB 0 +#define PSM_WDSEL_ROSC_RESET _u(0x0) +#define PSM_WDSEL_ROSC_BITS _u(0x00000001) +#define PSM_WDSEL_ROSC_MSB _u(0) +#define PSM_WDSEL_ROSC_LSB _u(0) #define PSM_WDSEL_ROSC_ACCESS "RW" // ============================================================================= // Register : PSM_DONE // Description : Indicates the peripheral's registers are ready to access. -#define PSM_DONE_OFFSET 0x0000000c -#define PSM_DONE_BITS 0x0001ffff -#define PSM_DONE_RESET 0x00000000 +#define PSM_DONE_OFFSET _u(0x0000000c) +#define PSM_DONE_BITS _u(0x0001ffff) +#define PSM_DONE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PSM_DONE_PROC1 // Description : None -#define PSM_DONE_PROC1_RESET 0x0 -#define PSM_DONE_PROC1_BITS 0x00010000 -#define PSM_DONE_PROC1_MSB 16 -#define PSM_DONE_PROC1_LSB 16 +#define PSM_DONE_PROC1_RESET _u(0x0) +#define PSM_DONE_PROC1_BITS _u(0x00010000) +#define PSM_DONE_PROC1_MSB _u(16) +#define PSM_DONE_PROC1_LSB _u(16) #define PSM_DONE_PROC1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_PROC0 // Description : None -#define PSM_DONE_PROC0_RESET 0x0 -#define PSM_DONE_PROC0_BITS 0x00008000 -#define PSM_DONE_PROC0_MSB 15 -#define PSM_DONE_PROC0_LSB 15 +#define PSM_DONE_PROC0_RESET _u(0x0) +#define PSM_DONE_PROC0_BITS _u(0x00008000) +#define PSM_DONE_PROC0_MSB _u(15) +#define PSM_DONE_PROC0_LSB _u(15) #define PSM_DONE_PROC0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SIO // Description : None -#define PSM_DONE_SIO_RESET 0x0 -#define PSM_DONE_SIO_BITS 0x00004000 -#define PSM_DONE_SIO_MSB 14 -#define PSM_DONE_SIO_LSB 14 +#define PSM_DONE_SIO_RESET _u(0x0) +#define PSM_DONE_SIO_BITS _u(0x00004000) +#define PSM_DONE_SIO_MSB _u(14) +#define PSM_DONE_SIO_LSB _u(14) #define PSM_DONE_SIO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_VREG_AND_CHIP_RESET // Description : None -#define PSM_DONE_VREG_AND_CHIP_RESET_RESET 0x0 -#define PSM_DONE_VREG_AND_CHIP_RESET_BITS 0x00002000 -#define PSM_DONE_VREG_AND_CHIP_RESET_MSB 13 -#define PSM_DONE_VREG_AND_CHIP_RESET_LSB 13 +#define PSM_DONE_VREG_AND_CHIP_RESET_RESET _u(0x0) +#define PSM_DONE_VREG_AND_CHIP_RESET_BITS _u(0x00002000) +#define PSM_DONE_VREG_AND_CHIP_RESET_MSB _u(13) +#define PSM_DONE_VREG_AND_CHIP_RESET_LSB _u(13) #define PSM_DONE_VREG_AND_CHIP_RESET_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_XIP // Description : None -#define PSM_DONE_XIP_RESET 0x0 -#define PSM_DONE_XIP_BITS 0x00001000 -#define PSM_DONE_XIP_MSB 12 -#define PSM_DONE_XIP_LSB 12 +#define PSM_DONE_XIP_RESET _u(0x0) +#define PSM_DONE_XIP_BITS _u(0x00001000) +#define PSM_DONE_XIP_MSB _u(12) +#define PSM_DONE_XIP_LSB _u(12) #define PSM_DONE_XIP_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM5 // Description : None -#define PSM_DONE_SRAM5_RESET 0x0 -#define PSM_DONE_SRAM5_BITS 0x00000800 -#define PSM_DONE_SRAM5_MSB 11 -#define PSM_DONE_SRAM5_LSB 11 +#define PSM_DONE_SRAM5_RESET _u(0x0) +#define PSM_DONE_SRAM5_BITS _u(0x00000800) +#define PSM_DONE_SRAM5_MSB _u(11) +#define PSM_DONE_SRAM5_LSB _u(11) #define PSM_DONE_SRAM5_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM4 // Description : None -#define PSM_DONE_SRAM4_RESET 0x0 -#define PSM_DONE_SRAM4_BITS 0x00000400 -#define PSM_DONE_SRAM4_MSB 10 -#define PSM_DONE_SRAM4_LSB 10 +#define PSM_DONE_SRAM4_RESET _u(0x0) +#define PSM_DONE_SRAM4_BITS _u(0x00000400) +#define PSM_DONE_SRAM4_MSB _u(10) +#define PSM_DONE_SRAM4_LSB _u(10) #define PSM_DONE_SRAM4_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM3 // Description : None -#define PSM_DONE_SRAM3_RESET 0x0 -#define PSM_DONE_SRAM3_BITS 0x00000200 -#define PSM_DONE_SRAM3_MSB 9 -#define PSM_DONE_SRAM3_LSB 9 +#define PSM_DONE_SRAM3_RESET _u(0x0) +#define PSM_DONE_SRAM3_BITS _u(0x00000200) +#define PSM_DONE_SRAM3_MSB _u(9) +#define PSM_DONE_SRAM3_LSB _u(9) #define PSM_DONE_SRAM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM2 // Description : None -#define PSM_DONE_SRAM2_RESET 0x0 -#define PSM_DONE_SRAM2_BITS 0x00000100 -#define PSM_DONE_SRAM2_MSB 8 -#define PSM_DONE_SRAM2_LSB 8 +#define PSM_DONE_SRAM2_RESET _u(0x0) +#define PSM_DONE_SRAM2_BITS _u(0x00000100) +#define PSM_DONE_SRAM2_MSB _u(8) +#define PSM_DONE_SRAM2_LSB _u(8) #define PSM_DONE_SRAM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM1 // Description : None -#define PSM_DONE_SRAM1_RESET 0x0 -#define PSM_DONE_SRAM1_BITS 0x00000080 -#define PSM_DONE_SRAM1_MSB 7 -#define PSM_DONE_SRAM1_LSB 7 +#define PSM_DONE_SRAM1_RESET _u(0x0) +#define PSM_DONE_SRAM1_BITS _u(0x00000080) +#define PSM_DONE_SRAM1_MSB _u(7) +#define PSM_DONE_SRAM1_LSB _u(7) #define PSM_DONE_SRAM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM0 // Description : None -#define PSM_DONE_SRAM0_RESET 0x0 -#define PSM_DONE_SRAM0_BITS 0x00000040 -#define PSM_DONE_SRAM0_MSB 6 -#define PSM_DONE_SRAM0_LSB 6 +#define PSM_DONE_SRAM0_RESET _u(0x0) +#define PSM_DONE_SRAM0_BITS _u(0x00000040) +#define PSM_DONE_SRAM0_MSB _u(6) +#define PSM_DONE_SRAM0_LSB _u(6) #define PSM_DONE_SRAM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_ROM // Description : None -#define PSM_DONE_ROM_RESET 0x0 -#define PSM_DONE_ROM_BITS 0x00000020 -#define PSM_DONE_ROM_MSB 5 -#define PSM_DONE_ROM_LSB 5 +#define PSM_DONE_ROM_RESET _u(0x0) +#define PSM_DONE_ROM_BITS _u(0x00000020) +#define PSM_DONE_ROM_MSB _u(5) +#define PSM_DONE_ROM_LSB _u(5) #define PSM_DONE_ROM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_BUSFABRIC // Description : None -#define PSM_DONE_BUSFABRIC_RESET 0x0 -#define PSM_DONE_BUSFABRIC_BITS 0x00000010 -#define PSM_DONE_BUSFABRIC_MSB 4 -#define PSM_DONE_BUSFABRIC_LSB 4 +#define PSM_DONE_BUSFABRIC_RESET _u(0x0) +#define PSM_DONE_BUSFABRIC_BITS _u(0x00000010) +#define PSM_DONE_BUSFABRIC_MSB _u(4) +#define PSM_DONE_BUSFABRIC_LSB _u(4) #define PSM_DONE_BUSFABRIC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_RESETS // Description : None -#define PSM_DONE_RESETS_RESET 0x0 -#define PSM_DONE_RESETS_BITS 0x00000008 -#define PSM_DONE_RESETS_MSB 3 -#define PSM_DONE_RESETS_LSB 3 +#define PSM_DONE_RESETS_RESET _u(0x0) +#define PSM_DONE_RESETS_BITS _u(0x00000008) +#define PSM_DONE_RESETS_MSB _u(3) +#define PSM_DONE_RESETS_LSB _u(3) #define PSM_DONE_RESETS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_CLOCKS // Description : None -#define PSM_DONE_CLOCKS_RESET 0x0 -#define PSM_DONE_CLOCKS_BITS 0x00000004 -#define PSM_DONE_CLOCKS_MSB 2 -#define PSM_DONE_CLOCKS_LSB 2 +#define PSM_DONE_CLOCKS_RESET _u(0x0) +#define PSM_DONE_CLOCKS_BITS _u(0x00000004) +#define PSM_DONE_CLOCKS_MSB _u(2) +#define PSM_DONE_CLOCKS_LSB _u(2) #define PSM_DONE_CLOCKS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_XOSC // Description : None -#define PSM_DONE_XOSC_RESET 0x0 -#define PSM_DONE_XOSC_BITS 0x00000002 -#define PSM_DONE_XOSC_MSB 1 -#define PSM_DONE_XOSC_LSB 1 +#define PSM_DONE_XOSC_RESET _u(0x0) +#define PSM_DONE_XOSC_BITS _u(0x00000002) +#define PSM_DONE_XOSC_MSB _u(1) +#define PSM_DONE_XOSC_LSB _u(1) #define PSM_DONE_XOSC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_ROSC // Description : None -#define PSM_DONE_ROSC_RESET 0x0 -#define PSM_DONE_ROSC_BITS 0x00000001 -#define PSM_DONE_ROSC_MSB 0 -#define PSM_DONE_ROSC_LSB 0 +#define PSM_DONE_ROSC_RESET _u(0x0) +#define PSM_DONE_ROSC_BITS _u(0x00000001) +#define PSM_DONE_ROSC_MSB _u(0) +#define PSM_DONE_ROSC_LSB _u(0) #define PSM_DONE_ROSC_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_PSM_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pwm.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pwm.h index 01e2e5c21..a85359787 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pwm.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/pwm.h @@ -14,9 +14,9 @@ // ============================================================================= // Register : PWM_CH0_CSR // Description : Control and status register -#define PWM_CH0_CSR_OFFSET 0x00000000 -#define PWM_CH0_CSR_BITS 0x000000ff -#define PWM_CH0_CSR_RESET 0x00000000 +#define PWM_CH0_CSR_OFFSET _u(0x00000000) +#define PWM_CH0_CSR_BITS _u(0x000000ff) +#define PWM_CH0_CSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_PH_ADV // Description : Advance the phase of the counter by 1 count, while it is @@ -24,10 +24,10 @@ // Self-clearing. Write a 1, and poll until low. Counter must be // running // at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH0_CSR_PH_ADV_RESET 0x0 -#define PWM_CH0_CSR_PH_ADV_BITS 0x00000080 -#define PWM_CH0_CSR_PH_ADV_MSB 7 -#define PWM_CH0_CSR_PH_ADV_LSB 7 +#define PWM_CH0_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH0_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH0_CSR_PH_ADV_MSB _u(7) +#define PWM_CH0_CSR_PH_ADV_LSB _u(7) #define PWM_CH0_CSR_PH_ADV_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_PH_RET @@ -35,10 +35,10 @@ // running. // Self-clearing. Write a 1, and poll until low. Counter must be // running. -#define PWM_CH0_CSR_PH_RET_RESET 0x0 -#define PWM_CH0_CSR_PH_RET_BITS 0x00000040 -#define PWM_CH0_CSR_PH_RET_MSB 6 -#define PWM_CH0_CSR_PH_RET_LSB 6 +#define PWM_CH0_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH0_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH0_CSR_PH_RET_MSB _u(6) +#define PWM_CH0_CSR_PH_RET_LSB _u(6) #define PWM_CH0_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_DIVMODE @@ -48,117 +48,117 @@ // 0x2 -> Counter advances with each rising edge of the PWM B pin. // 0x3 -> Counter advances with each falling edge of the PWM B // pin. -#define PWM_CH0_CSR_DIVMODE_RESET 0x0 -#define PWM_CH0_CSR_DIVMODE_BITS 0x00000030 -#define PWM_CH0_CSR_DIVMODE_MSB 5 -#define PWM_CH0_CSR_DIVMODE_LSB 4 +#define PWM_CH0_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH0_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH0_CSR_DIVMODE_MSB _u(5) +#define PWM_CH0_CSR_DIVMODE_LSB _u(4) #define PWM_CH0_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH0_CSR_DIVMODE_VALUE_DIV 0x0 -#define PWM_CH0_CSR_DIVMODE_VALUE_LEVEL 0x1 -#define PWM_CH0_CSR_DIVMODE_VALUE_RISE 0x2 -#define PWM_CH0_CSR_DIVMODE_VALUE_FALL 0x3 +#define PWM_CH0_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH0_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH0_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH0_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_B_INV // Description : Invert output B -#define PWM_CH0_CSR_B_INV_RESET 0x0 -#define PWM_CH0_CSR_B_INV_BITS 0x00000008 -#define PWM_CH0_CSR_B_INV_MSB 3 -#define PWM_CH0_CSR_B_INV_LSB 3 +#define PWM_CH0_CSR_B_INV_RESET _u(0x0) +#define PWM_CH0_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH0_CSR_B_INV_MSB _u(3) +#define PWM_CH0_CSR_B_INV_LSB _u(3) #define PWM_CH0_CSR_B_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_A_INV // Description : Invert output A -#define PWM_CH0_CSR_A_INV_RESET 0x0 -#define PWM_CH0_CSR_A_INV_BITS 0x00000004 -#define PWM_CH0_CSR_A_INV_MSB 2 -#define PWM_CH0_CSR_A_INV_LSB 2 +#define PWM_CH0_CSR_A_INV_RESET _u(0x0) +#define PWM_CH0_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH0_CSR_A_INV_MSB _u(2) +#define PWM_CH0_CSR_A_INV_LSB _u(2) #define PWM_CH0_CSR_A_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_PH_CORRECT // Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH0_CSR_PH_CORRECT_RESET 0x0 -#define PWM_CH0_CSR_PH_CORRECT_BITS 0x00000002 -#define PWM_CH0_CSR_PH_CORRECT_MSB 1 -#define PWM_CH0_CSR_PH_CORRECT_LSB 1 +#define PWM_CH0_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH0_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH0_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH0_CSR_PH_CORRECT_LSB _u(1) #define PWM_CH0_CSR_PH_CORRECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_EN // Description : Enable the PWM channel. -#define PWM_CH0_CSR_EN_RESET 0x0 -#define PWM_CH0_CSR_EN_BITS 0x00000001 -#define PWM_CH0_CSR_EN_MSB 0 -#define PWM_CH0_CSR_EN_LSB 0 +#define PWM_CH0_CSR_EN_RESET _u(0x0) +#define PWM_CH0_CSR_EN_BITS _u(0x00000001) +#define PWM_CH0_CSR_EN_MSB _u(0) +#define PWM_CH0_CSR_EN_LSB _u(0) #define PWM_CH0_CSR_EN_ACCESS "RW" // ============================================================================= // Register : PWM_CH0_DIV // Description : INT and FRAC form a fixed-point fractional number. // Counting rate is system clock frequency divided by this number. // Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH0_DIV_OFFSET 0x00000004 -#define PWM_CH0_DIV_BITS 0x00000fff -#define PWM_CH0_DIV_RESET 0x00000010 +#define PWM_CH0_DIV_OFFSET _u(0x00000004) +#define PWM_CH0_DIV_BITS _u(0x00000fff) +#define PWM_CH0_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH0_DIV_INT // Description : None -#define PWM_CH0_DIV_INT_RESET 0x01 -#define PWM_CH0_DIV_INT_BITS 0x00000ff0 -#define PWM_CH0_DIV_INT_MSB 11 -#define PWM_CH0_DIV_INT_LSB 4 +#define PWM_CH0_DIV_INT_RESET _u(0x01) +#define PWM_CH0_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH0_DIV_INT_MSB _u(11) +#define PWM_CH0_DIV_INT_LSB _u(4) #define PWM_CH0_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH0_DIV_FRAC // Description : None -#define PWM_CH0_DIV_FRAC_RESET 0x0 -#define PWM_CH0_DIV_FRAC_BITS 0x0000000f -#define PWM_CH0_DIV_FRAC_MSB 3 -#define PWM_CH0_DIV_FRAC_LSB 0 +#define PWM_CH0_DIV_FRAC_RESET _u(0x0) +#define PWM_CH0_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH0_DIV_FRAC_MSB _u(3) +#define PWM_CH0_DIV_FRAC_LSB _u(0) #define PWM_CH0_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PWM_CH0_CTR // Description : Direct access to the PWM counter -#define PWM_CH0_CTR_OFFSET 0x00000008 -#define PWM_CH0_CTR_BITS 0x0000ffff -#define PWM_CH0_CTR_RESET 0x00000000 -#define PWM_CH0_CTR_MSB 15 -#define PWM_CH0_CTR_LSB 0 +#define PWM_CH0_CTR_OFFSET _u(0x00000008) +#define PWM_CH0_CTR_BITS _u(0x0000ffff) +#define PWM_CH0_CTR_RESET _u(0x00000000) +#define PWM_CH0_CTR_MSB _u(15) +#define PWM_CH0_CTR_LSB _u(0) #define PWM_CH0_CTR_ACCESS "RW" // ============================================================================= // Register : PWM_CH0_CC // Description : Counter compare values -#define PWM_CH0_CC_OFFSET 0x0000000c -#define PWM_CH0_CC_BITS 0xffffffff -#define PWM_CH0_CC_RESET 0x00000000 +#define PWM_CH0_CC_OFFSET _u(0x0000000c) +#define PWM_CH0_CC_BITS _u(0xffffffff) +#define PWM_CH0_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH0_CC_B // Description : None -#define PWM_CH0_CC_B_RESET 0x0000 -#define PWM_CH0_CC_B_BITS 0xffff0000 -#define PWM_CH0_CC_B_MSB 31 -#define PWM_CH0_CC_B_LSB 16 +#define PWM_CH0_CC_B_RESET _u(0x0000) +#define PWM_CH0_CC_B_BITS _u(0xffff0000) +#define PWM_CH0_CC_B_MSB _u(31) +#define PWM_CH0_CC_B_LSB _u(16) #define PWM_CH0_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH0_CC_A // Description : None -#define PWM_CH0_CC_A_RESET 0x0000 -#define PWM_CH0_CC_A_BITS 0x0000ffff -#define PWM_CH0_CC_A_MSB 15 -#define PWM_CH0_CC_A_LSB 0 +#define PWM_CH0_CC_A_RESET _u(0x0000) +#define PWM_CH0_CC_A_BITS _u(0x0000ffff) +#define PWM_CH0_CC_A_MSB _u(15) +#define PWM_CH0_CC_A_LSB _u(0) #define PWM_CH0_CC_A_ACCESS "RW" // ============================================================================= // Register : PWM_CH0_TOP // Description : Counter wrap value -#define PWM_CH0_TOP_OFFSET 0x00000010 -#define PWM_CH0_TOP_BITS 0x0000ffff -#define PWM_CH0_TOP_RESET 0x0000ffff -#define PWM_CH0_TOP_MSB 15 -#define PWM_CH0_TOP_LSB 0 +#define PWM_CH0_TOP_OFFSET _u(0x00000010) +#define PWM_CH0_TOP_BITS _u(0x0000ffff) +#define PWM_CH0_TOP_RESET _u(0x0000ffff) +#define PWM_CH0_TOP_MSB _u(15) +#define PWM_CH0_TOP_LSB _u(0) #define PWM_CH0_TOP_ACCESS "RW" // ============================================================================= // Register : PWM_CH1_CSR // Description : Control and status register -#define PWM_CH1_CSR_OFFSET 0x00000014 -#define PWM_CH1_CSR_BITS 0x000000ff -#define PWM_CH1_CSR_RESET 0x00000000 +#define PWM_CH1_CSR_OFFSET _u(0x00000014) +#define PWM_CH1_CSR_BITS _u(0x000000ff) +#define PWM_CH1_CSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_PH_ADV // Description : Advance the phase of the counter by 1 count, while it is @@ -166,10 +166,10 @@ // Self-clearing. Write a 1, and poll until low. Counter must be // running // at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH1_CSR_PH_ADV_RESET 0x0 -#define PWM_CH1_CSR_PH_ADV_BITS 0x00000080 -#define PWM_CH1_CSR_PH_ADV_MSB 7 -#define PWM_CH1_CSR_PH_ADV_LSB 7 +#define PWM_CH1_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH1_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH1_CSR_PH_ADV_MSB _u(7) +#define PWM_CH1_CSR_PH_ADV_LSB _u(7) #define PWM_CH1_CSR_PH_ADV_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_PH_RET @@ -177,10 +177,10 @@ // running. // Self-clearing. Write a 1, and poll until low. Counter must be // running. -#define PWM_CH1_CSR_PH_RET_RESET 0x0 -#define PWM_CH1_CSR_PH_RET_BITS 0x00000040 -#define PWM_CH1_CSR_PH_RET_MSB 6 -#define PWM_CH1_CSR_PH_RET_LSB 6 +#define PWM_CH1_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH1_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH1_CSR_PH_RET_MSB _u(6) +#define PWM_CH1_CSR_PH_RET_LSB _u(6) #define PWM_CH1_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_DIVMODE @@ -190,117 +190,117 @@ // 0x2 -> Counter advances with each rising edge of the PWM B pin. // 0x3 -> Counter advances with each falling edge of the PWM B // pin. -#define PWM_CH1_CSR_DIVMODE_RESET 0x0 -#define PWM_CH1_CSR_DIVMODE_BITS 0x00000030 -#define PWM_CH1_CSR_DIVMODE_MSB 5 -#define PWM_CH1_CSR_DIVMODE_LSB 4 +#define PWM_CH1_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH1_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH1_CSR_DIVMODE_MSB _u(5) +#define PWM_CH1_CSR_DIVMODE_LSB _u(4) #define PWM_CH1_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH1_CSR_DIVMODE_VALUE_DIV 0x0 -#define PWM_CH1_CSR_DIVMODE_VALUE_LEVEL 0x1 -#define PWM_CH1_CSR_DIVMODE_VALUE_RISE 0x2 -#define PWM_CH1_CSR_DIVMODE_VALUE_FALL 0x3 +#define PWM_CH1_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH1_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH1_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH1_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_B_INV // Description : Invert output B -#define PWM_CH1_CSR_B_INV_RESET 0x0 -#define PWM_CH1_CSR_B_INV_BITS 0x00000008 -#define PWM_CH1_CSR_B_INV_MSB 3 -#define PWM_CH1_CSR_B_INV_LSB 3 +#define PWM_CH1_CSR_B_INV_RESET _u(0x0) +#define PWM_CH1_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH1_CSR_B_INV_MSB _u(3) +#define PWM_CH1_CSR_B_INV_LSB _u(3) #define PWM_CH1_CSR_B_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_A_INV // Description : Invert output A -#define PWM_CH1_CSR_A_INV_RESET 0x0 -#define PWM_CH1_CSR_A_INV_BITS 0x00000004 -#define PWM_CH1_CSR_A_INV_MSB 2 -#define PWM_CH1_CSR_A_INV_LSB 2 +#define PWM_CH1_CSR_A_INV_RESET _u(0x0) +#define PWM_CH1_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH1_CSR_A_INV_MSB _u(2) +#define PWM_CH1_CSR_A_INV_LSB _u(2) #define PWM_CH1_CSR_A_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_PH_CORRECT // Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH1_CSR_PH_CORRECT_RESET 0x0 -#define PWM_CH1_CSR_PH_CORRECT_BITS 0x00000002 -#define PWM_CH1_CSR_PH_CORRECT_MSB 1 -#define PWM_CH1_CSR_PH_CORRECT_LSB 1 +#define PWM_CH1_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH1_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH1_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH1_CSR_PH_CORRECT_LSB _u(1) #define PWM_CH1_CSR_PH_CORRECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_EN // Description : Enable the PWM channel. -#define PWM_CH1_CSR_EN_RESET 0x0 -#define PWM_CH1_CSR_EN_BITS 0x00000001 -#define PWM_CH1_CSR_EN_MSB 0 -#define PWM_CH1_CSR_EN_LSB 0 +#define PWM_CH1_CSR_EN_RESET _u(0x0) +#define PWM_CH1_CSR_EN_BITS _u(0x00000001) +#define PWM_CH1_CSR_EN_MSB _u(0) +#define PWM_CH1_CSR_EN_LSB _u(0) #define PWM_CH1_CSR_EN_ACCESS "RW" // ============================================================================= // Register : PWM_CH1_DIV // Description : INT and FRAC form a fixed-point fractional number. // Counting rate is system clock frequency divided by this number. // Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH1_DIV_OFFSET 0x00000018 -#define PWM_CH1_DIV_BITS 0x00000fff -#define PWM_CH1_DIV_RESET 0x00000010 +#define PWM_CH1_DIV_OFFSET _u(0x00000018) +#define PWM_CH1_DIV_BITS _u(0x00000fff) +#define PWM_CH1_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH1_DIV_INT // Description : None -#define PWM_CH1_DIV_INT_RESET 0x01 -#define PWM_CH1_DIV_INT_BITS 0x00000ff0 -#define PWM_CH1_DIV_INT_MSB 11 -#define PWM_CH1_DIV_INT_LSB 4 +#define PWM_CH1_DIV_INT_RESET _u(0x01) +#define PWM_CH1_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH1_DIV_INT_MSB _u(11) +#define PWM_CH1_DIV_INT_LSB _u(4) #define PWM_CH1_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH1_DIV_FRAC // Description : None -#define PWM_CH1_DIV_FRAC_RESET 0x0 -#define PWM_CH1_DIV_FRAC_BITS 0x0000000f -#define PWM_CH1_DIV_FRAC_MSB 3 -#define PWM_CH1_DIV_FRAC_LSB 0 +#define PWM_CH1_DIV_FRAC_RESET _u(0x0) +#define PWM_CH1_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH1_DIV_FRAC_MSB _u(3) +#define PWM_CH1_DIV_FRAC_LSB _u(0) #define PWM_CH1_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PWM_CH1_CTR // Description : Direct access to the PWM counter -#define PWM_CH1_CTR_OFFSET 0x0000001c -#define PWM_CH1_CTR_BITS 0x0000ffff -#define PWM_CH1_CTR_RESET 0x00000000 -#define PWM_CH1_CTR_MSB 15 -#define PWM_CH1_CTR_LSB 0 +#define PWM_CH1_CTR_OFFSET _u(0x0000001c) +#define PWM_CH1_CTR_BITS _u(0x0000ffff) +#define PWM_CH1_CTR_RESET _u(0x00000000) +#define PWM_CH1_CTR_MSB _u(15) +#define PWM_CH1_CTR_LSB _u(0) #define PWM_CH1_CTR_ACCESS "RW" // ============================================================================= // Register : PWM_CH1_CC // Description : Counter compare values -#define PWM_CH1_CC_OFFSET 0x00000020 -#define PWM_CH1_CC_BITS 0xffffffff -#define PWM_CH1_CC_RESET 0x00000000 +#define PWM_CH1_CC_OFFSET _u(0x00000020) +#define PWM_CH1_CC_BITS _u(0xffffffff) +#define PWM_CH1_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH1_CC_B // Description : None -#define PWM_CH1_CC_B_RESET 0x0000 -#define PWM_CH1_CC_B_BITS 0xffff0000 -#define PWM_CH1_CC_B_MSB 31 -#define PWM_CH1_CC_B_LSB 16 +#define PWM_CH1_CC_B_RESET _u(0x0000) +#define PWM_CH1_CC_B_BITS _u(0xffff0000) +#define PWM_CH1_CC_B_MSB _u(31) +#define PWM_CH1_CC_B_LSB _u(16) #define PWM_CH1_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH1_CC_A // Description : None -#define PWM_CH1_CC_A_RESET 0x0000 -#define PWM_CH1_CC_A_BITS 0x0000ffff -#define PWM_CH1_CC_A_MSB 15 -#define PWM_CH1_CC_A_LSB 0 +#define PWM_CH1_CC_A_RESET _u(0x0000) +#define PWM_CH1_CC_A_BITS _u(0x0000ffff) +#define PWM_CH1_CC_A_MSB _u(15) +#define PWM_CH1_CC_A_LSB _u(0) #define PWM_CH1_CC_A_ACCESS "RW" // ============================================================================= // Register : PWM_CH1_TOP // Description : Counter wrap value -#define PWM_CH1_TOP_OFFSET 0x00000024 -#define PWM_CH1_TOP_BITS 0x0000ffff -#define PWM_CH1_TOP_RESET 0x0000ffff -#define PWM_CH1_TOP_MSB 15 -#define PWM_CH1_TOP_LSB 0 +#define PWM_CH1_TOP_OFFSET _u(0x00000024) +#define PWM_CH1_TOP_BITS _u(0x0000ffff) +#define PWM_CH1_TOP_RESET _u(0x0000ffff) +#define PWM_CH1_TOP_MSB _u(15) +#define PWM_CH1_TOP_LSB _u(0) #define PWM_CH1_TOP_ACCESS "RW" // ============================================================================= // Register : PWM_CH2_CSR // Description : Control and status register -#define PWM_CH2_CSR_OFFSET 0x00000028 -#define PWM_CH2_CSR_BITS 0x000000ff -#define PWM_CH2_CSR_RESET 0x00000000 +#define PWM_CH2_CSR_OFFSET _u(0x00000028) +#define PWM_CH2_CSR_BITS _u(0x000000ff) +#define PWM_CH2_CSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_PH_ADV // Description : Advance the phase of the counter by 1 count, while it is @@ -308,10 +308,10 @@ // Self-clearing. Write a 1, and poll until low. Counter must be // running // at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH2_CSR_PH_ADV_RESET 0x0 -#define PWM_CH2_CSR_PH_ADV_BITS 0x00000080 -#define PWM_CH2_CSR_PH_ADV_MSB 7 -#define PWM_CH2_CSR_PH_ADV_LSB 7 +#define PWM_CH2_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH2_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH2_CSR_PH_ADV_MSB _u(7) +#define PWM_CH2_CSR_PH_ADV_LSB _u(7) #define PWM_CH2_CSR_PH_ADV_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_PH_RET @@ -319,10 +319,10 @@ // running. // Self-clearing. Write a 1, and poll until low. Counter must be // running. -#define PWM_CH2_CSR_PH_RET_RESET 0x0 -#define PWM_CH2_CSR_PH_RET_BITS 0x00000040 -#define PWM_CH2_CSR_PH_RET_MSB 6 -#define PWM_CH2_CSR_PH_RET_LSB 6 +#define PWM_CH2_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH2_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH2_CSR_PH_RET_MSB _u(6) +#define PWM_CH2_CSR_PH_RET_LSB _u(6) #define PWM_CH2_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_DIVMODE @@ -332,117 +332,117 @@ // 0x2 -> Counter advances with each rising edge of the PWM B pin. // 0x3 -> Counter advances with each falling edge of the PWM B // pin. -#define PWM_CH2_CSR_DIVMODE_RESET 0x0 -#define PWM_CH2_CSR_DIVMODE_BITS 0x00000030 -#define PWM_CH2_CSR_DIVMODE_MSB 5 -#define PWM_CH2_CSR_DIVMODE_LSB 4 +#define PWM_CH2_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH2_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH2_CSR_DIVMODE_MSB _u(5) +#define PWM_CH2_CSR_DIVMODE_LSB _u(4) #define PWM_CH2_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH2_CSR_DIVMODE_VALUE_DIV 0x0 -#define PWM_CH2_CSR_DIVMODE_VALUE_LEVEL 0x1 -#define PWM_CH2_CSR_DIVMODE_VALUE_RISE 0x2 -#define PWM_CH2_CSR_DIVMODE_VALUE_FALL 0x3 +#define PWM_CH2_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH2_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH2_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH2_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_B_INV // Description : Invert output B -#define PWM_CH2_CSR_B_INV_RESET 0x0 -#define PWM_CH2_CSR_B_INV_BITS 0x00000008 -#define PWM_CH2_CSR_B_INV_MSB 3 -#define PWM_CH2_CSR_B_INV_LSB 3 +#define PWM_CH2_CSR_B_INV_RESET _u(0x0) +#define PWM_CH2_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH2_CSR_B_INV_MSB _u(3) +#define PWM_CH2_CSR_B_INV_LSB _u(3) #define PWM_CH2_CSR_B_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_A_INV // Description : Invert output A -#define PWM_CH2_CSR_A_INV_RESET 0x0 -#define PWM_CH2_CSR_A_INV_BITS 0x00000004 -#define PWM_CH2_CSR_A_INV_MSB 2 -#define PWM_CH2_CSR_A_INV_LSB 2 +#define PWM_CH2_CSR_A_INV_RESET _u(0x0) +#define PWM_CH2_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH2_CSR_A_INV_MSB _u(2) +#define PWM_CH2_CSR_A_INV_LSB _u(2) #define PWM_CH2_CSR_A_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_PH_CORRECT // Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH2_CSR_PH_CORRECT_RESET 0x0 -#define PWM_CH2_CSR_PH_CORRECT_BITS 0x00000002 -#define PWM_CH2_CSR_PH_CORRECT_MSB 1 -#define PWM_CH2_CSR_PH_CORRECT_LSB 1 +#define PWM_CH2_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH2_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH2_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH2_CSR_PH_CORRECT_LSB _u(1) #define PWM_CH2_CSR_PH_CORRECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_EN // Description : Enable the PWM channel. -#define PWM_CH2_CSR_EN_RESET 0x0 -#define PWM_CH2_CSR_EN_BITS 0x00000001 -#define PWM_CH2_CSR_EN_MSB 0 -#define PWM_CH2_CSR_EN_LSB 0 +#define PWM_CH2_CSR_EN_RESET _u(0x0) +#define PWM_CH2_CSR_EN_BITS _u(0x00000001) +#define PWM_CH2_CSR_EN_MSB _u(0) +#define PWM_CH2_CSR_EN_LSB _u(0) #define PWM_CH2_CSR_EN_ACCESS "RW" // ============================================================================= // Register : PWM_CH2_DIV // Description : INT and FRAC form a fixed-point fractional number. // Counting rate is system clock frequency divided by this number. // Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH2_DIV_OFFSET 0x0000002c -#define PWM_CH2_DIV_BITS 0x00000fff -#define PWM_CH2_DIV_RESET 0x00000010 +#define PWM_CH2_DIV_OFFSET _u(0x0000002c) +#define PWM_CH2_DIV_BITS _u(0x00000fff) +#define PWM_CH2_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH2_DIV_INT // Description : None -#define PWM_CH2_DIV_INT_RESET 0x01 -#define PWM_CH2_DIV_INT_BITS 0x00000ff0 -#define PWM_CH2_DIV_INT_MSB 11 -#define PWM_CH2_DIV_INT_LSB 4 +#define PWM_CH2_DIV_INT_RESET _u(0x01) +#define PWM_CH2_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH2_DIV_INT_MSB _u(11) +#define PWM_CH2_DIV_INT_LSB _u(4) #define PWM_CH2_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH2_DIV_FRAC // Description : None -#define PWM_CH2_DIV_FRAC_RESET 0x0 -#define PWM_CH2_DIV_FRAC_BITS 0x0000000f -#define PWM_CH2_DIV_FRAC_MSB 3 -#define PWM_CH2_DIV_FRAC_LSB 0 +#define PWM_CH2_DIV_FRAC_RESET _u(0x0) +#define PWM_CH2_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH2_DIV_FRAC_MSB _u(3) +#define PWM_CH2_DIV_FRAC_LSB _u(0) #define PWM_CH2_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PWM_CH2_CTR // Description : Direct access to the PWM counter -#define PWM_CH2_CTR_OFFSET 0x00000030 -#define PWM_CH2_CTR_BITS 0x0000ffff -#define PWM_CH2_CTR_RESET 0x00000000 -#define PWM_CH2_CTR_MSB 15 -#define PWM_CH2_CTR_LSB 0 +#define PWM_CH2_CTR_OFFSET _u(0x00000030) +#define PWM_CH2_CTR_BITS _u(0x0000ffff) +#define PWM_CH2_CTR_RESET _u(0x00000000) +#define PWM_CH2_CTR_MSB _u(15) +#define PWM_CH2_CTR_LSB _u(0) #define PWM_CH2_CTR_ACCESS "RW" // ============================================================================= // Register : PWM_CH2_CC // Description : Counter compare values -#define PWM_CH2_CC_OFFSET 0x00000034 -#define PWM_CH2_CC_BITS 0xffffffff -#define PWM_CH2_CC_RESET 0x00000000 +#define PWM_CH2_CC_OFFSET _u(0x00000034) +#define PWM_CH2_CC_BITS _u(0xffffffff) +#define PWM_CH2_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH2_CC_B // Description : None -#define PWM_CH2_CC_B_RESET 0x0000 -#define PWM_CH2_CC_B_BITS 0xffff0000 -#define PWM_CH2_CC_B_MSB 31 -#define PWM_CH2_CC_B_LSB 16 +#define PWM_CH2_CC_B_RESET _u(0x0000) +#define PWM_CH2_CC_B_BITS _u(0xffff0000) +#define PWM_CH2_CC_B_MSB _u(31) +#define PWM_CH2_CC_B_LSB _u(16) #define PWM_CH2_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH2_CC_A // Description : None -#define PWM_CH2_CC_A_RESET 0x0000 -#define PWM_CH2_CC_A_BITS 0x0000ffff -#define PWM_CH2_CC_A_MSB 15 -#define PWM_CH2_CC_A_LSB 0 +#define PWM_CH2_CC_A_RESET _u(0x0000) +#define PWM_CH2_CC_A_BITS _u(0x0000ffff) +#define PWM_CH2_CC_A_MSB _u(15) +#define PWM_CH2_CC_A_LSB _u(0) #define PWM_CH2_CC_A_ACCESS "RW" // ============================================================================= // Register : PWM_CH2_TOP // Description : Counter wrap value -#define PWM_CH2_TOP_OFFSET 0x00000038 -#define PWM_CH2_TOP_BITS 0x0000ffff -#define PWM_CH2_TOP_RESET 0x0000ffff -#define PWM_CH2_TOP_MSB 15 -#define PWM_CH2_TOP_LSB 0 +#define PWM_CH2_TOP_OFFSET _u(0x00000038) +#define PWM_CH2_TOP_BITS _u(0x0000ffff) +#define PWM_CH2_TOP_RESET _u(0x0000ffff) +#define PWM_CH2_TOP_MSB _u(15) +#define PWM_CH2_TOP_LSB _u(0) #define PWM_CH2_TOP_ACCESS "RW" // ============================================================================= // Register : PWM_CH3_CSR // Description : Control and status register -#define PWM_CH3_CSR_OFFSET 0x0000003c -#define PWM_CH3_CSR_BITS 0x000000ff -#define PWM_CH3_CSR_RESET 0x00000000 +#define PWM_CH3_CSR_OFFSET _u(0x0000003c) +#define PWM_CH3_CSR_BITS _u(0x000000ff) +#define PWM_CH3_CSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_PH_ADV // Description : Advance the phase of the counter by 1 count, while it is @@ -450,10 +450,10 @@ // Self-clearing. Write a 1, and poll until low. Counter must be // running // at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH3_CSR_PH_ADV_RESET 0x0 -#define PWM_CH3_CSR_PH_ADV_BITS 0x00000080 -#define PWM_CH3_CSR_PH_ADV_MSB 7 -#define PWM_CH3_CSR_PH_ADV_LSB 7 +#define PWM_CH3_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH3_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH3_CSR_PH_ADV_MSB _u(7) +#define PWM_CH3_CSR_PH_ADV_LSB _u(7) #define PWM_CH3_CSR_PH_ADV_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_PH_RET @@ -461,10 +461,10 @@ // running. // Self-clearing. Write a 1, and poll until low. Counter must be // running. -#define PWM_CH3_CSR_PH_RET_RESET 0x0 -#define PWM_CH3_CSR_PH_RET_BITS 0x00000040 -#define PWM_CH3_CSR_PH_RET_MSB 6 -#define PWM_CH3_CSR_PH_RET_LSB 6 +#define PWM_CH3_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH3_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH3_CSR_PH_RET_MSB _u(6) +#define PWM_CH3_CSR_PH_RET_LSB _u(6) #define PWM_CH3_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_DIVMODE @@ -474,117 +474,117 @@ // 0x2 -> Counter advances with each rising edge of the PWM B pin. // 0x3 -> Counter advances with each falling edge of the PWM B // pin. -#define PWM_CH3_CSR_DIVMODE_RESET 0x0 -#define PWM_CH3_CSR_DIVMODE_BITS 0x00000030 -#define PWM_CH3_CSR_DIVMODE_MSB 5 -#define PWM_CH3_CSR_DIVMODE_LSB 4 +#define PWM_CH3_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH3_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH3_CSR_DIVMODE_MSB _u(5) +#define PWM_CH3_CSR_DIVMODE_LSB _u(4) #define PWM_CH3_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH3_CSR_DIVMODE_VALUE_DIV 0x0 -#define PWM_CH3_CSR_DIVMODE_VALUE_LEVEL 0x1 -#define PWM_CH3_CSR_DIVMODE_VALUE_RISE 0x2 -#define PWM_CH3_CSR_DIVMODE_VALUE_FALL 0x3 +#define PWM_CH3_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH3_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH3_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH3_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_B_INV // Description : Invert output B -#define PWM_CH3_CSR_B_INV_RESET 0x0 -#define PWM_CH3_CSR_B_INV_BITS 0x00000008 -#define PWM_CH3_CSR_B_INV_MSB 3 -#define PWM_CH3_CSR_B_INV_LSB 3 +#define PWM_CH3_CSR_B_INV_RESET _u(0x0) +#define PWM_CH3_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH3_CSR_B_INV_MSB _u(3) +#define PWM_CH3_CSR_B_INV_LSB _u(3) #define PWM_CH3_CSR_B_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_A_INV // Description : Invert output A -#define PWM_CH3_CSR_A_INV_RESET 0x0 -#define PWM_CH3_CSR_A_INV_BITS 0x00000004 -#define PWM_CH3_CSR_A_INV_MSB 2 -#define PWM_CH3_CSR_A_INV_LSB 2 +#define PWM_CH3_CSR_A_INV_RESET _u(0x0) +#define PWM_CH3_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH3_CSR_A_INV_MSB _u(2) +#define PWM_CH3_CSR_A_INV_LSB _u(2) #define PWM_CH3_CSR_A_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_PH_CORRECT // Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH3_CSR_PH_CORRECT_RESET 0x0 -#define PWM_CH3_CSR_PH_CORRECT_BITS 0x00000002 -#define PWM_CH3_CSR_PH_CORRECT_MSB 1 -#define PWM_CH3_CSR_PH_CORRECT_LSB 1 +#define PWM_CH3_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH3_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH3_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH3_CSR_PH_CORRECT_LSB _u(1) #define PWM_CH3_CSR_PH_CORRECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_EN // Description : Enable the PWM channel. -#define PWM_CH3_CSR_EN_RESET 0x0 -#define PWM_CH3_CSR_EN_BITS 0x00000001 -#define PWM_CH3_CSR_EN_MSB 0 -#define PWM_CH3_CSR_EN_LSB 0 +#define PWM_CH3_CSR_EN_RESET _u(0x0) +#define PWM_CH3_CSR_EN_BITS _u(0x00000001) +#define PWM_CH3_CSR_EN_MSB _u(0) +#define PWM_CH3_CSR_EN_LSB _u(0) #define PWM_CH3_CSR_EN_ACCESS "RW" // ============================================================================= // Register : PWM_CH3_DIV // Description : INT and FRAC form a fixed-point fractional number. // Counting rate is system clock frequency divided by this number. // Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH3_DIV_OFFSET 0x00000040 -#define PWM_CH3_DIV_BITS 0x00000fff -#define PWM_CH3_DIV_RESET 0x00000010 +#define PWM_CH3_DIV_OFFSET _u(0x00000040) +#define PWM_CH3_DIV_BITS _u(0x00000fff) +#define PWM_CH3_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH3_DIV_INT // Description : None -#define PWM_CH3_DIV_INT_RESET 0x01 -#define PWM_CH3_DIV_INT_BITS 0x00000ff0 -#define PWM_CH3_DIV_INT_MSB 11 -#define PWM_CH3_DIV_INT_LSB 4 +#define PWM_CH3_DIV_INT_RESET _u(0x01) +#define PWM_CH3_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH3_DIV_INT_MSB _u(11) +#define PWM_CH3_DIV_INT_LSB _u(4) #define PWM_CH3_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH3_DIV_FRAC // Description : None -#define PWM_CH3_DIV_FRAC_RESET 0x0 -#define PWM_CH3_DIV_FRAC_BITS 0x0000000f -#define PWM_CH3_DIV_FRAC_MSB 3 -#define PWM_CH3_DIV_FRAC_LSB 0 +#define PWM_CH3_DIV_FRAC_RESET _u(0x0) +#define PWM_CH3_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH3_DIV_FRAC_MSB _u(3) +#define PWM_CH3_DIV_FRAC_LSB _u(0) #define PWM_CH3_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PWM_CH3_CTR // Description : Direct access to the PWM counter -#define PWM_CH3_CTR_OFFSET 0x00000044 -#define PWM_CH3_CTR_BITS 0x0000ffff -#define PWM_CH3_CTR_RESET 0x00000000 -#define PWM_CH3_CTR_MSB 15 -#define PWM_CH3_CTR_LSB 0 +#define PWM_CH3_CTR_OFFSET _u(0x00000044) +#define PWM_CH3_CTR_BITS _u(0x0000ffff) +#define PWM_CH3_CTR_RESET _u(0x00000000) +#define PWM_CH3_CTR_MSB _u(15) +#define PWM_CH3_CTR_LSB _u(0) #define PWM_CH3_CTR_ACCESS "RW" // ============================================================================= // Register : PWM_CH3_CC // Description : Counter compare values -#define PWM_CH3_CC_OFFSET 0x00000048 -#define PWM_CH3_CC_BITS 0xffffffff -#define PWM_CH3_CC_RESET 0x00000000 +#define PWM_CH3_CC_OFFSET _u(0x00000048) +#define PWM_CH3_CC_BITS _u(0xffffffff) +#define PWM_CH3_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH3_CC_B // Description : None -#define PWM_CH3_CC_B_RESET 0x0000 -#define PWM_CH3_CC_B_BITS 0xffff0000 -#define PWM_CH3_CC_B_MSB 31 -#define PWM_CH3_CC_B_LSB 16 +#define PWM_CH3_CC_B_RESET _u(0x0000) +#define PWM_CH3_CC_B_BITS _u(0xffff0000) +#define PWM_CH3_CC_B_MSB _u(31) +#define PWM_CH3_CC_B_LSB _u(16) #define PWM_CH3_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH3_CC_A // Description : None -#define PWM_CH3_CC_A_RESET 0x0000 -#define PWM_CH3_CC_A_BITS 0x0000ffff -#define PWM_CH3_CC_A_MSB 15 -#define PWM_CH3_CC_A_LSB 0 +#define PWM_CH3_CC_A_RESET _u(0x0000) +#define PWM_CH3_CC_A_BITS _u(0x0000ffff) +#define PWM_CH3_CC_A_MSB _u(15) +#define PWM_CH3_CC_A_LSB _u(0) #define PWM_CH3_CC_A_ACCESS "RW" // ============================================================================= // Register : PWM_CH3_TOP // Description : Counter wrap value -#define PWM_CH3_TOP_OFFSET 0x0000004c -#define PWM_CH3_TOP_BITS 0x0000ffff -#define PWM_CH3_TOP_RESET 0x0000ffff -#define PWM_CH3_TOP_MSB 15 -#define PWM_CH3_TOP_LSB 0 +#define PWM_CH3_TOP_OFFSET _u(0x0000004c) +#define PWM_CH3_TOP_BITS _u(0x0000ffff) +#define PWM_CH3_TOP_RESET _u(0x0000ffff) +#define PWM_CH3_TOP_MSB _u(15) +#define PWM_CH3_TOP_LSB _u(0) #define PWM_CH3_TOP_ACCESS "RW" // ============================================================================= // Register : PWM_CH4_CSR // Description : Control and status register -#define PWM_CH4_CSR_OFFSET 0x00000050 -#define PWM_CH4_CSR_BITS 0x000000ff -#define PWM_CH4_CSR_RESET 0x00000000 +#define PWM_CH4_CSR_OFFSET _u(0x00000050) +#define PWM_CH4_CSR_BITS _u(0x000000ff) +#define PWM_CH4_CSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_PH_ADV // Description : Advance the phase of the counter by 1 count, while it is @@ -592,10 +592,10 @@ // Self-clearing. Write a 1, and poll until low. Counter must be // running // at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH4_CSR_PH_ADV_RESET 0x0 -#define PWM_CH4_CSR_PH_ADV_BITS 0x00000080 -#define PWM_CH4_CSR_PH_ADV_MSB 7 -#define PWM_CH4_CSR_PH_ADV_LSB 7 +#define PWM_CH4_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH4_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH4_CSR_PH_ADV_MSB _u(7) +#define PWM_CH4_CSR_PH_ADV_LSB _u(7) #define PWM_CH4_CSR_PH_ADV_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_PH_RET @@ -603,10 +603,10 @@ // running. // Self-clearing. Write a 1, and poll until low. Counter must be // running. -#define PWM_CH4_CSR_PH_RET_RESET 0x0 -#define PWM_CH4_CSR_PH_RET_BITS 0x00000040 -#define PWM_CH4_CSR_PH_RET_MSB 6 -#define PWM_CH4_CSR_PH_RET_LSB 6 +#define PWM_CH4_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH4_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH4_CSR_PH_RET_MSB _u(6) +#define PWM_CH4_CSR_PH_RET_LSB _u(6) #define PWM_CH4_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_DIVMODE @@ -616,117 +616,117 @@ // 0x2 -> Counter advances with each rising edge of the PWM B pin. // 0x3 -> Counter advances with each falling edge of the PWM B // pin. -#define PWM_CH4_CSR_DIVMODE_RESET 0x0 -#define PWM_CH4_CSR_DIVMODE_BITS 0x00000030 -#define PWM_CH4_CSR_DIVMODE_MSB 5 -#define PWM_CH4_CSR_DIVMODE_LSB 4 +#define PWM_CH4_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH4_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH4_CSR_DIVMODE_MSB _u(5) +#define PWM_CH4_CSR_DIVMODE_LSB _u(4) #define PWM_CH4_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH4_CSR_DIVMODE_VALUE_DIV 0x0 -#define PWM_CH4_CSR_DIVMODE_VALUE_LEVEL 0x1 -#define PWM_CH4_CSR_DIVMODE_VALUE_RISE 0x2 -#define PWM_CH4_CSR_DIVMODE_VALUE_FALL 0x3 +#define PWM_CH4_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH4_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH4_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH4_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_B_INV // Description : Invert output B -#define PWM_CH4_CSR_B_INV_RESET 0x0 -#define PWM_CH4_CSR_B_INV_BITS 0x00000008 -#define PWM_CH4_CSR_B_INV_MSB 3 -#define PWM_CH4_CSR_B_INV_LSB 3 +#define PWM_CH4_CSR_B_INV_RESET _u(0x0) +#define PWM_CH4_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH4_CSR_B_INV_MSB _u(3) +#define PWM_CH4_CSR_B_INV_LSB _u(3) #define PWM_CH4_CSR_B_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_A_INV // Description : Invert output A -#define PWM_CH4_CSR_A_INV_RESET 0x0 -#define PWM_CH4_CSR_A_INV_BITS 0x00000004 -#define PWM_CH4_CSR_A_INV_MSB 2 -#define PWM_CH4_CSR_A_INV_LSB 2 +#define PWM_CH4_CSR_A_INV_RESET _u(0x0) +#define PWM_CH4_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH4_CSR_A_INV_MSB _u(2) +#define PWM_CH4_CSR_A_INV_LSB _u(2) #define PWM_CH4_CSR_A_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_PH_CORRECT // Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH4_CSR_PH_CORRECT_RESET 0x0 -#define PWM_CH4_CSR_PH_CORRECT_BITS 0x00000002 -#define PWM_CH4_CSR_PH_CORRECT_MSB 1 -#define PWM_CH4_CSR_PH_CORRECT_LSB 1 +#define PWM_CH4_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH4_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH4_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH4_CSR_PH_CORRECT_LSB _u(1) #define PWM_CH4_CSR_PH_CORRECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_EN // Description : Enable the PWM channel. -#define PWM_CH4_CSR_EN_RESET 0x0 -#define PWM_CH4_CSR_EN_BITS 0x00000001 -#define PWM_CH4_CSR_EN_MSB 0 -#define PWM_CH4_CSR_EN_LSB 0 +#define PWM_CH4_CSR_EN_RESET _u(0x0) +#define PWM_CH4_CSR_EN_BITS _u(0x00000001) +#define PWM_CH4_CSR_EN_MSB _u(0) +#define PWM_CH4_CSR_EN_LSB _u(0) #define PWM_CH4_CSR_EN_ACCESS "RW" // ============================================================================= // Register : PWM_CH4_DIV // Description : INT and FRAC form a fixed-point fractional number. // Counting rate is system clock frequency divided by this number. // Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH4_DIV_OFFSET 0x00000054 -#define PWM_CH4_DIV_BITS 0x00000fff -#define PWM_CH4_DIV_RESET 0x00000010 +#define PWM_CH4_DIV_OFFSET _u(0x00000054) +#define PWM_CH4_DIV_BITS _u(0x00000fff) +#define PWM_CH4_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH4_DIV_INT // Description : None -#define PWM_CH4_DIV_INT_RESET 0x01 -#define PWM_CH4_DIV_INT_BITS 0x00000ff0 -#define PWM_CH4_DIV_INT_MSB 11 -#define PWM_CH4_DIV_INT_LSB 4 +#define PWM_CH4_DIV_INT_RESET _u(0x01) +#define PWM_CH4_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH4_DIV_INT_MSB _u(11) +#define PWM_CH4_DIV_INT_LSB _u(4) #define PWM_CH4_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH4_DIV_FRAC // Description : None -#define PWM_CH4_DIV_FRAC_RESET 0x0 -#define PWM_CH4_DIV_FRAC_BITS 0x0000000f -#define PWM_CH4_DIV_FRAC_MSB 3 -#define PWM_CH4_DIV_FRAC_LSB 0 +#define PWM_CH4_DIV_FRAC_RESET _u(0x0) +#define PWM_CH4_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH4_DIV_FRAC_MSB _u(3) +#define PWM_CH4_DIV_FRAC_LSB _u(0) #define PWM_CH4_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PWM_CH4_CTR // Description : Direct access to the PWM counter -#define PWM_CH4_CTR_OFFSET 0x00000058 -#define PWM_CH4_CTR_BITS 0x0000ffff -#define PWM_CH4_CTR_RESET 0x00000000 -#define PWM_CH4_CTR_MSB 15 -#define PWM_CH4_CTR_LSB 0 +#define PWM_CH4_CTR_OFFSET _u(0x00000058) +#define PWM_CH4_CTR_BITS _u(0x0000ffff) +#define PWM_CH4_CTR_RESET _u(0x00000000) +#define PWM_CH4_CTR_MSB _u(15) +#define PWM_CH4_CTR_LSB _u(0) #define PWM_CH4_CTR_ACCESS "RW" // ============================================================================= // Register : PWM_CH4_CC // Description : Counter compare values -#define PWM_CH4_CC_OFFSET 0x0000005c -#define PWM_CH4_CC_BITS 0xffffffff -#define PWM_CH4_CC_RESET 0x00000000 +#define PWM_CH4_CC_OFFSET _u(0x0000005c) +#define PWM_CH4_CC_BITS _u(0xffffffff) +#define PWM_CH4_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH4_CC_B // Description : None -#define PWM_CH4_CC_B_RESET 0x0000 -#define PWM_CH4_CC_B_BITS 0xffff0000 -#define PWM_CH4_CC_B_MSB 31 -#define PWM_CH4_CC_B_LSB 16 +#define PWM_CH4_CC_B_RESET _u(0x0000) +#define PWM_CH4_CC_B_BITS _u(0xffff0000) +#define PWM_CH4_CC_B_MSB _u(31) +#define PWM_CH4_CC_B_LSB _u(16) #define PWM_CH4_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH4_CC_A // Description : None -#define PWM_CH4_CC_A_RESET 0x0000 -#define PWM_CH4_CC_A_BITS 0x0000ffff -#define PWM_CH4_CC_A_MSB 15 -#define PWM_CH4_CC_A_LSB 0 +#define PWM_CH4_CC_A_RESET _u(0x0000) +#define PWM_CH4_CC_A_BITS _u(0x0000ffff) +#define PWM_CH4_CC_A_MSB _u(15) +#define PWM_CH4_CC_A_LSB _u(0) #define PWM_CH4_CC_A_ACCESS "RW" // ============================================================================= // Register : PWM_CH4_TOP // Description : Counter wrap value -#define PWM_CH4_TOP_OFFSET 0x00000060 -#define PWM_CH4_TOP_BITS 0x0000ffff -#define PWM_CH4_TOP_RESET 0x0000ffff -#define PWM_CH4_TOP_MSB 15 -#define PWM_CH4_TOP_LSB 0 +#define PWM_CH4_TOP_OFFSET _u(0x00000060) +#define PWM_CH4_TOP_BITS _u(0x0000ffff) +#define PWM_CH4_TOP_RESET _u(0x0000ffff) +#define PWM_CH4_TOP_MSB _u(15) +#define PWM_CH4_TOP_LSB _u(0) #define PWM_CH4_TOP_ACCESS "RW" // ============================================================================= // Register : PWM_CH5_CSR // Description : Control and status register -#define PWM_CH5_CSR_OFFSET 0x00000064 -#define PWM_CH5_CSR_BITS 0x000000ff -#define PWM_CH5_CSR_RESET 0x00000000 +#define PWM_CH5_CSR_OFFSET _u(0x00000064) +#define PWM_CH5_CSR_BITS _u(0x000000ff) +#define PWM_CH5_CSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_PH_ADV // Description : Advance the phase of the counter by 1 count, while it is @@ -734,10 +734,10 @@ // Self-clearing. Write a 1, and poll until low. Counter must be // running // at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH5_CSR_PH_ADV_RESET 0x0 -#define PWM_CH5_CSR_PH_ADV_BITS 0x00000080 -#define PWM_CH5_CSR_PH_ADV_MSB 7 -#define PWM_CH5_CSR_PH_ADV_LSB 7 +#define PWM_CH5_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH5_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH5_CSR_PH_ADV_MSB _u(7) +#define PWM_CH5_CSR_PH_ADV_LSB _u(7) #define PWM_CH5_CSR_PH_ADV_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_PH_RET @@ -745,10 +745,10 @@ // running. // Self-clearing. Write a 1, and poll until low. Counter must be // running. -#define PWM_CH5_CSR_PH_RET_RESET 0x0 -#define PWM_CH5_CSR_PH_RET_BITS 0x00000040 -#define PWM_CH5_CSR_PH_RET_MSB 6 -#define PWM_CH5_CSR_PH_RET_LSB 6 +#define PWM_CH5_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH5_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH5_CSR_PH_RET_MSB _u(6) +#define PWM_CH5_CSR_PH_RET_LSB _u(6) #define PWM_CH5_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_DIVMODE @@ -758,117 +758,117 @@ // 0x2 -> Counter advances with each rising edge of the PWM B pin. // 0x3 -> Counter advances with each falling edge of the PWM B // pin. -#define PWM_CH5_CSR_DIVMODE_RESET 0x0 -#define PWM_CH5_CSR_DIVMODE_BITS 0x00000030 -#define PWM_CH5_CSR_DIVMODE_MSB 5 -#define PWM_CH5_CSR_DIVMODE_LSB 4 +#define PWM_CH5_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH5_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH5_CSR_DIVMODE_MSB _u(5) +#define PWM_CH5_CSR_DIVMODE_LSB _u(4) #define PWM_CH5_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH5_CSR_DIVMODE_VALUE_DIV 0x0 -#define PWM_CH5_CSR_DIVMODE_VALUE_LEVEL 0x1 -#define PWM_CH5_CSR_DIVMODE_VALUE_RISE 0x2 -#define PWM_CH5_CSR_DIVMODE_VALUE_FALL 0x3 +#define PWM_CH5_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH5_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH5_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH5_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_B_INV // Description : Invert output B -#define PWM_CH5_CSR_B_INV_RESET 0x0 -#define PWM_CH5_CSR_B_INV_BITS 0x00000008 -#define PWM_CH5_CSR_B_INV_MSB 3 -#define PWM_CH5_CSR_B_INV_LSB 3 +#define PWM_CH5_CSR_B_INV_RESET _u(0x0) +#define PWM_CH5_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH5_CSR_B_INV_MSB _u(3) +#define PWM_CH5_CSR_B_INV_LSB _u(3) #define PWM_CH5_CSR_B_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_A_INV // Description : Invert output A -#define PWM_CH5_CSR_A_INV_RESET 0x0 -#define PWM_CH5_CSR_A_INV_BITS 0x00000004 -#define PWM_CH5_CSR_A_INV_MSB 2 -#define PWM_CH5_CSR_A_INV_LSB 2 +#define PWM_CH5_CSR_A_INV_RESET _u(0x0) +#define PWM_CH5_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH5_CSR_A_INV_MSB _u(2) +#define PWM_CH5_CSR_A_INV_LSB _u(2) #define PWM_CH5_CSR_A_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_PH_CORRECT // Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH5_CSR_PH_CORRECT_RESET 0x0 -#define PWM_CH5_CSR_PH_CORRECT_BITS 0x00000002 -#define PWM_CH5_CSR_PH_CORRECT_MSB 1 -#define PWM_CH5_CSR_PH_CORRECT_LSB 1 +#define PWM_CH5_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH5_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH5_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH5_CSR_PH_CORRECT_LSB _u(1) #define PWM_CH5_CSR_PH_CORRECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_EN // Description : Enable the PWM channel. -#define PWM_CH5_CSR_EN_RESET 0x0 -#define PWM_CH5_CSR_EN_BITS 0x00000001 -#define PWM_CH5_CSR_EN_MSB 0 -#define PWM_CH5_CSR_EN_LSB 0 +#define PWM_CH5_CSR_EN_RESET _u(0x0) +#define PWM_CH5_CSR_EN_BITS _u(0x00000001) +#define PWM_CH5_CSR_EN_MSB _u(0) +#define PWM_CH5_CSR_EN_LSB _u(0) #define PWM_CH5_CSR_EN_ACCESS "RW" // ============================================================================= // Register : PWM_CH5_DIV // Description : INT and FRAC form a fixed-point fractional number. // Counting rate is system clock frequency divided by this number. // Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH5_DIV_OFFSET 0x00000068 -#define PWM_CH5_DIV_BITS 0x00000fff -#define PWM_CH5_DIV_RESET 0x00000010 +#define PWM_CH5_DIV_OFFSET _u(0x00000068) +#define PWM_CH5_DIV_BITS _u(0x00000fff) +#define PWM_CH5_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH5_DIV_INT // Description : None -#define PWM_CH5_DIV_INT_RESET 0x01 -#define PWM_CH5_DIV_INT_BITS 0x00000ff0 -#define PWM_CH5_DIV_INT_MSB 11 -#define PWM_CH5_DIV_INT_LSB 4 +#define PWM_CH5_DIV_INT_RESET _u(0x01) +#define PWM_CH5_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH5_DIV_INT_MSB _u(11) +#define PWM_CH5_DIV_INT_LSB _u(4) #define PWM_CH5_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH5_DIV_FRAC // Description : None -#define PWM_CH5_DIV_FRAC_RESET 0x0 -#define PWM_CH5_DIV_FRAC_BITS 0x0000000f -#define PWM_CH5_DIV_FRAC_MSB 3 -#define PWM_CH5_DIV_FRAC_LSB 0 +#define PWM_CH5_DIV_FRAC_RESET _u(0x0) +#define PWM_CH5_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH5_DIV_FRAC_MSB _u(3) +#define PWM_CH5_DIV_FRAC_LSB _u(0) #define PWM_CH5_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PWM_CH5_CTR // Description : Direct access to the PWM counter -#define PWM_CH5_CTR_OFFSET 0x0000006c -#define PWM_CH5_CTR_BITS 0x0000ffff -#define PWM_CH5_CTR_RESET 0x00000000 -#define PWM_CH5_CTR_MSB 15 -#define PWM_CH5_CTR_LSB 0 +#define PWM_CH5_CTR_OFFSET _u(0x0000006c) +#define PWM_CH5_CTR_BITS _u(0x0000ffff) +#define PWM_CH5_CTR_RESET _u(0x00000000) +#define PWM_CH5_CTR_MSB _u(15) +#define PWM_CH5_CTR_LSB _u(0) #define PWM_CH5_CTR_ACCESS "RW" // ============================================================================= // Register : PWM_CH5_CC // Description : Counter compare values -#define PWM_CH5_CC_OFFSET 0x00000070 -#define PWM_CH5_CC_BITS 0xffffffff -#define PWM_CH5_CC_RESET 0x00000000 +#define PWM_CH5_CC_OFFSET _u(0x00000070) +#define PWM_CH5_CC_BITS _u(0xffffffff) +#define PWM_CH5_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH5_CC_B // Description : None -#define PWM_CH5_CC_B_RESET 0x0000 -#define PWM_CH5_CC_B_BITS 0xffff0000 -#define PWM_CH5_CC_B_MSB 31 -#define PWM_CH5_CC_B_LSB 16 +#define PWM_CH5_CC_B_RESET _u(0x0000) +#define PWM_CH5_CC_B_BITS _u(0xffff0000) +#define PWM_CH5_CC_B_MSB _u(31) +#define PWM_CH5_CC_B_LSB _u(16) #define PWM_CH5_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH5_CC_A // Description : None -#define PWM_CH5_CC_A_RESET 0x0000 -#define PWM_CH5_CC_A_BITS 0x0000ffff -#define PWM_CH5_CC_A_MSB 15 -#define PWM_CH5_CC_A_LSB 0 +#define PWM_CH5_CC_A_RESET _u(0x0000) +#define PWM_CH5_CC_A_BITS _u(0x0000ffff) +#define PWM_CH5_CC_A_MSB _u(15) +#define PWM_CH5_CC_A_LSB _u(0) #define PWM_CH5_CC_A_ACCESS "RW" // ============================================================================= // Register : PWM_CH5_TOP // Description : Counter wrap value -#define PWM_CH5_TOP_OFFSET 0x00000074 -#define PWM_CH5_TOP_BITS 0x0000ffff -#define PWM_CH5_TOP_RESET 0x0000ffff -#define PWM_CH5_TOP_MSB 15 -#define PWM_CH5_TOP_LSB 0 +#define PWM_CH5_TOP_OFFSET _u(0x00000074) +#define PWM_CH5_TOP_BITS _u(0x0000ffff) +#define PWM_CH5_TOP_RESET _u(0x0000ffff) +#define PWM_CH5_TOP_MSB _u(15) +#define PWM_CH5_TOP_LSB _u(0) #define PWM_CH5_TOP_ACCESS "RW" // ============================================================================= // Register : PWM_CH6_CSR // Description : Control and status register -#define PWM_CH6_CSR_OFFSET 0x00000078 -#define PWM_CH6_CSR_BITS 0x000000ff -#define PWM_CH6_CSR_RESET 0x00000000 +#define PWM_CH6_CSR_OFFSET _u(0x00000078) +#define PWM_CH6_CSR_BITS _u(0x000000ff) +#define PWM_CH6_CSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_PH_ADV // Description : Advance the phase of the counter by 1 count, while it is @@ -876,10 +876,10 @@ // Self-clearing. Write a 1, and poll until low. Counter must be // running // at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH6_CSR_PH_ADV_RESET 0x0 -#define PWM_CH6_CSR_PH_ADV_BITS 0x00000080 -#define PWM_CH6_CSR_PH_ADV_MSB 7 -#define PWM_CH6_CSR_PH_ADV_LSB 7 +#define PWM_CH6_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH6_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH6_CSR_PH_ADV_MSB _u(7) +#define PWM_CH6_CSR_PH_ADV_LSB _u(7) #define PWM_CH6_CSR_PH_ADV_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_PH_RET @@ -887,10 +887,10 @@ // running. // Self-clearing. Write a 1, and poll until low. Counter must be // running. -#define PWM_CH6_CSR_PH_RET_RESET 0x0 -#define PWM_CH6_CSR_PH_RET_BITS 0x00000040 -#define PWM_CH6_CSR_PH_RET_MSB 6 -#define PWM_CH6_CSR_PH_RET_LSB 6 +#define PWM_CH6_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH6_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH6_CSR_PH_RET_MSB _u(6) +#define PWM_CH6_CSR_PH_RET_LSB _u(6) #define PWM_CH6_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_DIVMODE @@ -900,117 +900,117 @@ // 0x2 -> Counter advances with each rising edge of the PWM B pin. // 0x3 -> Counter advances with each falling edge of the PWM B // pin. -#define PWM_CH6_CSR_DIVMODE_RESET 0x0 -#define PWM_CH6_CSR_DIVMODE_BITS 0x00000030 -#define PWM_CH6_CSR_DIVMODE_MSB 5 -#define PWM_CH6_CSR_DIVMODE_LSB 4 +#define PWM_CH6_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH6_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH6_CSR_DIVMODE_MSB _u(5) +#define PWM_CH6_CSR_DIVMODE_LSB _u(4) #define PWM_CH6_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH6_CSR_DIVMODE_VALUE_DIV 0x0 -#define PWM_CH6_CSR_DIVMODE_VALUE_LEVEL 0x1 -#define PWM_CH6_CSR_DIVMODE_VALUE_RISE 0x2 -#define PWM_CH6_CSR_DIVMODE_VALUE_FALL 0x3 +#define PWM_CH6_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH6_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH6_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH6_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_B_INV // Description : Invert output B -#define PWM_CH6_CSR_B_INV_RESET 0x0 -#define PWM_CH6_CSR_B_INV_BITS 0x00000008 -#define PWM_CH6_CSR_B_INV_MSB 3 -#define PWM_CH6_CSR_B_INV_LSB 3 +#define PWM_CH6_CSR_B_INV_RESET _u(0x0) +#define PWM_CH6_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH6_CSR_B_INV_MSB _u(3) +#define PWM_CH6_CSR_B_INV_LSB _u(3) #define PWM_CH6_CSR_B_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_A_INV // Description : Invert output A -#define PWM_CH6_CSR_A_INV_RESET 0x0 -#define PWM_CH6_CSR_A_INV_BITS 0x00000004 -#define PWM_CH6_CSR_A_INV_MSB 2 -#define PWM_CH6_CSR_A_INV_LSB 2 +#define PWM_CH6_CSR_A_INV_RESET _u(0x0) +#define PWM_CH6_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH6_CSR_A_INV_MSB _u(2) +#define PWM_CH6_CSR_A_INV_LSB _u(2) #define PWM_CH6_CSR_A_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_PH_CORRECT // Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH6_CSR_PH_CORRECT_RESET 0x0 -#define PWM_CH6_CSR_PH_CORRECT_BITS 0x00000002 -#define PWM_CH6_CSR_PH_CORRECT_MSB 1 -#define PWM_CH6_CSR_PH_CORRECT_LSB 1 +#define PWM_CH6_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH6_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH6_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH6_CSR_PH_CORRECT_LSB _u(1) #define PWM_CH6_CSR_PH_CORRECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_EN // Description : Enable the PWM channel. -#define PWM_CH6_CSR_EN_RESET 0x0 -#define PWM_CH6_CSR_EN_BITS 0x00000001 -#define PWM_CH6_CSR_EN_MSB 0 -#define PWM_CH6_CSR_EN_LSB 0 +#define PWM_CH6_CSR_EN_RESET _u(0x0) +#define PWM_CH6_CSR_EN_BITS _u(0x00000001) +#define PWM_CH6_CSR_EN_MSB _u(0) +#define PWM_CH6_CSR_EN_LSB _u(0) #define PWM_CH6_CSR_EN_ACCESS "RW" // ============================================================================= // Register : PWM_CH6_DIV // Description : INT and FRAC form a fixed-point fractional number. // Counting rate is system clock frequency divided by this number. // Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH6_DIV_OFFSET 0x0000007c -#define PWM_CH6_DIV_BITS 0x00000fff -#define PWM_CH6_DIV_RESET 0x00000010 +#define PWM_CH6_DIV_OFFSET _u(0x0000007c) +#define PWM_CH6_DIV_BITS _u(0x00000fff) +#define PWM_CH6_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH6_DIV_INT // Description : None -#define PWM_CH6_DIV_INT_RESET 0x01 -#define PWM_CH6_DIV_INT_BITS 0x00000ff0 -#define PWM_CH6_DIV_INT_MSB 11 -#define PWM_CH6_DIV_INT_LSB 4 +#define PWM_CH6_DIV_INT_RESET _u(0x01) +#define PWM_CH6_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH6_DIV_INT_MSB _u(11) +#define PWM_CH6_DIV_INT_LSB _u(4) #define PWM_CH6_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH6_DIV_FRAC // Description : None -#define PWM_CH6_DIV_FRAC_RESET 0x0 -#define PWM_CH6_DIV_FRAC_BITS 0x0000000f -#define PWM_CH6_DIV_FRAC_MSB 3 -#define PWM_CH6_DIV_FRAC_LSB 0 +#define PWM_CH6_DIV_FRAC_RESET _u(0x0) +#define PWM_CH6_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH6_DIV_FRAC_MSB _u(3) +#define PWM_CH6_DIV_FRAC_LSB _u(0) #define PWM_CH6_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PWM_CH6_CTR // Description : Direct access to the PWM counter -#define PWM_CH6_CTR_OFFSET 0x00000080 -#define PWM_CH6_CTR_BITS 0x0000ffff -#define PWM_CH6_CTR_RESET 0x00000000 -#define PWM_CH6_CTR_MSB 15 -#define PWM_CH6_CTR_LSB 0 +#define PWM_CH6_CTR_OFFSET _u(0x00000080) +#define PWM_CH6_CTR_BITS _u(0x0000ffff) +#define PWM_CH6_CTR_RESET _u(0x00000000) +#define PWM_CH6_CTR_MSB _u(15) +#define PWM_CH6_CTR_LSB _u(0) #define PWM_CH6_CTR_ACCESS "RW" // ============================================================================= // Register : PWM_CH6_CC // Description : Counter compare values -#define PWM_CH6_CC_OFFSET 0x00000084 -#define PWM_CH6_CC_BITS 0xffffffff -#define PWM_CH6_CC_RESET 0x00000000 +#define PWM_CH6_CC_OFFSET _u(0x00000084) +#define PWM_CH6_CC_BITS _u(0xffffffff) +#define PWM_CH6_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH6_CC_B // Description : None -#define PWM_CH6_CC_B_RESET 0x0000 -#define PWM_CH6_CC_B_BITS 0xffff0000 -#define PWM_CH6_CC_B_MSB 31 -#define PWM_CH6_CC_B_LSB 16 +#define PWM_CH6_CC_B_RESET _u(0x0000) +#define PWM_CH6_CC_B_BITS _u(0xffff0000) +#define PWM_CH6_CC_B_MSB _u(31) +#define PWM_CH6_CC_B_LSB _u(16) #define PWM_CH6_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH6_CC_A // Description : None -#define PWM_CH6_CC_A_RESET 0x0000 -#define PWM_CH6_CC_A_BITS 0x0000ffff -#define PWM_CH6_CC_A_MSB 15 -#define PWM_CH6_CC_A_LSB 0 +#define PWM_CH6_CC_A_RESET _u(0x0000) +#define PWM_CH6_CC_A_BITS _u(0x0000ffff) +#define PWM_CH6_CC_A_MSB _u(15) +#define PWM_CH6_CC_A_LSB _u(0) #define PWM_CH6_CC_A_ACCESS "RW" // ============================================================================= // Register : PWM_CH6_TOP // Description : Counter wrap value -#define PWM_CH6_TOP_OFFSET 0x00000088 -#define PWM_CH6_TOP_BITS 0x0000ffff -#define PWM_CH6_TOP_RESET 0x0000ffff -#define PWM_CH6_TOP_MSB 15 -#define PWM_CH6_TOP_LSB 0 +#define PWM_CH6_TOP_OFFSET _u(0x00000088) +#define PWM_CH6_TOP_BITS _u(0x0000ffff) +#define PWM_CH6_TOP_RESET _u(0x0000ffff) +#define PWM_CH6_TOP_MSB _u(15) +#define PWM_CH6_TOP_LSB _u(0) #define PWM_CH6_TOP_ACCESS "RW" // ============================================================================= // Register : PWM_CH7_CSR // Description : Control and status register -#define PWM_CH7_CSR_OFFSET 0x0000008c -#define PWM_CH7_CSR_BITS 0x000000ff -#define PWM_CH7_CSR_RESET 0x00000000 +#define PWM_CH7_CSR_OFFSET _u(0x0000008c) +#define PWM_CH7_CSR_BITS _u(0x000000ff) +#define PWM_CH7_CSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_PH_ADV // Description : Advance the phase of the counter by 1 count, while it is @@ -1018,10 +1018,10 @@ // Self-clearing. Write a 1, and poll until low. Counter must be // running // at less than full speed (div_int + div_frac / 16 > 1) -#define PWM_CH7_CSR_PH_ADV_RESET 0x0 -#define PWM_CH7_CSR_PH_ADV_BITS 0x00000080 -#define PWM_CH7_CSR_PH_ADV_MSB 7 -#define PWM_CH7_CSR_PH_ADV_LSB 7 +#define PWM_CH7_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH7_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH7_CSR_PH_ADV_MSB _u(7) +#define PWM_CH7_CSR_PH_ADV_LSB _u(7) #define PWM_CH7_CSR_PH_ADV_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_PH_RET @@ -1029,10 +1029,10 @@ // running. // Self-clearing. Write a 1, and poll until low. Counter must be // running. -#define PWM_CH7_CSR_PH_RET_RESET 0x0 -#define PWM_CH7_CSR_PH_RET_BITS 0x00000040 -#define PWM_CH7_CSR_PH_RET_MSB 6 -#define PWM_CH7_CSR_PH_RET_LSB 6 +#define PWM_CH7_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH7_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH7_CSR_PH_RET_MSB _u(6) +#define PWM_CH7_CSR_PH_RET_LSB _u(6) #define PWM_CH7_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_DIVMODE @@ -1042,110 +1042,110 @@ // 0x2 -> Counter advances with each rising edge of the PWM B pin. // 0x3 -> Counter advances with each falling edge of the PWM B // pin. -#define PWM_CH7_CSR_DIVMODE_RESET 0x0 -#define PWM_CH7_CSR_DIVMODE_BITS 0x00000030 -#define PWM_CH7_CSR_DIVMODE_MSB 5 -#define PWM_CH7_CSR_DIVMODE_LSB 4 +#define PWM_CH7_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH7_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH7_CSR_DIVMODE_MSB _u(5) +#define PWM_CH7_CSR_DIVMODE_LSB _u(4) #define PWM_CH7_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH7_CSR_DIVMODE_VALUE_DIV 0x0 -#define PWM_CH7_CSR_DIVMODE_VALUE_LEVEL 0x1 -#define PWM_CH7_CSR_DIVMODE_VALUE_RISE 0x2 -#define PWM_CH7_CSR_DIVMODE_VALUE_FALL 0x3 +#define PWM_CH7_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH7_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH7_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH7_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_B_INV // Description : Invert output B -#define PWM_CH7_CSR_B_INV_RESET 0x0 -#define PWM_CH7_CSR_B_INV_BITS 0x00000008 -#define PWM_CH7_CSR_B_INV_MSB 3 -#define PWM_CH7_CSR_B_INV_LSB 3 +#define PWM_CH7_CSR_B_INV_RESET _u(0x0) +#define PWM_CH7_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH7_CSR_B_INV_MSB _u(3) +#define PWM_CH7_CSR_B_INV_LSB _u(3) #define PWM_CH7_CSR_B_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_A_INV // Description : Invert output A -#define PWM_CH7_CSR_A_INV_RESET 0x0 -#define PWM_CH7_CSR_A_INV_BITS 0x00000004 -#define PWM_CH7_CSR_A_INV_MSB 2 -#define PWM_CH7_CSR_A_INV_LSB 2 +#define PWM_CH7_CSR_A_INV_RESET _u(0x0) +#define PWM_CH7_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH7_CSR_A_INV_MSB _u(2) +#define PWM_CH7_CSR_A_INV_LSB _u(2) #define PWM_CH7_CSR_A_INV_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_PH_CORRECT // Description : 1: Enable phase-correct modulation. 0: Trailing-edge -#define PWM_CH7_CSR_PH_CORRECT_RESET 0x0 -#define PWM_CH7_CSR_PH_CORRECT_BITS 0x00000002 -#define PWM_CH7_CSR_PH_CORRECT_MSB 1 -#define PWM_CH7_CSR_PH_CORRECT_LSB 1 +#define PWM_CH7_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH7_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH7_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH7_CSR_PH_CORRECT_LSB _u(1) #define PWM_CH7_CSR_PH_CORRECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_EN // Description : Enable the PWM channel. -#define PWM_CH7_CSR_EN_RESET 0x0 -#define PWM_CH7_CSR_EN_BITS 0x00000001 -#define PWM_CH7_CSR_EN_MSB 0 -#define PWM_CH7_CSR_EN_LSB 0 +#define PWM_CH7_CSR_EN_RESET _u(0x0) +#define PWM_CH7_CSR_EN_BITS _u(0x00000001) +#define PWM_CH7_CSR_EN_MSB _u(0) +#define PWM_CH7_CSR_EN_LSB _u(0) #define PWM_CH7_CSR_EN_ACCESS "RW" // ============================================================================= // Register : PWM_CH7_DIV // Description : INT and FRAC form a fixed-point fractional number. // Counting rate is system clock frequency divided by this number. // Fractional division uses simple 1st-order sigma-delta. -#define PWM_CH7_DIV_OFFSET 0x00000090 -#define PWM_CH7_DIV_BITS 0x00000fff -#define PWM_CH7_DIV_RESET 0x00000010 +#define PWM_CH7_DIV_OFFSET _u(0x00000090) +#define PWM_CH7_DIV_BITS _u(0x00000fff) +#define PWM_CH7_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH7_DIV_INT // Description : None -#define PWM_CH7_DIV_INT_RESET 0x01 -#define PWM_CH7_DIV_INT_BITS 0x00000ff0 -#define PWM_CH7_DIV_INT_MSB 11 -#define PWM_CH7_DIV_INT_LSB 4 +#define PWM_CH7_DIV_INT_RESET _u(0x01) +#define PWM_CH7_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH7_DIV_INT_MSB _u(11) +#define PWM_CH7_DIV_INT_LSB _u(4) #define PWM_CH7_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH7_DIV_FRAC // Description : None -#define PWM_CH7_DIV_FRAC_RESET 0x0 -#define PWM_CH7_DIV_FRAC_BITS 0x0000000f -#define PWM_CH7_DIV_FRAC_MSB 3 -#define PWM_CH7_DIV_FRAC_LSB 0 +#define PWM_CH7_DIV_FRAC_RESET _u(0x0) +#define PWM_CH7_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH7_DIV_FRAC_MSB _u(3) +#define PWM_CH7_DIV_FRAC_LSB _u(0) #define PWM_CH7_DIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PWM_CH7_CTR // Description : Direct access to the PWM counter -#define PWM_CH7_CTR_OFFSET 0x00000094 -#define PWM_CH7_CTR_BITS 0x0000ffff -#define PWM_CH7_CTR_RESET 0x00000000 -#define PWM_CH7_CTR_MSB 15 -#define PWM_CH7_CTR_LSB 0 +#define PWM_CH7_CTR_OFFSET _u(0x00000094) +#define PWM_CH7_CTR_BITS _u(0x0000ffff) +#define PWM_CH7_CTR_RESET _u(0x00000000) +#define PWM_CH7_CTR_MSB _u(15) +#define PWM_CH7_CTR_LSB _u(0) #define PWM_CH7_CTR_ACCESS "RW" // ============================================================================= // Register : PWM_CH7_CC // Description : Counter compare values -#define PWM_CH7_CC_OFFSET 0x00000098 -#define PWM_CH7_CC_BITS 0xffffffff -#define PWM_CH7_CC_RESET 0x00000000 +#define PWM_CH7_CC_OFFSET _u(0x00000098) +#define PWM_CH7_CC_BITS _u(0xffffffff) +#define PWM_CH7_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH7_CC_B // Description : None -#define PWM_CH7_CC_B_RESET 0x0000 -#define PWM_CH7_CC_B_BITS 0xffff0000 -#define PWM_CH7_CC_B_MSB 31 -#define PWM_CH7_CC_B_LSB 16 +#define PWM_CH7_CC_B_RESET _u(0x0000) +#define PWM_CH7_CC_B_BITS _u(0xffff0000) +#define PWM_CH7_CC_B_MSB _u(31) +#define PWM_CH7_CC_B_LSB _u(16) #define PWM_CH7_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH7_CC_A // Description : None -#define PWM_CH7_CC_A_RESET 0x0000 -#define PWM_CH7_CC_A_BITS 0x0000ffff -#define PWM_CH7_CC_A_MSB 15 -#define PWM_CH7_CC_A_LSB 0 +#define PWM_CH7_CC_A_RESET _u(0x0000) +#define PWM_CH7_CC_A_BITS _u(0x0000ffff) +#define PWM_CH7_CC_A_MSB _u(15) +#define PWM_CH7_CC_A_LSB _u(0) #define PWM_CH7_CC_A_ACCESS "RW" // ============================================================================= // Register : PWM_CH7_TOP // Description : Counter wrap value -#define PWM_CH7_TOP_OFFSET 0x0000009c -#define PWM_CH7_TOP_BITS 0x0000ffff -#define PWM_CH7_TOP_RESET 0x0000ffff -#define PWM_CH7_TOP_MSB 15 -#define PWM_CH7_TOP_LSB 0 +#define PWM_CH7_TOP_OFFSET _u(0x0000009c) +#define PWM_CH7_TOP_BITS _u(0x0000ffff) +#define PWM_CH7_TOP_RESET _u(0x0000ffff) +#define PWM_CH7_TOP_MSB _u(15) +#define PWM_CH7_TOP_LSB _u(0) #define PWM_CH7_TOP_ACCESS "RW" // ============================================================================= // Register : PWM_EN @@ -1154,352 +1154,352 @@ // or disabled simultaneously, so they can run in perfect sync. // For each channel, there is only one physical EN register bit, // which can be accessed through here or CHx_CSR. -#define PWM_EN_OFFSET 0x000000a0 -#define PWM_EN_BITS 0x000000ff -#define PWM_EN_RESET 0x00000000 +#define PWM_EN_OFFSET _u(0x000000a0) +#define PWM_EN_BITS _u(0x000000ff) +#define PWM_EN_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_EN_CH7 // Description : None -#define PWM_EN_CH7_RESET 0x0 -#define PWM_EN_CH7_BITS 0x00000080 -#define PWM_EN_CH7_MSB 7 -#define PWM_EN_CH7_LSB 7 +#define PWM_EN_CH7_RESET _u(0x0) +#define PWM_EN_CH7_BITS _u(0x00000080) +#define PWM_EN_CH7_MSB _u(7) +#define PWM_EN_CH7_LSB _u(7) #define PWM_EN_CH7_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH6 // Description : None -#define PWM_EN_CH6_RESET 0x0 -#define PWM_EN_CH6_BITS 0x00000040 -#define PWM_EN_CH6_MSB 6 -#define PWM_EN_CH6_LSB 6 +#define PWM_EN_CH6_RESET _u(0x0) +#define PWM_EN_CH6_BITS _u(0x00000040) +#define PWM_EN_CH6_MSB _u(6) +#define PWM_EN_CH6_LSB _u(6) #define PWM_EN_CH6_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH5 // Description : None -#define PWM_EN_CH5_RESET 0x0 -#define PWM_EN_CH5_BITS 0x00000020 -#define PWM_EN_CH5_MSB 5 -#define PWM_EN_CH5_LSB 5 +#define PWM_EN_CH5_RESET _u(0x0) +#define PWM_EN_CH5_BITS _u(0x00000020) +#define PWM_EN_CH5_MSB _u(5) +#define PWM_EN_CH5_LSB _u(5) #define PWM_EN_CH5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH4 // Description : None -#define PWM_EN_CH4_RESET 0x0 -#define PWM_EN_CH4_BITS 0x00000010 -#define PWM_EN_CH4_MSB 4 -#define PWM_EN_CH4_LSB 4 +#define PWM_EN_CH4_RESET _u(0x0) +#define PWM_EN_CH4_BITS _u(0x00000010) +#define PWM_EN_CH4_MSB _u(4) +#define PWM_EN_CH4_LSB _u(4) #define PWM_EN_CH4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH3 // Description : None -#define PWM_EN_CH3_RESET 0x0 -#define PWM_EN_CH3_BITS 0x00000008 -#define PWM_EN_CH3_MSB 3 -#define PWM_EN_CH3_LSB 3 +#define PWM_EN_CH3_RESET _u(0x0) +#define PWM_EN_CH3_BITS _u(0x00000008) +#define PWM_EN_CH3_MSB _u(3) +#define PWM_EN_CH3_LSB _u(3) #define PWM_EN_CH3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH2 // Description : None -#define PWM_EN_CH2_RESET 0x0 -#define PWM_EN_CH2_BITS 0x00000004 -#define PWM_EN_CH2_MSB 2 -#define PWM_EN_CH2_LSB 2 +#define PWM_EN_CH2_RESET _u(0x0) +#define PWM_EN_CH2_BITS _u(0x00000004) +#define PWM_EN_CH2_MSB _u(2) +#define PWM_EN_CH2_LSB _u(2) #define PWM_EN_CH2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH1 // Description : None -#define PWM_EN_CH1_RESET 0x0 -#define PWM_EN_CH1_BITS 0x00000002 -#define PWM_EN_CH1_MSB 1 -#define PWM_EN_CH1_LSB 1 +#define PWM_EN_CH1_RESET _u(0x0) +#define PWM_EN_CH1_BITS _u(0x00000002) +#define PWM_EN_CH1_MSB _u(1) +#define PWM_EN_CH1_LSB _u(1) #define PWM_EN_CH1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH0 // Description : None -#define PWM_EN_CH0_RESET 0x0 -#define PWM_EN_CH0_BITS 0x00000001 -#define PWM_EN_CH0_MSB 0 -#define PWM_EN_CH0_LSB 0 +#define PWM_EN_CH0_RESET _u(0x0) +#define PWM_EN_CH0_BITS _u(0x00000001) +#define PWM_EN_CH0_MSB _u(0) +#define PWM_EN_CH0_LSB _u(0) #define PWM_EN_CH0_ACCESS "RW" // ============================================================================= // Register : PWM_INTR // Description : Raw Interrupts -#define PWM_INTR_OFFSET 0x000000a4 -#define PWM_INTR_BITS 0x000000ff -#define PWM_INTR_RESET 0x00000000 +#define PWM_INTR_OFFSET _u(0x000000a4) +#define PWM_INTR_BITS _u(0x000000ff) +#define PWM_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH7 // Description : None -#define PWM_INTR_CH7_RESET 0x0 -#define PWM_INTR_CH7_BITS 0x00000080 -#define PWM_INTR_CH7_MSB 7 -#define PWM_INTR_CH7_LSB 7 +#define PWM_INTR_CH7_RESET _u(0x0) +#define PWM_INTR_CH7_BITS _u(0x00000080) +#define PWM_INTR_CH7_MSB _u(7) +#define PWM_INTR_CH7_LSB _u(7) #define PWM_INTR_CH7_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH6 // Description : None -#define PWM_INTR_CH6_RESET 0x0 -#define PWM_INTR_CH6_BITS 0x00000040 -#define PWM_INTR_CH6_MSB 6 -#define PWM_INTR_CH6_LSB 6 +#define PWM_INTR_CH6_RESET _u(0x0) +#define PWM_INTR_CH6_BITS _u(0x00000040) +#define PWM_INTR_CH6_MSB _u(6) +#define PWM_INTR_CH6_LSB _u(6) #define PWM_INTR_CH6_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH5 // Description : None -#define PWM_INTR_CH5_RESET 0x0 -#define PWM_INTR_CH5_BITS 0x00000020 -#define PWM_INTR_CH5_MSB 5 -#define PWM_INTR_CH5_LSB 5 +#define PWM_INTR_CH5_RESET _u(0x0) +#define PWM_INTR_CH5_BITS _u(0x00000020) +#define PWM_INTR_CH5_MSB _u(5) +#define PWM_INTR_CH5_LSB _u(5) #define PWM_INTR_CH5_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH4 // Description : None -#define PWM_INTR_CH4_RESET 0x0 -#define PWM_INTR_CH4_BITS 0x00000010 -#define PWM_INTR_CH4_MSB 4 -#define PWM_INTR_CH4_LSB 4 +#define PWM_INTR_CH4_RESET _u(0x0) +#define PWM_INTR_CH4_BITS _u(0x00000010) +#define PWM_INTR_CH4_MSB _u(4) +#define PWM_INTR_CH4_LSB _u(4) #define PWM_INTR_CH4_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH3 // Description : None -#define PWM_INTR_CH3_RESET 0x0 -#define PWM_INTR_CH3_BITS 0x00000008 -#define PWM_INTR_CH3_MSB 3 -#define PWM_INTR_CH3_LSB 3 +#define PWM_INTR_CH3_RESET _u(0x0) +#define PWM_INTR_CH3_BITS _u(0x00000008) +#define PWM_INTR_CH3_MSB _u(3) +#define PWM_INTR_CH3_LSB _u(3) #define PWM_INTR_CH3_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH2 // Description : None -#define PWM_INTR_CH2_RESET 0x0 -#define PWM_INTR_CH2_BITS 0x00000004 -#define PWM_INTR_CH2_MSB 2 -#define PWM_INTR_CH2_LSB 2 +#define PWM_INTR_CH2_RESET _u(0x0) +#define PWM_INTR_CH2_BITS _u(0x00000004) +#define PWM_INTR_CH2_MSB _u(2) +#define PWM_INTR_CH2_LSB _u(2) #define PWM_INTR_CH2_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH1 // Description : None -#define PWM_INTR_CH1_RESET 0x0 -#define PWM_INTR_CH1_BITS 0x00000002 -#define PWM_INTR_CH1_MSB 1 -#define PWM_INTR_CH1_LSB 1 +#define PWM_INTR_CH1_RESET _u(0x0) +#define PWM_INTR_CH1_BITS _u(0x00000002) +#define PWM_INTR_CH1_MSB _u(1) +#define PWM_INTR_CH1_LSB _u(1) #define PWM_INTR_CH1_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH0 // Description : None -#define PWM_INTR_CH0_RESET 0x0 -#define PWM_INTR_CH0_BITS 0x00000001 -#define PWM_INTR_CH0_MSB 0 -#define PWM_INTR_CH0_LSB 0 +#define PWM_INTR_CH0_RESET _u(0x0) +#define PWM_INTR_CH0_BITS _u(0x00000001) +#define PWM_INTR_CH0_MSB _u(0) +#define PWM_INTR_CH0_LSB _u(0) #define PWM_INTR_CH0_ACCESS "WC" // ============================================================================= // Register : PWM_INTE // Description : Interrupt Enable -#define PWM_INTE_OFFSET 0x000000a8 -#define PWM_INTE_BITS 0x000000ff -#define PWM_INTE_RESET 0x00000000 +#define PWM_INTE_OFFSET _u(0x000000a8) +#define PWM_INTE_BITS _u(0x000000ff) +#define PWM_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH7 // Description : None -#define PWM_INTE_CH7_RESET 0x0 -#define PWM_INTE_CH7_BITS 0x00000080 -#define PWM_INTE_CH7_MSB 7 -#define PWM_INTE_CH7_LSB 7 +#define PWM_INTE_CH7_RESET _u(0x0) +#define PWM_INTE_CH7_BITS _u(0x00000080) +#define PWM_INTE_CH7_MSB _u(7) +#define PWM_INTE_CH7_LSB _u(7) #define PWM_INTE_CH7_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH6 // Description : None -#define PWM_INTE_CH6_RESET 0x0 -#define PWM_INTE_CH6_BITS 0x00000040 -#define PWM_INTE_CH6_MSB 6 -#define PWM_INTE_CH6_LSB 6 +#define PWM_INTE_CH6_RESET _u(0x0) +#define PWM_INTE_CH6_BITS _u(0x00000040) +#define PWM_INTE_CH6_MSB _u(6) +#define PWM_INTE_CH6_LSB _u(6) #define PWM_INTE_CH6_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH5 // Description : None -#define PWM_INTE_CH5_RESET 0x0 -#define PWM_INTE_CH5_BITS 0x00000020 -#define PWM_INTE_CH5_MSB 5 -#define PWM_INTE_CH5_LSB 5 +#define PWM_INTE_CH5_RESET _u(0x0) +#define PWM_INTE_CH5_BITS _u(0x00000020) +#define PWM_INTE_CH5_MSB _u(5) +#define PWM_INTE_CH5_LSB _u(5) #define PWM_INTE_CH5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH4 // Description : None -#define PWM_INTE_CH4_RESET 0x0 -#define PWM_INTE_CH4_BITS 0x00000010 -#define PWM_INTE_CH4_MSB 4 -#define PWM_INTE_CH4_LSB 4 +#define PWM_INTE_CH4_RESET _u(0x0) +#define PWM_INTE_CH4_BITS _u(0x00000010) +#define PWM_INTE_CH4_MSB _u(4) +#define PWM_INTE_CH4_LSB _u(4) #define PWM_INTE_CH4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH3 // Description : None -#define PWM_INTE_CH3_RESET 0x0 -#define PWM_INTE_CH3_BITS 0x00000008 -#define PWM_INTE_CH3_MSB 3 -#define PWM_INTE_CH3_LSB 3 +#define PWM_INTE_CH3_RESET _u(0x0) +#define PWM_INTE_CH3_BITS _u(0x00000008) +#define PWM_INTE_CH3_MSB _u(3) +#define PWM_INTE_CH3_LSB _u(3) #define PWM_INTE_CH3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH2 // Description : None -#define PWM_INTE_CH2_RESET 0x0 -#define PWM_INTE_CH2_BITS 0x00000004 -#define PWM_INTE_CH2_MSB 2 -#define PWM_INTE_CH2_LSB 2 +#define PWM_INTE_CH2_RESET _u(0x0) +#define PWM_INTE_CH2_BITS _u(0x00000004) +#define PWM_INTE_CH2_MSB _u(2) +#define PWM_INTE_CH2_LSB _u(2) #define PWM_INTE_CH2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH1 // Description : None -#define PWM_INTE_CH1_RESET 0x0 -#define PWM_INTE_CH1_BITS 0x00000002 -#define PWM_INTE_CH1_MSB 1 -#define PWM_INTE_CH1_LSB 1 +#define PWM_INTE_CH1_RESET _u(0x0) +#define PWM_INTE_CH1_BITS _u(0x00000002) +#define PWM_INTE_CH1_MSB _u(1) +#define PWM_INTE_CH1_LSB _u(1) #define PWM_INTE_CH1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH0 // Description : None -#define PWM_INTE_CH0_RESET 0x0 -#define PWM_INTE_CH0_BITS 0x00000001 -#define PWM_INTE_CH0_MSB 0 -#define PWM_INTE_CH0_LSB 0 +#define PWM_INTE_CH0_RESET _u(0x0) +#define PWM_INTE_CH0_BITS _u(0x00000001) +#define PWM_INTE_CH0_MSB _u(0) +#define PWM_INTE_CH0_LSB _u(0) #define PWM_INTE_CH0_ACCESS "RW" // ============================================================================= // Register : PWM_INTF // Description : Interrupt Force -#define PWM_INTF_OFFSET 0x000000ac -#define PWM_INTF_BITS 0x000000ff -#define PWM_INTF_RESET 0x00000000 +#define PWM_INTF_OFFSET _u(0x000000ac) +#define PWM_INTF_BITS _u(0x000000ff) +#define PWM_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH7 // Description : None -#define PWM_INTF_CH7_RESET 0x0 -#define PWM_INTF_CH7_BITS 0x00000080 -#define PWM_INTF_CH7_MSB 7 -#define PWM_INTF_CH7_LSB 7 +#define PWM_INTF_CH7_RESET _u(0x0) +#define PWM_INTF_CH7_BITS _u(0x00000080) +#define PWM_INTF_CH7_MSB _u(7) +#define PWM_INTF_CH7_LSB _u(7) #define PWM_INTF_CH7_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH6 // Description : None -#define PWM_INTF_CH6_RESET 0x0 -#define PWM_INTF_CH6_BITS 0x00000040 -#define PWM_INTF_CH6_MSB 6 -#define PWM_INTF_CH6_LSB 6 +#define PWM_INTF_CH6_RESET _u(0x0) +#define PWM_INTF_CH6_BITS _u(0x00000040) +#define PWM_INTF_CH6_MSB _u(6) +#define PWM_INTF_CH6_LSB _u(6) #define PWM_INTF_CH6_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH5 // Description : None -#define PWM_INTF_CH5_RESET 0x0 -#define PWM_INTF_CH5_BITS 0x00000020 -#define PWM_INTF_CH5_MSB 5 -#define PWM_INTF_CH5_LSB 5 +#define PWM_INTF_CH5_RESET _u(0x0) +#define PWM_INTF_CH5_BITS _u(0x00000020) +#define PWM_INTF_CH5_MSB _u(5) +#define PWM_INTF_CH5_LSB _u(5) #define PWM_INTF_CH5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH4 // Description : None -#define PWM_INTF_CH4_RESET 0x0 -#define PWM_INTF_CH4_BITS 0x00000010 -#define PWM_INTF_CH4_MSB 4 -#define PWM_INTF_CH4_LSB 4 +#define PWM_INTF_CH4_RESET _u(0x0) +#define PWM_INTF_CH4_BITS _u(0x00000010) +#define PWM_INTF_CH4_MSB _u(4) +#define PWM_INTF_CH4_LSB _u(4) #define PWM_INTF_CH4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH3 // Description : None -#define PWM_INTF_CH3_RESET 0x0 -#define PWM_INTF_CH3_BITS 0x00000008 -#define PWM_INTF_CH3_MSB 3 -#define PWM_INTF_CH3_LSB 3 +#define PWM_INTF_CH3_RESET _u(0x0) +#define PWM_INTF_CH3_BITS _u(0x00000008) +#define PWM_INTF_CH3_MSB _u(3) +#define PWM_INTF_CH3_LSB _u(3) #define PWM_INTF_CH3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH2 // Description : None -#define PWM_INTF_CH2_RESET 0x0 -#define PWM_INTF_CH2_BITS 0x00000004 -#define PWM_INTF_CH2_MSB 2 -#define PWM_INTF_CH2_LSB 2 +#define PWM_INTF_CH2_RESET _u(0x0) +#define PWM_INTF_CH2_BITS _u(0x00000004) +#define PWM_INTF_CH2_MSB _u(2) +#define PWM_INTF_CH2_LSB _u(2) #define PWM_INTF_CH2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH1 // Description : None -#define PWM_INTF_CH1_RESET 0x0 -#define PWM_INTF_CH1_BITS 0x00000002 -#define PWM_INTF_CH1_MSB 1 -#define PWM_INTF_CH1_LSB 1 +#define PWM_INTF_CH1_RESET _u(0x0) +#define PWM_INTF_CH1_BITS _u(0x00000002) +#define PWM_INTF_CH1_MSB _u(1) +#define PWM_INTF_CH1_LSB _u(1) #define PWM_INTF_CH1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH0 // Description : None -#define PWM_INTF_CH0_RESET 0x0 -#define PWM_INTF_CH0_BITS 0x00000001 -#define PWM_INTF_CH0_MSB 0 -#define PWM_INTF_CH0_LSB 0 +#define PWM_INTF_CH0_RESET _u(0x0) +#define PWM_INTF_CH0_BITS _u(0x00000001) +#define PWM_INTF_CH0_MSB _u(0) +#define PWM_INTF_CH0_LSB _u(0) #define PWM_INTF_CH0_ACCESS "RW" // ============================================================================= // Register : PWM_INTS // Description : Interrupt status after masking & forcing -#define PWM_INTS_OFFSET 0x000000b0 -#define PWM_INTS_BITS 0x000000ff -#define PWM_INTS_RESET 0x00000000 +#define PWM_INTS_OFFSET _u(0x000000b0) +#define PWM_INTS_BITS _u(0x000000ff) +#define PWM_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH7 // Description : None -#define PWM_INTS_CH7_RESET 0x0 -#define PWM_INTS_CH7_BITS 0x00000080 -#define PWM_INTS_CH7_MSB 7 -#define PWM_INTS_CH7_LSB 7 +#define PWM_INTS_CH7_RESET _u(0x0) +#define PWM_INTS_CH7_BITS _u(0x00000080) +#define PWM_INTS_CH7_MSB _u(7) +#define PWM_INTS_CH7_LSB _u(7) #define PWM_INTS_CH7_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH6 // Description : None -#define PWM_INTS_CH6_RESET 0x0 -#define PWM_INTS_CH6_BITS 0x00000040 -#define PWM_INTS_CH6_MSB 6 -#define PWM_INTS_CH6_LSB 6 +#define PWM_INTS_CH6_RESET _u(0x0) +#define PWM_INTS_CH6_BITS _u(0x00000040) +#define PWM_INTS_CH6_MSB _u(6) +#define PWM_INTS_CH6_LSB _u(6) #define PWM_INTS_CH6_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH5 // Description : None -#define PWM_INTS_CH5_RESET 0x0 -#define PWM_INTS_CH5_BITS 0x00000020 -#define PWM_INTS_CH5_MSB 5 -#define PWM_INTS_CH5_LSB 5 +#define PWM_INTS_CH5_RESET _u(0x0) +#define PWM_INTS_CH5_BITS _u(0x00000020) +#define PWM_INTS_CH5_MSB _u(5) +#define PWM_INTS_CH5_LSB _u(5) #define PWM_INTS_CH5_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH4 // Description : None -#define PWM_INTS_CH4_RESET 0x0 -#define PWM_INTS_CH4_BITS 0x00000010 -#define PWM_INTS_CH4_MSB 4 -#define PWM_INTS_CH4_LSB 4 +#define PWM_INTS_CH4_RESET _u(0x0) +#define PWM_INTS_CH4_BITS _u(0x00000010) +#define PWM_INTS_CH4_MSB _u(4) +#define PWM_INTS_CH4_LSB _u(4) #define PWM_INTS_CH4_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH3 // Description : None -#define PWM_INTS_CH3_RESET 0x0 -#define PWM_INTS_CH3_BITS 0x00000008 -#define PWM_INTS_CH3_MSB 3 -#define PWM_INTS_CH3_LSB 3 +#define PWM_INTS_CH3_RESET _u(0x0) +#define PWM_INTS_CH3_BITS _u(0x00000008) +#define PWM_INTS_CH3_MSB _u(3) +#define PWM_INTS_CH3_LSB _u(3) #define PWM_INTS_CH3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH2 // Description : None -#define PWM_INTS_CH2_RESET 0x0 -#define PWM_INTS_CH2_BITS 0x00000004 -#define PWM_INTS_CH2_MSB 2 -#define PWM_INTS_CH2_LSB 2 +#define PWM_INTS_CH2_RESET _u(0x0) +#define PWM_INTS_CH2_BITS _u(0x00000004) +#define PWM_INTS_CH2_MSB _u(2) +#define PWM_INTS_CH2_LSB _u(2) #define PWM_INTS_CH2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH1 // Description : None -#define PWM_INTS_CH1_RESET 0x0 -#define PWM_INTS_CH1_BITS 0x00000002 -#define PWM_INTS_CH1_MSB 1 -#define PWM_INTS_CH1_LSB 1 +#define PWM_INTS_CH1_RESET _u(0x0) +#define PWM_INTS_CH1_BITS _u(0x00000002) +#define PWM_INTS_CH1_MSB _u(1) +#define PWM_INTS_CH1_LSB _u(1) #define PWM_INTS_CH1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH0 // Description : None -#define PWM_INTS_CH0_RESET 0x0 -#define PWM_INTS_CH0_BITS 0x00000001 -#define PWM_INTS_CH0_MSB 0 -#define PWM_INTS_CH0_LSB 0 +#define PWM_INTS_CH0_RESET _u(0x0) +#define PWM_INTS_CH0_BITS _u(0x00000001) +#define PWM_INTS_CH0_MSB _u(0) +#define PWM_INTS_CH0_LSB _u(0) #define PWM_INTS_CH0_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_PWM_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/resets.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/resets.h index b51235037..689a358b0 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/resets.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/resets.h @@ -15,623 +15,623 @@ // Register : RESETS_RESET // Description : Reset control. If a bit is set it means the peripheral is in // reset. 0 means the peripheral's reset is deasserted. -#define RESETS_RESET_OFFSET 0x00000000 -#define RESETS_RESET_BITS 0x01ffffff -#define RESETS_RESET_RESET 0x01ffffff +#define RESETS_RESET_OFFSET _u(0x00000000) +#define RESETS_RESET_BITS _u(0x01ffffff) +#define RESETS_RESET_RESET _u(0x01ffffff) // ----------------------------------------------------------------------------- // Field : RESETS_RESET_USBCTRL // Description : None -#define RESETS_RESET_USBCTRL_RESET 0x1 -#define RESETS_RESET_USBCTRL_BITS 0x01000000 -#define RESETS_RESET_USBCTRL_MSB 24 -#define RESETS_RESET_USBCTRL_LSB 24 +#define RESETS_RESET_USBCTRL_RESET _u(0x1) +#define RESETS_RESET_USBCTRL_BITS _u(0x01000000) +#define RESETS_RESET_USBCTRL_MSB _u(24) +#define RESETS_RESET_USBCTRL_LSB _u(24) #define RESETS_RESET_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_UART1 // Description : None -#define RESETS_RESET_UART1_RESET 0x1 -#define RESETS_RESET_UART1_BITS 0x00800000 -#define RESETS_RESET_UART1_MSB 23 -#define RESETS_RESET_UART1_LSB 23 +#define RESETS_RESET_UART1_RESET _u(0x1) +#define RESETS_RESET_UART1_BITS _u(0x00800000) +#define RESETS_RESET_UART1_MSB _u(23) +#define RESETS_RESET_UART1_LSB _u(23) #define RESETS_RESET_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_UART0 // Description : None -#define RESETS_RESET_UART0_RESET 0x1 -#define RESETS_RESET_UART0_BITS 0x00400000 -#define RESETS_RESET_UART0_MSB 22 -#define RESETS_RESET_UART0_LSB 22 +#define RESETS_RESET_UART0_RESET _u(0x1) +#define RESETS_RESET_UART0_BITS _u(0x00400000) +#define RESETS_RESET_UART0_MSB _u(22) +#define RESETS_RESET_UART0_LSB _u(22) #define RESETS_RESET_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_TIMER // Description : None -#define RESETS_RESET_TIMER_RESET 0x1 -#define RESETS_RESET_TIMER_BITS 0x00200000 -#define RESETS_RESET_TIMER_MSB 21 -#define RESETS_RESET_TIMER_LSB 21 +#define RESETS_RESET_TIMER_RESET _u(0x1) +#define RESETS_RESET_TIMER_BITS _u(0x00200000) +#define RESETS_RESET_TIMER_MSB _u(21) +#define RESETS_RESET_TIMER_LSB _u(21) #define RESETS_RESET_TIMER_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_TBMAN // Description : None -#define RESETS_RESET_TBMAN_RESET 0x1 -#define RESETS_RESET_TBMAN_BITS 0x00100000 -#define RESETS_RESET_TBMAN_MSB 20 -#define RESETS_RESET_TBMAN_LSB 20 +#define RESETS_RESET_TBMAN_RESET _u(0x1) +#define RESETS_RESET_TBMAN_BITS _u(0x00100000) +#define RESETS_RESET_TBMAN_MSB _u(20) +#define RESETS_RESET_TBMAN_LSB _u(20) #define RESETS_RESET_TBMAN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_SYSINFO // Description : None -#define RESETS_RESET_SYSINFO_RESET 0x1 -#define RESETS_RESET_SYSINFO_BITS 0x00080000 -#define RESETS_RESET_SYSINFO_MSB 19 -#define RESETS_RESET_SYSINFO_LSB 19 +#define RESETS_RESET_SYSINFO_RESET _u(0x1) +#define RESETS_RESET_SYSINFO_BITS _u(0x00080000) +#define RESETS_RESET_SYSINFO_MSB _u(19) +#define RESETS_RESET_SYSINFO_LSB _u(19) #define RESETS_RESET_SYSINFO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_SYSCFG // Description : None -#define RESETS_RESET_SYSCFG_RESET 0x1 -#define RESETS_RESET_SYSCFG_BITS 0x00040000 -#define RESETS_RESET_SYSCFG_MSB 18 -#define RESETS_RESET_SYSCFG_LSB 18 +#define RESETS_RESET_SYSCFG_RESET _u(0x1) +#define RESETS_RESET_SYSCFG_BITS _u(0x00040000) +#define RESETS_RESET_SYSCFG_MSB _u(18) +#define RESETS_RESET_SYSCFG_LSB _u(18) #define RESETS_RESET_SYSCFG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_SPI1 // Description : None -#define RESETS_RESET_SPI1_RESET 0x1 -#define RESETS_RESET_SPI1_BITS 0x00020000 -#define RESETS_RESET_SPI1_MSB 17 -#define RESETS_RESET_SPI1_LSB 17 +#define RESETS_RESET_SPI1_RESET _u(0x1) +#define RESETS_RESET_SPI1_BITS _u(0x00020000) +#define RESETS_RESET_SPI1_MSB _u(17) +#define RESETS_RESET_SPI1_LSB _u(17) #define RESETS_RESET_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_SPI0 // Description : None -#define RESETS_RESET_SPI0_RESET 0x1 -#define RESETS_RESET_SPI0_BITS 0x00010000 -#define RESETS_RESET_SPI0_MSB 16 -#define RESETS_RESET_SPI0_LSB 16 +#define RESETS_RESET_SPI0_RESET _u(0x1) +#define RESETS_RESET_SPI0_BITS _u(0x00010000) +#define RESETS_RESET_SPI0_MSB _u(16) +#define RESETS_RESET_SPI0_LSB _u(16) #define RESETS_RESET_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_RTC // Description : None -#define RESETS_RESET_RTC_RESET 0x1 -#define RESETS_RESET_RTC_BITS 0x00008000 -#define RESETS_RESET_RTC_MSB 15 -#define RESETS_RESET_RTC_LSB 15 +#define RESETS_RESET_RTC_RESET _u(0x1) +#define RESETS_RESET_RTC_BITS _u(0x00008000) +#define RESETS_RESET_RTC_MSB _u(15) +#define RESETS_RESET_RTC_LSB _u(15) #define RESETS_RESET_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PWM // Description : None -#define RESETS_RESET_PWM_RESET 0x1 -#define RESETS_RESET_PWM_BITS 0x00004000 -#define RESETS_RESET_PWM_MSB 14 -#define RESETS_RESET_PWM_LSB 14 +#define RESETS_RESET_PWM_RESET _u(0x1) +#define RESETS_RESET_PWM_BITS _u(0x00004000) +#define RESETS_RESET_PWM_MSB _u(14) +#define RESETS_RESET_PWM_LSB _u(14) #define RESETS_RESET_PWM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PLL_USB // Description : None -#define RESETS_RESET_PLL_USB_RESET 0x1 -#define RESETS_RESET_PLL_USB_BITS 0x00002000 -#define RESETS_RESET_PLL_USB_MSB 13 -#define RESETS_RESET_PLL_USB_LSB 13 +#define RESETS_RESET_PLL_USB_RESET _u(0x1) +#define RESETS_RESET_PLL_USB_BITS _u(0x00002000) +#define RESETS_RESET_PLL_USB_MSB _u(13) +#define RESETS_RESET_PLL_USB_LSB _u(13) #define RESETS_RESET_PLL_USB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PLL_SYS // Description : None -#define RESETS_RESET_PLL_SYS_RESET 0x1 -#define RESETS_RESET_PLL_SYS_BITS 0x00001000 -#define RESETS_RESET_PLL_SYS_MSB 12 -#define RESETS_RESET_PLL_SYS_LSB 12 +#define RESETS_RESET_PLL_SYS_RESET _u(0x1) +#define RESETS_RESET_PLL_SYS_BITS _u(0x00001000) +#define RESETS_RESET_PLL_SYS_MSB _u(12) +#define RESETS_RESET_PLL_SYS_LSB _u(12) #define RESETS_RESET_PLL_SYS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PIO1 // Description : None -#define RESETS_RESET_PIO1_RESET 0x1 -#define RESETS_RESET_PIO1_BITS 0x00000800 -#define RESETS_RESET_PIO1_MSB 11 -#define RESETS_RESET_PIO1_LSB 11 +#define RESETS_RESET_PIO1_RESET _u(0x1) +#define RESETS_RESET_PIO1_BITS _u(0x00000800) +#define RESETS_RESET_PIO1_MSB _u(11) +#define RESETS_RESET_PIO1_LSB _u(11) #define RESETS_RESET_PIO1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PIO0 // Description : None -#define RESETS_RESET_PIO0_RESET 0x1 -#define RESETS_RESET_PIO0_BITS 0x00000400 -#define RESETS_RESET_PIO0_MSB 10 -#define RESETS_RESET_PIO0_LSB 10 +#define RESETS_RESET_PIO0_RESET _u(0x1) +#define RESETS_RESET_PIO0_BITS _u(0x00000400) +#define RESETS_RESET_PIO0_MSB _u(10) +#define RESETS_RESET_PIO0_LSB _u(10) #define RESETS_RESET_PIO0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PADS_QSPI // Description : None -#define RESETS_RESET_PADS_QSPI_RESET 0x1 -#define RESETS_RESET_PADS_QSPI_BITS 0x00000200 -#define RESETS_RESET_PADS_QSPI_MSB 9 -#define RESETS_RESET_PADS_QSPI_LSB 9 +#define RESETS_RESET_PADS_QSPI_RESET _u(0x1) +#define RESETS_RESET_PADS_QSPI_BITS _u(0x00000200) +#define RESETS_RESET_PADS_QSPI_MSB _u(9) +#define RESETS_RESET_PADS_QSPI_LSB _u(9) #define RESETS_RESET_PADS_QSPI_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PADS_BANK0 // Description : None -#define RESETS_RESET_PADS_BANK0_RESET 0x1 -#define RESETS_RESET_PADS_BANK0_BITS 0x00000100 -#define RESETS_RESET_PADS_BANK0_MSB 8 -#define RESETS_RESET_PADS_BANK0_LSB 8 +#define RESETS_RESET_PADS_BANK0_RESET _u(0x1) +#define RESETS_RESET_PADS_BANK0_BITS _u(0x00000100) +#define RESETS_RESET_PADS_BANK0_MSB _u(8) +#define RESETS_RESET_PADS_BANK0_LSB _u(8) #define RESETS_RESET_PADS_BANK0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_JTAG // Description : None -#define RESETS_RESET_JTAG_RESET 0x1 -#define RESETS_RESET_JTAG_BITS 0x00000080 -#define RESETS_RESET_JTAG_MSB 7 -#define RESETS_RESET_JTAG_LSB 7 +#define RESETS_RESET_JTAG_RESET _u(0x1) +#define RESETS_RESET_JTAG_BITS _u(0x00000080) +#define RESETS_RESET_JTAG_MSB _u(7) +#define RESETS_RESET_JTAG_LSB _u(7) #define RESETS_RESET_JTAG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_IO_QSPI // Description : None -#define RESETS_RESET_IO_QSPI_RESET 0x1 -#define RESETS_RESET_IO_QSPI_BITS 0x00000040 -#define RESETS_RESET_IO_QSPI_MSB 6 -#define RESETS_RESET_IO_QSPI_LSB 6 +#define RESETS_RESET_IO_QSPI_RESET _u(0x1) +#define RESETS_RESET_IO_QSPI_BITS _u(0x00000040) +#define RESETS_RESET_IO_QSPI_MSB _u(6) +#define RESETS_RESET_IO_QSPI_LSB _u(6) #define RESETS_RESET_IO_QSPI_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_IO_BANK0 // Description : None -#define RESETS_RESET_IO_BANK0_RESET 0x1 -#define RESETS_RESET_IO_BANK0_BITS 0x00000020 -#define RESETS_RESET_IO_BANK0_MSB 5 -#define RESETS_RESET_IO_BANK0_LSB 5 +#define RESETS_RESET_IO_BANK0_RESET _u(0x1) +#define RESETS_RESET_IO_BANK0_BITS _u(0x00000020) +#define RESETS_RESET_IO_BANK0_MSB _u(5) +#define RESETS_RESET_IO_BANK0_LSB _u(5) #define RESETS_RESET_IO_BANK0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_I2C1 // Description : None -#define RESETS_RESET_I2C1_RESET 0x1 -#define RESETS_RESET_I2C1_BITS 0x00000010 -#define RESETS_RESET_I2C1_MSB 4 -#define RESETS_RESET_I2C1_LSB 4 +#define RESETS_RESET_I2C1_RESET _u(0x1) +#define RESETS_RESET_I2C1_BITS _u(0x00000010) +#define RESETS_RESET_I2C1_MSB _u(4) +#define RESETS_RESET_I2C1_LSB _u(4) #define RESETS_RESET_I2C1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_I2C0 // Description : None -#define RESETS_RESET_I2C0_RESET 0x1 -#define RESETS_RESET_I2C0_BITS 0x00000008 -#define RESETS_RESET_I2C0_MSB 3 -#define RESETS_RESET_I2C0_LSB 3 +#define RESETS_RESET_I2C0_RESET _u(0x1) +#define RESETS_RESET_I2C0_BITS _u(0x00000008) +#define RESETS_RESET_I2C0_MSB _u(3) +#define RESETS_RESET_I2C0_LSB _u(3) #define RESETS_RESET_I2C0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DMA // Description : None -#define RESETS_RESET_DMA_RESET 0x1 -#define RESETS_RESET_DMA_BITS 0x00000004 -#define RESETS_RESET_DMA_MSB 2 -#define RESETS_RESET_DMA_LSB 2 +#define RESETS_RESET_DMA_RESET _u(0x1) +#define RESETS_RESET_DMA_BITS _u(0x00000004) +#define RESETS_RESET_DMA_MSB _u(2) +#define RESETS_RESET_DMA_LSB _u(2) #define RESETS_RESET_DMA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_BUSCTRL // Description : None -#define RESETS_RESET_BUSCTRL_RESET 0x1 -#define RESETS_RESET_BUSCTRL_BITS 0x00000002 -#define RESETS_RESET_BUSCTRL_MSB 1 -#define RESETS_RESET_BUSCTRL_LSB 1 +#define RESETS_RESET_BUSCTRL_RESET _u(0x1) +#define RESETS_RESET_BUSCTRL_BITS _u(0x00000002) +#define RESETS_RESET_BUSCTRL_MSB _u(1) +#define RESETS_RESET_BUSCTRL_LSB _u(1) #define RESETS_RESET_BUSCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_ADC // Description : None -#define RESETS_RESET_ADC_RESET 0x1 -#define RESETS_RESET_ADC_BITS 0x00000001 -#define RESETS_RESET_ADC_MSB 0 -#define RESETS_RESET_ADC_LSB 0 +#define RESETS_RESET_ADC_RESET _u(0x1) +#define RESETS_RESET_ADC_BITS _u(0x00000001) +#define RESETS_RESET_ADC_MSB _u(0) +#define RESETS_RESET_ADC_LSB _u(0) #define RESETS_RESET_ADC_ACCESS "RW" // ============================================================================= // Register : RESETS_WDSEL // Description : Watchdog select. If a bit is set then the watchdog will reset // this peripheral when the watchdog fires. -#define RESETS_WDSEL_OFFSET 0x00000004 -#define RESETS_WDSEL_BITS 0x01ffffff -#define RESETS_WDSEL_RESET 0x00000000 +#define RESETS_WDSEL_OFFSET _u(0x00000004) +#define RESETS_WDSEL_BITS _u(0x01ffffff) +#define RESETS_WDSEL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_USBCTRL // Description : None -#define RESETS_WDSEL_USBCTRL_RESET 0x0 -#define RESETS_WDSEL_USBCTRL_BITS 0x01000000 -#define RESETS_WDSEL_USBCTRL_MSB 24 -#define RESETS_WDSEL_USBCTRL_LSB 24 +#define RESETS_WDSEL_USBCTRL_RESET _u(0x0) +#define RESETS_WDSEL_USBCTRL_BITS _u(0x01000000) +#define RESETS_WDSEL_USBCTRL_MSB _u(24) +#define RESETS_WDSEL_USBCTRL_LSB _u(24) #define RESETS_WDSEL_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_UART1 // Description : None -#define RESETS_WDSEL_UART1_RESET 0x0 -#define RESETS_WDSEL_UART1_BITS 0x00800000 -#define RESETS_WDSEL_UART1_MSB 23 -#define RESETS_WDSEL_UART1_LSB 23 +#define RESETS_WDSEL_UART1_RESET _u(0x0) +#define RESETS_WDSEL_UART1_BITS _u(0x00800000) +#define RESETS_WDSEL_UART1_MSB _u(23) +#define RESETS_WDSEL_UART1_LSB _u(23) #define RESETS_WDSEL_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_UART0 // Description : None -#define RESETS_WDSEL_UART0_RESET 0x0 -#define RESETS_WDSEL_UART0_BITS 0x00400000 -#define RESETS_WDSEL_UART0_MSB 22 -#define RESETS_WDSEL_UART0_LSB 22 +#define RESETS_WDSEL_UART0_RESET _u(0x0) +#define RESETS_WDSEL_UART0_BITS _u(0x00400000) +#define RESETS_WDSEL_UART0_MSB _u(22) +#define RESETS_WDSEL_UART0_LSB _u(22) #define RESETS_WDSEL_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_TIMER // Description : None -#define RESETS_WDSEL_TIMER_RESET 0x0 -#define RESETS_WDSEL_TIMER_BITS 0x00200000 -#define RESETS_WDSEL_TIMER_MSB 21 -#define RESETS_WDSEL_TIMER_LSB 21 +#define RESETS_WDSEL_TIMER_RESET _u(0x0) +#define RESETS_WDSEL_TIMER_BITS _u(0x00200000) +#define RESETS_WDSEL_TIMER_MSB _u(21) +#define RESETS_WDSEL_TIMER_LSB _u(21) #define RESETS_WDSEL_TIMER_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_TBMAN // Description : None -#define RESETS_WDSEL_TBMAN_RESET 0x0 -#define RESETS_WDSEL_TBMAN_BITS 0x00100000 -#define RESETS_WDSEL_TBMAN_MSB 20 -#define RESETS_WDSEL_TBMAN_LSB 20 +#define RESETS_WDSEL_TBMAN_RESET _u(0x0) +#define RESETS_WDSEL_TBMAN_BITS _u(0x00100000) +#define RESETS_WDSEL_TBMAN_MSB _u(20) +#define RESETS_WDSEL_TBMAN_LSB _u(20) #define RESETS_WDSEL_TBMAN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_SYSINFO // Description : None -#define RESETS_WDSEL_SYSINFO_RESET 0x0 -#define RESETS_WDSEL_SYSINFO_BITS 0x00080000 -#define RESETS_WDSEL_SYSINFO_MSB 19 -#define RESETS_WDSEL_SYSINFO_LSB 19 +#define RESETS_WDSEL_SYSINFO_RESET _u(0x0) +#define RESETS_WDSEL_SYSINFO_BITS _u(0x00080000) +#define RESETS_WDSEL_SYSINFO_MSB _u(19) +#define RESETS_WDSEL_SYSINFO_LSB _u(19) #define RESETS_WDSEL_SYSINFO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_SYSCFG // Description : None -#define RESETS_WDSEL_SYSCFG_RESET 0x0 -#define RESETS_WDSEL_SYSCFG_BITS 0x00040000 -#define RESETS_WDSEL_SYSCFG_MSB 18 -#define RESETS_WDSEL_SYSCFG_LSB 18 +#define RESETS_WDSEL_SYSCFG_RESET _u(0x0) +#define RESETS_WDSEL_SYSCFG_BITS _u(0x00040000) +#define RESETS_WDSEL_SYSCFG_MSB _u(18) +#define RESETS_WDSEL_SYSCFG_LSB _u(18) #define RESETS_WDSEL_SYSCFG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_SPI1 // Description : None -#define RESETS_WDSEL_SPI1_RESET 0x0 -#define RESETS_WDSEL_SPI1_BITS 0x00020000 -#define RESETS_WDSEL_SPI1_MSB 17 -#define RESETS_WDSEL_SPI1_LSB 17 +#define RESETS_WDSEL_SPI1_RESET _u(0x0) +#define RESETS_WDSEL_SPI1_BITS _u(0x00020000) +#define RESETS_WDSEL_SPI1_MSB _u(17) +#define RESETS_WDSEL_SPI1_LSB _u(17) #define RESETS_WDSEL_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_SPI0 // Description : None -#define RESETS_WDSEL_SPI0_RESET 0x0 -#define RESETS_WDSEL_SPI0_BITS 0x00010000 -#define RESETS_WDSEL_SPI0_MSB 16 -#define RESETS_WDSEL_SPI0_LSB 16 +#define RESETS_WDSEL_SPI0_RESET _u(0x0) +#define RESETS_WDSEL_SPI0_BITS _u(0x00010000) +#define RESETS_WDSEL_SPI0_MSB _u(16) +#define RESETS_WDSEL_SPI0_LSB _u(16) #define RESETS_WDSEL_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_RTC // Description : None -#define RESETS_WDSEL_RTC_RESET 0x0 -#define RESETS_WDSEL_RTC_BITS 0x00008000 -#define RESETS_WDSEL_RTC_MSB 15 -#define RESETS_WDSEL_RTC_LSB 15 +#define RESETS_WDSEL_RTC_RESET _u(0x0) +#define RESETS_WDSEL_RTC_BITS _u(0x00008000) +#define RESETS_WDSEL_RTC_MSB _u(15) +#define RESETS_WDSEL_RTC_LSB _u(15) #define RESETS_WDSEL_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PWM // Description : None -#define RESETS_WDSEL_PWM_RESET 0x0 -#define RESETS_WDSEL_PWM_BITS 0x00004000 -#define RESETS_WDSEL_PWM_MSB 14 -#define RESETS_WDSEL_PWM_LSB 14 +#define RESETS_WDSEL_PWM_RESET _u(0x0) +#define RESETS_WDSEL_PWM_BITS _u(0x00004000) +#define RESETS_WDSEL_PWM_MSB _u(14) +#define RESETS_WDSEL_PWM_LSB _u(14) #define RESETS_WDSEL_PWM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PLL_USB // Description : None -#define RESETS_WDSEL_PLL_USB_RESET 0x0 -#define RESETS_WDSEL_PLL_USB_BITS 0x00002000 -#define RESETS_WDSEL_PLL_USB_MSB 13 -#define RESETS_WDSEL_PLL_USB_LSB 13 +#define RESETS_WDSEL_PLL_USB_RESET _u(0x0) +#define RESETS_WDSEL_PLL_USB_BITS _u(0x00002000) +#define RESETS_WDSEL_PLL_USB_MSB _u(13) +#define RESETS_WDSEL_PLL_USB_LSB _u(13) #define RESETS_WDSEL_PLL_USB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PLL_SYS // Description : None -#define RESETS_WDSEL_PLL_SYS_RESET 0x0 -#define RESETS_WDSEL_PLL_SYS_BITS 0x00001000 -#define RESETS_WDSEL_PLL_SYS_MSB 12 -#define RESETS_WDSEL_PLL_SYS_LSB 12 +#define RESETS_WDSEL_PLL_SYS_RESET _u(0x0) +#define RESETS_WDSEL_PLL_SYS_BITS _u(0x00001000) +#define RESETS_WDSEL_PLL_SYS_MSB _u(12) +#define RESETS_WDSEL_PLL_SYS_LSB _u(12) #define RESETS_WDSEL_PLL_SYS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PIO1 // Description : None -#define RESETS_WDSEL_PIO1_RESET 0x0 -#define RESETS_WDSEL_PIO1_BITS 0x00000800 -#define RESETS_WDSEL_PIO1_MSB 11 -#define RESETS_WDSEL_PIO1_LSB 11 +#define RESETS_WDSEL_PIO1_RESET _u(0x0) +#define RESETS_WDSEL_PIO1_BITS _u(0x00000800) +#define RESETS_WDSEL_PIO1_MSB _u(11) +#define RESETS_WDSEL_PIO1_LSB _u(11) #define RESETS_WDSEL_PIO1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PIO0 // Description : None -#define RESETS_WDSEL_PIO0_RESET 0x0 -#define RESETS_WDSEL_PIO0_BITS 0x00000400 -#define RESETS_WDSEL_PIO0_MSB 10 -#define RESETS_WDSEL_PIO0_LSB 10 +#define RESETS_WDSEL_PIO0_RESET _u(0x0) +#define RESETS_WDSEL_PIO0_BITS _u(0x00000400) +#define RESETS_WDSEL_PIO0_MSB _u(10) +#define RESETS_WDSEL_PIO0_LSB _u(10) #define RESETS_WDSEL_PIO0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PADS_QSPI // Description : None -#define RESETS_WDSEL_PADS_QSPI_RESET 0x0 -#define RESETS_WDSEL_PADS_QSPI_BITS 0x00000200 -#define RESETS_WDSEL_PADS_QSPI_MSB 9 -#define RESETS_WDSEL_PADS_QSPI_LSB 9 +#define RESETS_WDSEL_PADS_QSPI_RESET _u(0x0) +#define RESETS_WDSEL_PADS_QSPI_BITS _u(0x00000200) +#define RESETS_WDSEL_PADS_QSPI_MSB _u(9) +#define RESETS_WDSEL_PADS_QSPI_LSB _u(9) #define RESETS_WDSEL_PADS_QSPI_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PADS_BANK0 // Description : None -#define RESETS_WDSEL_PADS_BANK0_RESET 0x0 -#define RESETS_WDSEL_PADS_BANK0_BITS 0x00000100 -#define RESETS_WDSEL_PADS_BANK0_MSB 8 -#define RESETS_WDSEL_PADS_BANK0_LSB 8 +#define RESETS_WDSEL_PADS_BANK0_RESET _u(0x0) +#define RESETS_WDSEL_PADS_BANK0_BITS _u(0x00000100) +#define RESETS_WDSEL_PADS_BANK0_MSB _u(8) +#define RESETS_WDSEL_PADS_BANK0_LSB _u(8) #define RESETS_WDSEL_PADS_BANK0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_JTAG // Description : None -#define RESETS_WDSEL_JTAG_RESET 0x0 -#define RESETS_WDSEL_JTAG_BITS 0x00000080 -#define RESETS_WDSEL_JTAG_MSB 7 -#define RESETS_WDSEL_JTAG_LSB 7 +#define RESETS_WDSEL_JTAG_RESET _u(0x0) +#define RESETS_WDSEL_JTAG_BITS _u(0x00000080) +#define RESETS_WDSEL_JTAG_MSB _u(7) +#define RESETS_WDSEL_JTAG_LSB _u(7) #define RESETS_WDSEL_JTAG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_IO_QSPI // Description : None -#define RESETS_WDSEL_IO_QSPI_RESET 0x0 -#define RESETS_WDSEL_IO_QSPI_BITS 0x00000040 -#define RESETS_WDSEL_IO_QSPI_MSB 6 -#define RESETS_WDSEL_IO_QSPI_LSB 6 +#define RESETS_WDSEL_IO_QSPI_RESET _u(0x0) +#define RESETS_WDSEL_IO_QSPI_BITS _u(0x00000040) +#define RESETS_WDSEL_IO_QSPI_MSB _u(6) +#define RESETS_WDSEL_IO_QSPI_LSB _u(6) #define RESETS_WDSEL_IO_QSPI_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_IO_BANK0 // Description : None -#define RESETS_WDSEL_IO_BANK0_RESET 0x0 -#define RESETS_WDSEL_IO_BANK0_BITS 0x00000020 -#define RESETS_WDSEL_IO_BANK0_MSB 5 -#define RESETS_WDSEL_IO_BANK0_LSB 5 +#define RESETS_WDSEL_IO_BANK0_RESET _u(0x0) +#define RESETS_WDSEL_IO_BANK0_BITS _u(0x00000020) +#define RESETS_WDSEL_IO_BANK0_MSB _u(5) +#define RESETS_WDSEL_IO_BANK0_LSB _u(5) #define RESETS_WDSEL_IO_BANK0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_I2C1 // Description : None -#define RESETS_WDSEL_I2C1_RESET 0x0 -#define RESETS_WDSEL_I2C1_BITS 0x00000010 -#define RESETS_WDSEL_I2C1_MSB 4 -#define RESETS_WDSEL_I2C1_LSB 4 +#define RESETS_WDSEL_I2C1_RESET _u(0x0) +#define RESETS_WDSEL_I2C1_BITS _u(0x00000010) +#define RESETS_WDSEL_I2C1_MSB _u(4) +#define RESETS_WDSEL_I2C1_LSB _u(4) #define RESETS_WDSEL_I2C1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_I2C0 // Description : None -#define RESETS_WDSEL_I2C0_RESET 0x0 -#define RESETS_WDSEL_I2C0_BITS 0x00000008 -#define RESETS_WDSEL_I2C0_MSB 3 -#define RESETS_WDSEL_I2C0_LSB 3 +#define RESETS_WDSEL_I2C0_RESET _u(0x0) +#define RESETS_WDSEL_I2C0_BITS _u(0x00000008) +#define RESETS_WDSEL_I2C0_MSB _u(3) +#define RESETS_WDSEL_I2C0_LSB _u(3) #define RESETS_WDSEL_I2C0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_DMA // Description : None -#define RESETS_WDSEL_DMA_RESET 0x0 -#define RESETS_WDSEL_DMA_BITS 0x00000004 -#define RESETS_WDSEL_DMA_MSB 2 -#define RESETS_WDSEL_DMA_LSB 2 +#define RESETS_WDSEL_DMA_RESET _u(0x0) +#define RESETS_WDSEL_DMA_BITS _u(0x00000004) +#define RESETS_WDSEL_DMA_MSB _u(2) +#define RESETS_WDSEL_DMA_LSB _u(2) #define RESETS_WDSEL_DMA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_BUSCTRL // Description : None -#define RESETS_WDSEL_BUSCTRL_RESET 0x0 -#define RESETS_WDSEL_BUSCTRL_BITS 0x00000002 -#define RESETS_WDSEL_BUSCTRL_MSB 1 -#define RESETS_WDSEL_BUSCTRL_LSB 1 +#define RESETS_WDSEL_BUSCTRL_RESET _u(0x0) +#define RESETS_WDSEL_BUSCTRL_BITS _u(0x00000002) +#define RESETS_WDSEL_BUSCTRL_MSB _u(1) +#define RESETS_WDSEL_BUSCTRL_LSB _u(1) #define RESETS_WDSEL_BUSCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_ADC // Description : None -#define RESETS_WDSEL_ADC_RESET 0x0 -#define RESETS_WDSEL_ADC_BITS 0x00000001 -#define RESETS_WDSEL_ADC_MSB 0 -#define RESETS_WDSEL_ADC_LSB 0 +#define RESETS_WDSEL_ADC_RESET _u(0x0) +#define RESETS_WDSEL_ADC_BITS _u(0x00000001) +#define RESETS_WDSEL_ADC_MSB _u(0) +#define RESETS_WDSEL_ADC_LSB _u(0) #define RESETS_WDSEL_ADC_ACCESS "RW" // ============================================================================= // Register : RESETS_RESET_DONE // Description : Reset done. If a bit is set then a reset done signal has been // returned by the peripheral. This indicates that the // peripheral's registers are ready to be accessed. -#define RESETS_RESET_DONE_OFFSET 0x00000008 -#define RESETS_RESET_DONE_BITS 0x01ffffff -#define RESETS_RESET_DONE_RESET 0x00000000 +#define RESETS_RESET_DONE_OFFSET _u(0x00000008) +#define RESETS_RESET_DONE_BITS _u(0x01ffffff) +#define RESETS_RESET_DONE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_USBCTRL // Description : None -#define RESETS_RESET_DONE_USBCTRL_RESET 0x0 -#define RESETS_RESET_DONE_USBCTRL_BITS 0x01000000 -#define RESETS_RESET_DONE_USBCTRL_MSB 24 -#define RESETS_RESET_DONE_USBCTRL_LSB 24 +#define RESETS_RESET_DONE_USBCTRL_RESET _u(0x0) +#define RESETS_RESET_DONE_USBCTRL_BITS _u(0x01000000) +#define RESETS_RESET_DONE_USBCTRL_MSB _u(24) +#define RESETS_RESET_DONE_USBCTRL_LSB _u(24) #define RESETS_RESET_DONE_USBCTRL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_UART1 // Description : None -#define RESETS_RESET_DONE_UART1_RESET 0x0 -#define RESETS_RESET_DONE_UART1_BITS 0x00800000 -#define RESETS_RESET_DONE_UART1_MSB 23 -#define RESETS_RESET_DONE_UART1_LSB 23 +#define RESETS_RESET_DONE_UART1_RESET _u(0x0) +#define RESETS_RESET_DONE_UART1_BITS _u(0x00800000) +#define RESETS_RESET_DONE_UART1_MSB _u(23) +#define RESETS_RESET_DONE_UART1_LSB _u(23) #define RESETS_RESET_DONE_UART1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_UART0 // Description : None -#define RESETS_RESET_DONE_UART0_RESET 0x0 -#define RESETS_RESET_DONE_UART0_BITS 0x00400000 -#define RESETS_RESET_DONE_UART0_MSB 22 -#define RESETS_RESET_DONE_UART0_LSB 22 +#define RESETS_RESET_DONE_UART0_RESET _u(0x0) +#define RESETS_RESET_DONE_UART0_BITS _u(0x00400000) +#define RESETS_RESET_DONE_UART0_MSB _u(22) +#define RESETS_RESET_DONE_UART0_LSB _u(22) #define RESETS_RESET_DONE_UART0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_TIMER // Description : None -#define RESETS_RESET_DONE_TIMER_RESET 0x0 -#define RESETS_RESET_DONE_TIMER_BITS 0x00200000 -#define RESETS_RESET_DONE_TIMER_MSB 21 -#define RESETS_RESET_DONE_TIMER_LSB 21 +#define RESETS_RESET_DONE_TIMER_RESET _u(0x0) +#define RESETS_RESET_DONE_TIMER_BITS _u(0x00200000) +#define RESETS_RESET_DONE_TIMER_MSB _u(21) +#define RESETS_RESET_DONE_TIMER_LSB _u(21) #define RESETS_RESET_DONE_TIMER_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_TBMAN // Description : None -#define RESETS_RESET_DONE_TBMAN_RESET 0x0 -#define RESETS_RESET_DONE_TBMAN_BITS 0x00100000 -#define RESETS_RESET_DONE_TBMAN_MSB 20 -#define RESETS_RESET_DONE_TBMAN_LSB 20 +#define RESETS_RESET_DONE_TBMAN_RESET _u(0x0) +#define RESETS_RESET_DONE_TBMAN_BITS _u(0x00100000) +#define RESETS_RESET_DONE_TBMAN_MSB _u(20) +#define RESETS_RESET_DONE_TBMAN_LSB _u(20) #define RESETS_RESET_DONE_TBMAN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_SYSINFO // Description : None -#define RESETS_RESET_DONE_SYSINFO_RESET 0x0 -#define RESETS_RESET_DONE_SYSINFO_BITS 0x00080000 -#define RESETS_RESET_DONE_SYSINFO_MSB 19 -#define RESETS_RESET_DONE_SYSINFO_LSB 19 +#define RESETS_RESET_DONE_SYSINFO_RESET _u(0x0) +#define RESETS_RESET_DONE_SYSINFO_BITS _u(0x00080000) +#define RESETS_RESET_DONE_SYSINFO_MSB _u(19) +#define RESETS_RESET_DONE_SYSINFO_LSB _u(19) #define RESETS_RESET_DONE_SYSINFO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_SYSCFG // Description : None -#define RESETS_RESET_DONE_SYSCFG_RESET 0x0 -#define RESETS_RESET_DONE_SYSCFG_BITS 0x00040000 -#define RESETS_RESET_DONE_SYSCFG_MSB 18 -#define RESETS_RESET_DONE_SYSCFG_LSB 18 +#define RESETS_RESET_DONE_SYSCFG_RESET _u(0x0) +#define RESETS_RESET_DONE_SYSCFG_BITS _u(0x00040000) +#define RESETS_RESET_DONE_SYSCFG_MSB _u(18) +#define RESETS_RESET_DONE_SYSCFG_LSB _u(18) #define RESETS_RESET_DONE_SYSCFG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_SPI1 // Description : None -#define RESETS_RESET_DONE_SPI1_RESET 0x0 -#define RESETS_RESET_DONE_SPI1_BITS 0x00020000 -#define RESETS_RESET_DONE_SPI1_MSB 17 -#define RESETS_RESET_DONE_SPI1_LSB 17 +#define RESETS_RESET_DONE_SPI1_RESET _u(0x0) +#define RESETS_RESET_DONE_SPI1_BITS _u(0x00020000) +#define RESETS_RESET_DONE_SPI1_MSB _u(17) +#define RESETS_RESET_DONE_SPI1_LSB _u(17) #define RESETS_RESET_DONE_SPI1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_SPI0 // Description : None -#define RESETS_RESET_DONE_SPI0_RESET 0x0 -#define RESETS_RESET_DONE_SPI0_BITS 0x00010000 -#define RESETS_RESET_DONE_SPI0_MSB 16 -#define RESETS_RESET_DONE_SPI0_LSB 16 +#define RESETS_RESET_DONE_SPI0_RESET _u(0x0) +#define RESETS_RESET_DONE_SPI0_BITS _u(0x00010000) +#define RESETS_RESET_DONE_SPI0_MSB _u(16) +#define RESETS_RESET_DONE_SPI0_LSB _u(16) #define RESETS_RESET_DONE_SPI0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_RTC // Description : None -#define RESETS_RESET_DONE_RTC_RESET 0x0 -#define RESETS_RESET_DONE_RTC_BITS 0x00008000 -#define RESETS_RESET_DONE_RTC_MSB 15 -#define RESETS_RESET_DONE_RTC_LSB 15 +#define RESETS_RESET_DONE_RTC_RESET _u(0x0) +#define RESETS_RESET_DONE_RTC_BITS _u(0x00008000) +#define RESETS_RESET_DONE_RTC_MSB _u(15) +#define RESETS_RESET_DONE_RTC_LSB _u(15) #define RESETS_RESET_DONE_RTC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PWM // Description : None -#define RESETS_RESET_DONE_PWM_RESET 0x0 -#define RESETS_RESET_DONE_PWM_BITS 0x00004000 -#define RESETS_RESET_DONE_PWM_MSB 14 -#define RESETS_RESET_DONE_PWM_LSB 14 +#define RESETS_RESET_DONE_PWM_RESET _u(0x0) +#define RESETS_RESET_DONE_PWM_BITS _u(0x00004000) +#define RESETS_RESET_DONE_PWM_MSB _u(14) +#define RESETS_RESET_DONE_PWM_LSB _u(14) #define RESETS_RESET_DONE_PWM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PLL_USB // Description : None -#define RESETS_RESET_DONE_PLL_USB_RESET 0x0 -#define RESETS_RESET_DONE_PLL_USB_BITS 0x00002000 -#define RESETS_RESET_DONE_PLL_USB_MSB 13 -#define RESETS_RESET_DONE_PLL_USB_LSB 13 +#define RESETS_RESET_DONE_PLL_USB_RESET _u(0x0) +#define RESETS_RESET_DONE_PLL_USB_BITS _u(0x00002000) +#define RESETS_RESET_DONE_PLL_USB_MSB _u(13) +#define RESETS_RESET_DONE_PLL_USB_LSB _u(13) #define RESETS_RESET_DONE_PLL_USB_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PLL_SYS // Description : None -#define RESETS_RESET_DONE_PLL_SYS_RESET 0x0 -#define RESETS_RESET_DONE_PLL_SYS_BITS 0x00001000 -#define RESETS_RESET_DONE_PLL_SYS_MSB 12 -#define RESETS_RESET_DONE_PLL_SYS_LSB 12 +#define RESETS_RESET_DONE_PLL_SYS_RESET _u(0x0) +#define RESETS_RESET_DONE_PLL_SYS_BITS _u(0x00001000) +#define RESETS_RESET_DONE_PLL_SYS_MSB _u(12) +#define RESETS_RESET_DONE_PLL_SYS_LSB _u(12) #define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PIO1 // Description : None -#define RESETS_RESET_DONE_PIO1_RESET 0x0 -#define RESETS_RESET_DONE_PIO1_BITS 0x00000800 -#define RESETS_RESET_DONE_PIO1_MSB 11 -#define RESETS_RESET_DONE_PIO1_LSB 11 +#define RESETS_RESET_DONE_PIO1_RESET _u(0x0) +#define RESETS_RESET_DONE_PIO1_BITS _u(0x00000800) +#define RESETS_RESET_DONE_PIO1_MSB _u(11) +#define RESETS_RESET_DONE_PIO1_LSB _u(11) #define RESETS_RESET_DONE_PIO1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PIO0 // Description : None -#define RESETS_RESET_DONE_PIO0_RESET 0x0 -#define RESETS_RESET_DONE_PIO0_BITS 0x00000400 -#define RESETS_RESET_DONE_PIO0_MSB 10 -#define RESETS_RESET_DONE_PIO0_LSB 10 +#define RESETS_RESET_DONE_PIO0_RESET _u(0x0) +#define RESETS_RESET_DONE_PIO0_BITS _u(0x00000400) +#define RESETS_RESET_DONE_PIO0_MSB _u(10) +#define RESETS_RESET_DONE_PIO0_LSB _u(10) #define RESETS_RESET_DONE_PIO0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PADS_QSPI // Description : None -#define RESETS_RESET_DONE_PADS_QSPI_RESET 0x0 -#define RESETS_RESET_DONE_PADS_QSPI_BITS 0x00000200 -#define RESETS_RESET_DONE_PADS_QSPI_MSB 9 -#define RESETS_RESET_DONE_PADS_QSPI_LSB 9 +#define RESETS_RESET_DONE_PADS_QSPI_RESET _u(0x0) +#define RESETS_RESET_DONE_PADS_QSPI_BITS _u(0x00000200) +#define RESETS_RESET_DONE_PADS_QSPI_MSB _u(9) +#define RESETS_RESET_DONE_PADS_QSPI_LSB _u(9) #define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PADS_BANK0 // Description : None -#define RESETS_RESET_DONE_PADS_BANK0_RESET 0x0 -#define RESETS_RESET_DONE_PADS_BANK0_BITS 0x00000100 -#define RESETS_RESET_DONE_PADS_BANK0_MSB 8 -#define RESETS_RESET_DONE_PADS_BANK0_LSB 8 +#define RESETS_RESET_DONE_PADS_BANK0_RESET _u(0x0) +#define RESETS_RESET_DONE_PADS_BANK0_BITS _u(0x00000100) +#define RESETS_RESET_DONE_PADS_BANK0_MSB _u(8) +#define RESETS_RESET_DONE_PADS_BANK0_LSB _u(8) #define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_JTAG // Description : None -#define RESETS_RESET_DONE_JTAG_RESET 0x0 -#define RESETS_RESET_DONE_JTAG_BITS 0x00000080 -#define RESETS_RESET_DONE_JTAG_MSB 7 -#define RESETS_RESET_DONE_JTAG_LSB 7 +#define RESETS_RESET_DONE_JTAG_RESET _u(0x0) +#define RESETS_RESET_DONE_JTAG_BITS _u(0x00000080) +#define RESETS_RESET_DONE_JTAG_MSB _u(7) +#define RESETS_RESET_DONE_JTAG_LSB _u(7) #define RESETS_RESET_DONE_JTAG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_IO_QSPI // Description : None -#define RESETS_RESET_DONE_IO_QSPI_RESET 0x0 -#define RESETS_RESET_DONE_IO_QSPI_BITS 0x00000040 -#define RESETS_RESET_DONE_IO_QSPI_MSB 6 -#define RESETS_RESET_DONE_IO_QSPI_LSB 6 +#define RESETS_RESET_DONE_IO_QSPI_RESET _u(0x0) +#define RESETS_RESET_DONE_IO_QSPI_BITS _u(0x00000040) +#define RESETS_RESET_DONE_IO_QSPI_MSB _u(6) +#define RESETS_RESET_DONE_IO_QSPI_LSB _u(6) #define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_IO_BANK0 // Description : None -#define RESETS_RESET_DONE_IO_BANK0_RESET 0x0 -#define RESETS_RESET_DONE_IO_BANK0_BITS 0x00000020 -#define RESETS_RESET_DONE_IO_BANK0_MSB 5 -#define RESETS_RESET_DONE_IO_BANK0_LSB 5 +#define RESETS_RESET_DONE_IO_BANK0_RESET _u(0x0) +#define RESETS_RESET_DONE_IO_BANK0_BITS _u(0x00000020) +#define RESETS_RESET_DONE_IO_BANK0_MSB _u(5) +#define RESETS_RESET_DONE_IO_BANK0_LSB _u(5) #define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_I2C1 // Description : None -#define RESETS_RESET_DONE_I2C1_RESET 0x0 -#define RESETS_RESET_DONE_I2C1_BITS 0x00000010 -#define RESETS_RESET_DONE_I2C1_MSB 4 -#define RESETS_RESET_DONE_I2C1_LSB 4 +#define RESETS_RESET_DONE_I2C1_RESET _u(0x0) +#define RESETS_RESET_DONE_I2C1_BITS _u(0x00000010) +#define RESETS_RESET_DONE_I2C1_MSB _u(4) +#define RESETS_RESET_DONE_I2C1_LSB _u(4) #define RESETS_RESET_DONE_I2C1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_I2C0 // Description : None -#define RESETS_RESET_DONE_I2C0_RESET 0x0 -#define RESETS_RESET_DONE_I2C0_BITS 0x00000008 -#define RESETS_RESET_DONE_I2C0_MSB 3 -#define RESETS_RESET_DONE_I2C0_LSB 3 +#define RESETS_RESET_DONE_I2C0_RESET _u(0x0) +#define RESETS_RESET_DONE_I2C0_BITS _u(0x00000008) +#define RESETS_RESET_DONE_I2C0_MSB _u(3) +#define RESETS_RESET_DONE_I2C0_LSB _u(3) #define RESETS_RESET_DONE_I2C0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_DMA // Description : None -#define RESETS_RESET_DONE_DMA_RESET 0x0 -#define RESETS_RESET_DONE_DMA_BITS 0x00000004 -#define RESETS_RESET_DONE_DMA_MSB 2 -#define RESETS_RESET_DONE_DMA_LSB 2 +#define RESETS_RESET_DONE_DMA_RESET _u(0x0) +#define RESETS_RESET_DONE_DMA_BITS _u(0x00000004) +#define RESETS_RESET_DONE_DMA_MSB _u(2) +#define RESETS_RESET_DONE_DMA_LSB _u(2) #define RESETS_RESET_DONE_DMA_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_BUSCTRL // Description : None -#define RESETS_RESET_DONE_BUSCTRL_RESET 0x0 -#define RESETS_RESET_DONE_BUSCTRL_BITS 0x00000002 -#define RESETS_RESET_DONE_BUSCTRL_MSB 1 -#define RESETS_RESET_DONE_BUSCTRL_LSB 1 +#define RESETS_RESET_DONE_BUSCTRL_RESET _u(0x0) +#define RESETS_RESET_DONE_BUSCTRL_BITS _u(0x00000002) +#define RESETS_RESET_DONE_BUSCTRL_MSB _u(1) +#define RESETS_RESET_DONE_BUSCTRL_LSB _u(1) #define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_ADC // Description : None -#define RESETS_RESET_DONE_ADC_RESET 0x0 -#define RESETS_RESET_DONE_ADC_BITS 0x00000001 -#define RESETS_RESET_DONE_ADC_MSB 0 -#define RESETS_RESET_DONE_ADC_LSB 0 +#define RESETS_RESET_DONE_ADC_RESET _u(0x0) +#define RESETS_RESET_DONE_ADC_BITS _u(0x00000001) +#define RESETS_RESET_DONE_ADC_MSB _u(0) +#define RESETS_RESET_DONE_ADC_LSB _u(0) #define RESETS_RESET_DONE_ADC_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_RESETS_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rosc.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rosc.h index 1f9e8ccc5..5501e7ef2 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rosc.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rosc.h @@ -14,9 +14,9 @@ // ============================================================================= // Register : ROSC_CTRL // Description : Ring Oscillator control -#define ROSC_CTRL_OFFSET 0x00000000 -#define ROSC_CTRL_BITS 0x00ffffff -#define ROSC_CTRL_RESET 0x00000aa0 +#define ROSC_CTRL_OFFSET _u(0x00000000) +#define ROSC_CTRL_BITS _u(0x00ffffff) +#define ROSC_CTRL_RESET _u(0x00000aa0) // ----------------------------------------------------------------------------- // Field : ROSC_CTRL_ENABLE // Description : On power-up this field is initialised to ENABLE @@ -28,12 +28,12 @@ // 0xd1e -> DISABLE // 0xfab -> ENABLE #define ROSC_CTRL_ENABLE_RESET "-" -#define ROSC_CTRL_ENABLE_BITS 0x00fff000 -#define ROSC_CTRL_ENABLE_MSB 23 -#define ROSC_CTRL_ENABLE_LSB 12 +#define ROSC_CTRL_ENABLE_BITS _u(0x00fff000) +#define ROSC_CTRL_ENABLE_MSB _u(23) +#define ROSC_CTRL_ENABLE_LSB _u(12) #define ROSC_CTRL_ENABLE_ACCESS "RW" -#define ROSC_CTRL_ENABLE_VALUE_DISABLE 0xd1e -#define ROSC_CTRL_ENABLE_VALUE_ENABLE 0xfab +#define ROSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e) +#define ROSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab) // ----------------------------------------------------------------------------- // Field : ROSC_CTRL_FREQ_RANGE // Description : Controls the number of delay stages in the ROSC ring @@ -51,15 +51,15 @@ // 0xfa5 -> MEDIUM // 0xfa7 -> HIGH // 0xfa6 -> TOOHIGH -#define ROSC_CTRL_FREQ_RANGE_RESET 0xaa0 -#define ROSC_CTRL_FREQ_RANGE_BITS 0x00000fff -#define ROSC_CTRL_FREQ_RANGE_MSB 11 -#define ROSC_CTRL_FREQ_RANGE_LSB 0 +#define ROSC_CTRL_FREQ_RANGE_RESET _u(0xaa0) +#define ROSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff) +#define ROSC_CTRL_FREQ_RANGE_MSB _u(11) +#define ROSC_CTRL_FREQ_RANGE_LSB _u(0) #define ROSC_CTRL_FREQ_RANGE_ACCESS "RW" -#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW 0xfa4 -#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM 0xfa5 -#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH 0xfa7 -#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH 0xfa6 +#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW _u(0xfa4) +#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM _u(0xfa5) +#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH _u(0xfa7) +#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH _u(0xfa6) // ============================================================================= // Register : ROSC_FREQA // Description : The FREQA & FREQB registers control the frequency by @@ -72,100 +72,100 @@ // 1 bit set doubles the drive strength // 2 bits set triples drive strength // 3 bits set quadruples drive strength -#define ROSC_FREQA_OFFSET 0x00000004 -#define ROSC_FREQA_BITS 0xffff7777 -#define ROSC_FREQA_RESET 0x00000000 +#define ROSC_FREQA_OFFSET _u(0x00000004) +#define ROSC_FREQA_BITS _u(0xffff7777) +#define ROSC_FREQA_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ROSC_FREQA_PASSWD // Description : Set to 0x9696 to apply the settings // Any other value in this field will set all drive strengths to 0 // 0x9696 -> PASS -#define ROSC_FREQA_PASSWD_RESET 0x0000 -#define ROSC_FREQA_PASSWD_BITS 0xffff0000 -#define ROSC_FREQA_PASSWD_MSB 31 -#define ROSC_FREQA_PASSWD_LSB 16 +#define ROSC_FREQA_PASSWD_RESET _u(0x0000) +#define ROSC_FREQA_PASSWD_BITS _u(0xffff0000) +#define ROSC_FREQA_PASSWD_MSB _u(31) +#define ROSC_FREQA_PASSWD_LSB _u(16) #define ROSC_FREQA_PASSWD_ACCESS "RW" -#define ROSC_FREQA_PASSWD_VALUE_PASS 0x9696 +#define ROSC_FREQA_PASSWD_VALUE_PASS _u(0x9696) // ----------------------------------------------------------------------------- // Field : ROSC_FREQA_DS3 // Description : Stage 3 drive strength -#define ROSC_FREQA_DS3_RESET 0x0 -#define ROSC_FREQA_DS3_BITS 0x00007000 -#define ROSC_FREQA_DS3_MSB 14 -#define ROSC_FREQA_DS3_LSB 12 +#define ROSC_FREQA_DS3_RESET _u(0x0) +#define ROSC_FREQA_DS3_BITS _u(0x00007000) +#define ROSC_FREQA_DS3_MSB _u(14) +#define ROSC_FREQA_DS3_LSB _u(12) #define ROSC_FREQA_DS3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ROSC_FREQA_DS2 // Description : Stage 2 drive strength -#define ROSC_FREQA_DS2_RESET 0x0 -#define ROSC_FREQA_DS2_BITS 0x00000700 -#define ROSC_FREQA_DS2_MSB 10 -#define ROSC_FREQA_DS2_LSB 8 +#define ROSC_FREQA_DS2_RESET _u(0x0) +#define ROSC_FREQA_DS2_BITS _u(0x00000700) +#define ROSC_FREQA_DS2_MSB _u(10) +#define ROSC_FREQA_DS2_LSB _u(8) #define ROSC_FREQA_DS2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ROSC_FREQA_DS1 // Description : Stage 1 drive strength -#define ROSC_FREQA_DS1_RESET 0x0 -#define ROSC_FREQA_DS1_BITS 0x00000070 -#define ROSC_FREQA_DS1_MSB 6 -#define ROSC_FREQA_DS1_LSB 4 +#define ROSC_FREQA_DS1_RESET _u(0x0) +#define ROSC_FREQA_DS1_BITS _u(0x00000070) +#define ROSC_FREQA_DS1_MSB _u(6) +#define ROSC_FREQA_DS1_LSB _u(4) #define ROSC_FREQA_DS1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ROSC_FREQA_DS0 // Description : Stage 0 drive strength -#define ROSC_FREQA_DS0_RESET 0x0 -#define ROSC_FREQA_DS0_BITS 0x00000007 -#define ROSC_FREQA_DS0_MSB 2 -#define ROSC_FREQA_DS0_LSB 0 +#define ROSC_FREQA_DS0_RESET _u(0x0) +#define ROSC_FREQA_DS0_BITS _u(0x00000007) +#define ROSC_FREQA_DS0_MSB _u(2) +#define ROSC_FREQA_DS0_LSB _u(0) #define ROSC_FREQA_DS0_ACCESS "RW" // ============================================================================= // Register : ROSC_FREQB // Description : For a detailed description see freqa register -#define ROSC_FREQB_OFFSET 0x00000008 -#define ROSC_FREQB_BITS 0xffff7777 -#define ROSC_FREQB_RESET 0x00000000 +#define ROSC_FREQB_OFFSET _u(0x00000008) +#define ROSC_FREQB_BITS _u(0xffff7777) +#define ROSC_FREQB_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ROSC_FREQB_PASSWD // Description : Set to 0x9696 to apply the settings // Any other value in this field will set all drive strengths to 0 // 0x9696 -> PASS -#define ROSC_FREQB_PASSWD_RESET 0x0000 -#define ROSC_FREQB_PASSWD_BITS 0xffff0000 -#define ROSC_FREQB_PASSWD_MSB 31 -#define ROSC_FREQB_PASSWD_LSB 16 +#define ROSC_FREQB_PASSWD_RESET _u(0x0000) +#define ROSC_FREQB_PASSWD_BITS _u(0xffff0000) +#define ROSC_FREQB_PASSWD_MSB _u(31) +#define ROSC_FREQB_PASSWD_LSB _u(16) #define ROSC_FREQB_PASSWD_ACCESS "RW" -#define ROSC_FREQB_PASSWD_VALUE_PASS 0x9696 +#define ROSC_FREQB_PASSWD_VALUE_PASS _u(0x9696) // ----------------------------------------------------------------------------- // Field : ROSC_FREQB_DS7 // Description : Stage 7 drive strength -#define ROSC_FREQB_DS7_RESET 0x0 -#define ROSC_FREQB_DS7_BITS 0x00007000 -#define ROSC_FREQB_DS7_MSB 14 -#define ROSC_FREQB_DS7_LSB 12 +#define ROSC_FREQB_DS7_RESET _u(0x0) +#define ROSC_FREQB_DS7_BITS _u(0x00007000) +#define ROSC_FREQB_DS7_MSB _u(14) +#define ROSC_FREQB_DS7_LSB _u(12) #define ROSC_FREQB_DS7_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ROSC_FREQB_DS6 // Description : Stage 6 drive strength -#define ROSC_FREQB_DS6_RESET 0x0 -#define ROSC_FREQB_DS6_BITS 0x00000700 -#define ROSC_FREQB_DS6_MSB 10 -#define ROSC_FREQB_DS6_LSB 8 +#define ROSC_FREQB_DS6_RESET _u(0x0) +#define ROSC_FREQB_DS6_BITS _u(0x00000700) +#define ROSC_FREQB_DS6_MSB _u(10) +#define ROSC_FREQB_DS6_LSB _u(8) #define ROSC_FREQB_DS6_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ROSC_FREQB_DS5 // Description : Stage 5 drive strength -#define ROSC_FREQB_DS5_RESET 0x0 -#define ROSC_FREQB_DS5_BITS 0x00000070 -#define ROSC_FREQB_DS5_MSB 6 -#define ROSC_FREQB_DS5_LSB 4 +#define ROSC_FREQB_DS5_RESET _u(0x0) +#define ROSC_FREQB_DS5_BITS _u(0x00000070) +#define ROSC_FREQB_DS5_MSB _u(6) +#define ROSC_FREQB_DS5_LSB _u(4) #define ROSC_FREQB_DS5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ROSC_FREQB_DS4 // Description : Stage 4 drive strength -#define ROSC_FREQB_DS4_RESET 0x0 -#define ROSC_FREQB_DS4_BITS 0x00000007 -#define ROSC_FREQB_DS4_MSB 2 -#define ROSC_FREQB_DS4_LSB 0 +#define ROSC_FREQB_DS4_RESET _u(0x0) +#define ROSC_FREQB_DS4_BITS _u(0x00000007) +#define ROSC_FREQB_DS4_MSB _u(2) +#define ROSC_FREQB_DS4_LSB _u(0) #define ROSC_FREQB_DS4_ACCESS "RW" // ============================================================================= // Register : ROSC_DORMANT @@ -176,124 +176,124 @@ // Warning: setup the irq before selecting dormant mode // 0x636f6d61 -> DORMANT // 0x77616b65 -> WAKE -#define ROSC_DORMANT_OFFSET 0x0000000c -#define ROSC_DORMANT_BITS 0xffffffff +#define ROSC_DORMANT_OFFSET _u(0x0000000c) +#define ROSC_DORMANT_BITS _u(0xffffffff) #define ROSC_DORMANT_RESET "-" -#define ROSC_DORMANT_MSB 31 -#define ROSC_DORMANT_LSB 0 +#define ROSC_DORMANT_MSB _u(31) +#define ROSC_DORMANT_LSB _u(0) #define ROSC_DORMANT_ACCESS "RW" -#define ROSC_DORMANT_VALUE_DORMANT 0x636f6d61 -#define ROSC_DORMANT_VALUE_WAKE 0x77616b65 +#define ROSC_DORMANT_VALUE_DORMANT _u(0x636f6d61) +#define ROSC_DORMANT_VALUE_WAKE _u(0x77616b65) // ============================================================================= // Register : ROSC_DIV // Description : Controls the output divider // set to 0xaa0 + div where // div = 0 divides by 32 // div = 1-31 divides by div -// any other value sets div=0 and therefore divides by 32 +// any other value sets div=31 // this register resets to div=16 // 0xaa0 -> PASS -#define ROSC_DIV_OFFSET 0x00000010 -#define ROSC_DIV_BITS 0x00000fff +#define ROSC_DIV_OFFSET _u(0x00000010) +#define ROSC_DIV_BITS _u(0x00000fff) #define ROSC_DIV_RESET "-" -#define ROSC_DIV_MSB 11 -#define ROSC_DIV_LSB 0 +#define ROSC_DIV_MSB _u(11) +#define ROSC_DIV_LSB _u(0) #define ROSC_DIV_ACCESS "RW" -#define ROSC_DIV_VALUE_PASS 0xaa0 +#define ROSC_DIV_VALUE_PASS _u(0xaa0) // ============================================================================= // Register : ROSC_PHASE // Description : Controls the phase shifted output -#define ROSC_PHASE_OFFSET 0x00000014 -#define ROSC_PHASE_BITS 0x00000fff -#define ROSC_PHASE_RESET 0x00000008 +#define ROSC_PHASE_OFFSET _u(0x00000014) +#define ROSC_PHASE_BITS _u(0x00000fff) +#define ROSC_PHASE_RESET _u(0x00000008) // ----------------------------------------------------------------------------- // Field : ROSC_PHASE_PASSWD -// Description : set to 0xaa0 +// Description : set to 0xaa // any other value enables the output with shift=0 -#define ROSC_PHASE_PASSWD_RESET 0x00 -#define ROSC_PHASE_PASSWD_BITS 0x00000ff0 -#define ROSC_PHASE_PASSWD_MSB 11 -#define ROSC_PHASE_PASSWD_LSB 4 +#define ROSC_PHASE_PASSWD_RESET _u(0x00) +#define ROSC_PHASE_PASSWD_BITS _u(0x00000ff0) +#define ROSC_PHASE_PASSWD_MSB _u(11) +#define ROSC_PHASE_PASSWD_LSB _u(4) #define ROSC_PHASE_PASSWD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ROSC_PHASE_ENABLE // Description : enable the phase-shifted output // this can be changed on-the-fly -#define ROSC_PHASE_ENABLE_RESET 0x1 -#define ROSC_PHASE_ENABLE_BITS 0x00000008 -#define ROSC_PHASE_ENABLE_MSB 3 -#define ROSC_PHASE_ENABLE_LSB 3 +#define ROSC_PHASE_ENABLE_RESET _u(0x1) +#define ROSC_PHASE_ENABLE_BITS _u(0x00000008) +#define ROSC_PHASE_ENABLE_MSB _u(3) +#define ROSC_PHASE_ENABLE_LSB _u(3) #define ROSC_PHASE_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ROSC_PHASE_FLIP // Description : invert the phase-shifted output // this is ignored when div=1 -#define ROSC_PHASE_FLIP_RESET 0x0 -#define ROSC_PHASE_FLIP_BITS 0x00000004 -#define ROSC_PHASE_FLIP_MSB 2 -#define ROSC_PHASE_FLIP_LSB 2 +#define ROSC_PHASE_FLIP_RESET _u(0x0) +#define ROSC_PHASE_FLIP_BITS _u(0x00000004) +#define ROSC_PHASE_FLIP_MSB _u(2) +#define ROSC_PHASE_FLIP_LSB _u(2) #define ROSC_PHASE_FLIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : ROSC_PHASE_SHIFT // Description : phase shift the phase-shifted output by SHIFT input clocks // this can be changed on-the-fly // must be set to 0 before setting div=1 -#define ROSC_PHASE_SHIFT_RESET 0x0 -#define ROSC_PHASE_SHIFT_BITS 0x00000003 -#define ROSC_PHASE_SHIFT_MSB 1 -#define ROSC_PHASE_SHIFT_LSB 0 +#define ROSC_PHASE_SHIFT_RESET _u(0x0) +#define ROSC_PHASE_SHIFT_BITS _u(0x00000003) +#define ROSC_PHASE_SHIFT_MSB _u(1) +#define ROSC_PHASE_SHIFT_LSB _u(0) #define ROSC_PHASE_SHIFT_ACCESS "RW" // ============================================================================= // Register : ROSC_STATUS // Description : Ring Oscillator Status -#define ROSC_STATUS_OFFSET 0x00000018 -#define ROSC_STATUS_BITS 0x81011000 -#define ROSC_STATUS_RESET 0x00000000 +#define ROSC_STATUS_OFFSET _u(0x00000018) +#define ROSC_STATUS_BITS _u(0x81011000) +#define ROSC_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : ROSC_STATUS_STABLE // Description : Oscillator is running and stable -#define ROSC_STATUS_STABLE_RESET 0x0 -#define ROSC_STATUS_STABLE_BITS 0x80000000 -#define ROSC_STATUS_STABLE_MSB 31 -#define ROSC_STATUS_STABLE_LSB 31 +#define ROSC_STATUS_STABLE_RESET _u(0x0) +#define ROSC_STATUS_STABLE_BITS _u(0x80000000) +#define ROSC_STATUS_STABLE_MSB _u(31) +#define ROSC_STATUS_STABLE_LSB _u(31) #define ROSC_STATUS_STABLE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : ROSC_STATUS_BADWRITE // Description : An invalid value has been written to CTRL_ENABLE or -// CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT -#define ROSC_STATUS_BADWRITE_RESET 0x0 -#define ROSC_STATUS_BADWRITE_BITS 0x01000000 -#define ROSC_STATUS_BADWRITE_MSB 24 -#define ROSC_STATUS_BADWRITE_LSB 24 +// CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT +#define ROSC_STATUS_BADWRITE_RESET _u(0x0) +#define ROSC_STATUS_BADWRITE_BITS _u(0x01000000) +#define ROSC_STATUS_BADWRITE_MSB _u(24) +#define ROSC_STATUS_BADWRITE_LSB _u(24) #define ROSC_STATUS_BADWRITE_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : ROSC_STATUS_DIV_RUNNING // Description : post-divider is running // this resets to 0 but transitions to 1 during chip startup #define ROSC_STATUS_DIV_RUNNING_RESET "-" -#define ROSC_STATUS_DIV_RUNNING_BITS 0x00010000 -#define ROSC_STATUS_DIV_RUNNING_MSB 16 -#define ROSC_STATUS_DIV_RUNNING_LSB 16 +#define ROSC_STATUS_DIV_RUNNING_BITS _u(0x00010000) +#define ROSC_STATUS_DIV_RUNNING_MSB _u(16) +#define ROSC_STATUS_DIV_RUNNING_LSB _u(16) #define ROSC_STATUS_DIV_RUNNING_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : ROSC_STATUS_ENABLED // Description : Oscillator is enabled but not necessarily running and stable // this resets to 0 but transitions to 1 during chip startup #define ROSC_STATUS_ENABLED_RESET "-" -#define ROSC_STATUS_ENABLED_BITS 0x00001000 -#define ROSC_STATUS_ENABLED_MSB 12 -#define ROSC_STATUS_ENABLED_LSB 12 +#define ROSC_STATUS_ENABLED_BITS _u(0x00001000) +#define ROSC_STATUS_ENABLED_MSB _u(12) +#define ROSC_STATUS_ENABLED_LSB _u(12) #define ROSC_STATUS_ENABLED_ACCESS "RO" // ============================================================================= // Register : ROSC_RANDOMBIT // Description : This just reads the state of the oscillator output so // randomness is compromised if the ring oscillator is stopped or // run at a harmonic of the bus frequency -#define ROSC_RANDOMBIT_OFFSET 0x0000001c -#define ROSC_RANDOMBIT_BITS 0x00000001 -#define ROSC_RANDOMBIT_RESET 0x00000001 -#define ROSC_RANDOMBIT_MSB 0 -#define ROSC_RANDOMBIT_LSB 0 +#define ROSC_RANDOMBIT_OFFSET _u(0x0000001c) +#define ROSC_RANDOMBIT_BITS _u(0x00000001) +#define ROSC_RANDOMBIT_RESET _u(0x00000001) +#define ROSC_RANDOMBIT_MSB _u(0) +#define ROSC_RANDOMBIT_LSB _u(0) #define ROSC_RANDOMBIT_ACCESS "RO" // ============================================================================= // Register : ROSC_COUNT @@ -302,11 +302,11 @@ // To start the counter write a non-zero value. // Can be used for short software pauses when setting up time // sensitive hardware. -#define ROSC_COUNT_OFFSET 0x00000020 -#define ROSC_COUNT_BITS 0x000000ff -#define ROSC_COUNT_RESET 0x00000000 -#define ROSC_COUNT_MSB 7 -#define ROSC_COUNT_LSB 0 +#define ROSC_COUNT_OFFSET _u(0x00000020) +#define ROSC_COUNT_BITS _u(0x000000ff) +#define ROSC_COUNT_RESET _u(0x00000000) +#define ROSC_COUNT_MSB _u(7) +#define ROSC_COUNT_LSB _u(0) #define ROSC_COUNT_ACCESS "RW" // ============================================================================= #endif // HARDWARE_REGS_ROSC_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rtc.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rtc.h index 1287d9023..7d62c9d73 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rtc.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/rtc.h @@ -15,384 +15,384 @@ // Register : RTC_CLKDIV_M1 // Description : Divider minus 1 for the 1 second counter. Safe to change the // value when RTC is not enabled. -#define RTC_CLKDIV_M1_OFFSET 0x00000000 -#define RTC_CLKDIV_M1_BITS 0x0000ffff -#define RTC_CLKDIV_M1_RESET 0x00000000 -#define RTC_CLKDIV_M1_MSB 15 -#define RTC_CLKDIV_M1_LSB 0 +#define RTC_CLKDIV_M1_OFFSET _u(0x00000000) +#define RTC_CLKDIV_M1_BITS _u(0x0000ffff) +#define RTC_CLKDIV_M1_RESET _u(0x00000000) +#define RTC_CLKDIV_M1_MSB _u(15) +#define RTC_CLKDIV_M1_LSB _u(0) #define RTC_CLKDIV_M1_ACCESS "RW" // ============================================================================= // Register : RTC_SETUP_0 // Description : RTC setup register 0 -#define RTC_SETUP_0_OFFSET 0x00000004 -#define RTC_SETUP_0_BITS 0x00ffff1f -#define RTC_SETUP_0_RESET 0x00000000 +#define RTC_SETUP_0_OFFSET _u(0x00000004) +#define RTC_SETUP_0_BITS _u(0x00ffff1f) +#define RTC_SETUP_0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_SETUP_0_YEAR // Description : Year -#define RTC_SETUP_0_YEAR_RESET 0x000 -#define RTC_SETUP_0_YEAR_BITS 0x00fff000 -#define RTC_SETUP_0_YEAR_MSB 23 -#define RTC_SETUP_0_YEAR_LSB 12 +#define RTC_SETUP_0_YEAR_RESET _u(0x000) +#define RTC_SETUP_0_YEAR_BITS _u(0x00fff000) +#define RTC_SETUP_0_YEAR_MSB _u(23) +#define RTC_SETUP_0_YEAR_LSB _u(12) #define RTC_SETUP_0_YEAR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_SETUP_0_MONTH // Description : Month (1..12) -#define RTC_SETUP_0_MONTH_RESET 0x0 -#define RTC_SETUP_0_MONTH_BITS 0x00000f00 -#define RTC_SETUP_0_MONTH_MSB 11 -#define RTC_SETUP_0_MONTH_LSB 8 +#define RTC_SETUP_0_MONTH_RESET _u(0x0) +#define RTC_SETUP_0_MONTH_BITS _u(0x00000f00) +#define RTC_SETUP_0_MONTH_MSB _u(11) +#define RTC_SETUP_0_MONTH_LSB _u(8) #define RTC_SETUP_0_MONTH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_SETUP_0_DAY // Description : Day of the month (1..31) -#define RTC_SETUP_0_DAY_RESET 0x00 -#define RTC_SETUP_0_DAY_BITS 0x0000001f -#define RTC_SETUP_0_DAY_MSB 4 -#define RTC_SETUP_0_DAY_LSB 0 +#define RTC_SETUP_0_DAY_RESET _u(0x00) +#define RTC_SETUP_0_DAY_BITS _u(0x0000001f) +#define RTC_SETUP_0_DAY_MSB _u(4) +#define RTC_SETUP_0_DAY_LSB _u(0) #define RTC_SETUP_0_DAY_ACCESS "RW" // ============================================================================= // Register : RTC_SETUP_1 // Description : RTC setup register 1 -#define RTC_SETUP_1_OFFSET 0x00000008 -#define RTC_SETUP_1_BITS 0x071f3f3f -#define RTC_SETUP_1_RESET 0x00000000 +#define RTC_SETUP_1_OFFSET _u(0x00000008) +#define RTC_SETUP_1_BITS _u(0x071f3f3f) +#define RTC_SETUP_1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_SETUP_1_DOTW // Description : Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7 -#define RTC_SETUP_1_DOTW_RESET 0x0 -#define RTC_SETUP_1_DOTW_BITS 0x07000000 -#define RTC_SETUP_1_DOTW_MSB 26 -#define RTC_SETUP_1_DOTW_LSB 24 +#define RTC_SETUP_1_DOTW_RESET _u(0x0) +#define RTC_SETUP_1_DOTW_BITS _u(0x07000000) +#define RTC_SETUP_1_DOTW_MSB _u(26) +#define RTC_SETUP_1_DOTW_LSB _u(24) #define RTC_SETUP_1_DOTW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_SETUP_1_HOUR // Description : Hours -#define RTC_SETUP_1_HOUR_RESET 0x00 -#define RTC_SETUP_1_HOUR_BITS 0x001f0000 -#define RTC_SETUP_1_HOUR_MSB 20 -#define RTC_SETUP_1_HOUR_LSB 16 +#define RTC_SETUP_1_HOUR_RESET _u(0x00) +#define RTC_SETUP_1_HOUR_BITS _u(0x001f0000) +#define RTC_SETUP_1_HOUR_MSB _u(20) +#define RTC_SETUP_1_HOUR_LSB _u(16) #define RTC_SETUP_1_HOUR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_SETUP_1_MIN // Description : Minutes -#define RTC_SETUP_1_MIN_RESET 0x00 -#define RTC_SETUP_1_MIN_BITS 0x00003f00 -#define RTC_SETUP_1_MIN_MSB 13 -#define RTC_SETUP_1_MIN_LSB 8 +#define RTC_SETUP_1_MIN_RESET _u(0x00) +#define RTC_SETUP_1_MIN_BITS _u(0x00003f00) +#define RTC_SETUP_1_MIN_MSB _u(13) +#define RTC_SETUP_1_MIN_LSB _u(8) #define RTC_SETUP_1_MIN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_SETUP_1_SEC // Description : Seconds -#define RTC_SETUP_1_SEC_RESET 0x00 -#define RTC_SETUP_1_SEC_BITS 0x0000003f -#define RTC_SETUP_1_SEC_MSB 5 -#define RTC_SETUP_1_SEC_LSB 0 +#define RTC_SETUP_1_SEC_RESET _u(0x00) +#define RTC_SETUP_1_SEC_BITS _u(0x0000003f) +#define RTC_SETUP_1_SEC_MSB _u(5) +#define RTC_SETUP_1_SEC_LSB _u(0) #define RTC_SETUP_1_SEC_ACCESS "RW" // ============================================================================= // Register : RTC_CTRL // Description : RTC Control and status -#define RTC_CTRL_OFFSET 0x0000000c -#define RTC_CTRL_BITS 0x00000113 -#define RTC_CTRL_RESET 0x00000000 +#define RTC_CTRL_OFFSET _u(0x0000000c) +#define RTC_CTRL_BITS _u(0x00000113) +#define RTC_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_CTRL_FORCE_NOTLEAPYEAR // Description : If set, leapyear is forced off. // Useful for years divisible by 100 but not by 400 -#define RTC_CTRL_FORCE_NOTLEAPYEAR_RESET 0x0 -#define RTC_CTRL_FORCE_NOTLEAPYEAR_BITS 0x00000100 -#define RTC_CTRL_FORCE_NOTLEAPYEAR_MSB 8 -#define RTC_CTRL_FORCE_NOTLEAPYEAR_LSB 8 +#define RTC_CTRL_FORCE_NOTLEAPYEAR_RESET _u(0x0) +#define RTC_CTRL_FORCE_NOTLEAPYEAR_BITS _u(0x00000100) +#define RTC_CTRL_FORCE_NOTLEAPYEAR_MSB _u(8) +#define RTC_CTRL_FORCE_NOTLEAPYEAR_LSB _u(8) #define RTC_CTRL_FORCE_NOTLEAPYEAR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_CTRL_LOAD // Description : Load RTC -#define RTC_CTRL_LOAD_RESET 0x0 -#define RTC_CTRL_LOAD_BITS 0x00000010 -#define RTC_CTRL_LOAD_MSB 4 -#define RTC_CTRL_LOAD_LSB 4 +#define RTC_CTRL_LOAD_RESET _u(0x0) +#define RTC_CTRL_LOAD_BITS _u(0x00000010) +#define RTC_CTRL_LOAD_MSB _u(4) +#define RTC_CTRL_LOAD_LSB _u(4) #define RTC_CTRL_LOAD_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : RTC_CTRL_RTC_ACTIVE // Description : RTC enabled (running) #define RTC_CTRL_RTC_ACTIVE_RESET "-" -#define RTC_CTRL_RTC_ACTIVE_BITS 0x00000002 -#define RTC_CTRL_RTC_ACTIVE_MSB 1 -#define RTC_CTRL_RTC_ACTIVE_LSB 1 +#define RTC_CTRL_RTC_ACTIVE_BITS _u(0x00000002) +#define RTC_CTRL_RTC_ACTIVE_MSB _u(1) +#define RTC_CTRL_RTC_ACTIVE_LSB _u(1) #define RTC_CTRL_RTC_ACTIVE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RTC_CTRL_RTC_ENABLE // Description : Enable RTC -#define RTC_CTRL_RTC_ENABLE_RESET 0x0 -#define RTC_CTRL_RTC_ENABLE_BITS 0x00000001 -#define RTC_CTRL_RTC_ENABLE_MSB 0 -#define RTC_CTRL_RTC_ENABLE_LSB 0 +#define RTC_CTRL_RTC_ENABLE_RESET _u(0x0) +#define RTC_CTRL_RTC_ENABLE_BITS _u(0x00000001) +#define RTC_CTRL_RTC_ENABLE_MSB _u(0) +#define RTC_CTRL_RTC_ENABLE_LSB _u(0) #define RTC_CTRL_RTC_ENABLE_ACCESS "RW" // ============================================================================= // Register : RTC_IRQ_SETUP_0 // Description : Interrupt setup register 0 -#define RTC_IRQ_SETUP_0_OFFSET 0x00000010 -#define RTC_IRQ_SETUP_0_BITS 0x37ffff1f -#define RTC_IRQ_SETUP_0_RESET 0x00000000 +#define RTC_IRQ_SETUP_0_OFFSET _u(0x00000010) +#define RTC_IRQ_SETUP_0_BITS _u(0x37ffff1f) +#define RTC_IRQ_SETUP_0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_0_MATCH_ACTIVE // Description : None #define RTC_IRQ_SETUP_0_MATCH_ACTIVE_RESET "-" -#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS 0x20000000 -#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB 29 -#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_LSB 29 +#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS _u(0x20000000) +#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB _u(29) +#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_LSB _u(29) #define RTC_IRQ_SETUP_0_MATCH_ACTIVE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_0_MATCH_ENA // Description : Global match enable. Don't change any other value while this // one is enabled -#define RTC_IRQ_SETUP_0_MATCH_ENA_RESET 0x0 -#define RTC_IRQ_SETUP_0_MATCH_ENA_BITS 0x10000000 -#define RTC_IRQ_SETUP_0_MATCH_ENA_MSB 28 -#define RTC_IRQ_SETUP_0_MATCH_ENA_LSB 28 +#define RTC_IRQ_SETUP_0_MATCH_ENA_RESET _u(0x0) +#define RTC_IRQ_SETUP_0_MATCH_ENA_BITS _u(0x10000000) +#define RTC_IRQ_SETUP_0_MATCH_ENA_MSB _u(28) +#define RTC_IRQ_SETUP_0_MATCH_ENA_LSB _u(28) #define RTC_IRQ_SETUP_0_MATCH_ENA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_0_YEAR_ENA // Description : Enable year matching -#define RTC_IRQ_SETUP_0_YEAR_ENA_RESET 0x0 -#define RTC_IRQ_SETUP_0_YEAR_ENA_BITS 0x04000000 -#define RTC_IRQ_SETUP_0_YEAR_ENA_MSB 26 -#define RTC_IRQ_SETUP_0_YEAR_ENA_LSB 26 +#define RTC_IRQ_SETUP_0_YEAR_ENA_RESET _u(0x0) +#define RTC_IRQ_SETUP_0_YEAR_ENA_BITS _u(0x04000000) +#define RTC_IRQ_SETUP_0_YEAR_ENA_MSB _u(26) +#define RTC_IRQ_SETUP_0_YEAR_ENA_LSB _u(26) #define RTC_IRQ_SETUP_0_YEAR_ENA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_0_MONTH_ENA // Description : Enable month matching -#define RTC_IRQ_SETUP_0_MONTH_ENA_RESET 0x0 -#define RTC_IRQ_SETUP_0_MONTH_ENA_BITS 0x02000000 -#define RTC_IRQ_SETUP_0_MONTH_ENA_MSB 25 -#define RTC_IRQ_SETUP_0_MONTH_ENA_LSB 25 +#define RTC_IRQ_SETUP_0_MONTH_ENA_RESET _u(0x0) +#define RTC_IRQ_SETUP_0_MONTH_ENA_BITS _u(0x02000000) +#define RTC_IRQ_SETUP_0_MONTH_ENA_MSB _u(25) +#define RTC_IRQ_SETUP_0_MONTH_ENA_LSB _u(25) #define RTC_IRQ_SETUP_0_MONTH_ENA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_0_DAY_ENA // Description : Enable day matching -#define RTC_IRQ_SETUP_0_DAY_ENA_RESET 0x0 -#define RTC_IRQ_SETUP_0_DAY_ENA_BITS 0x01000000 -#define RTC_IRQ_SETUP_0_DAY_ENA_MSB 24 -#define RTC_IRQ_SETUP_0_DAY_ENA_LSB 24 +#define RTC_IRQ_SETUP_0_DAY_ENA_RESET _u(0x0) +#define RTC_IRQ_SETUP_0_DAY_ENA_BITS _u(0x01000000) +#define RTC_IRQ_SETUP_0_DAY_ENA_MSB _u(24) +#define RTC_IRQ_SETUP_0_DAY_ENA_LSB _u(24) #define RTC_IRQ_SETUP_0_DAY_ENA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_0_YEAR // Description : Year -#define RTC_IRQ_SETUP_0_YEAR_RESET 0x000 -#define RTC_IRQ_SETUP_0_YEAR_BITS 0x00fff000 -#define RTC_IRQ_SETUP_0_YEAR_MSB 23 -#define RTC_IRQ_SETUP_0_YEAR_LSB 12 +#define RTC_IRQ_SETUP_0_YEAR_RESET _u(0x000) +#define RTC_IRQ_SETUP_0_YEAR_BITS _u(0x00fff000) +#define RTC_IRQ_SETUP_0_YEAR_MSB _u(23) +#define RTC_IRQ_SETUP_0_YEAR_LSB _u(12) #define RTC_IRQ_SETUP_0_YEAR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_0_MONTH // Description : Month (1..12) -#define RTC_IRQ_SETUP_0_MONTH_RESET 0x0 -#define RTC_IRQ_SETUP_0_MONTH_BITS 0x00000f00 -#define RTC_IRQ_SETUP_0_MONTH_MSB 11 -#define RTC_IRQ_SETUP_0_MONTH_LSB 8 +#define RTC_IRQ_SETUP_0_MONTH_RESET _u(0x0) +#define RTC_IRQ_SETUP_0_MONTH_BITS _u(0x00000f00) +#define RTC_IRQ_SETUP_0_MONTH_MSB _u(11) +#define RTC_IRQ_SETUP_0_MONTH_LSB _u(8) #define RTC_IRQ_SETUP_0_MONTH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_0_DAY // Description : Day of the month (1..31) -#define RTC_IRQ_SETUP_0_DAY_RESET 0x00 -#define RTC_IRQ_SETUP_0_DAY_BITS 0x0000001f -#define RTC_IRQ_SETUP_0_DAY_MSB 4 -#define RTC_IRQ_SETUP_0_DAY_LSB 0 +#define RTC_IRQ_SETUP_0_DAY_RESET _u(0x00) +#define RTC_IRQ_SETUP_0_DAY_BITS _u(0x0000001f) +#define RTC_IRQ_SETUP_0_DAY_MSB _u(4) +#define RTC_IRQ_SETUP_0_DAY_LSB _u(0) #define RTC_IRQ_SETUP_0_DAY_ACCESS "RW" // ============================================================================= // Register : RTC_IRQ_SETUP_1 // Description : Interrupt setup register 1 -#define RTC_IRQ_SETUP_1_OFFSET 0x00000014 -#define RTC_IRQ_SETUP_1_BITS 0xf71f3f3f -#define RTC_IRQ_SETUP_1_RESET 0x00000000 +#define RTC_IRQ_SETUP_1_OFFSET _u(0x00000014) +#define RTC_IRQ_SETUP_1_BITS _u(0xf71f3f3f) +#define RTC_IRQ_SETUP_1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_1_DOTW_ENA // Description : Enable day of the week matching -#define RTC_IRQ_SETUP_1_DOTW_ENA_RESET 0x0 -#define RTC_IRQ_SETUP_1_DOTW_ENA_BITS 0x80000000 -#define RTC_IRQ_SETUP_1_DOTW_ENA_MSB 31 -#define RTC_IRQ_SETUP_1_DOTW_ENA_LSB 31 +#define RTC_IRQ_SETUP_1_DOTW_ENA_RESET _u(0x0) +#define RTC_IRQ_SETUP_1_DOTW_ENA_BITS _u(0x80000000) +#define RTC_IRQ_SETUP_1_DOTW_ENA_MSB _u(31) +#define RTC_IRQ_SETUP_1_DOTW_ENA_LSB _u(31) #define RTC_IRQ_SETUP_1_DOTW_ENA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_1_HOUR_ENA // Description : Enable hour matching -#define RTC_IRQ_SETUP_1_HOUR_ENA_RESET 0x0 -#define RTC_IRQ_SETUP_1_HOUR_ENA_BITS 0x40000000 -#define RTC_IRQ_SETUP_1_HOUR_ENA_MSB 30 -#define RTC_IRQ_SETUP_1_HOUR_ENA_LSB 30 +#define RTC_IRQ_SETUP_1_HOUR_ENA_RESET _u(0x0) +#define RTC_IRQ_SETUP_1_HOUR_ENA_BITS _u(0x40000000) +#define RTC_IRQ_SETUP_1_HOUR_ENA_MSB _u(30) +#define RTC_IRQ_SETUP_1_HOUR_ENA_LSB _u(30) #define RTC_IRQ_SETUP_1_HOUR_ENA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_1_MIN_ENA // Description : Enable minute matching -#define RTC_IRQ_SETUP_1_MIN_ENA_RESET 0x0 -#define RTC_IRQ_SETUP_1_MIN_ENA_BITS 0x20000000 -#define RTC_IRQ_SETUP_1_MIN_ENA_MSB 29 -#define RTC_IRQ_SETUP_1_MIN_ENA_LSB 29 +#define RTC_IRQ_SETUP_1_MIN_ENA_RESET _u(0x0) +#define RTC_IRQ_SETUP_1_MIN_ENA_BITS _u(0x20000000) +#define RTC_IRQ_SETUP_1_MIN_ENA_MSB _u(29) +#define RTC_IRQ_SETUP_1_MIN_ENA_LSB _u(29) #define RTC_IRQ_SETUP_1_MIN_ENA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_1_SEC_ENA // Description : Enable second matching -#define RTC_IRQ_SETUP_1_SEC_ENA_RESET 0x0 -#define RTC_IRQ_SETUP_1_SEC_ENA_BITS 0x10000000 -#define RTC_IRQ_SETUP_1_SEC_ENA_MSB 28 -#define RTC_IRQ_SETUP_1_SEC_ENA_LSB 28 +#define RTC_IRQ_SETUP_1_SEC_ENA_RESET _u(0x0) +#define RTC_IRQ_SETUP_1_SEC_ENA_BITS _u(0x10000000) +#define RTC_IRQ_SETUP_1_SEC_ENA_MSB _u(28) +#define RTC_IRQ_SETUP_1_SEC_ENA_LSB _u(28) #define RTC_IRQ_SETUP_1_SEC_ENA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_1_DOTW // Description : Day of the week -#define RTC_IRQ_SETUP_1_DOTW_RESET 0x0 -#define RTC_IRQ_SETUP_1_DOTW_BITS 0x07000000 -#define RTC_IRQ_SETUP_1_DOTW_MSB 26 -#define RTC_IRQ_SETUP_1_DOTW_LSB 24 +#define RTC_IRQ_SETUP_1_DOTW_RESET _u(0x0) +#define RTC_IRQ_SETUP_1_DOTW_BITS _u(0x07000000) +#define RTC_IRQ_SETUP_1_DOTW_MSB _u(26) +#define RTC_IRQ_SETUP_1_DOTW_LSB _u(24) #define RTC_IRQ_SETUP_1_DOTW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_1_HOUR // Description : Hours -#define RTC_IRQ_SETUP_1_HOUR_RESET 0x00 -#define RTC_IRQ_SETUP_1_HOUR_BITS 0x001f0000 -#define RTC_IRQ_SETUP_1_HOUR_MSB 20 -#define RTC_IRQ_SETUP_1_HOUR_LSB 16 +#define RTC_IRQ_SETUP_1_HOUR_RESET _u(0x00) +#define RTC_IRQ_SETUP_1_HOUR_BITS _u(0x001f0000) +#define RTC_IRQ_SETUP_1_HOUR_MSB _u(20) +#define RTC_IRQ_SETUP_1_HOUR_LSB _u(16) #define RTC_IRQ_SETUP_1_HOUR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_1_MIN // Description : Minutes -#define RTC_IRQ_SETUP_1_MIN_RESET 0x00 -#define RTC_IRQ_SETUP_1_MIN_BITS 0x00003f00 -#define RTC_IRQ_SETUP_1_MIN_MSB 13 -#define RTC_IRQ_SETUP_1_MIN_LSB 8 +#define RTC_IRQ_SETUP_1_MIN_RESET _u(0x00) +#define RTC_IRQ_SETUP_1_MIN_BITS _u(0x00003f00) +#define RTC_IRQ_SETUP_1_MIN_MSB _u(13) +#define RTC_IRQ_SETUP_1_MIN_LSB _u(8) #define RTC_IRQ_SETUP_1_MIN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_1_SEC // Description : Seconds -#define RTC_IRQ_SETUP_1_SEC_RESET 0x00 -#define RTC_IRQ_SETUP_1_SEC_BITS 0x0000003f -#define RTC_IRQ_SETUP_1_SEC_MSB 5 -#define RTC_IRQ_SETUP_1_SEC_LSB 0 +#define RTC_IRQ_SETUP_1_SEC_RESET _u(0x00) +#define RTC_IRQ_SETUP_1_SEC_BITS _u(0x0000003f) +#define RTC_IRQ_SETUP_1_SEC_MSB _u(5) +#define RTC_IRQ_SETUP_1_SEC_LSB _u(0) #define RTC_IRQ_SETUP_1_SEC_ACCESS "RW" // ============================================================================= // Register : RTC_RTC_1 // Description : RTC register 1. -#define RTC_RTC_1_OFFSET 0x00000018 -#define RTC_RTC_1_BITS 0x00ffff1f -#define RTC_RTC_1_RESET 0x00000000 +#define RTC_RTC_1_OFFSET _u(0x00000018) +#define RTC_RTC_1_BITS _u(0x00ffff1f) +#define RTC_RTC_1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_RTC_1_YEAR // Description : Year #define RTC_RTC_1_YEAR_RESET "-" -#define RTC_RTC_1_YEAR_BITS 0x00fff000 -#define RTC_RTC_1_YEAR_MSB 23 -#define RTC_RTC_1_YEAR_LSB 12 +#define RTC_RTC_1_YEAR_BITS _u(0x00fff000) +#define RTC_RTC_1_YEAR_MSB _u(23) +#define RTC_RTC_1_YEAR_LSB _u(12) #define RTC_RTC_1_YEAR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RTC_RTC_1_MONTH // Description : Month (1..12) #define RTC_RTC_1_MONTH_RESET "-" -#define RTC_RTC_1_MONTH_BITS 0x00000f00 -#define RTC_RTC_1_MONTH_MSB 11 -#define RTC_RTC_1_MONTH_LSB 8 +#define RTC_RTC_1_MONTH_BITS _u(0x00000f00) +#define RTC_RTC_1_MONTH_MSB _u(11) +#define RTC_RTC_1_MONTH_LSB _u(8) #define RTC_RTC_1_MONTH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RTC_RTC_1_DAY // Description : Day of the month (1..31) #define RTC_RTC_1_DAY_RESET "-" -#define RTC_RTC_1_DAY_BITS 0x0000001f -#define RTC_RTC_1_DAY_MSB 4 -#define RTC_RTC_1_DAY_LSB 0 +#define RTC_RTC_1_DAY_BITS _u(0x0000001f) +#define RTC_RTC_1_DAY_MSB _u(4) +#define RTC_RTC_1_DAY_LSB _u(0) #define RTC_RTC_1_DAY_ACCESS "RO" // ============================================================================= // Register : RTC_RTC_0 // Description : RTC register 0 // Read this before RTC 1! -#define RTC_RTC_0_OFFSET 0x0000001c -#define RTC_RTC_0_BITS 0x071f3f3f -#define RTC_RTC_0_RESET 0x00000000 +#define RTC_RTC_0_OFFSET _u(0x0000001c) +#define RTC_RTC_0_BITS _u(0x071f3f3f) +#define RTC_RTC_0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_RTC_0_DOTW // Description : Day of the week #define RTC_RTC_0_DOTW_RESET "-" -#define RTC_RTC_0_DOTW_BITS 0x07000000 -#define RTC_RTC_0_DOTW_MSB 26 -#define RTC_RTC_0_DOTW_LSB 24 +#define RTC_RTC_0_DOTW_BITS _u(0x07000000) +#define RTC_RTC_0_DOTW_MSB _u(26) +#define RTC_RTC_0_DOTW_LSB _u(24) #define RTC_RTC_0_DOTW_ACCESS "RF" // ----------------------------------------------------------------------------- // Field : RTC_RTC_0_HOUR // Description : Hours #define RTC_RTC_0_HOUR_RESET "-" -#define RTC_RTC_0_HOUR_BITS 0x001f0000 -#define RTC_RTC_0_HOUR_MSB 20 -#define RTC_RTC_0_HOUR_LSB 16 +#define RTC_RTC_0_HOUR_BITS _u(0x001f0000) +#define RTC_RTC_0_HOUR_MSB _u(20) +#define RTC_RTC_0_HOUR_LSB _u(16) #define RTC_RTC_0_HOUR_ACCESS "RF" // ----------------------------------------------------------------------------- // Field : RTC_RTC_0_MIN // Description : Minutes #define RTC_RTC_0_MIN_RESET "-" -#define RTC_RTC_0_MIN_BITS 0x00003f00 -#define RTC_RTC_0_MIN_MSB 13 -#define RTC_RTC_0_MIN_LSB 8 +#define RTC_RTC_0_MIN_BITS _u(0x00003f00) +#define RTC_RTC_0_MIN_MSB _u(13) +#define RTC_RTC_0_MIN_LSB _u(8) #define RTC_RTC_0_MIN_ACCESS "RF" // ----------------------------------------------------------------------------- // Field : RTC_RTC_0_SEC // Description : Seconds #define RTC_RTC_0_SEC_RESET "-" -#define RTC_RTC_0_SEC_BITS 0x0000003f -#define RTC_RTC_0_SEC_MSB 5 -#define RTC_RTC_0_SEC_LSB 0 +#define RTC_RTC_0_SEC_BITS _u(0x0000003f) +#define RTC_RTC_0_SEC_MSB _u(5) +#define RTC_RTC_0_SEC_LSB _u(0) #define RTC_RTC_0_SEC_ACCESS "RF" // ============================================================================= // Register : RTC_INTR // Description : Raw Interrupts -#define RTC_INTR_OFFSET 0x00000020 -#define RTC_INTR_BITS 0x00000001 -#define RTC_INTR_RESET 0x00000000 +#define RTC_INTR_OFFSET _u(0x00000020) +#define RTC_INTR_BITS _u(0x00000001) +#define RTC_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_INTR_RTC // Description : None -#define RTC_INTR_RTC_RESET 0x0 -#define RTC_INTR_RTC_BITS 0x00000001 -#define RTC_INTR_RTC_MSB 0 -#define RTC_INTR_RTC_LSB 0 +#define RTC_INTR_RTC_RESET _u(0x0) +#define RTC_INTR_RTC_BITS _u(0x00000001) +#define RTC_INTR_RTC_MSB _u(0) +#define RTC_INTR_RTC_LSB _u(0) #define RTC_INTR_RTC_ACCESS "RO" // ============================================================================= // Register : RTC_INTE // Description : Interrupt Enable -#define RTC_INTE_OFFSET 0x00000024 -#define RTC_INTE_BITS 0x00000001 -#define RTC_INTE_RESET 0x00000000 +#define RTC_INTE_OFFSET _u(0x00000024) +#define RTC_INTE_BITS _u(0x00000001) +#define RTC_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_INTE_RTC // Description : None -#define RTC_INTE_RTC_RESET 0x0 -#define RTC_INTE_RTC_BITS 0x00000001 -#define RTC_INTE_RTC_MSB 0 -#define RTC_INTE_RTC_LSB 0 +#define RTC_INTE_RTC_RESET _u(0x0) +#define RTC_INTE_RTC_BITS _u(0x00000001) +#define RTC_INTE_RTC_MSB _u(0) +#define RTC_INTE_RTC_LSB _u(0) #define RTC_INTE_RTC_ACCESS "RW" // ============================================================================= // Register : RTC_INTF // Description : Interrupt Force -#define RTC_INTF_OFFSET 0x00000028 -#define RTC_INTF_BITS 0x00000001 -#define RTC_INTF_RESET 0x00000000 +#define RTC_INTF_OFFSET _u(0x00000028) +#define RTC_INTF_BITS _u(0x00000001) +#define RTC_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_INTF_RTC // Description : None -#define RTC_INTF_RTC_RESET 0x0 -#define RTC_INTF_RTC_BITS 0x00000001 -#define RTC_INTF_RTC_MSB 0 -#define RTC_INTF_RTC_LSB 0 +#define RTC_INTF_RTC_RESET _u(0x0) +#define RTC_INTF_RTC_BITS _u(0x00000001) +#define RTC_INTF_RTC_MSB _u(0) +#define RTC_INTF_RTC_LSB _u(0) #define RTC_INTF_RTC_ACCESS "RW" // ============================================================================= // Register : RTC_INTS // Description : Interrupt status after masking & forcing -#define RTC_INTS_OFFSET 0x0000002c -#define RTC_INTS_BITS 0x00000001 -#define RTC_INTS_RESET 0x00000000 +#define RTC_INTS_OFFSET _u(0x0000002c) +#define RTC_INTS_BITS _u(0x00000001) +#define RTC_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_INTS_RTC // Description : None -#define RTC_INTS_RTC_RESET 0x0 -#define RTC_INTS_RTC_BITS 0x00000001 -#define RTC_INTS_RTC_MSB 0 -#define RTC_INTS_RTC_LSB 0 +#define RTC_INTS_RTC_RESET _u(0x0) +#define RTC_INTS_RTC_BITS _u(0x00000001) +#define RTC_INTS_RTC_MSB _u(0) +#define RTC_INTS_RTC_LSB _u(0) #define RTC_INTS_RTC_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_RTC_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sio.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sio.h index 4480d76f0..f64153397 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sio.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sio.h @@ -18,32 +18,32 @@ // Description : Processor core identifier // Value is 0 when read from processor core 0, and 1 when read // from processor core 1. -#define SIO_CPUID_OFFSET 0x00000000 -#define SIO_CPUID_BITS 0xffffffff +#define SIO_CPUID_OFFSET _u(0x00000000) +#define SIO_CPUID_BITS _u(0xffffffff) #define SIO_CPUID_RESET "-" -#define SIO_CPUID_MSB 31 -#define SIO_CPUID_LSB 0 +#define SIO_CPUID_MSB _u(31) +#define SIO_CPUID_LSB _u(0) #define SIO_CPUID_ACCESS "RO" // ============================================================================= // Register : SIO_GPIO_IN // Description : Input value for GPIO pins // Input value for GPIO0...29 -#define SIO_GPIO_IN_OFFSET 0x00000004 -#define SIO_GPIO_IN_BITS 0x3fffffff -#define SIO_GPIO_IN_RESET 0x00000000 -#define SIO_GPIO_IN_MSB 29 -#define SIO_GPIO_IN_LSB 0 +#define SIO_GPIO_IN_OFFSET _u(0x00000004) +#define SIO_GPIO_IN_BITS _u(0x3fffffff) +#define SIO_GPIO_IN_RESET _u(0x00000000) +#define SIO_GPIO_IN_MSB _u(29) +#define SIO_GPIO_IN_LSB _u(0) #define SIO_GPIO_IN_ACCESS "RO" // ============================================================================= // Register : SIO_GPIO_HI_IN // Description : Input value for QSPI pins // Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, // SD3 -#define SIO_GPIO_HI_IN_OFFSET 0x00000008 -#define SIO_GPIO_HI_IN_BITS 0x0000003f -#define SIO_GPIO_HI_IN_RESET 0x00000000 -#define SIO_GPIO_HI_IN_MSB 5 -#define SIO_GPIO_HI_IN_LSB 0 +#define SIO_GPIO_HI_IN_OFFSET _u(0x00000008) +#define SIO_GPIO_HI_IN_BITS _u(0x0000003f) +#define SIO_GPIO_HI_IN_RESET _u(0x00000000) +#define SIO_GPIO_HI_IN_MSB _u(5) +#define SIO_GPIO_HI_IN_LSB _u(0) #define SIO_GPIO_HI_IN_ACCESS "RO" // ============================================================================= // Register : SIO_GPIO_OUT @@ -56,44 +56,44 @@ // the result is as though the write from core 0 took place first, // and the write from core 1 was then applied to that intermediate // result. -#define SIO_GPIO_OUT_OFFSET 0x00000010 -#define SIO_GPIO_OUT_BITS 0x3fffffff -#define SIO_GPIO_OUT_RESET 0x00000000 -#define SIO_GPIO_OUT_MSB 29 -#define SIO_GPIO_OUT_LSB 0 +#define SIO_GPIO_OUT_OFFSET _u(0x00000010) +#define SIO_GPIO_OUT_BITS _u(0x3fffffff) +#define SIO_GPIO_OUT_RESET _u(0x00000000) +#define SIO_GPIO_OUT_MSB _u(29) +#define SIO_GPIO_OUT_LSB _u(0) #define SIO_GPIO_OUT_ACCESS "RW" // ============================================================================= // Register : SIO_GPIO_OUT_SET // Description : GPIO output value set // Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` -#define SIO_GPIO_OUT_SET_OFFSET 0x00000014 -#define SIO_GPIO_OUT_SET_BITS 0x3fffffff -#define SIO_GPIO_OUT_SET_RESET 0x00000000 -#define SIO_GPIO_OUT_SET_MSB 29 -#define SIO_GPIO_OUT_SET_LSB 0 -#define SIO_GPIO_OUT_SET_ACCESS "RW" +#define SIO_GPIO_OUT_SET_OFFSET _u(0x00000014) +#define SIO_GPIO_OUT_SET_BITS _u(0x3fffffff) +#define SIO_GPIO_OUT_SET_RESET _u(0x00000000) +#define SIO_GPIO_OUT_SET_MSB _u(29) +#define SIO_GPIO_OUT_SET_LSB _u(0) +#define SIO_GPIO_OUT_SET_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_OUT_CLR // Description : GPIO output value clear // Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= // ~wdata` -#define SIO_GPIO_OUT_CLR_OFFSET 0x00000018 -#define SIO_GPIO_OUT_CLR_BITS 0x3fffffff -#define SIO_GPIO_OUT_CLR_RESET 0x00000000 -#define SIO_GPIO_OUT_CLR_MSB 29 -#define SIO_GPIO_OUT_CLR_LSB 0 -#define SIO_GPIO_OUT_CLR_ACCESS "RW" +#define SIO_GPIO_OUT_CLR_OFFSET _u(0x00000018) +#define SIO_GPIO_OUT_CLR_BITS _u(0x3fffffff) +#define SIO_GPIO_OUT_CLR_RESET _u(0x00000000) +#define SIO_GPIO_OUT_CLR_MSB _u(29) +#define SIO_GPIO_OUT_CLR_LSB _u(0) +#define SIO_GPIO_OUT_CLR_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_OUT_XOR // Description : GPIO output value XOR // Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= // wdata` -#define SIO_GPIO_OUT_XOR_OFFSET 0x0000001c -#define SIO_GPIO_OUT_XOR_BITS 0x3fffffff -#define SIO_GPIO_OUT_XOR_RESET 0x00000000 -#define SIO_GPIO_OUT_XOR_MSB 29 -#define SIO_GPIO_OUT_XOR_LSB 0 -#define SIO_GPIO_OUT_XOR_ACCESS "RW" +#define SIO_GPIO_OUT_XOR_OFFSET _u(0x0000001c) +#define SIO_GPIO_OUT_XOR_BITS _u(0x3fffffff) +#define SIO_GPIO_OUT_XOR_RESET _u(0x00000000) +#define SIO_GPIO_OUT_XOR_MSB _u(29) +#define SIO_GPIO_OUT_XOR_LSB _u(0) +#define SIO_GPIO_OUT_XOR_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_OE // Description : GPIO output enable @@ -104,44 +104,44 @@ // the result is as though the write from core 0 took place first, // and the write from core 1 was then applied to that intermediate // result. -#define SIO_GPIO_OE_OFFSET 0x00000020 -#define SIO_GPIO_OE_BITS 0x3fffffff -#define SIO_GPIO_OE_RESET 0x00000000 -#define SIO_GPIO_OE_MSB 29 -#define SIO_GPIO_OE_LSB 0 +#define SIO_GPIO_OE_OFFSET _u(0x00000020) +#define SIO_GPIO_OE_BITS _u(0x3fffffff) +#define SIO_GPIO_OE_RESET _u(0x00000000) +#define SIO_GPIO_OE_MSB _u(29) +#define SIO_GPIO_OE_LSB _u(0) #define SIO_GPIO_OE_ACCESS "RW" // ============================================================================= // Register : SIO_GPIO_OE_SET // Description : GPIO output enable set // Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` -#define SIO_GPIO_OE_SET_OFFSET 0x00000024 -#define SIO_GPIO_OE_SET_BITS 0x3fffffff -#define SIO_GPIO_OE_SET_RESET 0x00000000 -#define SIO_GPIO_OE_SET_MSB 29 -#define SIO_GPIO_OE_SET_LSB 0 -#define SIO_GPIO_OE_SET_ACCESS "RW" +#define SIO_GPIO_OE_SET_OFFSET _u(0x00000024) +#define SIO_GPIO_OE_SET_BITS _u(0x3fffffff) +#define SIO_GPIO_OE_SET_RESET _u(0x00000000) +#define SIO_GPIO_OE_SET_MSB _u(29) +#define SIO_GPIO_OE_SET_LSB _u(0) +#define SIO_GPIO_OE_SET_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_OE_CLR // Description : GPIO output enable clear // Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= // ~wdata` -#define SIO_GPIO_OE_CLR_OFFSET 0x00000028 -#define SIO_GPIO_OE_CLR_BITS 0x3fffffff -#define SIO_GPIO_OE_CLR_RESET 0x00000000 -#define SIO_GPIO_OE_CLR_MSB 29 -#define SIO_GPIO_OE_CLR_LSB 0 -#define SIO_GPIO_OE_CLR_ACCESS "RW" +#define SIO_GPIO_OE_CLR_OFFSET _u(0x00000028) +#define SIO_GPIO_OE_CLR_BITS _u(0x3fffffff) +#define SIO_GPIO_OE_CLR_RESET _u(0x00000000) +#define SIO_GPIO_OE_CLR_MSB _u(29) +#define SIO_GPIO_OE_CLR_LSB _u(0) +#define SIO_GPIO_OE_CLR_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_OE_XOR // Description : GPIO output enable XOR // Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= // wdata` -#define SIO_GPIO_OE_XOR_OFFSET 0x0000002c -#define SIO_GPIO_OE_XOR_BITS 0x3fffffff -#define SIO_GPIO_OE_XOR_RESET 0x00000000 -#define SIO_GPIO_OE_XOR_MSB 29 -#define SIO_GPIO_OE_XOR_LSB 0 -#define SIO_GPIO_OE_XOR_ACCESS "RW" +#define SIO_GPIO_OE_XOR_OFFSET _u(0x0000002c) +#define SIO_GPIO_OE_XOR_BITS _u(0x3fffffff) +#define SIO_GPIO_OE_XOR_RESET _u(0x00000000) +#define SIO_GPIO_OE_XOR_MSB _u(29) +#define SIO_GPIO_OE_XOR_LSB _u(0) +#define SIO_GPIO_OE_XOR_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_HI_OUT // Description : QSPI output value @@ -153,45 +153,45 @@ // the result is as though the write from core 0 took place first, // and the write from core 1 was then applied to that intermediate // result. -#define SIO_GPIO_HI_OUT_OFFSET 0x00000030 -#define SIO_GPIO_HI_OUT_BITS 0x0000003f -#define SIO_GPIO_HI_OUT_RESET 0x00000000 -#define SIO_GPIO_HI_OUT_MSB 5 -#define SIO_GPIO_HI_OUT_LSB 0 +#define SIO_GPIO_HI_OUT_OFFSET _u(0x00000030) +#define SIO_GPIO_HI_OUT_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OUT_RESET _u(0x00000000) +#define SIO_GPIO_HI_OUT_MSB _u(5) +#define SIO_GPIO_HI_OUT_LSB _u(0) #define SIO_GPIO_HI_OUT_ACCESS "RW" // ============================================================================= // Register : SIO_GPIO_HI_OUT_SET // Description : QSPI output value set // Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= // wdata` -#define SIO_GPIO_HI_OUT_SET_OFFSET 0x00000034 -#define SIO_GPIO_HI_OUT_SET_BITS 0x0000003f -#define SIO_GPIO_HI_OUT_SET_RESET 0x00000000 -#define SIO_GPIO_HI_OUT_SET_MSB 5 -#define SIO_GPIO_HI_OUT_SET_LSB 0 -#define SIO_GPIO_HI_OUT_SET_ACCESS "RW" +#define SIO_GPIO_HI_OUT_SET_OFFSET _u(0x00000034) +#define SIO_GPIO_HI_OUT_SET_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OUT_SET_RESET _u(0x00000000) +#define SIO_GPIO_HI_OUT_SET_MSB _u(5) +#define SIO_GPIO_HI_OUT_SET_LSB _u(0) +#define SIO_GPIO_HI_OUT_SET_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_HI_OUT_CLR // Description : QSPI output value clear // Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT // &= ~wdata` -#define SIO_GPIO_HI_OUT_CLR_OFFSET 0x00000038 -#define SIO_GPIO_HI_OUT_CLR_BITS 0x0000003f -#define SIO_GPIO_HI_OUT_CLR_RESET 0x00000000 -#define SIO_GPIO_HI_OUT_CLR_MSB 5 -#define SIO_GPIO_HI_OUT_CLR_LSB 0 -#define SIO_GPIO_HI_OUT_CLR_ACCESS "RW" +#define SIO_GPIO_HI_OUT_CLR_OFFSET _u(0x00000038) +#define SIO_GPIO_HI_OUT_CLR_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OUT_CLR_RESET _u(0x00000000) +#define SIO_GPIO_HI_OUT_CLR_MSB _u(5) +#define SIO_GPIO_HI_OUT_CLR_LSB _u(0) +#define SIO_GPIO_HI_OUT_CLR_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_HI_OUT_XOR // Description : QSPI output value XOR // Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT // ^= wdata` -#define SIO_GPIO_HI_OUT_XOR_OFFSET 0x0000003c -#define SIO_GPIO_HI_OUT_XOR_BITS 0x0000003f -#define SIO_GPIO_HI_OUT_XOR_RESET 0x00000000 -#define SIO_GPIO_HI_OUT_XOR_MSB 5 -#define SIO_GPIO_HI_OUT_XOR_LSB 0 -#define SIO_GPIO_HI_OUT_XOR_ACCESS "RW" +#define SIO_GPIO_HI_OUT_XOR_OFFSET _u(0x0000003c) +#define SIO_GPIO_HI_OUT_XOR_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OUT_XOR_RESET _u(0x00000000) +#define SIO_GPIO_HI_OUT_XOR_MSB _u(5) +#define SIO_GPIO_HI_OUT_XOR_LSB _u(0) +#define SIO_GPIO_HI_OUT_XOR_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_HI_OE // Description : QSPI output enable @@ -202,45 +202,45 @@ // the result is as though the write from core 0 took place first, // and the write from core 1 was then applied to that intermediate // result. -#define SIO_GPIO_HI_OE_OFFSET 0x00000040 -#define SIO_GPIO_HI_OE_BITS 0x0000003f -#define SIO_GPIO_HI_OE_RESET 0x00000000 -#define SIO_GPIO_HI_OE_MSB 5 -#define SIO_GPIO_HI_OE_LSB 0 +#define SIO_GPIO_HI_OE_OFFSET _u(0x00000040) +#define SIO_GPIO_HI_OE_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OE_RESET _u(0x00000000) +#define SIO_GPIO_HI_OE_MSB _u(5) +#define SIO_GPIO_HI_OE_LSB _u(0) #define SIO_GPIO_HI_OE_ACCESS "RW" // ============================================================================= // Register : SIO_GPIO_HI_OE_SET // Description : QSPI output enable set // Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= // wdata` -#define SIO_GPIO_HI_OE_SET_OFFSET 0x00000044 -#define SIO_GPIO_HI_OE_SET_BITS 0x0000003f -#define SIO_GPIO_HI_OE_SET_RESET 0x00000000 -#define SIO_GPIO_HI_OE_SET_MSB 5 -#define SIO_GPIO_HI_OE_SET_LSB 0 -#define SIO_GPIO_HI_OE_SET_ACCESS "RW" +#define SIO_GPIO_HI_OE_SET_OFFSET _u(0x00000044) +#define SIO_GPIO_HI_OE_SET_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OE_SET_RESET _u(0x00000000) +#define SIO_GPIO_HI_OE_SET_MSB _u(5) +#define SIO_GPIO_HI_OE_SET_LSB _u(0) +#define SIO_GPIO_HI_OE_SET_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_HI_OE_CLR // Description : QSPI output enable clear // Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= // ~wdata` -#define SIO_GPIO_HI_OE_CLR_OFFSET 0x00000048 -#define SIO_GPIO_HI_OE_CLR_BITS 0x0000003f -#define SIO_GPIO_HI_OE_CLR_RESET 0x00000000 -#define SIO_GPIO_HI_OE_CLR_MSB 5 -#define SIO_GPIO_HI_OE_CLR_LSB 0 -#define SIO_GPIO_HI_OE_CLR_ACCESS "RW" +#define SIO_GPIO_HI_OE_CLR_OFFSET _u(0x00000048) +#define SIO_GPIO_HI_OE_CLR_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OE_CLR_RESET _u(0x00000000) +#define SIO_GPIO_HI_OE_CLR_MSB _u(5) +#define SIO_GPIO_HI_OE_CLR_LSB _u(0) +#define SIO_GPIO_HI_OE_CLR_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_HI_OE_XOR // Description : QSPI output enable XOR // Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE // ^= wdata` -#define SIO_GPIO_HI_OE_XOR_OFFSET 0x0000004c -#define SIO_GPIO_HI_OE_XOR_BITS 0x0000003f -#define SIO_GPIO_HI_OE_XOR_RESET 0x00000000 -#define SIO_GPIO_HI_OE_XOR_MSB 5 -#define SIO_GPIO_HI_OE_XOR_LSB 0 -#define SIO_GPIO_HI_OE_XOR_ACCESS "RW" +#define SIO_GPIO_HI_OE_XOR_OFFSET _u(0x0000004c) +#define SIO_GPIO_HI_OE_XOR_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OE_XOR_RESET _u(0x00000000) +#define SIO_GPIO_HI_OE_XOR_MSB _u(5) +#define SIO_GPIO_HI_OE_XOR_LSB _u(0) +#define SIO_GPIO_HI_OE_XOR_ACCESS "WO" // ============================================================================= // Register : SIO_FIFO_ST // Description : Status register for inter-core FIFOs (mailboxes). @@ -252,73 +252,73 @@ // write side of 1->0 FIFO (TX). // The SIO IRQ for each core is the logical OR of the VLD, WOF and // ROE fields of its FIFO_ST register. -#define SIO_FIFO_ST_OFFSET 0x00000050 -#define SIO_FIFO_ST_BITS 0x0000000f -#define SIO_FIFO_ST_RESET 0x00000002 +#define SIO_FIFO_ST_OFFSET _u(0x00000050) +#define SIO_FIFO_ST_BITS _u(0x0000000f) +#define SIO_FIFO_ST_RESET _u(0x00000002) // ----------------------------------------------------------------------------- // Field : SIO_FIFO_ST_ROE // Description : Sticky flag indicating the RX FIFO was read when empty. This // read was ignored by the FIFO. -#define SIO_FIFO_ST_ROE_RESET 0x0 -#define SIO_FIFO_ST_ROE_BITS 0x00000008 -#define SIO_FIFO_ST_ROE_MSB 3 -#define SIO_FIFO_ST_ROE_LSB 3 +#define SIO_FIFO_ST_ROE_RESET _u(0x0) +#define SIO_FIFO_ST_ROE_BITS _u(0x00000008) +#define SIO_FIFO_ST_ROE_MSB _u(3) +#define SIO_FIFO_ST_ROE_LSB _u(3) #define SIO_FIFO_ST_ROE_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : SIO_FIFO_ST_WOF // Description : Sticky flag indicating the TX FIFO was written when full. This // write was ignored by the FIFO. -#define SIO_FIFO_ST_WOF_RESET 0x0 -#define SIO_FIFO_ST_WOF_BITS 0x00000004 -#define SIO_FIFO_ST_WOF_MSB 2 -#define SIO_FIFO_ST_WOF_LSB 2 +#define SIO_FIFO_ST_WOF_RESET _u(0x0) +#define SIO_FIFO_ST_WOF_BITS _u(0x00000004) +#define SIO_FIFO_ST_WOF_MSB _u(2) +#define SIO_FIFO_ST_WOF_LSB _u(2) #define SIO_FIFO_ST_WOF_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : SIO_FIFO_ST_RDY // Description : Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR // is ready for more data) -#define SIO_FIFO_ST_RDY_RESET 0x1 -#define SIO_FIFO_ST_RDY_BITS 0x00000002 -#define SIO_FIFO_ST_RDY_MSB 1 -#define SIO_FIFO_ST_RDY_LSB 1 +#define SIO_FIFO_ST_RDY_RESET _u(0x1) +#define SIO_FIFO_ST_RDY_BITS _u(0x00000002) +#define SIO_FIFO_ST_RDY_MSB _u(1) +#define SIO_FIFO_ST_RDY_LSB _u(1) #define SIO_FIFO_ST_RDY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SIO_FIFO_ST_VLD // Description : Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD // is valid) -#define SIO_FIFO_ST_VLD_RESET 0x0 -#define SIO_FIFO_ST_VLD_BITS 0x00000001 -#define SIO_FIFO_ST_VLD_MSB 0 -#define SIO_FIFO_ST_VLD_LSB 0 +#define SIO_FIFO_ST_VLD_RESET _u(0x0) +#define SIO_FIFO_ST_VLD_BITS _u(0x00000001) +#define SIO_FIFO_ST_VLD_MSB _u(0) +#define SIO_FIFO_ST_VLD_LSB _u(0) #define SIO_FIFO_ST_VLD_ACCESS "RO" // ============================================================================= // Register : SIO_FIFO_WR // Description : Write access to this core's TX FIFO -#define SIO_FIFO_WR_OFFSET 0x00000054 -#define SIO_FIFO_WR_BITS 0xffffffff -#define SIO_FIFO_WR_RESET 0x00000000 -#define SIO_FIFO_WR_MSB 31 -#define SIO_FIFO_WR_LSB 0 +#define SIO_FIFO_WR_OFFSET _u(0x00000054) +#define SIO_FIFO_WR_BITS _u(0xffffffff) +#define SIO_FIFO_WR_RESET _u(0x00000000) +#define SIO_FIFO_WR_MSB _u(31) +#define SIO_FIFO_WR_LSB _u(0) #define SIO_FIFO_WR_ACCESS "WF" // ============================================================================= // Register : SIO_FIFO_RD // Description : Read access to this core's RX FIFO -#define SIO_FIFO_RD_OFFSET 0x00000058 -#define SIO_FIFO_RD_BITS 0xffffffff +#define SIO_FIFO_RD_OFFSET _u(0x00000058) +#define SIO_FIFO_RD_BITS _u(0xffffffff) #define SIO_FIFO_RD_RESET "-" -#define SIO_FIFO_RD_MSB 31 -#define SIO_FIFO_RD_LSB 0 +#define SIO_FIFO_RD_MSB _u(31) +#define SIO_FIFO_RD_LSB _u(0) #define SIO_FIFO_RD_ACCESS "RF" // ============================================================================= // Register : SIO_SPINLOCK_ST // Description : Spinlock state // A bitmap containing the state of all 32 spinlocks (1=locked). // Mainly intended for debugging. -#define SIO_SPINLOCK_ST_OFFSET 0x0000005c -#define SIO_SPINLOCK_ST_BITS 0xffffffff -#define SIO_SPINLOCK_ST_RESET 0x00000000 -#define SIO_SPINLOCK_ST_MSB 31 -#define SIO_SPINLOCK_ST_LSB 0 +#define SIO_SPINLOCK_ST_OFFSET _u(0x0000005c) +#define SIO_SPINLOCK_ST_BITS _u(0xffffffff) +#define SIO_SPINLOCK_ST_RESET _u(0x00000000) +#define SIO_SPINLOCK_ST_MSB _u(31) +#define SIO_SPINLOCK_ST_LSB _u(0) #define SIO_SPINLOCK_ST_ACCESS "RO" // ============================================================================= // Register : SIO_DIV_UDIVIDEND @@ -331,11 +331,11 @@ // The U alias starts an // unsigned calculation, and the S alias starts a signed // calculation. -#define SIO_DIV_UDIVIDEND_OFFSET 0x00000060 -#define SIO_DIV_UDIVIDEND_BITS 0xffffffff -#define SIO_DIV_UDIVIDEND_RESET 0x00000000 -#define SIO_DIV_UDIVIDEND_MSB 31 -#define SIO_DIV_UDIVIDEND_LSB 0 +#define SIO_DIV_UDIVIDEND_OFFSET _u(0x00000060) +#define SIO_DIV_UDIVIDEND_BITS _u(0xffffffff) +#define SIO_DIV_UDIVIDEND_RESET _u(0x00000000) +#define SIO_DIV_UDIVIDEND_MSB _u(31) +#define SIO_DIV_UDIVIDEND_LSB _u(0) #define SIO_DIV_UDIVIDEND_ACCESS "RW" // ============================================================================= // Register : SIO_DIV_UDIVISOR @@ -348,33 +348,33 @@ // The U alias starts an // unsigned calculation, and the S alias starts a signed // calculation. -#define SIO_DIV_UDIVISOR_OFFSET 0x00000064 -#define SIO_DIV_UDIVISOR_BITS 0xffffffff -#define SIO_DIV_UDIVISOR_RESET 0x00000000 -#define SIO_DIV_UDIVISOR_MSB 31 -#define SIO_DIV_UDIVISOR_LSB 0 +#define SIO_DIV_UDIVISOR_OFFSET _u(0x00000064) +#define SIO_DIV_UDIVISOR_BITS _u(0xffffffff) +#define SIO_DIV_UDIVISOR_RESET _u(0x00000000) +#define SIO_DIV_UDIVISOR_MSB _u(31) +#define SIO_DIV_UDIVISOR_LSB _u(0) #define SIO_DIV_UDIVISOR_ACCESS "RW" // ============================================================================= // Register : SIO_DIV_SDIVIDEND // Description : Divider signed dividend // The same as UDIVIDEND, but starts a signed calculation, rather // than unsigned. -#define SIO_DIV_SDIVIDEND_OFFSET 0x00000068 -#define SIO_DIV_SDIVIDEND_BITS 0xffffffff -#define SIO_DIV_SDIVIDEND_RESET 0x00000000 -#define SIO_DIV_SDIVIDEND_MSB 31 -#define SIO_DIV_SDIVIDEND_LSB 0 +#define SIO_DIV_SDIVIDEND_OFFSET _u(0x00000068) +#define SIO_DIV_SDIVIDEND_BITS _u(0xffffffff) +#define SIO_DIV_SDIVIDEND_RESET _u(0x00000000) +#define SIO_DIV_SDIVIDEND_MSB _u(31) +#define SIO_DIV_SDIVIDEND_LSB _u(0) #define SIO_DIV_SDIVIDEND_ACCESS "RW" // ============================================================================= // Register : SIO_DIV_SDIVISOR // Description : Divider signed divisor // The same as UDIVISOR, but starts a signed calculation, rather // than unsigned. -#define SIO_DIV_SDIVISOR_OFFSET 0x0000006c -#define SIO_DIV_SDIVISOR_BITS 0xffffffff -#define SIO_DIV_SDIVISOR_RESET 0x00000000 -#define SIO_DIV_SDIVISOR_MSB 31 -#define SIO_DIV_SDIVISOR_LSB 0 +#define SIO_DIV_SDIVISOR_OFFSET _u(0x0000006c) +#define SIO_DIV_SDIVISOR_BITS _u(0xffffffff) +#define SIO_DIV_SDIVISOR_RESET _u(0x00000000) +#define SIO_DIV_SDIVISOR_MSB _u(31) +#define SIO_DIV_SDIVISOR_LSB _u(0) #define SIO_DIV_SDIVISOR_ACCESS "RW" // ============================================================================= // Register : SIO_DIV_QUOTIENT @@ -390,11 +390,11 @@ // Reading from QUOTIENT clears the CSR_DIRTY flag, so should read // results in the order // REMAINDER, QUOTIENT if CSR_DIRTY is used. -#define SIO_DIV_QUOTIENT_OFFSET 0x00000070 -#define SIO_DIV_QUOTIENT_BITS 0xffffffff -#define SIO_DIV_QUOTIENT_RESET 0x00000000 -#define SIO_DIV_QUOTIENT_MSB 31 -#define SIO_DIV_QUOTIENT_LSB 0 +#define SIO_DIV_QUOTIENT_OFFSET _u(0x00000070) +#define SIO_DIV_QUOTIENT_BITS _u(0xffffffff) +#define SIO_DIV_QUOTIENT_RESET _u(0x00000000) +#define SIO_DIV_QUOTIENT_MSB _u(31) +#define SIO_DIV_QUOTIENT_LSB _u(0) #define SIO_DIV_QUOTIENT_ACCESS "RW" // ============================================================================= // Register : SIO_DIV_REMAINDER @@ -407,18 +407,18 @@ // save/restore purposes. This halts any // in-progress calculation and sets the CSR_READY and CSR_DIRTY // flags. -#define SIO_DIV_REMAINDER_OFFSET 0x00000074 -#define SIO_DIV_REMAINDER_BITS 0xffffffff -#define SIO_DIV_REMAINDER_RESET 0x00000000 -#define SIO_DIV_REMAINDER_MSB 31 -#define SIO_DIV_REMAINDER_LSB 0 +#define SIO_DIV_REMAINDER_OFFSET _u(0x00000074) +#define SIO_DIV_REMAINDER_BITS _u(0xffffffff) +#define SIO_DIV_REMAINDER_RESET _u(0x00000000) +#define SIO_DIV_REMAINDER_MSB _u(31) +#define SIO_DIV_REMAINDER_LSB _u(0) #define SIO_DIV_REMAINDER_ACCESS "RW" // ============================================================================= // Register : SIO_DIV_CSR // Description : Control and status register for divider. -#define SIO_DIV_CSR_OFFSET 0x00000078 -#define SIO_DIV_CSR_BITS 0x00000003 -#define SIO_DIV_CSR_RESET 0x00000001 +#define SIO_DIV_CSR_OFFSET _u(0x00000078) +#define SIO_DIV_CSR_BITS _u(0x00000003) +#define SIO_DIV_CSR_RESET _u(0x00000001) // ----------------------------------------------------------------------------- // Field : SIO_DIV_CSR_DIRTY // Description : Changes to 1 when any register is written, and back to 0 when @@ -429,10 +429,10 @@ // read QUOTIENT only, // or REMAINDER and then QUOTIENT, to prevent data loss on context // switch. -#define SIO_DIV_CSR_DIRTY_RESET 0x0 -#define SIO_DIV_CSR_DIRTY_BITS 0x00000002 -#define SIO_DIV_CSR_DIRTY_MSB 1 -#define SIO_DIV_CSR_DIRTY_LSB 1 +#define SIO_DIV_CSR_DIRTY_RESET _u(0x0) +#define SIO_DIV_CSR_DIRTY_BITS _u(0x00000002) +#define SIO_DIV_CSR_DIRTY_MSB _u(1) +#define SIO_DIV_CSR_DIRTY_LSB _u(1) #define SIO_DIV_CSR_DIRTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SIO_DIV_CSR_READY @@ -443,142 +443,142 @@ // Writing to a result register will immediately terminate any // in-progress calculation // and set the READY and DIRTY flags. -#define SIO_DIV_CSR_READY_RESET 0x1 -#define SIO_DIV_CSR_READY_BITS 0x00000001 -#define SIO_DIV_CSR_READY_MSB 0 -#define SIO_DIV_CSR_READY_LSB 0 +#define SIO_DIV_CSR_READY_RESET _u(0x1) +#define SIO_DIV_CSR_READY_BITS _u(0x00000001) +#define SIO_DIV_CSR_READY_MSB _u(0) +#define SIO_DIV_CSR_READY_LSB _u(0) #define SIO_DIV_CSR_READY_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP0_ACCUM0 // Description : Read/write access to accumulator 0 -#define SIO_INTERP0_ACCUM0_OFFSET 0x00000080 -#define SIO_INTERP0_ACCUM0_BITS 0xffffffff -#define SIO_INTERP0_ACCUM0_RESET 0x00000000 -#define SIO_INTERP0_ACCUM0_MSB 31 -#define SIO_INTERP0_ACCUM0_LSB 0 +#define SIO_INTERP0_ACCUM0_OFFSET _u(0x00000080) +#define SIO_INTERP0_ACCUM0_BITS _u(0xffffffff) +#define SIO_INTERP0_ACCUM0_RESET _u(0x00000000) +#define SIO_INTERP0_ACCUM0_MSB _u(31) +#define SIO_INTERP0_ACCUM0_LSB _u(0) #define SIO_INTERP0_ACCUM0_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP0_ACCUM1 // Description : Read/write access to accumulator 1 -#define SIO_INTERP0_ACCUM1_OFFSET 0x00000084 -#define SIO_INTERP0_ACCUM1_BITS 0xffffffff -#define SIO_INTERP0_ACCUM1_RESET 0x00000000 -#define SIO_INTERP0_ACCUM1_MSB 31 -#define SIO_INTERP0_ACCUM1_LSB 0 +#define SIO_INTERP0_ACCUM1_OFFSET _u(0x00000084) +#define SIO_INTERP0_ACCUM1_BITS _u(0xffffffff) +#define SIO_INTERP0_ACCUM1_RESET _u(0x00000000) +#define SIO_INTERP0_ACCUM1_MSB _u(31) +#define SIO_INTERP0_ACCUM1_LSB _u(0) #define SIO_INTERP0_ACCUM1_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP0_BASE0 // Description : Read/write access to BASE0 register. -#define SIO_INTERP0_BASE0_OFFSET 0x00000088 -#define SIO_INTERP0_BASE0_BITS 0xffffffff -#define SIO_INTERP0_BASE0_RESET 0x00000000 -#define SIO_INTERP0_BASE0_MSB 31 -#define SIO_INTERP0_BASE0_LSB 0 +#define SIO_INTERP0_BASE0_OFFSET _u(0x00000088) +#define SIO_INTERP0_BASE0_BITS _u(0xffffffff) +#define SIO_INTERP0_BASE0_RESET _u(0x00000000) +#define SIO_INTERP0_BASE0_MSB _u(31) +#define SIO_INTERP0_BASE0_LSB _u(0) #define SIO_INTERP0_BASE0_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP0_BASE1 // Description : Read/write access to BASE1 register. -#define SIO_INTERP0_BASE1_OFFSET 0x0000008c -#define SIO_INTERP0_BASE1_BITS 0xffffffff -#define SIO_INTERP0_BASE1_RESET 0x00000000 -#define SIO_INTERP0_BASE1_MSB 31 -#define SIO_INTERP0_BASE1_LSB 0 +#define SIO_INTERP0_BASE1_OFFSET _u(0x0000008c) +#define SIO_INTERP0_BASE1_BITS _u(0xffffffff) +#define SIO_INTERP0_BASE1_RESET _u(0x00000000) +#define SIO_INTERP0_BASE1_MSB _u(31) +#define SIO_INTERP0_BASE1_LSB _u(0) #define SIO_INTERP0_BASE1_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP0_BASE2 // Description : Read/write access to BASE2 register. -#define SIO_INTERP0_BASE2_OFFSET 0x00000090 -#define SIO_INTERP0_BASE2_BITS 0xffffffff -#define SIO_INTERP0_BASE2_RESET 0x00000000 -#define SIO_INTERP0_BASE2_MSB 31 -#define SIO_INTERP0_BASE2_LSB 0 +#define SIO_INTERP0_BASE2_OFFSET _u(0x00000090) +#define SIO_INTERP0_BASE2_BITS _u(0xffffffff) +#define SIO_INTERP0_BASE2_RESET _u(0x00000000) +#define SIO_INTERP0_BASE2_MSB _u(31) +#define SIO_INTERP0_BASE2_LSB _u(0) #define SIO_INTERP0_BASE2_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP0_POP_LANE0 // Description : Read LANE0 result, and simultaneously write lane results to // both accumulators (POP). -#define SIO_INTERP0_POP_LANE0_OFFSET 0x00000094 -#define SIO_INTERP0_POP_LANE0_BITS 0xffffffff -#define SIO_INTERP0_POP_LANE0_RESET 0x00000000 -#define SIO_INTERP0_POP_LANE0_MSB 31 -#define SIO_INTERP0_POP_LANE0_LSB 0 +#define SIO_INTERP0_POP_LANE0_OFFSET _u(0x00000094) +#define SIO_INTERP0_POP_LANE0_BITS _u(0xffffffff) +#define SIO_INTERP0_POP_LANE0_RESET _u(0x00000000) +#define SIO_INTERP0_POP_LANE0_MSB _u(31) +#define SIO_INTERP0_POP_LANE0_LSB _u(0) #define SIO_INTERP0_POP_LANE0_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP0_POP_LANE1 // Description : Read LANE1 result, and simultaneously write lane results to // both accumulators (POP). -#define SIO_INTERP0_POP_LANE1_OFFSET 0x00000098 -#define SIO_INTERP0_POP_LANE1_BITS 0xffffffff -#define SIO_INTERP0_POP_LANE1_RESET 0x00000000 -#define SIO_INTERP0_POP_LANE1_MSB 31 -#define SIO_INTERP0_POP_LANE1_LSB 0 +#define SIO_INTERP0_POP_LANE1_OFFSET _u(0x00000098) +#define SIO_INTERP0_POP_LANE1_BITS _u(0xffffffff) +#define SIO_INTERP0_POP_LANE1_RESET _u(0x00000000) +#define SIO_INTERP0_POP_LANE1_MSB _u(31) +#define SIO_INTERP0_POP_LANE1_LSB _u(0) #define SIO_INTERP0_POP_LANE1_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP0_POP_FULL // Description : Read FULL result, and simultaneously write lane results to both // accumulators (POP). -#define SIO_INTERP0_POP_FULL_OFFSET 0x0000009c -#define SIO_INTERP0_POP_FULL_BITS 0xffffffff -#define SIO_INTERP0_POP_FULL_RESET 0x00000000 -#define SIO_INTERP0_POP_FULL_MSB 31 -#define SIO_INTERP0_POP_FULL_LSB 0 +#define SIO_INTERP0_POP_FULL_OFFSET _u(0x0000009c) +#define SIO_INTERP0_POP_FULL_BITS _u(0xffffffff) +#define SIO_INTERP0_POP_FULL_RESET _u(0x00000000) +#define SIO_INTERP0_POP_FULL_MSB _u(31) +#define SIO_INTERP0_POP_FULL_LSB _u(0) #define SIO_INTERP0_POP_FULL_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP0_PEEK_LANE0 // Description : Read LANE0 result, without altering any internal state (PEEK). -#define SIO_INTERP0_PEEK_LANE0_OFFSET 0x000000a0 -#define SIO_INTERP0_PEEK_LANE0_BITS 0xffffffff -#define SIO_INTERP0_PEEK_LANE0_RESET 0x00000000 -#define SIO_INTERP0_PEEK_LANE0_MSB 31 -#define SIO_INTERP0_PEEK_LANE0_LSB 0 +#define SIO_INTERP0_PEEK_LANE0_OFFSET _u(0x000000a0) +#define SIO_INTERP0_PEEK_LANE0_BITS _u(0xffffffff) +#define SIO_INTERP0_PEEK_LANE0_RESET _u(0x00000000) +#define SIO_INTERP0_PEEK_LANE0_MSB _u(31) +#define SIO_INTERP0_PEEK_LANE0_LSB _u(0) #define SIO_INTERP0_PEEK_LANE0_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP0_PEEK_LANE1 // Description : Read LANE1 result, without altering any internal state (PEEK). -#define SIO_INTERP0_PEEK_LANE1_OFFSET 0x000000a4 -#define SIO_INTERP0_PEEK_LANE1_BITS 0xffffffff -#define SIO_INTERP0_PEEK_LANE1_RESET 0x00000000 -#define SIO_INTERP0_PEEK_LANE1_MSB 31 -#define SIO_INTERP0_PEEK_LANE1_LSB 0 +#define SIO_INTERP0_PEEK_LANE1_OFFSET _u(0x000000a4) +#define SIO_INTERP0_PEEK_LANE1_BITS _u(0xffffffff) +#define SIO_INTERP0_PEEK_LANE1_RESET _u(0x00000000) +#define SIO_INTERP0_PEEK_LANE1_MSB _u(31) +#define SIO_INTERP0_PEEK_LANE1_LSB _u(0) #define SIO_INTERP0_PEEK_LANE1_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP0_PEEK_FULL // Description : Read FULL result, without altering any internal state (PEEK). -#define SIO_INTERP0_PEEK_FULL_OFFSET 0x000000a8 -#define SIO_INTERP0_PEEK_FULL_BITS 0xffffffff -#define SIO_INTERP0_PEEK_FULL_RESET 0x00000000 -#define SIO_INTERP0_PEEK_FULL_MSB 31 -#define SIO_INTERP0_PEEK_FULL_LSB 0 +#define SIO_INTERP0_PEEK_FULL_OFFSET _u(0x000000a8) +#define SIO_INTERP0_PEEK_FULL_BITS _u(0xffffffff) +#define SIO_INTERP0_PEEK_FULL_RESET _u(0x00000000) +#define SIO_INTERP0_PEEK_FULL_MSB _u(31) +#define SIO_INTERP0_PEEK_FULL_LSB _u(0) #define SIO_INTERP0_PEEK_FULL_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP0_CTRL_LANE0 // Description : Control register for lane 0 -#define SIO_INTERP0_CTRL_LANE0_OFFSET 0x000000ac -#define SIO_INTERP0_CTRL_LANE0_BITS 0x03bfffff -#define SIO_INTERP0_CTRL_LANE0_RESET 0x00000000 +#define SIO_INTERP0_CTRL_LANE0_OFFSET _u(0x000000ac) +#define SIO_INTERP0_CTRL_LANE0_BITS _u(0x03bfffff) +#define SIO_INTERP0_CTRL_LANE0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_OVERF // Description : Set if either OVERF0 or OVERF1 is set. -#define SIO_INTERP0_CTRL_LANE0_OVERF_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE0_OVERF_BITS 0x02000000 -#define SIO_INTERP0_CTRL_LANE0_OVERF_MSB 25 -#define SIO_INTERP0_CTRL_LANE0_OVERF_LSB 25 +#define SIO_INTERP0_CTRL_LANE0_OVERF_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_OVERF_BITS _u(0x02000000) +#define SIO_INTERP0_CTRL_LANE0_OVERF_MSB _u(25) +#define SIO_INTERP0_CTRL_LANE0_OVERF_LSB _u(25) #define SIO_INTERP0_CTRL_LANE0_OVERF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_OVERF1 // Description : Indicates if any masked-off MSBs in ACCUM1 are set. -#define SIO_INTERP0_CTRL_LANE0_OVERF1_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE0_OVERF1_BITS 0x01000000 -#define SIO_INTERP0_CTRL_LANE0_OVERF1_MSB 24 -#define SIO_INTERP0_CTRL_LANE0_OVERF1_LSB 24 +#define SIO_INTERP0_CTRL_LANE0_OVERF1_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_OVERF1_BITS _u(0x01000000) +#define SIO_INTERP0_CTRL_LANE0_OVERF1_MSB _u(24) +#define SIO_INTERP0_CTRL_LANE0_OVERF1_LSB _u(24) #define SIO_INTERP0_CTRL_LANE0_OVERF1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_OVERF0 // Description : Indicates if any masked-off MSBs in ACCUM0 are set. -#define SIO_INTERP0_CTRL_LANE0_OVERF0_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE0_OVERF0_BITS 0x00800000 -#define SIO_INTERP0_CTRL_LANE0_OVERF0_MSB 23 -#define SIO_INTERP0_CTRL_LANE0_OVERF0_LSB 23 +#define SIO_INTERP0_CTRL_LANE0_OVERF0_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_OVERF0_BITS _u(0x00800000) +#define SIO_INTERP0_CTRL_LANE0_OVERF0_MSB _u(23) +#define SIO_INTERP0_CTRL_LANE0_OVERF0_LSB _u(23) #define SIO_INTERP0_CTRL_LANE0_OVERF0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_BLEND @@ -594,10 +594,10 @@ // (BASE2 + lane 0 shift+mask) // LANE1 SIGNED flag controls whether the interpolation is signed // or unsigned. -#define SIO_INTERP0_CTRL_LANE0_BLEND_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE0_BLEND_BITS 0x00200000 -#define SIO_INTERP0_CTRL_LANE0_BLEND_MSB 21 -#define SIO_INTERP0_CTRL_LANE0_BLEND_LSB 21 +#define SIO_INTERP0_CTRL_LANE0_BLEND_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_BLEND_BITS _u(0x00200000) +#define SIO_INTERP0_CTRL_LANE0_BLEND_MSB _u(21) +#define SIO_INTERP0_CTRL_LANE0_BLEND_LSB _u(21) #define SIO_INTERP0_CTRL_LANE0_BLEND_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_FORCE_MSB @@ -606,28 +606,28 @@ // No effect on the internal 32-bit datapath. Handy for using a // lane to generate sequence // of pointers into flash or SRAM. -#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS 0x00180000 -#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MSB 20 -#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB 19 +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS _u(0x00180000) +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MSB _u(20) +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB _u(19) #define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_ADD_RAW // Description : If 1, mask + shift is bypassed for LANE0 result. This does not // affect FULL result. -#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS 0x00040000 -#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_MSB 18 -#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_LSB 18 +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS _u(0x00040000) +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_MSB _u(18) +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_LSB _u(18) #define SIO_INTERP0_CTRL_LANE0_ADD_RAW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_CROSS_RESULT // Description : If 1, feed the opposite lane's result into this lane's // accumulator on POP. -#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS 0x00020000 -#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_MSB 17 -#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_LSB 17 +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS _u(0x00020000) +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_MSB _u(17) +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_LSB _u(17) #define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_CROSS_INPUT @@ -635,10 +635,10 @@ // shift + mask hardware. // Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is // before the shift+mask bypass) -#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS 0x00010000 -#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_MSB 16 -#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_LSB 16 +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS _u(0x00010000) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_MSB _u(16) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_LSB _u(16) #define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_SIGNED @@ -646,44 +646,44 @@ // sign-extended to 32 bits // before adding to BASE0, and LANE0 PEEK/POP appear extended to // 32 bits when read by processor. -#define SIO_INTERP0_CTRL_LANE0_SIGNED_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE0_SIGNED_BITS 0x00008000 -#define SIO_INTERP0_CTRL_LANE0_SIGNED_MSB 15 -#define SIO_INTERP0_CTRL_LANE0_SIGNED_LSB 15 +#define SIO_INTERP0_CTRL_LANE0_SIGNED_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_SIGNED_BITS _u(0x00008000) +#define SIO_INTERP0_CTRL_LANE0_SIGNED_MSB _u(15) +#define SIO_INTERP0_CTRL_LANE0_SIGNED_LSB _u(15) #define SIO_INTERP0_CTRL_LANE0_SIGNED_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_MASK_MSB // Description : The most-significant bit allowed to pass by the mask // (inclusive) // Setting MSB < LSB may cause chip to turn inside-out -#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_RESET 0x00 -#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS 0x00007c00 -#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_MSB 14 -#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB 10 +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS _u(0x00007c00) +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_MSB _u(14) +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB _u(10) #define SIO_INTERP0_CTRL_LANE0_MASK_MSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_MASK_LSB // Description : The least-significant bit allowed to pass by the mask // (inclusive) -#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_RESET 0x00 -#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS 0x000003e0 -#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_MSB 9 -#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB 5 +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS _u(0x000003e0) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_MSB _u(9) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB _u(5) #define SIO_INTERP0_CTRL_LANE0_MASK_LSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE0_SHIFT // Description : Logical right-shift applied to accumulator before masking -#define SIO_INTERP0_CTRL_LANE0_SHIFT_RESET 0x00 -#define SIO_INTERP0_CTRL_LANE0_SHIFT_BITS 0x0000001f -#define SIO_INTERP0_CTRL_LANE0_SHIFT_MSB 4 -#define SIO_INTERP0_CTRL_LANE0_SHIFT_LSB 0 +#define SIO_INTERP0_CTRL_LANE0_SHIFT_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE0_SHIFT_BITS _u(0x0000001f) +#define SIO_INTERP0_CTRL_LANE0_SHIFT_MSB _u(4) +#define SIO_INTERP0_CTRL_LANE0_SHIFT_LSB _u(0) #define SIO_INTERP0_CTRL_LANE0_SHIFT_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP0_CTRL_LANE1 // Description : Control register for lane 1 -#define SIO_INTERP0_CTRL_LANE1_OFFSET 0x000000b0 -#define SIO_INTERP0_CTRL_LANE1_BITS 0x001fffff -#define SIO_INTERP0_CTRL_LANE1_RESET 0x00000000 +#define SIO_INTERP0_CTRL_LANE1_OFFSET _u(0x000000b0) +#define SIO_INTERP0_CTRL_LANE1_BITS _u(0x001fffff) +#define SIO_INTERP0_CTRL_LANE1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE1_FORCE_MSB // Description : ORed into bits 29:28 of the lane result presented to the @@ -691,28 +691,28 @@ // No effect on the internal 32-bit datapath. Handy for using a // lane to generate sequence // of pointers into flash or SRAM. -#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_BITS 0x00180000 -#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MSB 20 -#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_LSB 19 +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_BITS _u(0x00180000) +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MSB _u(20) +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_LSB _u(19) #define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE1_ADD_RAW // Description : If 1, mask + shift is bypassed for LANE1 result. This does not // affect FULL result. -#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_BITS 0x00040000 -#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_MSB 18 -#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_LSB 18 +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_BITS _u(0x00040000) +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_MSB _u(18) +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_LSB _u(18) #define SIO_INTERP0_CTRL_LANE1_ADD_RAW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE1_CROSS_RESULT // Description : If 1, feed the opposite lane's result into this lane's // accumulator on POP. -#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_BITS 0x00020000 -#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_MSB 17 -#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_LSB 17 +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_BITS _u(0x00020000) +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_MSB _u(17) +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_LSB _u(17) #define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE1_CROSS_INPUT @@ -720,10 +720,10 @@ // shift + mask hardware. // Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is // before the shift+mask bypass) -#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_BITS 0x00010000 -#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_MSB 16 -#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_LSB 16 +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_BITS _u(0x00010000) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_MSB _u(16) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_LSB _u(16) #define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE1_SIGNED @@ -731,59 +731,59 @@ // sign-extended to 32 bits // before adding to BASE1, and LANE1 PEEK/POP appear extended to // 32 bits when read by processor. -#define SIO_INTERP0_CTRL_LANE1_SIGNED_RESET 0x0 -#define SIO_INTERP0_CTRL_LANE1_SIGNED_BITS 0x00008000 -#define SIO_INTERP0_CTRL_LANE1_SIGNED_MSB 15 -#define SIO_INTERP0_CTRL_LANE1_SIGNED_LSB 15 +#define SIO_INTERP0_CTRL_LANE1_SIGNED_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_SIGNED_BITS _u(0x00008000) +#define SIO_INTERP0_CTRL_LANE1_SIGNED_MSB _u(15) +#define SIO_INTERP0_CTRL_LANE1_SIGNED_LSB _u(15) #define SIO_INTERP0_CTRL_LANE1_SIGNED_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE1_MASK_MSB // Description : The most-significant bit allowed to pass by the mask // (inclusive) // Setting MSB < LSB may cause chip to turn inside-out -#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_RESET 0x00 -#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_BITS 0x00007c00 -#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_MSB 14 -#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_LSB 10 +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_BITS _u(0x00007c00) +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_MSB _u(14) +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_LSB _u(10) #define SIO_INTERP0_CTRL_LANE1_MASK_MSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE1_MASK_LSB // Description : The least-significant bit allowed to pass by the mask // (inclusive) -#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_RESET 0x00 -#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_BITS 0x000003e0 -#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_MSB 9 -#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_LSB 5 +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_BITS _u(0x000003e0) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_MSB _u(9) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_LSB _u(5) #define SIO_INTERP0_CTRL_LANE1_MASK_LSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP0_CTRL_LANE1_SHIFT // Description : Logical right-shift applied to accumulator before masking -#define SIO_INTERP0_CTRL_LANE1_SHIFT_RESET 0x00 -#define SIO_INTERP0_CTRL_LANE1_SHIFT_BITS 0x0000001f -#define SIO_INTERP0_CTRL_LANE1_SHIFT_MSB 4 -#define SIO_INTERP0_CTRL_LANE1_SHIFT_LSB 0 +#define SIO_INTERP0_CTRL_LANE1_SHIFT_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE1_SHIFT_BITS _u(0x0000001f) +#define SIO_INTERP0_CTRL_LANE1_SHIFT_MSB _u(4) +#define SIO_INTERP0_CTRL_LANE1_SHIFT_LSB _u(0) #define SIO_INTERP0_CTRL_LANE1_SHIFT_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP0_ACCUM0_ADD // Description : Values written here are atomically added to ACCUM0 // Reading yields lane 0's raw shift and mask value (BASE0 not // added). -#define SIO_INTERP0_ACCUM0_ADD_OFFSET 0x000000b4 -#define SIO_INTERP0_ACCUM0_ADD_BITS 0x00ffffff -#define SIO_INTERP0_ACCUM0_ADD_RESET 0x00000000 -#define SIO_INTERP0_ACCUM0_ADD_MSB 23 -#define SIO_INTERP0_ACCUM0_ADD_LSB 0 +#define SIO_INTERP0_ACCUM0_ADD_OFFSET _u(0x000000b4) +#define SIO_INTERP0_ACCUM0_ADD_BITS _u(0x00ffffff) +#define SIO_INTERP0_ACCUM0_ADD_RESET _u(0x00000000) +#define SIO_INTERP0_ACCUM0_ADD_MSB _u(23) +#define SIO_INTERP0_ACCUM0_ADD_LSB _u(0) #define SIO_INTERP0_ACCUM0_ADD_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP0_ACCUM1_ADD // Description : Values written here are atomically added to ACCUM1 // Reading yields lane 1's raw shift and mask value (BASE1 not // added). -#define SIO_INTERP0_ACCUM1_ADD_OFFSET 0x000000b8 -#define SIO_INTERP0_ACCUM1_ADD_BITS 0x00ffffff -#define SIO_INTERP0_ACCUM1_ADD_RESET 0x00000000 -#define SIO_INTERP0_ACCUM1_ADD_MSB 23 -#define SIO_INTERP0_ACCUM1_ADD_LSB 0 +#define SIO_INTERP0_ACCUM1_ADD_OFFSET _u(0x000000b8) +#define SIO_INTERP0_ACCUM1_ADD_BITS _u(0x00ffffff) +#define SIO_INTERP0_ACCUM1_ADD_RESET _u(0x00000000) +#define SIO_INTERP0_ACCUM1_ADD_MSB _u(23) +#define SIO_INTERP0_ACCUM1_ADD_LSB _u(0) #define SIO_INTERP0_ACCUM1_ADD_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP0_BASE_1AND0 @@ -791,143 +791,143 @@ // simultaneously. // Each half is sign-extended to 32 bits if that lane's SIGNED // flag is set. -#define SIO_INTERP0_BASE_1AND0_OFFSET 0x000000bc -#define SIO_INTERP0_BASE_1AND0_BITS 0xffffffff -#define SIO_INTERP0_BASE_1AND0_RESET 0x00000000 -#define SIO_INTERP0_BASE_1AND0_MSB 31 -#define SIO_INTERP0_BASE_1AND0_LSB 0 +#define SIO_INTERP0_BASE_1AND0_OFFSET _u(0x000000bc) +#define SIO_INTERP0_BASE_1AND0_BITS _u(0xffffffff) +#define SIO_INTERP0_BASE_1AND0_RESET _u(0x00000000) +#define SIO_INTERP0_BASE_1AND0_MSB _u(31) +#define SIO_INTERP0_BASE_1AND0_LSB _u(0) #define SIO_INTERP0_BASE_1AND0_ACCESS "WO" // ============================================================================= // Register : SIO_INTERP1_ACCUM0 // Description : Read/write access to accumulator 0 -#define SIO_INTERP1_ACCUM0_OFFSET 0x000000c0 -#define SIO_INTERP1_ACCUM0_BITS 0xffffffff -#define SIO_INTERP1_ACCUM0_RESET 0x00000000 -#define SIO_INTERP1_ACCUM0_MSB 31 -#define SIO_INTERP1_ACCUM0_LSB 0 +#define SIO_INTERP1_ACCUM0_OFFSET _u(0x000000c0) +#define SIO_INTERP1_ACCUM0_BITS _u(0xffffffff) +#define SIO_INTERP1_ACCUM0_RESET _u(0x00000000) +#define SIO_INTERP1_ACCUM0_MSB _u(31) +#define SIO_INTERP1_ACCUM0_LSB _u(0) #define SIO_INTERP1_ACCUM0_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP1_ACCUM1 // Description : Read/write access to accumulator 1 -#define SIO_INTERP1_ACCUM1_OFFSET 0x000000c4 -#define SIO_INTERP1_ACCUM1_BITS 0xffffffff -#define SIO_INTERP1_ACCUM1_RESET 0x00000000 -#define SIO_INTERP1_ACCUM1_MSB 31 -#define SIO_INTERP1_ACCUM1_LSB 0 +#define SIO_INTERP1_ACCUM1_OFFSET _u(0x000000c4) +#define SIO_INTERP1_ACCUM1_BITS _u(0xffffffff) +#define SIO_INTERP1_ACCUM1_RESET _u(0x00000000) +#define SIO_INTERP1_ACCUM1_MSB _u(31) +#define SIO_INTERP1_ACCUM1_LSB _u(0) #define SIO_INTERP1_ACCUM1_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP1_BASE0 // Description : Read/write access to BASE0 register. -#define SIO_INTERP1_BASE0_OFFSET 0x000000c8 -#define SIO_INTERP1_BASE0_BITS 0xffffffff -#define SIO_INTERP1_BASE0_RESET 0x00000000 -#define SIO_INTERP1_BASE0_MSB 31 -#define SIO_INTERP1_BASE0_LSB 0 +#define SIO_INTERP1_BASE0_OFFSET _u(0x000000c8) +#define SIO_INTERP1_BASE0_BITS _u(0xffffffff) +#define SIO_INTERP1_BASE0_RESET _u(0x00000000) +#define SIO_INTERP1_BASE0_MSB _u(31) +#define SIO_INTERP1_BASE0_LSB _u(0) #define SIO_INTERP1_BASE0_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP1_BASE1 // Description : Read/write access to BASE1 register. -#define SIO_INTERP1_BASE1_OFFSET 0x000000cc -#define SIO_INTERP1_BASE1_BITS 0xffffffff -#define SIO_INTERP1_BASE1_RESET 0x00000000 -#define SIO_INTERP1_BASE1_MSB 31 -#define SIO_INTERP1_BASE1_LSB 0 +#define SIO_INTERP1_BASE1_OFFSET _u(0x000000cc) +#define SIO_INTERP1_BASE1_BITS _u(0xffffffff) +#define SIO_INTERP1_BASE1_RESET _u(0x00000000) +#define SIO_INTERP1_BASE1_MSB _u(31) +#define SIO_INTERP1_BASE1_LSB _u(0) #define SIO_INTERP1_BASE1_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP1_BASE2 // Description : Read/write access to BASE2 register. -#define SIO_INTERP1_BASE2_OFFSET 0x000000d0 -#define SIO_INTERP1_BASE2_BITS 0xffffffff -#define SIO_INTERP1_BASE2_RESET 0x00000000 -#define SIO_INTERP1_BASE2_MSB 31 -#define SIO_INTERP1_BASE2_LSB 0 +#define SIO_INTERP1_BASE2_OFFSET _u(0x000000d0) +#define SIO_INTERP1_BASE2_BITS _u(0xffffffff) +#define SIO_INTERP1_BASE2_RESET _u(0x00000000) +#define SIO_INTERP1_BASE2_MSB _u(31) +#define SIO_INTERP1_BASE2_LSB _u(0) #define SIO_INTERP1_BASE2_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP1_POP_LANE0 // Description : Read LANE0 result, and simultaneously write lane results to // both accumulators (POP). -#define SIO_INTERP1_POP_LANE0_OFFSET 0x000000d4 -#define SIO_INTERP1_POP_LANE0_BITS 0xffffffff -#define SIO_INTERP1_POP_LANE0_RESET 0x00000000 -#define SIO_INTERP1_POP_LANE0_MSB 31 -#define SIO_INTERP1_POP_LANE0_LSB 0 +#define SIO_INTERP1_POP_LANE0_OFFSET _u(0x000000d4) +#define SIO_INTERP1_POP_LANE0_BITS _u(0xffffffff) +#define SIO_INTERP1_POP_LANE0_RESET _u(0x00000000) +#define SIO_INTERP1_POP_LANE0_MSB _u(31) +#define SIO_INTERP1_POP_LANE0_LSB _u(0) #define SIO_INTERP1_POP_LANE0_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP1_POP_LANE1 // Description : Read LANE1 result, and simultaneously write lane results to // both accumulators (POP). -#define SIO_INTERP1_POP_LANE1_OFFSET 0x000000d8 -#define SIO_INTERP1_POP_LANE1_BITS 0xffffffff -#define SIO_INTERP1_POP_LANE1_RESET 0x00000000 -#define SIO_INTERP1_POP_LANE1_MSB 31 -#define SIO_INTERP1_POP_LANE1_LSB 0 +#define SIO_INTERP1_POP_LANE1_OFFSET _u(0x000000d8) +#define SIO_INTERP1_POP_LANE1_BITS _u(0xffffffff) +#define SIO_INTERP1_POP_LANE1_RESET _u(0x00000000) +#define SIO_INTERP1_POP_LANE1_MSB _u(31) +#define SIO_INTERP1_POP_LANE1_LSB _u(0) #define SIO_INTERP1_POP_LANE1_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP1_POP_FULL // Description : Read FULL result, and simultaneously write lane results to both // accumulators (POP). -#define SIO_INTERP1_POP_FULL_OFFSET 0x000000dc -#define SIO_INTERP1_POP_FULL_BITS 0xffffffff -#define SIO_INTERP1_POP_FULL_RESET 0x00000000 -#define SIO_INTERP1_POP_FULL_MSB 31 -#define SIO_INTERP1_POP_FULL_LSB 0 +#define SIO_INTERP1_POP_FULL_OFFSET _u(0x000000dc) +#define SIO_INTERP1_POP_FULL_BITS _u(0xffffffff) +#define SIO_INTERP1_POP_FULL_RESET _u(0x00000000) +#define SIO_INTERP1_POP_FULL_MSB _u(31) +#define SIO_INTERP1_POP_FULL_LSB _u(0) #define SIO_INTERP1_POP_FULL_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP1_PEEK_LANE0 // Description : Read LANE0 result, without altering any internal state (PEEK). -#define SIO_INTERP1_PEEK_LANE0_OFFSET 0x000000e0 -#define SIO_INTERP1_PEEK_LANE0_BITS 0xffffffff -#define SIO_INTERP1_PEEK_LANE0_RESET 0x00000000 -#define SIO_INTERP1_PEEK_LANE0_MSB 31 -#define SIO_INTERP1_PEEK_LANE0_LSB 0 +#define SIO_INTERP1_PEEK_LANE0_OFFSET _u(0x000000e0) +#define SIO_INTERP1_PEEK_LANE0_BITS _u(0xffffffff) +#define SIO_INTERP1_PEEK_LANE0_RESET _u(0x00000000) +#define SIO_INTERP1_PEEK_LANE0_MSB _u(31) +#define SIO_INTERP1_PEEK_LANE0_LSB _u(0) #define SIO_INTERP1_PEEK_LANE0_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP1_PEEK_LANE1 // Description : Read LANE1 result, without altering any internal state (PEEK). -#define SIO_INTERP1_PEEK_LANE1_OFFSET 0x000000e4 -#define SIO_INTERP1_PEEK_LANE1_BITS 0xffffffff -#define SIO_INTERP1_PEEK_LANE1_RESET 0x00000000 -#define SIO_INTERP1_PEEK_LANE1_MSB 31 -#define SIO_INTERP1_PEEK_LANE1_LSB 0 +#define SIO_INTERP1_PEEK_LANE1_OFFSET _u(0x000000e4) +#define SIO_INTERP1_PEEK_LANE1_BITS _u(0xffffffff) +#define SIO_INTERP1_PEEK_LANE1_RESET _u(0x00000000) +#define SIO_INTERP1_PEEK_LANE1_MSB _u(31) +#define SIO_INTERP1_PEEK_LANE1_LSB _u(0) #define SIO_INTERP1_PEEK_LANE1_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP1_PEEK_FULL // Description : Read FULL result, without altering any internal state (PEEK). -#define SIO_INTERP1_PEEK_FULL_OFFSET 0x000000e8 -#define SIO_INTERP1_PEEK_FULL_BITS 0xffffffff -#define SIO_INTERP1_PEEK_FULL_RESET 0x00000000 -#define SIO_INTERP1_PEEK_FULL_MSB 31 -#define SIO_INTERP1_PEEK_FULL_LSB 0 +#define SIO_INTERP1_PEEK_FULL_OFFSET _u(0x000000e8) +#define SIO_INTERP1_PEEK_FULL_BITS _u(0xffffffff) +#define SIO_INTERP1_PEEK_FULL_RESET _u(0x00000000) +#define SIO_INTERP1_PEEK_FULL_MSB _u(31) +#define SIO_INTERP1_PEEK_FULL_LSB _u(0) #define SIO_INTERP1_PEEK_FULL_ACCESS "RO" // ============================================================================= // Register : SIO_INTERP1_CTRL_LANE0 // Description : Control register for lane 0 -#define SIO_INTERP1_CTRL_LANE0_OFFSET 0x000000ec -#define SIO_INTERP1_CTRL_LANE0_BITS 0x03dfffff -#define SIO_INTERP1_CTRL_LANE0_RESET 0x00000000 +#define SIO_INTERP1_CTRL_LANE0_OFFSET _u(0x000000ec) +#define SIO_INTERP1_CTRL_LANE0_BITS _u(0x03dfffff) +#define SIO_INTERP1_CTRL_LANE0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_OVERF // Description : Set if either OVERF0 or OVERF1 is set. -#define SIO_INTERP1_CTRL_LANE0_OVERF_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE0_OVERF_BITS 0x02000000 -#define SIO_INTERP1_CTRL_LANE0_OVERF_MSB 25 -#define SIO_INTERP1_CTRL_LANE0_OVERF_LSB 25 +#define SIO_INTERP1_CTRL_LANE0_OVERF_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_OVERF_BITS _u(0x02000000) +#define SIO_INTERP1_CTRL_LANE0_OVERF_MSB _u(25) +#define SIO_INTERP1_CTRL_LANE0_OVERF_LSB _u(25) #define SIO_INTERP1_CTRL_LANE0_OVERF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_OVERF1 // Description : Indicates if any masked-off MSBs in ACCUM1 are set. -#define SIO_INTERP1_CTRL_LANE0_OVERF1_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE0_OVERF1_BITS 0x01000000 -#define SIO_INTERP1_CTRL_LANE0_OVERF1_MSB 24 -#define SIO_INTERP1_CTRL_LANE0_OVERF1_LSB 24 +#define SIO_INTERP1_CTRL_LANE0_OVERF1_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_OVERF1_BITS _u(0x01000000) +#define SIO_INTERP1_CTRL_LANE0_OVERF1_MSB _u(24) +#define SIO_INTERP1_CTRL_LANE0_OVERF1_LSB _u(24) #define SIO_INTERP1_CTRL_LANE0_OVERF1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_OVERF0 // Description : Indicates if any masked-off MSBs in ACCUM0 are set. -#define SIO_INTERP1_CTRL_LANE0_OVERF0_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE0_OVERF0_BITS 0x00800000 -#define SIO_INTERP1_CTRL_LANE0_OVERF0_MSB 23 -#define SIO_INTERP1_CTRL_LANE0_OVERF0_LSB 23 +#define SIO_INTERP1_CTRL_LANE0_OVERF0_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_OVERF0_BITS _u(0x00800000) +#define SIO_INTERP1_CTRL_LANE0_OVERF0_MSB _u(23) +#define SIO_INTERP1_CTRL_LANE0_OVERF0_LSB _u(23) #define SIO_INTERP1_CTRL_LANE0_OVERF0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_CLAMP @@ -937,10 +937,10 @@ // BASE0 and an upper bound of BASE1. // - Signedness of these comparisons is determined by // LANE0_CTRL_SIGNED -#define SIO_INTERP1_CTRL_LANE0_CLAMP_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE0_CLAMP_BITS 0x00400000 -#define SIO_INTERP1_CTRL_LANE0_CLAMP_MSB 22 -#define SIO_INTERP1_CTRL_LANE0_CLAMP_LSB 22 +#define SIO_INTERP1_CTRL_LANE0_CLAMP_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_CLAMP_BITS _u(0x00400000) +#define SIO_INTERP1_CTRL_LANE0_CLAMP_MSB _u(22) +#define SIO_INTERP1_CTRL_LANE0_CLAMP_LSB _u(22) #define SIO_INTERP1_CTRL_LANE0_CLAMP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_FORCE_MSB @@ -949,28 +949,28 @@ // No effect on the internal 32-bit datapath. Handy for using a // lane to generate sequence // of pointers into flash or SRAM. -#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_BITS 0x00180000 -#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MSB 20 -#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_LSB 19 +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_BITS _u(0x00180000) +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MSB _u(20) +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_LSB _u(19) #define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_ADD_RAW // Description : If 1, mask + shift is bypassed for LANE0 result. This does not // affect FULL result. -#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_BITS 0x00040000 -#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_MSB 18 -#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_LSB 18 +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_BITS _u(0x00040000) +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_MSB _u(18) +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_LSB _u(18) #define SIO_INTERP1_CTRL_LANE0_ADD_RAW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_CROSS_RESULT // Description : If 1, feed the opposite lane's result into this lane's // accumulator on POP. -#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_BITS 0x00020000 -#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_MSB 17 -#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_LSB 17 +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_BITS _u(0x00020000) +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_MSB _u(17) +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_LSB _u(17) #define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_CROSS_INPUT @@ -978,10 +978,10 @@ // shift + mask hardware. // Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is // before the shift+mask bypass) -#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_BITS 0x00010000 -#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_MSB 16 -#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_LSB 16 +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_BITS _u(0x00010000) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_MSB _u(16) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_LSB _u(16) #define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_SIGNED @@ -989,44 +989,44 @@ // sign-extended to 32 bits // before adding to BASE0, and LANE0 PEEK/POP appear extended to // 32 bits when read by processor. -#define SIO_INTERP1_CTRL_LANE0_SIGNED_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE0_SIGNED_BITS 0x00008000 -#define SIO_INTERP1_CTRL_LANE0_SIGNED_MSB 15 -#define SIO_INTERP1_CTRL_LANE0_SIGNED_LSB 15 +#define SIO_INTERP1_CTRL_LANE0_SIGNED_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_SIGNED_BITS _u(0x00008000) +#define SIO_INTERP1_CTRL_LANE0_SIGNED_MSB _u(15) +#define SIO_INTERP1_CTRL_LANE0_SIGNED_LSB _u(15) #define SIO_INTERP1_CTRL_LANE0_SIGNED_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_MASK_MSB // Description : The most-significant bit allowed to pass by the mask // (inclusive) // Setting MSB < LSB may cause chip to turn inside-out -#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_RESET 0x00 -#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_BITS 0x00007c00 -#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_MSB 14 -#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_LSB 10 +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_BITS _u(0x00007c00) +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_MSB _u(14) +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_LSB _u(10) #define SIO_INTERP1_CTRL_LANE0_MASK_MSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_MASK_LSB // Description : The least-significant bit allowed to pass by the mask // (inclusive) -#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_RESET 0x00 -#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_BITS 0x000003e0 -#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_MSB 9 -#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_LSB 5 +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_BITS _u(0x000003e0) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_MSB _u(9) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_LSB _u(5) #define SIO_INTERP1_CTRL_LANE0_MASK_LSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE0_SHIFT // Description : Logical right-shift applied to accumulator before masking -#define SIO_INTERP1_CTRL_LANE0_SHIFT_RESET 0x00 -#define SIO_INTERP1_CTRL_LANE0_SHIFT_BITS 0x0000001f -#define SIO_INTERP1_CTRL_LANE0_SHIFT_MSB 4 -#define SIO_INTERP1_CTRL_LANE0_SHIFT_LSB 0 +#define SIO_INTERP1_CTRL_LANE0_SHIFT_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE0_SHIFT_BITS _u(0x0000001f) +#define SIO_INTERP1_CTRL_LANE0_SHIFT_MSB _u(4) +#define SIO_INTERP1_CTRL_LANE0_SHIFT_LSB _u(0) #define SIO_INTERP1_CTRL_LANE0_SHIFT_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP1_CTRL_LANE1 // Description : Control register for lane 1 -#define SIO_INTERP1_CTRL_LANE1_OFFSET 0x000000f0 -#define SIO_INTERP1_CTRL_LANE1_BITS 0x001fffff -#define SIO_INTERP1_CTRL_LANE1_RESET 0x00000000 +#define SIO_INTERP1_CTRL_LANE1_OFFSET _u(0x000000f0) +#define SIO_INTERP1_CTRL_LANE1_BITS _u(0x001fffff) +#define SIO_INTERP1_CTRL_LANE1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE1_FORCE_MSB // Description : ORed into bits 29:28 of the lane result presented to the @@ -1034,28 +1034,28 @@ // No effect on the internal 32-bit datapath. Handy for using a // lane to generate sequence // of pointers into flash or SRAM. -#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_BITS 0x00180000 -#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MSB 20 -#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_LSB 19 +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_BITS _u(0x00180000) +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MSB _u(20) +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_LSB _u(19) #define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE1_ADD_RAW // Description : If 1, mask + shift is bypassed for LANE1 result. This does not // affect FULL result. -#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_BITS 0x00040000 -#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_MSB 18 -#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_LSB 18 +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_BITS _u(0x00040000) +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_MSB _u(18) +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_LSB _u(18) #define SIO_INTERP1_CTRL_LANE1_ADD_RAW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE1_CROSS_RESULT // Description : If 1, feed the opposite lane's result into this lane's // accumulator on POP. -#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_BITS 0x00020000 -#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_MSB 17 -#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_LSB 17 +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_BITS _u(0x00020000) +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_MSB _u(17) +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_LSB _u(17) #define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE1_CROSS_INPUT @@ -1063,10 +1063,10 @@ // shift + mask hardware. // Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is // before the shift+mask bypass) -#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_BITS 0x00010000 -#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_MSB 16 -#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_LSB 16 +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_BITS _u(0x00010000) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_MSB _u(16) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_LSB _u(16) #define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE1_SIGNED @@ -1074,59 +1074,59 @@ // sign-extended to 32 bits // before adding to BASE1, and LANE1 PEEK/POP appear extended to // 32 bits when read by processor. -#define SIO_INTERP1_CTRL_LANE1_SIGNED_RESET 0x0 -#define SIO_INTERP1_CTRL_LANE1_SIGNED_BITS 0x00008000 -#define SIO_INTERP1_CTRL_LANE1_SIGNED_MSB 15 -#define SIO_INTERP1_CTRL_LANE1_SIGNED_LSB 15 +#define SIO_INTERP1_CTRL_LANE1_SIGNED_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_SIGNED_BITS _u(0x00008000) +#define SIO_INTERP1_CTRL_LANE1_SIGNED_MSB _u(15) +#define SIO_INTERP1_CTRL_LANE1_SIGNED_LSB _u(15) #define SIO_INTERP1_CTRL_LANE1_SIGNED_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE1_MASK_MSB // Description : The most-significant bit allowed to pass by the mask // (inclusive) // Setting MSB < LSB may cause chip to turn inside-out -#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_RESET 0x00 -#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_BITS 0x00007c00 -#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_MSB 14 -#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_LSB 10 +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_BITS _u(0x00007c00) +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_MSB _u(14) +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_LSB _u(10) #define SIO_INTERP1_CTRL_LANE1_MASK_MSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE1_MASK_LSB // Description : The least-significant bit allowed to pass by the mask // (inclusive) -#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_RESET 0x00 -#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_BITS 0x000003e0 -#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_MSB 9 -#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_LSB 5 +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_BITS _u(0x000003e0) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_MSB _u(9) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_LSB _u(5) #define SIO_INTERP1_CTRL_LANE1_MASK_LSB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SIO_INTERP1_CTRL_LANE1_SHIFT // Description : Logical right-shift applied to accumulator before masking -#define SIO_INTERP1_CTRL_LANE1_SHIFT_RESET 0x00 -#define SIO_INTERP1_CTRL_LANE1_SHIFT_BITS 0x0000001f -#define SIO_INTERP1_CTRL_LANE1_SHIFT_MSB 4 -#define SIO_INTERP1_CTRL_LANE1_SHIFT_LSB 0 +#define SIO_INTERP1_CTRL_LANE1_SHIFT_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE1_SHIFT_BITS _u(0x0000001f) +#define SIO_INTERP1_CTRL_LANE1_SHIFT_MSB _u(4) +#define SIO_INTERP1_CTRL_LANE1_SHIFT_LSB _u(0) #define SIO_INTERP1_CTRL_LANE1_SHIFT_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP1_ACCUM0_ADD // Description : Values written here are atomically added to ACCUM0 // Reading yields lane 0's raw shift and mask value (BASE0 not // added). -#define SIO_INTERP1_ACCUM0_ADD_OFFSET 0x000000f4 -#define SIO_INTERP1_ACCUM0_ADD_BITS 0x00ffffff -#define SIO_INTERP1_ACCUM0_ADD_RESET 0x00000000 -#define SIO_INTERP1_ACCUM0_ADD_MSB 23 -#define SIO_INTERP1_ACCUM0_ADD_LSB 0 +#define SIO_INTERP1_ACCUM0_ADD_OFFSET _u(0x000000f4) +#define SIO_INTERP1_ACCUM0_ADD_BITS _u(0x00ffffff) +#define SIO_INTERP1_ACCUM0_ADD_RESET _u(0x00000000) +#define SIO_INTERP1_ACCUM0_ADD_MSB _u(23) +#define SIO_INTERP1_ACCUM0_ADD_LSB _u(0) #define SIO_INTERP1_ACCUM0_ADD_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP1_ACCUM1_ADD // Description : Values written here are atomically added to ACCUM1 // Reading yields lane 1's raw shift and mask value (BASE1 not // added). -#define SIO_INTERP1_ACCUM1_ADD_OFFSET 0x000000f8 -#define SIO_INTERP1_ACCUM1_ADD_BITS 0x00ffffff -#define SIO_INTERP1_ACCUM1_ADD_RESET 0x00000000 -#define SIO_INTERP1_ACCUM1_ADD_MSB 23 -#define SIO_INTERP1_ACCUM1_ADD_LSB 0 +#define SIO_INTERP1_ACCUM1_ADD_OFFSET _u(0x000000f8) +#define SIO_INTERP1_ACCUM1_ADD_BITS _u(0x00ffffff) +#define SIO_INTERP1_ACCUM1_ADD_RESET _u(0x00000000) +#define SIO_INTERP1_ACCUM1_ADD_MSB _u(23) +#define SIO_INTERP1_ACCUM1_ADD_LSB _u(0) #define SIO_INTERP1_ACCUM1_ADD_ACCESS "RW" // ============================================================================= // Register : SIO_INTERP1_BASE_1AND0 @@ -1134,11 +1134,11 @@ // simultaneously. // Each half is sign-extended to 32 bits if that lane's SIGNED // flag is set. -#define SIO_INTERP1_BASE_1AND0_OFFSET 0x000000fc -#define SIO_INTERP1_BASE_1AND0_BITS 0xffffffff -#define SIO_INTERP1_BASE_1AND0_RESET 0x00000000 -#define SIO_INTERP1_BASE_1AND0_MSB 31 -#define SIO_INTERP1_BASE_1AND0_LSB 0 +#define SIO_INTERP1_BASE_1AND0_OFFSET _u(0x000000fc) +#define SIO_INTERP1_BASE_1AND0_BITS _u(0xffffffff) +#define SIO_INTERP1_BASE_1AND0_RESET _u(0x00000000) +#define SIO_INTERP1_BASE_1AND0_MSB _u(31) +#define SIO_INTERP1_BASE_1AND0_LSB _u(0) #define SIO_INTERP1_BASE_1AND0_ACCESS "WO" // ============================================================================= // Register : SIO_SPINLOCK0 @@ -1150,12 +1150,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK0_OFFSET 0x00000100 -#define SIO_SPINLOCK0_BITS 0xffffffff -#define SIO_SPINLOCK0_RESET 0x00000000 -#define SIO_SPINLOCK0_MSB 31 -#define SIO_SPINLOCK0_LSB 0 -#define SIO_SPINLOCK0_ACCESS "RO" +#define SIO_SPINLOCK0_OFFSET _u(0x00000100) +#define SIO_SPINLOCK0_BITS _u(0xffffffff) +#define SIO_SPINLOCK0_RESET _u(0x00000000) +#define SIO_SPINLOCK0_MSB _u(31) +#define SIO_SPINLOCK0_LSB _u(0) +#define SIO_SPINLOCK0_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK1 // Description : Reading from a spinlock address will: @@ -1166,12 +1166,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK1_OFFSET 0x00000104 -#define SIO_SPINLOCK1_BITS 0xffffffff -#define SIO_SPINLOCK1_RESET 0x00000000 -#define SIO_SPINLOCK1_MSB 31 -#define SIO_SPINLOCK1_LSB 0 -#define SIO_SPINLOCK1_ACCESS "RO" +#define SIO_SPINLOCK1_OFFSET _u(0x00000104) +#define SIO_SPINLOCK1_BITS _u(0xffffffff) +#define SIO_SPINLOCK1_RESET _u(0x00000000) +#define SIO_SPINLOCK1_MSB _u(31) +#define SIO_SPINLOCK1_LSB _u(0) +#define SIO_SPINLOCK1_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK2 // Description : Reading from a spinlock address will: @@ -1182,12 +1182,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK2_OFFSET 0x00000108 -#define SIO_SPINLOCK2_BITS 0xffffffff -#define SIO_SPINLOCK2_RESET 0x00000000 -#define SIO_SPINLOCK2_MSB 31 -#define SIO_SPINLOCK2_LSB 0 -#define SIO_SPINLOCK2_ACCESS "RO" +#define SIO_SPINLOCK2_OFFSET _u(0x00000108) +#define SIO_SPINLOCK2_BITS _u(0xffffffff) +#define SIO_SPINLOCK2_RESET _u(0x00000000) +#define SIO_SPINLOCK2_MSB _u(31) +#define SIO_SPINLOCK2_LSB _u(0) +#define SIO_SPINLOCK2_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK3 // Description : Reading from a spinlock address will: @@ -1198,12 +1198,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK3_OFFSET 0x0000010c -#define SIO_SPINLOCK3_BITS 0xffffffff -#define SIO_SPINLOCK3_RESET 0x00000000 -#define SIO_SPINLOCK3_MSB 31 -#define SIO_SPINLOCK3_LSB 0 -#define SIO_SPINLOCK3_ACCESS "RO" +#define SIO_SPINLOCK3_OFFSET _u(0x0000010c) +#define SIO_SPINLOCK3_BITS _u(0xffffffff) +#define SIO_SPINLOCK3_RESET _u(0x00000000) +#define SIO_SPINLOCK3_MSB _u(31) +#define SIO_SPINLOCK3_LSB _u(0) +#define SIO_SPINLOCK3_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK4 // Description : Reading from a spinlock address will: @@ -1214,12 +1214,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK4_OFFSET 0x00000110 -#define SIO_SPINLOCK4_BITS 0xffffffff -#define SIO_SPINLOCK4_RESET 0x00000000 -#define SIO_SPINLOCK4_MSB 31 -#define SIO_SPINLOCK4_LSB 0 -#define SIO_SPINLOCK4_ACCESS "RO" +#define SIO_SPINLOCK4_OFFSET _u(0x00000110) +#define SIO_SPINLOCK4_BITS _u(0xffffffff) +#define SIO_SPINLOCK4_RESET _u(0x00000000) +#define SIO_SPINLOCK4_MSB _u(31) +#define SIO_SPINLOCK4_LSB _u(0) +#define SIO_SPINLOCK4_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK5 // Description : Reading from a spinlock address will: @@ -1230,12 +1230,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK5_OFFSET 0x00000114 -#define SIO_SPINLOCK5_BITS 0xffffffff -#define SIO_SPINLOCK5_RESET 0x00000000 -#define SIO_SPINLOCK5_MSB 31 -#define SIO_SPINLOCK5_LSB 0 -#define SIO_SPINLOCK5_ACCESS "RO" +#define SIO_SPINLOCK5_OFFSET _u(0x00000114) +#define SIO_SPINLOCK5_BITS _u(0xffffffff) +#define SIO_SPINLOCK5_RESET _u(0x00000000) +#define SIO_SPINLOCK5_MSB _u(31) +#define SIO_SPINLOCK5_LSB _u(0) +#define SIO_SPINLOCK5_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK6 // Description : Reading from a spinlock address will: @@ -1246,12 +1246,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK6_OFFSET 0x00000118 -#define SIO_SPINLOCK6_BITS 0xffffffff -#define SIO_SPINLOCK6_RESET 0x00000000 -#define SIO_SPINLOCK6_MSB 31 -#define SIO_SPINLOCK6_LSB 0 -#define SIO_SPINLOCK6_ACCESS "RO" +#define SIO_SPINLOCK6_OFFSET _u(0x00000118) +#define SIO_SPINLOCK6_BITS _u(0xffffffff) +#define SIO_SPINLOCK6_RESET _u(0x00000000) +#define SIO_SPINLOCK6_MSB _u(31) +#define SIO_SPINLOCK6_LSB _u(0) +#define SIO_SPINLOCK6_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK7 // Description : Reading from a spinlock address will: @@ -1262,12 +1262,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK7_OFFSET 0x0000011c -#define SIO_SPINLOCK7_BITS 0xffffffff -#define SIO_SPINLOCK7_RESET 0x00000000 -#define SIO_SPINLOCK7_MSB 31 -#define SIO_SPINLOCK7_LSB 0 -#define SIO_SPINLOCK7_ACCESS "RO" +#define SIO_SPINLOCK7_OFFSET _u(0x0000011c) +#define SIO_SPINLOCK7_BITS _u(0xffffffff) +#define SIO_SPINLOCK7_RESET _u(0x00000000) +#define SIO_SPINLOCK7_MSB _u(31) +#define SIO_SPINLOCK7_LSB _u(0) +#define SIO_SPINLOCK7_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK8 // Description : Reading from a spinlock address will: @@ -1278,12 +1278,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK8_OFFSET 0x00000120 -#define SIO_SPINLOCK8_BITS 0xffffffff -#define SIO_SPINLOCK8_RESET 0x00000000 -#define SIO_SPINLOCK8_MSB 31 -#define SIO_SPINLOCK8_LSB 0 -#define SIO_SPINLOCK8_ACCESS "RO" +#define SIO_SPINLOCK8_OFFSET _u(0x00000120) +#define SIO_SPINLOCK8_BITS _u(0xffffffff) +#define SIO_SPINLOCK8_RESET _u(0x00000000) +#define SIO_SPINLOCK8_MSB _u(31) +#define SIO_SPINLOCK8_LSB _u(0) +#define SIO_SPINLOCK8_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK9 // Description : Reading from a spinlock address will: @@ -1294,12 +1294,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK9_OFFSET 0x00000124 -#define SIO_SPINLOCK9_BITS 0xffffffff -#define SIO_SPINLOCK9_RESET 0x00000000 -#define SIO_SPINLOCK9_MSB 31 -#define SIO_SPINLOCK9_LSB 0 -#define SIO_SPINLOCK9_ACCESS "RO" +#define SIO_SPINLOCK9_OFFSET _u(0x00000124) +#define SIO_SPINLOCK9_BITS _u(0xffffffff) +#define SIO_SPINLOCK9_RESET _u(0x00000000) +#define SIO_SPINLOCK9_MSB _u(31) +#define SIO_SPINLOCK9_LSB _u(0) +#define SIO_SPINLOCK9_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK10 // Description : Reading from a spinlock address will: @@ -1310,12 +1310,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK10_OFFSET 0x00000128 -#define SIO_SPINLOCK10_BITS 0xffffffff -#define SIO_SPINLOCK10_RESET 0x00000000 -#define SIO_SPINLOCK10_MSB 31 -#define SIO_SPINLOCK10_LSB 0 -#define SIO_SPINLOCK10_ACCESS "RO" +#define SIO_SPINLOCK10_OFFSET _u(0x00000128) +#define SIO_SPINLOCK10_BITS _u(0xffffffff) +#define SIO_SPINLOCK10_RESET _u(0x00000000) +#define SIO_SPINLOCK10_MSB _u(31) +#define SIO_SPINLOCK10_LSB _u(0) +#define SIO_SPINLOCK10_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK11 // Description : Reading from a spinlock address will: @@ -1326,12 +1326,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK11_OFFSET 0x0000012c -#define SIO_SPINLOCK11_BITS 0xffffffff -#define SIO_SPINLOCK11_RESET 0x00000000 -#define SIO_SPINLOCK11_MSB 31 -#define SIO_SPINLOCK11_LSB 0 -#define SIO_SPINLOCK11_ACCESS "RO" +#define SIO_SPINLOCK11_OFFSET _u(0x0000012c) +#define SIO_SPINLOCK11_BITS _u(0xffffffff) +#define SIO_SPINLOCK11_RESET _u(0x00000000) +#define SIO_SPINLOCK11_MSB _u(31) +#define SIO_SPINLOCK11_LSB _u(0) +#define SIO_SPINLOCK11_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK12 // Description : Reading from a spinlock address will: @@ -1342,12 +1342,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK12_OFFSET 0x00000130 -#define SIO_SPINLOCK12_BITS 0xffffffff -#define SIO_SPINLOCK12_RESET 0x00000000 -#define SIO_SPINLOCK12_MSB 31 -#define SIO_SPINLOCK12_LSB 0 -#define SIO_SPINLOCK12_ACCESS "RO" +#define SIO_SPINLOCK12_OFFSET _u(0x00000130) +#define SIO_SPINLOCK12_BITS _u(0xffffffff) +#define SIO_SPINLOCK12_RESET _u(0x00000000) +#define SIO_SPINLOCK12_MSB _u(31) +#define SIO_SPINLOCK12_LSB _u(0) +#define SIO_SPINLOCK12_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK13 // Description : Reading from a spinlock address will: @@ -1358,12 +1358,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK13_OFFSET 0x00000134 -#define SIO_SPINLOCK13_BITS 0xffffffff -#define SIO_SPINLOCK13_RESET 0x00000000 -#define SIO_SPINLOCK13_MSB 31 -#define SIO_SPINLOCK13_LSB 0 -#define SIO_SPINLOCK13_ACCESS "RO" +#define SIO_SPINLOCK13_OFFSET _u(0x00000134) +#define SIO_SPINLOCK13_BITS _u(0xffffffff) +#define SIO_SPINLOCK13_RESET _u(0x00000000) +#define SIO_SPINLOCK13_MSB _u(31) +#define SIO_SPINLOCK13_LSB _u(0) +#define SIO_SPINLOCK13_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK14 // Description : Reading from a spinlock address will: @@ -1374,12 +1374,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK14_OFFSET 0x00000138 -#define SIO_SPINLOCK14_BITS 0xffffffff -#define SIO_SPINLOCK14_RESET 0x00000000 -#define SIO_SPINLOCK14_MSB 31 -#define SIO_SPINLOCK14_LSB 0 -#define SIO_SPINLOCK14_ACCESS "RO" +#define SIO_SPINLOCK14_OFFSET _u(0x00000138) +#define SIO_SPINLOCK14_BITS _u(0xffffffff) +#define SIO_SPINLOCK14_RESET _u(0x00000000) +#define SIO_SPINLOCK14_MSB _u(31) +#define SIO_SPINLOCK14_LSB _u(0) +#define SIO_SPINLOCK14_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK15 // Description : Reading from a spinlock address will: @@ -1390,12 +1390,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK15_OFFSET 0x0000013c -#define SIO_SPINLOCK15_BITS 0xffffffff -#define SIO_SPINLOCK15_RESET 0x00000000 -#define SIO_SPINLOCK15_MSB 31 -#define SIO_SPINLOCK15_LSB 0 -#define SIO_SPINLOCK15_ACCESS "RO" +#define SIO_SPINLOCK15_OFFSET _u(0x0000013c) +#define SIO_SPINLOCK15_BITS _u(0xffffffff) +#define SIO_SPINLOCK15_RESET _u(0x00000000) +#define SIO_SPINLOCK15_MSB _u(31) +#define SIO_SPINLOCK15_LSB _u(0) +#define SIO_SPINLOCK15_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK16 // Description : Reading from a spinlock address will: @@ -1406,12 +1406,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK16_OFFSET 0x00000140 -#define SIO_SPINLOCK16_BITS 0xffffffff -#define SIO_SPINLOCK16_RESET 0x00000000 -#define SIO_SPINLOCK16_MSB 31 -#define SIO_SPINLOCK16_LSB 0 -#define SIO_SPINLOCK16_ACCESS "RO" +#define SIO_SPINLOCK16_OFFSET _u(0x00000140) +#define SIO_SPINLOCK16_BITS _u(0xffffffff) +#define SIO_SPINLOCK16_RESET _u(0x00000000) +#define SIO_SPINLOCK16_MSB _u(31) +#define SIO_SPINLOCK16_LSB _u(0) +#define SIO_SPINLOCK16_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK17 // Description : Reading from a spinlock address will: @@ -1422,12 +1422,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK17_OFFSET 0x00000144 -#define SIO_SPINLOCK17_BITS 0xffffffff -#define SIO_SPINLOCK17_RESET 0x00000000 -#define SIO_SPINLOCK17_MSB 31 -#define SIO_SPINLOCK17_LSB 0 -#define SIO_SPINLOCK17_ACCESS "RO" +#define SIO_SPINLOCK17_OFFSET _u(0x00000144) +#define SIO_SPINLOCK17_BITS _u(0xffffffff) +#define SIO_SPINLOCK17_RESET _u(0x00000000) +#define SIO_SPINLOCK17_MSB _u(31) +#define SIO_SPINLOCK17_LSB _u(0) +#define SIO_SPINLOCK17_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK18 // Description : Reading from a spinlock address will: @@ -1438,12 +1438,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK18_OFFSET 0x00000148 -#define SIO_SPINLOCK18_BITS 0xffffffff -#define SIO_SPINLOCK18_RESET 0x00000000 -#define SIO_SPINLOCK18_MSB 31 -#define SIO_SPINLOCK18_LSB 0 -#define SIO_SPINLOCK18_ACCESS "RO" +#define SIO_SPINLOCK18_OFFSET _u(0x00000148) +#define SIO_SPINLOCK18_BITS _u(0xffffffff) +#define SIO_SPINLOCK18_RESET _u(0x00000000) +#define SIO_SPINLOCK18_MSB _u(31) +#define SIO_SPINLOCK18_LSB _u(0) +#define SIO_SPINLOCK18_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK19 // Description : Reading from a spinlock address will: @@ -1454,12 +1454,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK19_OFFSET 0x0000014c -#define SIO_SPINLOCK19_BITS 0xffffffff -#define SIO_SPINLOCK19_RESET 0x00000000 -#define SIO_SPINLOCK19_MSB 31 -#define SIO_SPINLOCK19_LSB 0 -#define SIO_SPINLOCK19_ACCESS "RO" +#define SIO_SPINLOCK19_OFFSET _u(0x0000014c) +#define SIO_SPINLOCK19_BITS _u(0xffffffff) +#define SIO_SPINLOCK19_RESET _u(0x00000000) +#define SIO_SPINLOCK19_MSB _u(31) +#define SIO_SPINLOCK19_LSB _u(0) +#define SIO_SPINLOCK19_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK20 // Description : Reading from a spinlock address will: @@ -1470,12 +1470,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK20_OFFSET 0x00000150 -#define SIO_SPINLOCK20_BITS 0xffffffff -#define SIO_SPINLOCK20_RESET 0x00000000 -#define SIO_SPINLOCK20_MSB 31 -#define SIO_SPINLOCK20_LSB 0 -#define SIO_SPINLOCK20_ACCESS "RO" +#define SIO_SPINLOCK20_OFFSET _u(0x00000150) +#define SIO_SPINLOCK20_BITS _u(0xffffffff) +#define SIO_SPINLOCK20_RESET _u(0x00000000) +#define SIO_SPINLOCK20_MSB _u(31) +#define SIO_SPINLOCK20_LSB _u(0) +#define SIO_SPINLOCK20_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK21 // Description : Reading from a spinlock address will: @@ -1486,12 +1486,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK21_OFFSET 0x00000154 -#define SIO_SPINLOCK21_BITS 0xffffffff -#define SIO_SPINLOCK21_RESET 0x00000000 -#define SIO_SPINLOCK21_MSB 31 -#define SIO_SPINLOCK21_LSB 0 -#define SIO_SPINLOCK21_ACCESS "RO" +#define SIO_SPINLOCK21_OFFSET _u(0x00000154) +#define SIO_SPINLOCK21_BITS _u(0xffffffff) +#define SIO_SPINLOCK21_RESET _u(0x00000000) +#define SIO_SPINLOCK21_MSB _u(31) +#define SIO_SPINLOCK21_LSB _u(0) +#define SIO_SPINLOCK21_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK22 // Description : Reading from a spinlock address will: @@ -1502,12 +1502,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK22_OFFSET 0x00000158 -#define SIO_SPINLOCK22_BITS 0xffffffff -#define SIO_SPINLOCK22_RESET 0x00000000 -#define SIO_SPINLOCK22_MSB 31 -#define SIO_SPINLOCK22_LSB 0 -#define SIO_SPINLOCK22_ACCESS "RO" +#define SIO_SPINLOCK22_OFFSET _u(0x00000158) +#define SIO_SPINLOCK22_BITS _u(0xffffffff) +#define SIO_SPINLOCK22_RESET _u(0x00000000) +#define SIO_SPINLOCK22_MSB _u(31) +#define SIO_SPINLOCK22_LSB _u(0) +#define SIO_SPINLOCK22_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK23 // Description : Reading from a spinlock address will: @@ -1518,12 +1518,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK23_OFFSET 0x0000015c -#define SIO_SPINLOCK23_BITS 0xffffffff -#define SIO_SPINLOCK23_RESET 0x00000000 -#define SIO_SPINLOCK23_MSB 31 -#define SIO_SPINLOCK23_LSB 0 -#define SIO_SPINLOCK23_ACCESS "RO" +#define SIO_SPINLOCK23_OFFSET _u(0x0000015c) +#define SIO_SPINLOCK23_BITS _u(0xffffffff) +#define SIO_SPINLOCK23_RESET _u(0x00000000) +#define SIO_SPINLOCK23_MSB _u(31) +#define SIO_SPINLOCK23_LSB _u(0) +#define SIO_SPINLOCK23_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK24 // Description : Reading from a spinlock address will: @@ -1534,12 +1534,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK24_OFFSET 0x00000160 -#define SIO_SPINLOCK24_BITS 0xffffffff -#define SIO_SPINLOCK24_RESET 0x00000000 -#define SIO_SPINLOCK24_MSB 31 -#define SIO_SPINLOCK24_LSB 0 -#define SIO_SPINLOCK24_ACCESS "RO" +#define SIO_SPINLOCK24_OFFSET _u(0x00000160) +#define SIO_SPINLOCK24_BITS _u(0xffffffff) +#define SIO_SPINLOCK24_RESET _u(0x00000000) +#define SIO_SPINLOCK24_MSB _u(31) +#define SIO_SPINLOCK24_LSB _u(0) +#define SIO_SPINLOCK24_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK25 // Description : Reading from a spinlock address will: @@ -1550,12 +1550,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK25_OFFSET 0x00000164 -#define SIO_SPINLOCK25_BITS 0xffffffff -#define SIO_SPINLOCK25_RESET 0x00000000 -#define SIO_SPINLOCK25_MSB 31 -#define SIO_SPINLOCK25_LSB 0 -#define SIO_SPINLOCK25_ACCESS "RO" +#define SIO_SPINLOCK25_OFFSET _u(0x00000164) +#define SIO_SPINLOCK25_BITS _u(0xffffffff) +#define SIO_SPINLOCK25_RESET _u(0x00000000) +#define SIO_SPINLOCK25_MSB _u(31) +#define SIO_SPINLOCK25_LSB _u(0) +#define SIO_SPINLOCK25_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK26 // Description : Reading from a spinlock address will: @@ -1566,12 +1566,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK26_OFFSET 0x00000168 -#define SIO_SPINLOCK26_BITS 0xffffffff -#define SIO_SPINLOCK26_RESET 0x00000000 -#define SIO_SPINLOCK26_MSB 31 -#define SIO_SPINLOCK26_LSB 0 -#define SIO_SPINLOCK26_ACCESS "RO" +#define SIO_SPINLOCK26_OFFSET _u(0x00000168) +#define SIO_SPINLOCK26_BITS _u(0xffffffff) +#define SIO_SPINLOCK26_RESET _u(0x00000000) +#define SIO_SPINLOCK26_MSB _u(31) +#define SIO_SPINLOCK26_LSB _u(0) +#define SIO_SPINLOCK26_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK27 // Description : Reading from a spinlock address will: @@ -1582,12 +1582,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK27_OFFSET 0x0000016c -#define SIO_SPINLOCK27_BITS 0xffffffff -#define SIO_SPINLOCK27_RESET 0x00000000 -#define SIO_SPINLOCK27_MSB 31 -#define SIO_SPINLOCK27_LSB 0 -#define SIO_SPINLOCK27_ACCESS "RO" +#define SIO_SPINLOCK27_OFFSET _u(0x0000016c) +#define SIO_SPINLOCK27_BITS _u(0xffffffff) +#define SIO_SPINLOCK27_RESET _u(0x00000000) +#define SIO_SPINLOCK27_MSB _u(31) +#define SIO_SPINLOCK27_LSB _u(0) +#define SIO_SPINLOCK27_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK28 // Description : Reading from a spinlock address will: @@ -1598,12 +1598,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK28_OFFSET 0x00000170 -#define SIO_SPINLOCK28_BITS 0xffffffff -#define SIO_SPINLOCK28_RESET 0x00000000 -#define SIO_SPINLOCK28_MSB 31 -#define SIO_SPINLOCK28_LSB 0 -#define SIO_SPINLOCK28_ACCESS "RO" +#define SIO_SPINLOCK28_OFFSET _u(0x00000170) +#define SIO_SPINLOCK28_BITS _u(0xffffffff) +#define SIO_SPINLOCK28_RESET _u(0x00000000) +#define SIO_SPINLOCK28_MSB _u(31) +#define SIO_SPINLOCK28_LSB _u(0) +#define SIO_SPINLOCK28_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK29 // Description : Reading from a spinlock address will: @@ -1614,12 +1614,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK29_OFFSET 0x00000174 -#define SIO_SPINLOCK29_BITS 0xffffffff -#define SIO_SPINLOCK29_RESET 0x00000000 -#define SIO_SPINLOCK29_MSB 31 -#define SIO_SPINLOCK29_LSB 0 -#define SIO_SPINLOCK29_ACCESS "RO" +#define SIO_SPINLOCK29_OFFSET _u(0x00000174) +#define SIO_SPINLOCK29_BITS _u(0xffffffff) +#define SIO_SPINLOCK29_RESET _u(0x00000000) +#define SIO_SPINLOCK29_MSB _u(31) +#define SIO_SPINLOCK29_LSB _u(0) +#define SIO_SPINLOCK29_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK30 // Description : Reading from a spinlock address will: @@ -1630,12 +1630,12 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK30_OFFSET 0x00000178 -#define SIO_SPINLOCK30_BITS 0xffffffff -#define SIO_SPINLOCK30_RESET 0x00000000 -#define SIO_SPINLOCK30_MSB 31 -#define SIO_SPINLOCK30_LSB 0 -#define SIO_SPINLOCK30_ACCESS "RO" +#define SIO_SPINLOCK30_OFFSET _u(0x00000178) +#define SIO_SPINLOCK30_BITS _u(0xffffffff) +#define SIO_SPINLOCK30_RESET _u(0x00000000) +#define SIO_SPINLOCK30_MSB _u(31) +#define SIO_SPINLOCK30_LSB _u(0) +#define SIO_SPINLOCK30_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK31 // Description : Reading from a spinlock address will: @@ -1646,11 +1646,11 @@ // If core 0 and core 1 attempt to claim the same lock // simultaneously, core 0 wins. // The value returned on success is 0x1 << lock number. -#define SIO_SPINLOCK31_OFFSET 0x0000017c -#define SIO_SPINLOCK31_BITS 0xffffffff -#define SIO_SPINLOCK31_RESET 0x00000000 -#define SIO_SPINLOCK31_MSB 31 -#define SIO_SPINLOCK31_LSB 0 -#define SIO_SPINLOCK31_ACCESS "RO" +#define SIO_SPINLOCK31_OFFSET _u(0x0000017c) +#define SIO_SPINLOCK31_BITS _u(0xffffffff) +#define SIO_SPINLOCK31_RESET _u(0x00000000) +#define SIO_SPINLOCK31_MSB _u(31) +#define SIO_SPINLOCK31_LSB _u(0) +#define SIO_SPINLOCK31_ACCESS "RW" // ============================================================================= #endif // HARDWARE_REGS_SIO_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/spi.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/spi.h index 9670b8309..816e15024 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/spi.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/spi.h @@ -14,9 +14,9 @@ // ============================================================================= // Register : SPI_SSPCR0 // Description : Control register 0, SSPCR0 on page 3-4 -#define SPI_SSPCR0_OFFSET 0x00000000 -#define SPI_SSPCR0_BITS 0x0000ffff -#define SPI_SSPCR0_RESET 0x00000000 +#define SPI_SSPCR0_OFFSET _u(0x00000000) +#define SPI_SSPCR0_BITS _u(0x0000ffff) +#define SPI_SSPCR0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SPI_SSPCR0_SCR // Description : Serial clock rate. The value SCR is used to generate the @@ -24,38 +24,38 @@ // rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even // value from 2-254, programmed through the SSPCPSR register and // SCR is a value from 0-255. -#define SPI_SSPCR0_SCR_RESET 0x00 -#define SPI_SSPCR0_SCR_BITS 0x0000ff00 -#define SPI_SSPCR0_SCR_MSB 15 -#define SPI_SSPCR0_SCR_LSB 8 +#define SPI_SSPCR0_SCR_RESET _u(0x00) +#define SPI_SSPCR0_SCR_BITS _u(0x0000ff00) +#define SPI_SSPCR0_SCR_MSB _u(15) +#define SPI_SSPCR0_SCR_LSB _u(8) #define SPI_SSPCR0_SCR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPCR0_SPH // Description : SSPCLKOUT phase, applicable to Motorola SPI frame format only. // See Motorola SPI frame format on page 2-10. -#define SPI_SSPCR0_SPH_RESET 0x0 -#define SPI_SSPCR0_SPH_BITS 0x00000080 -#define SPI_SSPCR0_SPH_MSB 7 -#define SPI_SSPCR0_SPH_LSB 7 +#define SPI_SSPCR0_SPH_RESET _u(0x0) +#define SPI_SSPCR0_SPH_BITS _u(0x00000080) +#define SPI_SSPCR0_SPH_MSB _u(7) +#define SPI_SSPCR0_SPH_LSB _u(7) #define SPI_SSPCR0_SPH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPCR0_SPO // Description : SSPCLKOUT polarity, applicable to Motorola SPI frame format // only. See Motorola SPI frame format on page 2-10. -#define SPI_SSPCR0_SPO_RESET 0x0 -#define SPI_SSPCR0_SPO_BITS 0x00000040 -#define SPI_SSPCR0_SPO_MSB 6 -#define SPI_SSPCR0_SPO_LSB 6 +#define SPI_SSPCR0_SPO_RESET _u(0x0) +#define SPI_SSPCR0_SPO_BITS _u(0x00000040) +#define SPI_SSPCR0_SPO_MSB _u(6) +#define SPI_SSPCR0_SPO_LSB _u(6) #define SPI_SSPCR0_SPO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPCR0_FRF // Description : Frame format: 00 Motorola SPI frame format. 01 TI synchronous // serial frame format. 10 National Microwire frame format. 11 // Reserved, undefined operation. -#define SPI_SSPCR0_FRF_RESET 0x0 -#define SPI_SSPCR0_FRF_BITS 0x00000030 -#define SPI_SSPCR0_FRF_MSB 5 -#define SPI_SSPCR0_FRF_LSB 4 +#define SPI_SSPCR0_FRF_RESET _u(0x0) +#define SPI_SSPCR0_FRF_BITS _u(0x00000030) +#define SPI_SSPCR0_FRF_MSB _u(5) +#define SPI_SSPCR0_FRF_LSB _u(4) #define SPI_SSPCR0_FRF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPCR0_DSS @@ -65,17 +65,17 @@ // 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit // data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. // 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. -#define SPI_SSPCR0_DSS_RESET 0x0 -#define SPI_SSPCR0_DSS_BITS 0x0000000f -#define SPI_SSPCR0_DSS_MSB 3 -#define SPI_SSPCR0_DSS_LSB 0 +#define SPI_SSPCR0_DSS_RESET _u(0x0) +#define SPI_SSPCR0_DSS_BITS _u(0x0000000f) +#define SPI_SSPCR0_DSS_MSB _u(3) +#define SPI_SSPCR0_DSS_LSB _u(0) #define SPI_SSPCR0_DSS_ACCESS "RW" // ============================================================================= // Register : SPI_SSPCR1 // Description : Control register 1, SSPCR1 on page 3-5 -#define SPI_SSPCR1_OFFSET 0x00000004 -#define SPI_SSPCR1_BITS 0x0000000f -#define SPI_SSPCR1_RESET 0x00000000 +#define SPI_SSPCR1_OFFSET _u(0x00000004) +#define SPI_SSPCR1_BITS _u(0x0000000f) +#define SPI_SSPCR1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SPI_SSPCR1_SOD // Description : Slave-mode output disable. This bit is relevant only in the @@ -88,45 +88,45 @@ // not supposed to drive the SSPTXD line: 0 SSP can drive the // SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD // output in slave mode. -#define SPI_SSPCR1_SOD_RESET 0x0 -#define SPI_SSPCR1_SOD_BITS 0x00000008 -#define SPI_SSPCR1_SOD_MSB 3 -#define SPI_SSPCR1_SOD_LSB 3 +#define SPI_SSPCR1_SOD_RESET _u(0x0) +#define SPI_SSPCR1_SOD_BITS _u(0x00000008) +#define SPI_SSPCR1_SOD_MSB _u(3) +#define SPI_SSPCR1_SOD_LSB _u(3) #define SPI_SSPCR1_SOD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPCR1_MS // Description : Master or slave mode select. This bit can be modified only when // the PrimeCell SSP is disabled, SSE=0: 0 Device configured as // master, default. 1 Device configured as slave. -#define SPI_SSPCR1_MS_RESET 0x0 -#define SPI_SSPCR1_MS_BITS 0x00000004 -#define SPI_SSPCR1_MS_MSB 2 -#define SPI_SSPCR1_MS_LSB 2 +#define SPI_SSPCR1_MS_RESET _u(0x0) +#define SPI_SSPCR1_MS_BITS _u(0x00000004) +#define SPI_SSPCR1_MS_MSB _u(2) +#define SPI_SSPCR1_MS_LSB _u(2) #define SPI_SSPCR1_MS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPCR1_SSE // Description : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP // operation enabled. -#define SPI_SSPCR1_SSE_RESET 0x0 -#define SPI_SSPCR1_SSE_BITS 0x00000002 -#define SPI_SSPCR1_SSE_MSB 1 -#define SPI_SSPCR1_SSE_LSB 1 +#define SPI_SSPCR1_SSE_RESET _u(0x0) +#define SPI_SSPCR1_SSE_BITS _u(0x00000002) +#define SPI_SSPCR1_SSE_MSB _u(1) +#define SPI_SSPCR1_SSE_LSB _u(1) #define SPI_SSPCR1_SSE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPCR1_LBM // Description : Loop back mode: 0 Normal serial port operation enabled. 1 // Output of transmit serial shifter is connected to input of // receive serial shifter internally. -#define SPI_SSPCR1_LBM_RESET 0x0 -#define SPI_SSPCR1_LBM_BITS 0x00000001 -#define SPI_SSPCR1_LBM_MSB 0 -#define SPI_SSPCR1_LBM_LSB 0 +#define SPI_SSPCR1_LBM_RESET _u(0x0) +#define SPI_SSPCR1_LBM_BITS _u(0x00000001) +#define SPI_SSPCR1_LBM_MSB _u(0) +#define SPI_SSPCR1_LBM_LSB _u(0) #define SPI_SSPCR1_LBM_ACCESS "RW" // ============================================================================= // Register : SPI_SSPDR // Description : Data register, SSPDR on page 3-6 -#define SPI_SSPDR_OFFSET 0x00000008 -#define SPI_SSPDR_BITS 0x0000ffff +#define SPI_SSPDR_OFFSET _u(0x00000008) +#define SPI_SSPDR_BITS _u(0x0000ffff) #define SPI_SSPDR_RESET "-" // ----------------------------------------------------------------------------- // Field : SPI_SSPDR_DATA @@ -136,103 +136,103 @@ // bits at the top are ignored by transmit logic. The receive // logic automatically right-justifies. #define SPI_SSPDR_DATA_RESET "-" -#define SPI_SSPDR_DATA_BITS 0x0000ffff -#define SPI_SSPDR_DATA_MSB 15 -#define SPI_SSPDR_DATA_LSB 0 +#define SPI_SSPDR_DATA_BITS _u(0x0000ffff) +#define SPI_SSPDR_DATA_MSB _u(15) +#define SPI_SSPDR_DATA_LSB _u(0) #define SPI_SSPDR_DATA_ACCESS "RWF" // ============================================================================= // Register : SPI_SSPSR // Description : Status register, SSPSR on page 3-7 -#define SPI_SSPSR_OFFSET 0x0000000c -#define SPI_SSPSR_BITS 0x0000001f -#define SPI_SSPSR_RESET 0x00000003 +#define SPI_SSPSR_OFFSET _u(0x0000000c) +#define SPI_SSPSR_BITS _u(0x0000001f) +#define SPI_SSPSR_RESET _u(0x00000003) // ----------------------------------------------------------------------------- // Field : SPI_SSPSR_BSY // Description : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently // transmitting and/or receiving a frame or the transmit FIFO is // not empty. -#define SPI_SSPSR_BSY_RESET 0x0 -#define SPI_SSPSR_BSY_BITS 0x00000010 -#define SPI_SSPSR_BSY_MSB 4 -#define SPI_SSPSR_BSY_LSB 4 +#define SPI_SSPSR_BSY_RESET _u(0x0) +#define SPI_SSPSR_BSY_BITS _u(0x00000010) +#define SPI_SSPSR_BSY_MSB _u(4) +#define SPI_SSPSR_BSY_LSB _u(4) #define SPI_SSPSR_BSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPSR_RFF // Description : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive // FIFO is full. -#define SPI_SSPSR_RFF_RESET 0x0 -#define SPI_SSPSR_RFF_BITS 0x00000008 -#define SPI_SSPSR_RFF_MSB 3 -#define SPI_SSPSR_RFF_LSB 3 +#define SPI_SSPSR_RFF_RESET _u(0x0) +#define SPI_SSPSR_RFF_BITS _u(0x00000008) +#define SPI_SSPSR_RFF_MSB _u(3) +#define SPI_SSPSR_RFF_LSB _u(3) #define SPI_SSPSR_RFF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPSR_RNE // Description : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive // FIFO is not empty. -#define SPI_SSPSR_RNE_RESET 0x0 -#define SPI_SSPSR_RNE_BITS 0x00000004 -#define SPI_SSPSR_RNE_MSB 2 -#define SPI_SSPSR_RNE_LSB 2 +#define SPI_SSPSR_RNE_RESET _u(0x0) +#define SPI_SSPSR_RNE_BITS _u(0x00000004) +#define SPI_SSPSR_RNE_MSB _u(2) +#define SPI_SSPSR_RNE_LSB _u(2) #define SPI_SSPSR_RNE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPSR_TNF // Description : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit // FIFO is not full. -#define SPI_SSPSR_TNF_RESET 0x1 -#define SPI_SSPSR_TNF_BITS 0x00000002 -#define SPI_SSPSR_TNF_MSB 1 -#define SPI_SSPSR_TNF_LSB 1 +#define SPI_SSPSR_TNF_RESET _u(0x1) +#define SPI_SSPSR_TNF_BITS _u(0x00000002) +#define SPI_SSPSR_TNF_MSB _u(1) +#define SPI_SSPSR_TNF_LSB _u(1) #define SPI_SSPSR_TNF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPSR_TFE // Description : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 // Transmit FIFO is empty. -#define SPI_SSPSR_TFE_RESET 0x1 -#define SPI_SSPSR_TFE_BITS 0x00000001 -#define SPI_SSPSR_TFE_MSB 0 -#define SPI_SSPSR_TFE_LSB 0 +#define SPI_SSPSR_TFE_RESET _u(0x1) +#define SPI_SSPSR_TFE_BITS _u(0x00000001) +#define SPI_SSPSR_TFE_MSB _u(0) +#define SPI_SSPSR_TFE_LSB _u(0) #define SPI_SSPSR_TFE_ACCESS "RO" // ============================================================================= // Register : SPI_SSPCPSR // Description : Clock prescale register, SSPCPSR on page 3-8 -#define SPI_SSPCPSR_OFFSET 0x00000010 -#define SPI_SSPCPSR_BITS 0x000000ff -#define SPI_SSPCPSR_RESET 0x00000000 +#define SPI_SSPCPSR_OFFSET _u(0x00000010) +#define SPI_SSPCPSR_BITS _u(0x000000ff) +#define SPI_SSPCPSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SPI_SSPCPSR_CPSDVSR // Description : Clock prescale divisor. Must be an even number from 2-254, // depending on the frequency of SSPCLK. The least significant bit // always returns zero on reads. -#define SPI_SSPCPSR_CPSDVSR_RESET 0x00 -#define SPI_SSPCPSR_CPSDVSR_BITS 0x000000ff -#define SPI_SSPCPSR_CPSDVSR_MSB 7 -#define SPI_SSPCPSR_CPSDVSR_LSB 0 +#define SPI_SSPCPSR_CPSDVSR_RESET _u(0x00) +#define SPI_SSPCPSR_CPSDVSR_BITS _u(0x000000ff) +#define SPI_SSPCPSR_CPSDVSR_MSB _u(7) +#define SPI_SSPCPSR_CPSDVSR_LSB _u(0) #define SPI_SSPCPSR_CPSDVSR_ACCESS "RW" // ============================================================================= // Register : SPI_SSPIMSC // Description : Interrupt mask set or clear register, SSPIMSC on page 3-9 -#define SPI_SSPIMSC_OFFSET 0x00000014 -#define SPI_SSPIMSC_BITS 0x0000000f -#define SPI_SSPIMSC_RESET 0x00000000 +#define SPI_SSPIMSC_OFFSET _u(0x00000014) +#define SPI_SSPIMSC_BITS _u(0x0000000f) +#define SPI_SSPIMSC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SPI_SSPIMSC_TXIM // Description : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or // less condition interrupt is masked. 1 Transmit FIFO half empty // or less condition interrupt is not masked. -#define SPI_SSPIMSC_TXIM_RESET 0x0 -#define SPI_SSPIMSC_TXIM_BITS 0x00000008 -#define SPI_SSPIMSC_TXIM_MSB 3 -#define SPI_SSPIMSC_TXIM_LSB 3 +#define SPI_SSPIMSC_TXIM_RESET _u(0x0) +#define SPI_SSPIMSC_TXIM_BITS _u(0x00000008) +#define SPI_SSPIMSC_TXIM_MSB _u(3) +#define SPI_SSPIMSC_TXIM_LSB _u(3) #define SPI_SSPIMSC_TXIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPIMSC_RXIM // Description : Receive FIFO interrupt mask: 0 Receive FIFO half full or less // condition interrupt is masked. 1 Receive FIFO half full or less // condition interrupt is not masked. -#define SPI_SSPIMSC_RXIM_RESET 0x0 -#define SPI_SSPIMSC_RXIM_BITS 0x00000004 -#define SPI_SSPIMSC_RXIM_MSB 2 -#define SPI_SSPIMSC_RXIM_LSB 2 +#define SPI_SSPIMSC_RXIM_RESET _u(0x0) +#define SPI_SSPIMSC_RXIM_BITS _u(0x00000004) +#define SPI_SSPIMSC_RXIM_MSB _u(2) +#define SPI_SSPIMSC_RXIM_LSB _u(2) #define SPI_SSPIMSC_RXIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPIMSC_RTIM @@ -240,282 +240,282 @@ // read prior to timeout period interrupt is masked. 1 Receive // FIFO not empty and no read prior to timeout period interrupt is // not masked. -#define SPI_SSPIMSC_RTIM_RESET 0x0 -#define SPI_SSPIMSC_RTIM_BITS 0x00000002 -#define SPI_SSPIMSC_RTIM_MSB 1 -#define SPI_SSPIMSC_RTIM_LSB 1 +#define SPI_SSPIMSC_RTIM_RESET _u(0x0) +#define SPI_SSPIMSC_RTIM_BITS _u(0x00000002) +#define SPI_SSPIMSC_RTIM_MSB _u(1) +#define SPI_SSPIMSC_RTIM_LSB _u(1) #define SPI_SSPIMSC_RTIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPIMSC_RORIM // Description : Receive overrun interrupt mask: 0 Receive FIFO written to while // full condition interrupt is masked. 1 Receive FIFO written to // while full condition interrupt is not masked. -#define SPI_SSPIMSC_RORIM_RESET 0x0 -#define SPI_SSPIMSC_RORIM_BITS 0x00000001 -#define SPI_SSPIMSC_RORIM_MSB 0 -#define SPI_SSPIMSC_RORIM_LSB 0 +#define SPI_SSPIMSC_RORIM_RESET _u(0x0) +#define SPI_SSPIMSC_RORIM_BITS _u(0x00000001) +#define SPI_SSPIMSC_RORIM_MSB _u(0) +#define SPI_SSPIMSC_RORIM_LSB _u(0) #define SPI_SSPIMSC_RORIM_ACCESS "RW" // ============================================================================= // Register : SPI_SSPRIS // Description : Raw interrupt status register, SSPRIS on page 3-10 -#define SPI_SSPRIS_OFFSET 0x00000018 -#define SPI_SSPRIS_BITS 0x0000000f -#define SPI_SSPRIS_RESET 0x00000008 +#define SPI_SSPRIS_OFFSET _u(0x00000018) +#define SPI_SSPRIS_BITS _u(0x0000000f) +#define SPI_SSPRIS_RESET _u(0x00000008) // ----------------------------------------------------------------------------- // Field : SPI_SSPRIS_TXRIS // Description : Gives the raw interrupt state, prior to masking, of the // SSPTXINTR interrupt -#define SPI_SSPRIS_TXRIS_RESET 0x1 -#define SPI_SSPRIS_TXRIS_BITS 0x00000008 -#define SPI_SSPRIS_TXRIS_MSB 3 -#define SPI_SSPRIS_TXRIS_LSB 3 +#define SPI_SSPRIS_TXRIS_RESET _u(0x1) +#define SPI_SSPRIS_TXRIS_BITS _u(0x00000008) +#define SPI_SSPRIS_TXRIS_MSB _u(3) +#define SPI_SSPRIS_TXRIS_LSB _u(3) #define SPI_SSPRIS_TXRIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPRIS_RXRIS // Description : Gives the raw interrupt state, prior to masking, of the // SSPRXINTR interrupt -#define SPI_SSPRIS_RXRIS_RESET 0x0 -#define SPI_SSPRIS_RXRIS_BITS 0x00000004 -#define SPI_SSPRIS_RXRIS_MSB 2 -#define SPI_SSPRIS_RXRIS_LSB 2 +#define SPI_SSPRIS_RXRIS_RESET _u(0x0) +#define SPI_SSPRIS_RXRIS_BITS _u(0x00000004) +#define SPI_SSPRIS_RXRIS_MSB _u(2) +#define SPI_SSPRIS_RXRIS_LSB _u(2) #define SPI_SSPRIS_RXRIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPRIS_RTRIS // Description : Gives the raw interrupt state, prior to masking, of the // SSPRTINTR interrupt -#define SPI_SSPRIS_RTRIS_RESET 0x0 -#define SPI_SSPRIS_RTRIS_BITS 0x00000002 -#define SPI_SSPRIS_RTRIS_MSB 1 -#define SPI_SSPRIS_RTRIS_LSB 1 +#define SPI_SSPRIS_RTRIS_RESET _u(0x0) +#define SPI_SSPRIS_RTRIS_BITS _u(0x00000002) +#define SPI_SSPRIS_RTRIS_MSB _u(1) +#define SPI_SSPRIS_RTRIS_LSB _u(1) #define SPI_SSPRIS_RTRIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPRIS_RORRIS // Description : Gives the raw interrupt state, prior to masking, of the // SSPRORINTR interrupt -#define SPI_SSPRIS_RORRIS_RESET 0x0 -#define SPI_SSPRIS_RORRIS_BITS 0x00000001 -#define SPI_SSPRIS_RORRIS_MSB 0 -#define SPI_SSPRIS_RORRIS_LSB 0 +#define SPI_SSPRIS_RORRIS_RESET _u(0x0) +#define SPI_SSPRIS_RORRIS_BITS _u(0x00000001) +#define SPI_SSPRIS_RORRIS_MSB _u(0) +#define SPI_SSPRIS_RORRIS_LSB _u(0) #define SPI_SSPRIS_RORRIS_ACCESS "RO" // ============================================================================= // Register : SPI_SSPMIS // Description : Masked interrupt status register, SSPMIS on page 3-11 -#define SPI_SSPMIS_OFFSET 0x0000001c -#define SPI_SSPMIS_BITS 0x0000000f -#define SPI_SSPMIS_RESET 0x00000000 +#define SPI_SSPMIS_OFFSET _u(0x0000001c) +#define SPI_SSPMIS_BITS _u(0x0000000f) +#define SPI_SSPMIS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SPI_SSPMIS_TXMIS // Description : Gives the transmit FIFO masked interrupt state, after masking, // of the SSPTXINTR interrupt -#define SPI_SSPMIS_TXMIS_RESET 0x0 -#define SPI_SSPMIS_TXMIS_BITS 0x00000008 -#define SPI_SSPMIS_TXMIS_MSB 3 -#define SPI_SSPMIS_TXMIS_LSB 3 +#define SPI_SSPMIS_TXMIS_RESET _u(0x0) +#define SPI_SSPMIS_TXMIS_BITS _u(0x00000008) +#define SPI_SSPMIS_TXMIS_MSB _u(3) +#define SPI_SSPMIS_TXMIS_LSB _u(3) #define SPI_SSPMIS_TXMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPMIS_RXMIS // Description : Gives the receive FIFO masked interrupt state, after masking, // of the SSPRXINTR interrupt -#define SPI_SSPMIS_RXMIS_RESET 0x0 -#define SPI_SSPMIS_RXMIS_BITS 0x00000004 -#define SPI_SSPMIS_RXMIS_MSB 2 -#define SPI_SSPMIS_RXMIS_LSB 2 +#define SPI_SSPMIS_RXMIS_RESET _u(0x0) +#define SPI_SSPMIS_RXMIS_BITS _u(0x00000004) +#define SPI_SSPMIS_RXMIS_MSB _u(2) +#define SPI_SSPMIS_RXMIS_LSB _u(2) #define SPI_SSPMIS_RXMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPMIS_RTMIS // Description : Gives the receive timeout masked interrupt state, after // masking, of the SSPRTINTR interrupt -#define SPI_SSPMIS_RTMIS_RESET 0x0 -#define SPI_SSPMIS_RTMIS_BITS 0x00000002 -#define SPI_SSPMIS_RTMIS_MSB 1 -#define SPI_SSPMIS_RTMIS_LSB 1 +#define SPI_SSPMIS_RTMIS_RESET _u(0x0) +#define SPI_SSPMIS_RTMIS_BITS _u(0x00000002) +#define SPI_SSPMIS_RTMIS_MSB _u(1) +#define SPI_SSPMIS_RTMIS_LSB _u(1) #define SPI_SSPMIS_RTMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPMIS_RORMIS // Description : Gives the receive over run masked interrupt status, after // masking, of the SSPRORINTR interrupt -#define SPI_SSPMIS_RORMIS_RESET 0x0 -#define SPI_SSPMIS_RORMIS_BITS 0x00000001 -#define SPI_SSPMIS_RORMIS_MSB 0 -#define SPI_SSPMIS_RORMIS_LSB 0 +#define SPI_SSPMIS_RORMIS_RESET _u(0x0) +#define SPI_SSPMIS_RORMIS_BITS _u(0x00000001) +#define SPI_SSPMIS_RORMIS_MSB _u(0) +#define SPI_SSPMIS_RORMIS_LSB _u(0) #define SPI_SSPMIS_RORMIS_ACCESS "RO" // ============================================================================= // Register : SPI_SSPICR // Description : Interrupt clear register, SSPICR on page 3-11 -#define SPI_SSPICR_OFFSET 0x00000020 -#define SPI_SSPICR_BITS 0x00000003 -#define SPI_SSPICR_RESET 0x00000000 +#define SPI_SSPICR_OFFSET _u(0x00000020) +#define SPI_SSPICR_BITS _u(0x00000003) +#define SPI_SSPICR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SPI_SSPICR_RTIC // Description : Clears the SSPRTINTR interrupt -#define SPI_SSPICR_RTIC_RESET 0x0 -#define SPI_SSPICR_RTIC_BITS 0x00000002 -#define SPI_SSPICR_RTIC_MSB 1 -#define SPI_SSPICR_RTIC_LSB 1 +#define SPI_SSPICR_RTIC_RESET _u(0x0) +#define SPI_SSPICR_RTIC_BITS _u(0x00000002) +#define SPI_SSPICR_RTIC_MSB _u(1) +#define SPI_SSPICR_RTIC_LSB _u(1) #define SPI_SSPICR_RTIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : SPI_SSPICR_RORIC // Description : Clears the SSPRORINTR interrupt -#define SPI_SSPICR_RORIC_RESET 0x0 -#define SPI_SSPICR_RORIC_BITS 0x00000001 -#define SPI_SSPICR_RORIC_MSB 0 -#define SPI_SSPICR_RORIC_LSB 0 +#define SPI_SSPICR_RORIC_RESET _u(0x0) +#define SPI_SSPICR_RORIC_BITS _u(0x00000001) +#define SPI_SSPICR_RORIC_MSB _u(0) +#define SPI_SSPICR_RORIC_LSB _u(0) #define SPI_SSPICR_RORIC_ACCESS "WC" // ============================================================================= // Register : SPI_SSPDMACR // Description : DMA control register, SSPDMACR on page 3-12 -#define SPI_SSPDMACR_OFFSET 0x00000024 -#define SPI_SSPDMACR_BITS 0x00000003 -#define SPI_SSPDMACR_RESET 0x00000000 +#define SPI_SSPDMACR_OFFSET _u(0x00000024) +#define SPI_SSPDMACR_BITS _u(0x00000003) +#define SPI_SSPDMACR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SPI_SSPDMACR_TXDMAE // Description : Transmit DMA Enable. If this bit is set to 1, DMA for the // transmit FIFO is enabled. -#define SPI_SSPDMACR_TXDMAE_RESET 0x0 -#define SPI_SSPDMACR_TXDMAE_BITS 0x00000002 -#define SPI_SSPDMACR_TXDMAE_MSB 1 -#define SPI_SSPDMACR_TXDMAE_LSB 1 +#define SPI_SSPDMACR_TXDMAE_RESET _u(0x0) +#define SPI_SSPDMACR_TXDMAE_BITS _u(0x00000002) +#define SPI_SSPDMACR_TXDMAE_MSB _u(1) +#define SPI_SSPDMACR_TXDMAE_LSB _u(1) #define SPI_SSPDMACR_TXDMAE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SPI_SSPDMACR_RXDMAE // Description : Receive DMA Enable. If this bit is set to 1, DMA for the // receive FIFO is enabled. -#define SPI_SSPDMACR_RXDMAE_RESET 0x0 -#define SPI_SSPDMACR_RXDMAE_BITS 0x00000001 -#define SPI_SSPDMACR_RXDMAE_MSB 0 -#define SPI_SSPDMACR_RXDMAE_LSB 0 +#define SPI_SSPDMACR_RXDMAE_RESET _u(0x0) +#define SPI_SSPDMACR_RXDMAE_BITS _u(0x00000001) +#define SPI_SSPDMACR_RXDMAE_MSB _u(0) +#define SPI_SSPDMACR_RXDMAE_LSB _u(0) #define SPI_SSPDMACR_RXDMAE_ACCESS "RW" // ============================================================================= // Register : SPI_SSPPERIPHID0 // Description : Peripheral identification registers, SSPPeriphID0-3 on page // 3-13 -#define SPI_SSPPERIPHID0_OFFSET 0x00000fe0 -#define SPI_SSPPERIPHID0_BITS 0x000000ff -#define SPI_SSPPERIPHID0_RESET 0x00000022 +#define SPI_SSPPERIPHID0_OFFSET _u(0x00000fe0) +#define SPI_SSPPERIPHID0_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID0_RESET _u(0x00000022) // ----------------------------------------------------------------------------- // Field : SPI_SSPPERIPHID0_PARTNUMBER0 // Description : These bits read back as 0x22 -#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET 0x22 -#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS 0x000000ff -#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB 7 -#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB 0 +#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET _u(0x22) +#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB _u(7) +#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB _u(0) #define SPI_SSPPERIPHID0_PARTNUMBER0_ACCESS "RO" // ============================================================================= // Register : SPI_SSPPERIPHID1 // Description : Peripheral identification registers, SSPPeriphID0-3 on page // 3-13 -#define SPI_SSPPERIPHID1_OFFSET 0x00000fe4 -#define SPI_SSPPERIPHID1_BITS 0x000000ff -#define SPI_SSPPERIPHID1_RESET 0x00000010 +#define SPI_SSPPERIPHID1_OFFSET _u(0x00000fe4) +#define SPI_SSPPERIPHID1_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID1_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : SPI_SSPPERIPHID1_DESIGNER0 // Description : These bits read back as 0x1 -#define SPI_SSPPERIPHID1_DESIGNER0_RESET 0x1 -#define SPI_SSPPERIPHID1_DESIGNER0_BITS 0x000000f0 -#define SPI_SSPPERIPHID1_DESIGNER0_MSB 7 -#define SPI_SSPPERIPHID1_DESIGNER0_LSB 4 +#define SPI_SSPPERIPHID1_DESIGNER0_RESET _u(0x1) +#define SPI_SSPPERIPHID1_DESIGNER0_BITS _u(0x000000f0) +#define SPI_SSPPERIPHID1_DESIGNER0_MSB _u(7) +#define SPI_SSPPERIPHID1_DESIGNER0_LSB _u(4) #define SPI_SSPPERIPHID1_DESIGNER0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPPERIPHID1_PARTNUMBER1 // Description : These bits read back as 0x0 -#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET 0x0 -#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS 0x0000000f -#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB 3 -#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB 0 +#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET _u(0x0) +#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f) +#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB _u(3) +#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB _u(0) #define SPI_SSPPERIPHID1_PARTNUMBER1_ACCESS "RO" // ============================================================================= // Register : SPI_SSPPERIPHID2 // Description : Peripheral identification registers, SSPPeriphID0-3 on page // 3-13 -#define SPI_SSPPERIPHID2_OFFSET 0x00000fe8 -#define SPI_SSPPERIPHID2_BITS 0x000000ff -#define SPI_SSPPERIPHID2_RESET 0x00000034 +#define SPI_SSPPERIPHID2_OFFSET _u(0x00000fe8) +#define SPI_SSPPERIPHID2_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID2_RESET _u(0x00000034) // ----------------------------------------------------------------------------- // Field : SPI_SSPPERIPHID2_REVISION // Description : These bits return the peripheral revision -#define SPI_SSPPERIPHID2_REVISION_RESET 0x3 -#define SPI_SSPPERIPHID2_REVISION_BITS 0x000000f0 -#define SPI_SSPPERIPHID2_REVISION_MSB 7 -#define SPI_SSPPERIPHID2_REVISION_LSB 4 +#define SPI_SSPPERIPHID2_REVISION_RESET _u(0x3) +#define SPI_SSPPERIPHID2_REVISION_BITS _u(0x000000f0) +#define SPI_SSPPERIPHID2_REVISION_MSB _u(7) +#define SPI_SSPPERIPHID2_REVISION_LSB _u(4) #define SPI_SSPPERIPHID2_REVISION_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SPI_SSPPERIPHID2_DESIGNER1 // Description : These bits read back as 0x4 -#define SPI_SSPPERIPHID2_DESIGNER1_RESET 0x4 -#define SPI_SSPPERIPHID2_DESIGNER1_BITS 0x0000000f -#define SPI_SSPPERIPHID2_DESIGNER1_MSB 3 -#define SPI_SSPPERIPHID2_DESIGNER1_LSB 0 +#define SPI_SSPPERIPHID2_DESIGNER1_RESET _u(0x4) +#define SPI_SSPPERIPHID2_DESIGNER1_BITS _u(0x0000000f) +#define SPI_SSPPERIPHID2_DESIGNER1_MSB _u(3) +#define SPI_SSPPERIPHID2_DESIGNER1_LSB _u(0) #define SPI_SSPPERIPHID2_DESIGNER1_ACCESS "RO" // ============================================================================= // Register : SPI_SSPPERIPHID3 // Description : Peripheral identification registers, SSPPeriphID0-3 on page // 3-13 -#define SPI_SSPPERIPHID3_OFFSET 0x00000fec -#define SPI_SSPPERIPHID3_BITS 0x000000ff -#define SPI_SSPPERIPHID3_RESET 0x00000000 +#define SPI_SSPPERIPHID3_OFFSET _u(0x00000fec) +#define SPI_SSPPERIPHID3_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SPI_SSPPERIPHID3_CONFIGURATION // Description : These bits read back as 0x00 -#define SPI_SSPPERIPHID3_CONFIGURATION_RESET 0x00 -#define SPI_SSPPERIPHID3_CONFIGURATION_BITS 0x000000ff -#define SPI_SSPPERIPHID3_CONFIGURATION_MSB 7 -#define SPI_SSPPERIPHID3_CONFIGURATION_LSB 0 +#define SPI_SSPPERIPHID3_CONFIGURATION_RESET _u(0x00) +#define SPI_SSPPERIPHID3_CONFIGURATION_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID3_CONFIGURATION_MSB _u(7) +#define SPI_SSPPERIPHID3_CONFIGURATION_LSB _u(0) #define SPI_SSPPERIPHID3_CONFIGURATION_ACCESS "RO" // ============================================================================= // Register : SPI_SSPPCELLID0 // Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -#define SPI_SSPPCELLID0_OFFSET 0x00000ff0 -#define SPI_SSPPCELLID0_BITS 0x000000ff -#define SPI_SSPPCELLID0_RESET 0x0000000d +#define SPI_SSPPCELLID0_OFFSET _u(0x00000ff0) +#define SPI_SSPPCELLID0_BITS _u(0x000000ff) +#define SPI_SSPPCELLID0_RESET _u(0x0000000d) // ----------------------------------------------------------------------------- // Field : SPI_SSPPCELLID0_SSPPCELLID0 // Description : These bits read back as 0x0D -#define SPI_SSPPCELLID0_SSPPCELLID0_RESET 0x0d -#define SPI_SSPPCELLID0_SSPPCELLID0_BITS 0x000000ff -#define SPI_SSPPCELLID0_SSPPCELLID0_MSB 7 -#define SPI_SSPPCELLID0_SSPPCELLID0_LSB 0 +#define SPI_SSPPCELLID0_SSPPCELLID0_RESET _u(0x0d) +#define SPI_SSPPCELLID0_SSPPCELLID0_BITS _u(0x000000ff) +#define SPI_SSPPCELLID0_SSPPCELLID0_MSB _u(7) +#define SPI_SSPPCELLID0_SSPPCELLID0_LSB _u(0) #define SPI_SSPPCELLID0_SSPPCELLID0_ACCESS "RO" // ============================================================================= // Register : SPI_SSPPCELLID1 // Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -#define SPI_SSPPCELLID1_OFFSET 0x00000ff4 -#define SPI_SSPPCELLID1_BITS 0x000000ff -#define SPI_SSPPCELLID1_RESET 0x000000f0 +#define SPI_SSPPCELLID1_OFFSET _u(0x00000ff4) +#define SPI_SSPPCELLID1_BITS _u(0x000000ff) +#define SPI_SSPPCELLID1_RESET _u(0x000000f0) // ----------------------------------------------------------------------------- // Field : SPI_SSPPCELLID1_SSPPCELLID1 // Description : These bits read back as 0xF0 -#define SPI_SSPPCELLID1_SSPPCELLID1_RESET 0xf0 -#define SPI_SSPPCELLID1_SSPPCELLID1_BITS 0x000000ff -#define SPI_SSPPCELLID1_SSPPCELLID1_MSB 7 -#define SPI_SSPPCELLID1_SSPPCELLID1_LSB 0 +#define SPI_SSPPCELLID1_SSPPCELLID1_RESET _u(0xf0) +#define SPI_SSPPCELLID1_SSPPCELLID1_BITS _u(0x000000ff) +#define SPI_SSPPCELLID1_SSPPCELLID1_MSB _u(7) +#define SPI_SSPPCELLID1_SSPPCELLID1_LSB _u(0) #define SPI_SSPPCELLID1_SSPPCELLID1_ACCESS "RO" // ============================================================================= // Register : SPI_SSPPCELLID2 // Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -#define SPI_SSPPCELLID2_OFFSET 0x00000ff8 -#define SPI_SSPPCELLID2_BITS 0x000000ff -#define SPI_SSPPCELLID2_RESET 0x00000005 +#define SPI_SSPPCELLID2_OFFSET _u(0x00000ff8) +#define SPI_SSPPCELLID2_BITS _u(0x000000ff) +#define SPI_SSPPCELLID2_RESET _u(0x00000005) // ----------------------------------------------------------------------------- // Field : SPI_SSPPCELLID2_SSPPCELLID2 // Description : These bits read back as 0x05 -#define SPI_SSPPCELLID2_SSPPCELLID2_RESET 0x05 -#define SPI_SSPPCELLID2_SSPPCELLID2_BITS 0x000000ff -#define SPI_SSPPCELLID2_SSPPCELLID2_MSB 7 -#define SPI_SSPPCELLID2_SSPPCELLID2_LSB 0 +#define SPI_SSPPCELLID2_SSPPCELLID2_RESET _u(0x05) +#define SPI_SSPPCELLID2_SSPPCELLID2_BITS _u(0x000000ff) +#define SPI_SSPPCELLID2_SSPPCELLID2_MSB _u(7) +#define SPI_SSPPCELLID2_SSPPCELLID2_LSB _u(0) #define SPI_SSPPCELLID2_SSPPCELLID2_ACCESS "RO" // ============================================================================= // Register : SPI_SSPPCELLID3 // Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -#define SPI_SSPPCELLID3_OFFSET 0x00000ffc -#define SPI_SSPPCELLID3_BITS 0x000000ff -#define SPI_SSPPCELLID3_RESET 0x000000b1 +#define SPI_SSPPCELLID3_OFFSET _u(0x00000ffc) +#define SPI_SSPPCELLID3_BITS _u(0x000000ff) +#define SPI_SSPPCELLID3_RESET _u(0x000000b1) // ----------------------------------------------------------------------------- // Field : SPI_SSPPCELLID3_SSPPCELLID3 // Description : These bits read back as 0xB1 -#define SPI_SSPPCELLID3_SSPPCELLID3_RESET 0xb1 -#define SPI_SSPPCELLID3_SSPPCELLID3_BITS 0x000000ff -#define SPI_SSPPCELLID3_SSPPCELLID3_MSB 7 -#define SPI_SSPPCELLID3_SSPPCELLID3_LSB 0 +#define SPI_SSPPCELLID3_SSPPCELLID3_RESET _u(0xb1) +#define SPI_SSPPCELLID3_SSPPCELLID3_BITS _u(0x000000ff) +#define SPI_SSPPCELLID3_SSPPCELLID3_MSB _u(7) +#define SPI_SSPPCELLID3_SSPPCELLID3_LSB _u(0) #define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_SPI_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/ssi.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/ssi.h index 04eeccaf5..67fddc0a4 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/ssi.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/ssi.h @@ -74,16 +74,16 @@ // ============================================================================= // Register : SSI_CTRLR0 // Description : Control register 0 -#define SSI_CTRLR0_OFFSET 0x00000000 -#define SSI_CTRLR0_BITS 0x017fffff -#define SSI_CTRLR0_RESET 0x00000000 +#define SSI_CTRLR0_OFFSET _u(0x00000000) +#define SSI_CTRLR0_BITS _u(0x017fffff) +#define SSI_CTRLR0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_SSTE // Description : Slave select toggle enable -#define SSI_CTRLR0_SSTE_RESET 0x0 -#define SSI_CTRLR0_SSTE_BITS 0x01000000 -#define SSI_CTRLR0_SSTE_MSB 24 -#define SSI_CTRLR0_SSTE_LSB 24 +#define SSI_CTRLR0_SSTE_RESET _u(0x0) +#define SSI_CTRLR0_SSTE_BITS _u(0x01000000) +#define SSI_CTRLR0_SSTE_MSB _u(24) +#define SSI_CTRLR0_SSTE_LSB _u(24) #define SSI_CTRLR0_SSTE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_SPI_FRF @@ -92,47 +92,47 @@ // full-duplex // 0x1 -> Dual-SPI frame format; two bits per SCK, half-duplex // 0x2 -> Quad-SPI frame format; four bits per SCK, half-duplex -#define SSI_CTRLR0_SPI_FRF_RESET 0x0 -#define SSI_CTRLR0_SPI_FRF_BITS 0x00600000 -#define SSI_CTRLR0_SPI_FRF_MSB 22 -#define SSI_CTRLR0_SPI_FRF_LSB 21 +#define SSI_CTRLR0_SPI_FRF_RESET _u(0x0) +#define SSI_CTRLR0_SPI_FRF_BITS _u(0x00600000) +#define SSI_CTRLR0_SPI_FRF_MSB _u(22) +#define SSI_CTRLR0_SPI_FRF_LSB _u(21) #define SSI_CTRLR0_SPI_FRF_ACCESS "RW" -#define SSI_CTRLR0_SPI_FRF_VALUE_STD 0x0 -#define SSI_CTRLR0_SPI_FRF_VALUE_DUAL 0x1 -#define SSI_CTRLR0_SPI_FRF_VALUE_QUAD 0x2 +#define SSI_CTRLR0_SPI_FRF_VALUE_STD _u(0x0) +#define SSI_CTRLR0_SPI_FRF_VALUE_DUAL _u(0x1) +#define SSI_CTRLR0_SPI_FRF_VALUE_QUAD _u(0x2) // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_DFS_32 // Description : Data frame size in 32b transfer mode // Value of n -> n+1 clocks per frame. -#define SSI_CTRLR0_DFS_32_RESET 0x00 -#define SSI_CTRLR0_DFS_32_BITS 0x001f0000 -#define SSI_CTRLR0_DFS_32_MSB 20 -#define SSI_CTRLR0_DFS_32_LSB 16 +#define SSI_CTRLR0_DFS_32_RESET _u(0x00) +#define SSI_CTRLR0_DFS_32_BITS _u(0x001f0000) +#define SSI_CTRLR0_DFS_32_MSB _u(20) +#define SSI_CTRLR0_DFS_32_LSB _u(16) #define SSI_CTRLR0_DFS_32_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_CFS // Description : Control frame size // Value of n -> n+1 clocks per frame. -#define SSI_CTRLR0_CFS_RESET 0x0 -#define SSI_CTRLR0_CFS_BITS 0x0000f000 -#define SSI_CTRLR0_CFS_MSB 15 -#define SSI_CTRLR0_CFS_LSB 12 +#define SSI_CTRLR0_CFS_RESET _u(0x0) +#define SSI_CTRLR0_CFS_BITS _u(0x0000f000) +#define SSI_CTRLR0_CFS_MSB _u(15) +#define SSI_CTRLR0_CFS_LSB _u(12) #define SSI_CTRLR0_CFS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_SRL // Description : Shift register loop (test mode) -#define SSI_CTRLR0_SRL_RESET 0x0 -#define SSI_CTRLR0_SRL_BITS 0x00000800 -#define SSI_CTRLR0_SRL_MSB 11 -#define SSI_CTRLR0_SRL_LSB 11 +#define SSI_CTRLR0_SRL_RESET _u(0x0) +#define SSI_CTRLR0_SRL_BITS _u(0x00000800) +#define SSI_CTRLR0_SRL_MSB _u(11) +#define SSI_CTRLR0_SRL_LSB _u(11) #define SSI_CTRLR0_SRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_SLV_OE // Description : Slave output enable -#define SSI_CTRLR0_SLV_OE_RESET 0x0 -#define SSI_CTRLR0_SLV_OE_BITS 0x00000400 -#define SSI_CTRLR0_SLV_OE_MSB 10 -#define SSI_CTRLR0_SLV_OE_LSB 10 +#define SSI_CTRLR0_SLV_OE_RESET _u(0x0) +#define SSI_CTRLR0_SLV_OE_BITS _u(0x00000400) +#define SSI_CTRLR0_SLV_OE_MSB _u(10) +#define SSI_CTRLR0_SLV_OE_LSB _u(10) #define SSI_CTRLR0_SLV_OE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_TMOD @@ -142,104 +142,104 @@ // 0x2 -> Receive only (not for FRF == 0, standard SPI mode) // 0x3 -> EEPROM read mode (TX then RX; RX starts after control // data TX'd) -#define SSI_CTRLR0_TMOD_RESET 0x0 -#define SSI_CTRLR0_TMOD_BITS 0x00000300 -#define SSI_CTRLR0_TMOD_MSB 9 -#define SSI_CTRLR0_TMOD_LSB 8 +#define SSI_CTRLR0_TMOD_RESET _u(0x0) +#define SSI_CTRLR0_TMOD_BITS _u(0x00000300) +#define SSI_CTRLR0_TMOD_MSB _u(9) +#define SSI_CTRLR0_TMOD_LSB _u(8) #define SSI_CTRLR0_TMOD_ACCESS "RW" -#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX 0x0 -#define SSI_CTRLR0_TMOD_VALUE_TX_ONLY 0x1 -#define SSI_CTRLR0_TMOD_VALUE_RX_ONLY 0x2 -#define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ 0x3 +#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX _u(0x0) +#define SSI_CTRLR0_TMOD_VALUE_TX_ONLY _u(0x1) +#define SSI_CTRLR0_TMOD_VALUE_RX_ONLY _u(0x2) +#define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ _u(0x3) // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_SCPOL // Description : Serial clock polarity -#define SSI_CTRLR0_SCPOL_RESET 0x0 -#define SSI_CTRLR0_SCPOL_BITS 0x00000080 -#define SSI_CTRLR0_SCPOL_MSB 7 -#define SSI_CTRLR0_SCPOL_LSB 7 +#define SSI_CTRLR0_SCPOL_RESET _u(0x0) +#define SSI_CTRLR0_SCPOL_BITS _u(0x00000080) +#define SSI_CTRLR0_SCPOL_MSB _u(7) +#define SSI_CTRLR0_SCPOL_LSB _u(7) #define SSI_CTRLR0_SCPOL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_SCPH // Description : Serial clock phase -#define SSI_CTRLR0_SCPH_RESET 0x0 -#define SSI_CTRLR0_SCPH_BITS 0x00000040 -#define SSI_CTRLR0_SCPH_MSB 6 -#define SSI_CTRLR0_SCPH_LSB 6 +#define SSI_CTRLR0_SCPH_RESET _u(0x0) +#define SSI_CTRLR0_SCPH_BITS _u(0x00000040) +#define SSI_CTRLR0_SCPH_MSB _u(6) +#define SSI_CTRLR0_SCPH_LSB _u(6) #define SSI_CTRLR0_SCPH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_FRF // Description : Frame format -#define SSI_CTRLR0_FRF_RESET 0x0 -#define SSI_CTRLR0_FRF_BITS 0x00000030 -#define SSI_CTRLR0_FRF_MSB 5 -#define SSI_CTRLR0_FRF_LSB 4 +#define SSI_CTRLR0_FRF_RESET _u(0x0) +#define SSI_CTRLR0_FRF_BITS _u(0x00000030) +#define SSI_CTRLR0_FRF_MSB _u(5) +#define SSI_CTRLR0_FRF_LSB _u(4) #define SSI_CTRLR0_FRF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_DFS // Description : Data frame size -#define SSI_CTRLR0_DFS_RESET 0x0 -#define SSI_CTRLR0_DFS_BITS 0x0000000f -#define SSI_CTRLR0_DFS_MSB 3 -#define SSI_CTRLR0_DFS_LSB 0 +#define SSI_CTRLR0_DFS_RESET _u(0x0) +#define SSI_CTRLR0_DFS_BITS _u(0x0000000f) +#define SSI_CTRLR0_DFS_MSB _u(3) +#define SSI_CTRLR0_DFS_LSB _u(0) #define SSI_CTRLR0_DFS_ACCESS "RW" // ============================================================================= // Register : SSI_CTRLR1 // Description : Master Control register 1 -#define SSI_CTRLR1_OFFSET 0x00000004 -#define SSI_CTRLR1_BITS 0x0000ffff -#define SSI_CTRLR1_RESET 0x00000000 +#define SSI_CTRLR1_OFFSET _u(0x00000004) +#define SSI_CTRLR1_BITS _u(0x0000ffff) +#define SSI_CTRLR1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_CTRLR1_NDF // Description : Number of data frames -#define SSI_CTRLR1_NDF_RESET 0x0000 -#define SSI_CTRLR1_NDF_BITS 0x0000ffff -#define SSI_CTRLR1_NDF_MSB 15 -#define SSI_CTRLR1_NDF_LSB 0 +#define SSI_CTRLR1_NDF_RESET _u(0x0000) +#define SSI_CTRLR1_NDF_BITS _u(0x0000ffff) +#define SSI_CTRLR1_NDF_MSB _u(15) +#define SSI_CTRLR1_NDF_LSB _u(0) #define SSI_CTRLR1_NDF_ACCESS "RW" // ============================================================================= // Register : SSI_SSIENR // Description : SSI Enable -#define SSI_SSIENR_OFFSET 0x00000008 -#define SSI_SSIENR_BITS 0x00000001 -#define SSI_SSIENR_RESET 0x00000000 +#define SSI_SSIENR_OFFSET _u(0x00000008) +#define SSI_SSIENR_BITS _u(0x00000001) +#define SSI_SSIENR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_SSIENR_SSI_EN // Description : SSI enable -#define SSI_SSIENR_SSI_EN_RESET 0x0 -#define SSI_SSIENR_SSI_EN_BITS 0x00000001 -#define SSI_SSIENR_SSI_EN_MSB 0 -#define SSI_SSIENR_SSI_EN_LSB 0 +#define SSI_SSIENR_SSI_EN_RESET _u(0x0) +#define SSI_SSIENR_SSI_EN_BITS _u(0x00000001) +#define SSI_SSIENR_SSI_EN_MSB _u(0) +#define SSI_SSIENR_SSI_EN_LSB _u(0) #define SSI_SSIENR_SSI_EN_ACCESS "RW" // ============================================================================= // Register : SSI_MWCR // Description : Microwire Control -#define SSI_MWCR_OFFSET 0x0000000c -#define SSI_MWCR_BITS 0x00000007 -#define SSI_MWCR_RESET 0x00000000 +#define SSI_MWCR_OFFSET _u(0x0000000c) +#define SSI_MWCR_BITS _u(0x00000007) +#define SSI_MWCR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_MWCR_MHS // Description : Microwire handshaking -#define SSI_MWCR_MHS_RESET 0x0 -#define SSI_MWCR_MHS_BITS 0x00000004 -#define SSI_MWCR_MHS_MSB 2 -#define SSI_MWCR_MHS_LSB 2 +#define SSI_MWCR_MHS_RESET _u(0x0) +#define SSI_MWCR_MHS_BITS _u(0x00000004) +#define SSI_MWCR_MHS_MSB _u(2) +#define SSI_MWCR_MHS_LSB _u(2) #define SSI_MWCR_MHS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_MWCR_MDD // Description : Microwire control -#define SSI_MWCR_MDD_RESET 0x0 -#define SSI_MWCR_MDD_BITS 0x00000002 -#define SSI_MWCR_MDD_MSB 1 -#define SSI_MWCR_MDD_LSB 1 +#define SSI_MWCR_MDD_RESET _u(0x0) +#define SSI_MWCR_MDD_BITS _u(0x00000002) +#define SSI_MWCR_MDD_MSB _u(1) +#define SSI_MWCR_MDD_LSB _u(1) #define SSI_MWCR_MDD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_MWCR_MWMOD // Description : Microwire transfer mode -#define SSI_MWCR_MWMOD_RESET 0x0 -#define SSI_MWCR_MWMOD_BITS 0x00000001 -#define SSI_MWCR_MWMOD_MSB 0 -#define SSI_MWCR_MWMOD_LSB 0 +#define SSI_MWCR_MWMOD_RESET _u(0x0) +#define SSI_MWCR_MWMOD_BITS _u(0x00000001) +#define SSI_MWCR_MWMOD_MSB _u(0) +#define SSI_MWCR_MWMOD_LSB _u(0) #define SSI_MWCR_MWMOD_ACCESS "RW" // ============================================================================= // Register : SSI_SER @@ -247,509 +247,509 @@ // For each bit: // 0 -> slave not selected // 1 -> slave selected -#define SSI_SER_OFFSET 0x00000010 -#define SSI_SER_BITS 0x00000001 -#define SSI_SER_RESET 0x00000000 -#define SSI_SER_MSB 0 -#define SSI_SER_LSB 0 +#define SSI_SER_OFFSET _u(0x00000010) +#define SSI_SER_BITS _u(0x00000001) +#define SSI_SER_RESET _u(0x00000000) +#define SSI_SER_MSB _u(0) +#define SSI_SER_LSB _u(0) #define SSI_SER_ACCESS "RW" // ============================================================================= // Register : SSI_BAUDR // Description : Baud rate -#define SSI_BAUDR_OFFSET 0x00000014 -#define SSI_BAUDR_BITS 0x0000ffff -#define SSI_BAUDR_RESET 0x00000000 +#define SSI_BAUDR_OFFSET _u(0x00000014) +#define SSI_BAUDR_BITS _u(0x0000ffff) +#define SSI_BAUDR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_BAUDR_SCKDV // Description : SSI clock divider -#define SSI_BAUDR_SCKDV_RESET 0x0000 -#define SSI_BAUDR_SCKDV_BITS 0x0000ffff -#define SSI_BAUDR_SCKDV_MSB 15 -#define SSI_BAUDR_SCKDV_LSB 0 +#define SSI_BAUDR_SCKDV_RESET _u(0x0000) +#define SSI_BAUDR_SCKDV_BITS _u(0x0000ffff) +#define SSI_BAUDR_SCKDV_MSB _u(15) +#define SSI_BAUDR_SCKDV_LSB _u(0) #define SSI_BAUDR_SCKDV_ACCESS "RW" // ============================================================================= // Register : SSI_TXFTLR // Description : TX FIFO threshold level -#define SSI_TXFTLR_OFFSET 0x00000018 -#define SSI_TXFTLR_BITS 0x000000ff -#define SSI_TXFTLR_RESET 0x00000000 +#define SSI_TXFTLR_OFFSET _u(0x00000018) +#define SSI_TXFTLR_BITS _u(0x000000ff) +#define SSI_TXFTLR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_TXFTLR_TFT // Description : Transmit FIFO threshold -#define SSI_TXFTLR_TFT_RESET 0x00 -#define SSI_TXFTLR_TFT_BITS 0x000000ff -#define SSI_TXFTLR_TFT_MSB 7 -#define SSI_TXFTLR_TFT_LSB 0 +#define SSI_TXFTLR_TFT_RESET _u(0x00) +#define SSI_TXFTLR_TFT_BITS _u(0x000000ff) +#define SSI_TXFTLR_TFT_MSB _u(7) +#define SSI_TXFTLR_TFT_LSB _u(0) #define SSI_TXFTLR_TFT_ACCESS "RW" // ============================================================================= // Register : SSI_RXFTLR // Description : RX FIFO threshold level -#define SSI_RXFTLR_OFFSET 0x0000001c -#define SSI_RXFTLR_BITS 0x000000ff -#define SSI_RXFTLR_RESET 0x00000000 +#define SSI_RXFTLR_OFFSET _u(0x0000001c) +#define SSI_RXFTLR_BITS _u(0x000000ff) +#define SSI_RXFTLR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_RXFTLR_RFT // Description : Receive FIFO threshold -#define SSI_RXFTLR_RFT_RESET 0x00 -#define SSI_RXFTLR_RFT_BITS 0x000000ff -#define SSI_RXFTLR_RFT_MSB 7 -#define SSI_RXFTLR_RFT_LSB 0 +#define SSI_RXFTLR_RFT_RESET _u(0x00) +#define SSI_RXFTLR_RFT_BITS _u(0x000000ff) +#define SSI_RXFTLR_RFT_MSB _u(7) +#define SSI_RXFTLR_RFT_LSB _u(0) #define SSI_RXFTLR_RFT_ACCESS "RW" // ============================================================================= // Register : SSI_TXFLR // Description : TX FIFO level -#define SSI_TXFLR_OFFSET 0x00000020 -#define SSI_TXFLR_BITS 0x000000ff -#define SSI_TXFLR_RESET 0x00000000 +#define SSI_TXFLR_OFFSET _u(0x00000020) +#define SSI_TXFLR_BITS _u(0x000000ff) +#define SSI_TXFLR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_TXFLR_TFTFL // Description : Transmit FIFO level -#define SSI_TXFLR_TFTFL_RESET 0x00 -#define SSI_TXFLR_TFTFL_BITS 0x000000ff -#define SSI_TXFLR_TFTFL_MSB 7 -#define SSI_TXFLR_TFTFL_LSB 0 +#define SSI_TXFLR_TFTFL_RESET _u(0x00) +#define SSI_TXFLR_TFTFL_BITS _u(0x000000ff) +#define SSI_TXFLR_TFTFL_MSB _u(7) +#define SSI_TXFLR_TFTFL_LSB _u(0) #define SSI_TXFLR_TFTFL_ACCESS "RO" // ============================================================================= // Register : SSI_RXFLR // Description : RX FIFO level -#define SSI_RXFLR_OFFSET 0x00000024 -#define SSI_RXFLR_BITS 0x000000ff -#define SSI_RXFLR_RESET 0x00000000 +#define SSI_RXFLR_OFFSET _u(0x00000024) +#define SSI_RXFLR_BITS _u(0x000000ff) +#define SSI_RXFLR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_RXFLR_RXTFL // Description : Receive FIFO level -#define SSI_RXFLR_RXTFL_RESET 0x00 -#define SSI_RXFLR_RXTFL_BITS 0x000000ff -#define SSI_RXFLR_RXTFL_MSB 7 -#define SSI_RXFLR_RXTFL_LSB 0 +#define SSI_RXFLR_RXTFL_RESET _u(0x00) +#define SSI_RXFLR_RXTFL_BITS _u(0x000000ff) +#define SSI_RXFLR_RXTFL_MSB _u(7) +#define SSI_RXFLR_RXTFL_LSB _u(0) #define SSI_RXFLR_RXTFL_ACCESS "RO" // ============================================================================= // Register : SSI_SR // Description : Status register -#define SSI_SR_OFFSET 0x00000028 -#define SSI_SR_BITS 0x0000007f -#define SSI_SR_RESET 0x00000000 +#define SSI_SR_OFFSET _u(0x00000028) +#define SSI_SR_BITS _u(0x0000007f) +#define SSI_SR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_SR_DCOL // Description : Data collision error -#define SSI_SR_DCOL_RESET 0x0 -#define SSI_SR_DCOL_BITS 0x00000040 -#define SSI_SR_DCOL_MSB 6 -#define SSI_SR_DCOL_LSB 6 +#define SSI_SR_DCOL_RESET _u(0x0) +#define SSI_SR_DCOL_BITS _u(0x00000040) +#define SSI_SR_DCOL_MSB _u(6) +#define SSI_SR_DCOL_LSB _u(6) #define SSI_SR_DCOL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_SR_TXE // Description : Transmission error -#define SSI_SR_TXE_RESET 0x0 -#define SSI_SR_TXE_BITS 0x00000020 -#define SSI_SR_TXE_MSB 5 -#define SSI_SR_TXE_LSB 5 +#define SSI_SR_TXE_RESET _u(0x0) +#define SSI_SR_TXE_BITS _u(0x00000020) +#define SSI_SR_TXE_MSB _u(5) +#define SSI_SR_TXE_LSB _u(5) #define SSI_SR_TXE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_SR_RFF // Description : Receive FIFO full -#define SSI_SR_RFF_RESET 0x0 -#define SSI_SR_RFF_BITS 0x00000010 -#define SSI_SR_RFF_MSB 4 -#define SSI_SR_RFF_LSB 4 +#define SSI_SR_RFF_RESET _u(0x0) +#define SSI_SR_RFF_BITS _u(0x00000010) +#define SSI_SR_RFF_MSB _u(4) +#define SSI_SR_RFF_LSB _u(4) #define SSI_SR_RFF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_SR_RFNE // Description : Receive FIFO not empty -#define SSI_SR_RFNE_RESET 0x0 -#define SSI_SR_RFNE_BITS 0x00000008 -#define SSI_SR_RFNE_MSB 3 -#define SSI_SR_RFNE_LSB 3 +#define SSI_SR_RFNE_RESET _u(0x0) +#define SSI_SR_RFNE_BITS _u(0x00000008) +#define SSI_SR_RFNE_MSB _u(3) +#define SSI_SR_RFNE_LSB _u(3) #define SSI_SR_RFNE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_SR_TFE // Description : Transmit FIFO empty -#define SSI_SR_TFE_RESET 0x0 -#define SSI_SR_TFE_BITS 0x00000004 -#define SSI_SR_TFE_MSB 2 -#define SSI_SR_TFE_LSB 2 +#define SSI_SR_TFE_RESET _u(0x0) +#define SSI_SR_TFE_BITS _u(0x00000004) +#define SSI_SR_TFE_MSB _u(2) +#define SSI_SR_TFE_LSB _u(2) #define SSI_SR_TFE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_SR_TFNF // Description : Transmit FIFO not full -#define SSI_SR_TFNF_RESET 0x0 -#define SSI_SR_TFNF_BITS 0x00000002 -#define SSI_SR_TFNF_MSB 1 -#define SSI_SR_TFNF_LSB 1 +#define SSI_SR_TFNF_RESET _u(0x0) +#define SSI_SR_TFNF_BITS _u(0x00000002) +#define SSI_SR_TFNF_MSB _u(1) +#define SSI_SR_TFNF_LSB _u(1) #define SSI_SR_TFNF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_SR_BUSY // Description : SSI busy flag -#define SSI_SR_BUSY_RESET 0x0 -#define SSI_SR_BUSY_BITS 0x00000001 -#define SSI_SR_BUSY_MSB 0 -#define SSI_SR_BUSY_LSB 0 +#define SSI_SR_BUSY_RESET _u(0x0) +#define SSI_SR_BUSY_BITS _u(0x00000001) +#define SSI_SR_BUSY_MSB _u(0) +#define SSI_SR_BUSY_LSB _u(0) #define SSI_SR_BUSY_ACCESS "RO" // ============================================================================= // Register : SSI_IMR // Description : Interrupt mask -#define SSI_IMR_OFFSET 0x0000002c -#define SSI_IMR_BITS 0x0000003f -#define SSI_IMR_RESET 0x00000000 +#define SSI_IMR_OFFSET _u(0x0000002c) +#define SSI_IMR_BITS _u(0x0000003f) +#define SSI_IMR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_IMR_MSTIM // Description : Multi-master contention interrupt mask -#define SSI_IMR_MSTIM_RESET 0x0 -#define SSI_IMR_MSTIM_BITS 0x00000020 -#define SSI_IMR_MSTIM_MSB 5 -#define SSI_IMR_MSTIM_LSB 5 +#define SSI_IMR_MSTIM_RESET _u(0x0) +#define SSI_IMR_MSTIM_BITS _u(0x00000020) +#define SSI_IMR_MSTIM_MSB _u(5) +#define SSI_IMR_MSTIM_LSB _u(5) #define SSI_IMR_MSTIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_IMR_RXFIM // Description : Receive FIFO full interrupt mask -#define SSI_IMR_RXFIM_RESET 0x0 -#define SSI_IMR_RXFIM_BITS 0x00000010 -#define SSI_IMR_RXFIM_MSB 4 -#define SSI_IMR_RXFIM_LSB 4 +#define SSI_IMR_RXFIM_RESET _u(0x0) +#define SSI_IMR_RXFIM_BITS _u(0x00000010) +#define SSI_IMR_RXFIM_MSB _u(4) +#define SSI_IMR_RXFIM_LSB _u(4) #define SSI_IMR_RXFIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_IMR_RXOIM // Description : Receive FIFO overflow interrupt mask -#define SSI_IMR_RXOIM_RESET 0x0 -#define SSI_IMR_RXOIM_BITS 0x00000008 -#define SSI_IMR_RXOIM_MSB 3 -#define SSI_IMR_RXOIM_LSB 3 +#define SSI_IMR_RXOIM_RESET _u(0x0) +#define SSI_IMR_RXOIM_BITS _u(0x00000008) +#define SSI_IMR_RXOIM_MSB _u(3) +#define SSI_IMR_RXOIM_LSB _u(3) #define SSI_IMR_RXOIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_IMR_RXUIM // Description : Receive FIFO underflow interrupt mask -#define SSI_IMR_RXUIM_RESET 0x0 -#define SSI_IMR_RXUIM_BITS 0x00000004 -#define SSI_IMR_RXUIM_MSB 2 -#define SSI_IMR_RXUIM_LSB 2 +#define SSI_IMR_RXUIM_RESET _u(0x0) +#define SSI_IMR_RXUIM_BITS _u(0x00000004) +#define SSI_IMR_RXUIM_MSB _u(2) +#define SSI_IMR_RXUIM_LSB _u(2) #define SSI_IMR_RXUIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_IMR_TXOIM // Description : Transmit FIFO overflow interrupt mask -#define SSI_IMR_TXOIM_RESET 0x0 -#define SSI_IMR_TXOIM_BITS 0x00000002 -#define SSI_IMR_TXOIM_MSB 1 -#define SSI_IMR_TXOIM_LSB 1 +#define SSI_IMR_TXOIM_RESET _u(0x0) +#define SSI_IMR_TXOIM_BITS _u(0x00000002) +#define SSI_IMR_TXOIM_MSB _u(1) +#define SSI_IMR_TXOIM_LSB _u(1) #define SSI_IMR_TXOIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_IMR_TXEIM // Description : Transmit FIFO empty interrupt mask -#define SSI_IMR_TXEIM_RESET 0x0 -#define SSI_IMR_TXEIM_BITS 0x00000001 -#define SSI_IMR_TXEIM_MSB 0 -#define SSI_IMR_TXEIM_LSB 0 +#define SSI_IMR_TXEIM_RESET _u(0x0) +#define SSI_IMR_TXEIM_BITS _u(0x00000001) +#define SSI_IMR_TXEIM_MSB _u(0) +#define SSI_IMR_TXEIM_LSB _u(0) #define SSI_IMR_TXEIM_ACCESS "RW" // ============================================================================= // Register : SSI_ISR // Description : Interrupt status -#define SSI_ISR_OFFSET 0x00000030 -#define SSI_ISR_BITS 0x0000003f -#define SSI_ISR_RESET 0x00000000 +#define SSI_ISR_OFFSET _u(0x00000030) +#define SSI_ISR_BITS _u(0x0000003f) +#define SSI_ISR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_ISR_MSTIS // Description : Multi-master contention interrupt status -#define SSI_ISR_MSTIS_RESET 0x0 -#define SSI_ISR_MSTIS_BITS 0x00000020 -#define SSI_ISR_MSTIS_MSB 5 -#define SSI_ISR_MSTIS_LSB 5 +#define SSI_ISR_MSTIS_RESET _u(0x0) +#define SSI_ISR_MSTIS_BITS _u(0x00000020) +#define SSI_ISR_MSTIS_MSB _u(5) +#define SSI_ISR_MSTIS_LSB _u(5) #define SSI_ISR_MSTIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_ISR_RXFIS // Description : Receive FIFO full interrupt status -#define SSI_ISR_RXFIS_RESET 0x0 -#define SSI_ISR_RXFIS_BITS 0x00000010 -#define SSI_ISR_RXFIS_MSB 4 -#define SSI_ISR_RXFIS_LSB 4 +#define SSI_ISR_RXFIS_RESET _u(0x0) +#define SSI_ISR_RXFIS_BITS _u(0x00000010) +#define SSI_ISR_RXFIS_MSB _u(4) +#define SSI_ISR_RXFIS_LSB _u(4) #define SSI_ISR_RXFIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_ISR_RXOIS // Description : Receive FIFO overflow interrupt status -#define SSI_ISR_RXOIS_RESET 0x0 -#define SSI_ISR_RXOIS_BITS 0x00000008 -#define SSI_ISR_RXOIS_MSB 3 -#define SSI_ISR_RXOIS_LSB 3 +#define SSI_ISR_RXOIS_RESET _u(0x0) +#define SSI_ISR_RXOIS_BITS _u(0x00000008) +#define SSI_ISR_RXOIS_MSB _u(3) +#define SSI_ISR_RXOIS_LSB _u(3) #define SSI_ISR_RXOIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_ISR_RXUIS // Description : Receive FIFO underflow interrupt status -#define SSI_ISR_RXUIS_RESET 0x0 -#define SSI_ISR_RXUIS_BITS 0x00000004 -#define SSI_ISR_RXUIS_MSB 2 -#define SSI_ISR_RXUIS_LSB 2 +#define SSI_ISR_RXUIS_RESET _u(0x0) +#define SSI_ISR_RXUIS_BITS _u(0x00000004) +#define SSI_ISR_RXUIS_MSB _u(2) +#define SSI_ISR_RXUIS_LSB _u(2) #define SSI_ISR_RXUIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_ISR_TXOIS // Description : Transmit FIFO overflow interrupt status -#define SSI_ISR_TXOIS_RESET 0x0 -#define SSI_ISR_TXOIS_BITS 0x00000002 -#define SSI_ISR_TXOIS_MSB 1 -#define SSI_ISR_TXOIS_LSB 1 +#define SSI_ISR_TXOIS_RESET _u(0x0) +#define SSI_ISR_TXOIS_BITS _u(0x00000002) +#define SSI_ISR_TXOIS_MSB _u(1) +#define SSI_ISR_TXOIS_LSB _u(1) #define SSI_ISR_TXOIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_ISR_TXEIS // Description : Transmit FIFO empty interrupt status -#define SSI_ISR_TXEIS_RESET 0x0 -#define SSI_ISR_TXEIS_BITS 0x00000001 -#define SSI_ISR_TXEIS_MSB 0 -#define SSI_ISR_TXEIS_LSB 0 +#define SSI_ISR_TXEIS_RESET _u(0x0) +#define SSI_ISR_TXEIS_BITS _u(0x00000001) +#define SSI_ISR_TXEIS_MSB _u(0) +#define SSI_ISR_TXEIS_LSB _u(0) #define SSI_ISR_TXEIS_ACCESS "RO" // ============================================================================= // Register : SSI_RISR // Description : Raw interrupt status -#define SSI_RISR_OFFSET 0x00000034 -#define SSI_RISR_BITS 0x0000003f -#define SSI_RISR_RESET 0x00000000 +#define SSI_RISR_OFFSET _u(0x00000034) +#define SSI_RISR_BITS _u(0x0000003f) +#define SSI_RISR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_RISR_MSTIR // Description : Multi-master contention raw interrupt status -#define SSI_RISR_MSTIR_RESET 0x0 -#define SSI_RISR_MSTIR_BITS 0x00000020 -#define SSI_RISR_MSTIR_MSB 5 -#define SSI_RISR_MSTIR_LSB 5 +#define SSI_RISR_MSTIR_RESET _u(0x0) +#define SSI_RISR_MSTIR_BITS _u(0x00000020) +#define SSI_RISR_MSTIR_MSB _u(5) +#define SSI_RISR_MSTIR_LSB _u(5) #define SSI_RISR_MSTIR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_RISR_RXFIR // Description : Receive FIFO full raw interrupt status -#define SSI_RISR_RXFIR_RESET 0x0 -#define SSI_RISR_RXFIR_BITS 0x00000010 -#define SSI_RISR_RXFIR_MSB 4 -#define SSI_RISR_RXFIR_LSB 4 +#define SSI_RISR_RXFIR_RESET _u(0x0) +#define SSI_RISR_RXFIR_BITS _u(0x00000010) +#define SSI_RISR_RXFIR_MSB _u(4) +#define SSI_RISR_RXFIR_LSB _u(4) #define SSI_RISR_RXFIR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_RISR_RXOIR // Description : Receive FIFO overflow raw interrupt status -#define SSI_RISR_RXOIR_RESET 0x0 -#define SSI_RISR_RXOIR_BITS 0x00000008 -#define SSI_RISR_RXOIR_MSB 3 -#define SSI_RISR_RXOIR_LSB 3 +#define SSI_RISR_RXOIR_RESET _u(0x0) +#define SSI_RISR_RXOIR_BITS _u(0x00000008) +#define SSI_RISR_RXOIR_MSB _u(3) +#define SSI_RISR_RXOIR_LSB _u(3) #define SSI_RISR_RXOIR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_RISR_RXUIR // Description : Receive FIFO underflow raw interrupt status -#define SSI_RISR_RXUIR_RESET 0x0 -#define SSI_RISR_RXUIR_BITS 0x00000004 -#define SSI_RISR_RXUIR_MSB 2 -#define SSI_RISR_RXUIR_LSB 2 +#define SSI_RISR_RXUIR_RESET _u(0x0) +#define SSI_RISR_RXUIR_BITS _u(0x00000004) +#define SSI_RISR_RXUIR_MSB _u(2) +#define SSI_RISR_RXUIR_LSB _u(2) #define SSI_RISR_RXUIR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_RISR_TXOIR // Description : Transmit FIFO overflow raw interrupt status -#define SSI_RISR_TXOIR_RESET 0x0 -#define SSI_RISR_TXOIR_BITS 0x00000002 -#define SSI_RISR_TXOIR_MSB 1 -#define SSI_RISR_TXOIR_LSB 1 +#define SSI_RISR_TXOIR_RESET _u(0x0) +#define SSI_RISR_TXOIR_BITS _u(0x00000002) +#define SSI_RISR_TXOIR_MSB _u(1) +#define SSI_RISR_TXOIR_LSB _u(1) #define SSI_RISR_TXOIR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SSI_RISR_TXEIR // Description : Transmit FIFO empty raw interrupt status -#define SSI_RISR_TXEIR_RESET 0x0 -#define SSI_RISR_TXEIR_BITS 0x00000001 -#define SSI_RISR_TXEIR_MSB 0 -#define SSI_RISR_TXEIR_LSB 0 +#define SSI_RISR_TXEIR_RESET _u(0x0) +#define SSI_RISR_TXEIR_BITS _u(0x00000001) +#define SSI_RISR_TXEIR_MSB _u(0) +#define SSI_RISR_TXEIR_LSB _u(0) #define SSI_RISR_TXEIR_ACCESS "RO" // ============================================================================= // Register : SSI_TXOICR // Description : TX FIFO overflow interrupt clear // Clear-on-read transmit FIFO overflow interrupt -#define SSI_TXOICR_OFFSET 0x00000038 -#define SSI_TXOICR_BITS 0x00000001 -#define SSI_TXOICR_RESET 0x00000000 -#define SSI_TXOICR_MSB 0 -#define SSI_TXOICR_LSB 0 +#define SSI_TXOICR_OFFSET _u(0x00000038) +#define SSI_TXOICR_BITS _u(0x00000001) +#define SSI_TXOICR_RESET _u(0x00000000) +#define SSI_TXOICR_MSB _u(0) +#define SSI_TXOICR_LSB _u(0) #define SSI_TXOICR_ACCESS "RO" // ============================================================================= // Register : SSI_RXOICR // Description : RX FIFO overflow interrupt clear // Clear-on-read receive FIFO overflow interrupt -#define SSI_RXOICR_OFFSET 0x0000003c -#define SSI_RXOICR_BITS 0x00000001 -#define SSI_RXOICR_RESET 0x00000000 -#define SSI_RXOICR_MSB 0 -#define SSI_RXOICR_LSB 0 +#define SSI_RXOICR_OFFSET _u(0x0000003c) +#define SSI_RXOICR_BITS _u(0x00000001) +#define SSI_RXOICR_RESET _u(0x00000000) +#define SSI_RXOICR_MSB _u(0) +#define SSI_RXOICR_LSB _u(0) #define SSI_RXOICR_ACCESS "RO" // ============================================================================= // Register : SSI_RXUICR // Description : RX FIFO underflow interrupt clear // Clear-on-read receive FIFO underflow interrupt -#define SSI_RXUICR_OFFSET 0x00000040 -#define SSI_RXUICR_BITS 0x00000001 -#define SSI_RXUICR_RESET 0x00000000 -#define SSI_RXUICR_MSB 0 -#define SSI_RXUICR_LSB 0 +#define SSI_RXUICR_OFFSET _u(0x00000040) +#define SSI_RXUICR_BITS _u(0x00000001) +#define SSI_RXUICR_RESET _u(0x00000000) +#define SSI_RXUICR_MSB _u(0) +#define SSI_RXUICR_LSB _u(0) #define SSI_RXUICR_ACCESS "RO" // ============================================================================= // Register : SSI_MSTICR // Description : Multi-master interrupt clear // Clear-on-read multi-master contention interrupt -#define SSI_MSTICR_OFFSET 0x00000044 -#define SSI_MSTICR_BITS 0x00000001 -#define SSI_MSTICR_RESET 0x00000000 -#define SSI_MSTICR_MSB 0 -#define SSI_MSTICR_LSB 0 +#define SSI_MSTICR_OFFSET _u(0x00000044) +#define SSI_MSTICR_BITS _u(0x00000001) +#define SSI_MSTICR_RESET _u(0x00000000) +#define SSI_MSTICR_MSB _u(0) +#define SSI_MSTICR_LSB _u(0) #define SSI_MSTICR_ACCESS "RO" // ============================================================================= // Register : SSI_ICR // Description : Interrupt clear // Clear-on-read all active interrupts -#define SSI_ICR_OFFSET 0x00000048 -#define SSI_ICR_BITS 0x00000001 -#define SSI_ICR_RESET 0x00000000 -#define SSI_ICR_MSB 0 -#define SSI_ICR_LSB 0 +#define SSI_ICR_OFFSET _u(0x00000048) +#define SSI_ICR_BITS _u(0x00000001) +#define SSI_ICR_RESET _u(0x00000000) +#define SSI_ICR_MSB _u(0) +#define SSI_ICR_LSB _u(0) #define SSI_ICR_ACCESS "RO" // ============================================================================= // Register : SSI_DMACR // Description : DMA control -#define SSI_DMACR_OFFSET 0x0000004c -#define SSI_DMACR_BITS 0x00000003 -#define SSI_DMACR_RESET 0x00000000 +#define SSI_DMACR_OFFSET _u(0x0000004c) +#define SSI_DMACR_BITS _u(0x00000003) +#define SSI_DMACR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_DMACR_TDMAE // Description : Transmit DMA enable -#define SSI_DMACR_TDMAE_RESET 0x0 -#define SSI_DMACR_TDMAE_BITS 0x00000002 -#define SSI_DMACR_TDMAE_MSB 1 -#define SSI_DMACR_TDMAE_LSB 1 +#define SSI_DMACR_TDMAE_RESET _u(0x0) +#define SSI_DMACR_TDMAE_BITS _u(0x00000002) +#define SSI_DMACR_TDMAE_MSB _u(1) +#define SSI_DMACR_TDMAE_LSB _u(1) #define SSI_DMACR_TDMAE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_DMACR_RDMAE // Description : Receive DMA enable -#define SSI_DMACR_RDMAE_RESET 0x0 -#define SSI_DMACR_RDMAE_BITS 0x00000001 -#define SSI_DMACR_RDMAE_MSB 0 -#define SSI_DMACR_RDMAE_LSB 0 +#define SSI_DMACR_RDMAE_RESET _u(0x0) +#define SSI_DMACR_RDMAE_BITS _u(0x00000001) +#define SSI_DMACR_RDMAE_MSB _u(0) +#define SSI_DMACR_RDMAE_LSB _u(0) #define SSI_DMACR_RDMAE_ACCESS "RW" // ============================================================================= // Register : SSI_DMATDLR // Description : DMA TX data level -#define SSI_DMATDLR_OFFSET 0x00000050 -#define SSI_DMATDLR_BITS 0x000000ff -#define SSI_DMATDLR_RESET 0x00000000 +#define SSI_DMATDLR_OFFSET _u(0x00000050) +#define SSI_DMATDLR_BITS _u(0x000000ff) +#define SSI_DMATDLR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_DMATDLR_DMATDL // Description : Transmit data watermark level -#define SSI_DMATDLR_DMATDL_RESET 0x00 -#define SSI_DMATDLR_DMATDL_BITS 0x000000ff -#define SSI_DMATDLR_DMATDL_MSB 7 -#define SSI_DMATDLR_DMATDL_LSB 0 +#define SSI_DMATDLR_DMATDL_RESET _u(0x00) +#define SSI_DMATDLR_DMATDL_BITS _u(0x000000ff) +#define SSI_DMATDLR_DMATDL_MSB _u(7) +#define SSI_DMATDLR_DMATDL_LSB _u(0) #define SSI_DMATDLR_DMATDL_ACCESS "RW" // ============================================================================= // Register : SSI_DMARDLR // Description : DMA RX data level -#define SSI_DMARDLR_OFFSET 0x00000054 -#define SSI_DMARDLR_BITS 0x000000ff -#define SSI_DMARDLR_RESET 0x00000000 +#define SSI_DMARDLR_OFFSET _u(0x00000054) +#define SSI_DMARDLR_BITS _u(0x000000ff) +#define SSI_DMARDLR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_DMARDLR_DMARDL // Description : Receive data watermark level (DMARDLR+1) -#define SSI_DMARDLR_DMARDL_RESET 0x00 -#define SSI_DMARDLR_DMARDL_BITS 0x000000ff -#define SSI_DMARDLR_DMARDL_MSB 7 -#define SSI_DMARDLR_DMARDL_LSB 0 +#define SSI_DMARDLR_DMARDL_RESET _u(0x00) +#define SSI_DMARDLR_DMARDL_BITS _u(0x000000ff) +#define SSI_DMARDLR_DMARDL_MSB _u(7) +#define SSI_DMARDLR_DMARDL_LSB _u(0) #define SSI_DMARDLR_DMARDL_ACCESS "RW" // ============================================================================= // Register : SSI_IDR // Description : Identification register -#define SSI_IDR_OFFSET 0x00000058 -#define SSI_IDR_BITS 0xffffffff -#define SSI_IDR_RESET 0x51535049 +#define SSI_IDR_OFFSET _u(0x00000058) +#define SSI_IDR_BITS _u(0xffffffff) +#define SSI_IDR_RESET _u(0x51535049) // ----------------------------------------------------------------------------- // Field : SSI_IDR_IDCODE // Description : Peripheral dentification code -#define SSI_IDR_IDCODE_RESET 0x51535049 -#define SSI_IDR_IDCODE_BITS 0xffffffff -#define SSI_IDR_IDCODE_MSB 31 -#define SSI_IDR_IDCODE_LSB 0 +#define SSI_IDR_IDCODE_RESET _u(0x51535049) +#define SSI_IDR_IDCODE_BITS _u(0xffffffff) +#define SSI_IDR_IDCODE_MSB _u(31) +#define SSI_IDR_IDCODE_LSB _u(0) #define SSI_IDR_IDCODE_ACCESS "RO" // ============================================================================= // Register : SSI_SSI_VERSION_ID // Description : Version ID -#define SSI_SSI_VERSION_ID_OFFSET 0x0000005c -#define SSI_SSI_VERSION_ID_BITS 0xffffffff -#define SSI_SSI_VERSION_ID_RESET 0x3430312a +#define SSI_SSI_VERSION_ID_OFFSET _u(0x0000005c) +#define SSI_SSI_VERSION_ID_BITS _u(0xffffffff) +#define SSI_SSI_VERSION_ID_RESET _u(0x3430312a) // ----------------------------------------------------------------------------- // Field : SSI_SSI_VERSION_ID_SSI_COMP_VERSION // Description : SNPS component version (format X.YY) -#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_RESET 0x3430312a -#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_BITS 0xffffffff -#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_MSB 31 -#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_LSB 0 +#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_RESET _u(0x3430312a) +#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_BITS _u(0xffffffff) +#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_MSB _u(31) +#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_LSB _u(0) #define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_ACCESS "RO" // ============================================================================= // Register : SSI_DR0 // Description : Data Register 0 (of 36) -#define SSI_DR0_OFFSET 0x00000060 -#define SSI_DR0_BITS 0xffffffff -#define SSI_DR0_RESET 0x00000000 +#define SSI_DR0_OFFSET _u(0x00000060) +#define SSI_DR0_BITS _u(0xffffffff) +#define SSI_DR0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_DR0_DR // Description : First data register of 36 -#define SSI_DR0_DR_RESET 0x00000000 -#define SSI_DR0_DR_BITS 0xffffffff -#define SSI_DR0_DR_MSB 31 -#define SSI_DR0_DR_LSB 0 +#define SSI_DR0_DR_RESET _u(0x00000000) +#define SSI_DR0_DR_BITS _u(0xffffffff) +#define SSI_DR0_DR_MSB _u(31) +#define SSI_DR0_DR_LSB _u(0) #define SSI_DR0_DR_ACCESS "RW" // ============================================================================= // Register : SSI_RX_SAMPLE_DLY // Description : RX sample delay -#define SSI_RX_SAMPLE_DLY_OFFSET 0x000000f0 -#define SSI_RX_SAMPLE_DLY_BITS 0x000000ff -#define SSI_RX_SAMPLE_DLY_RESET 0x00000000 +#define SSI_RX_SAMPLE_DLY_OFFSET _u(0x000000f0) +#define SSI_RX_SAMPLE_DLY_BITS _u(0x000000ff) +#define SSI_RX_SAMPLE_DLY_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_RX_SAMPLE_DLY_RSD // Description : RXD sample delay (in SCLK cycles) -#define SSI_RX_SAMPLE_DLY_RSD_RESET 0x00 -#define SSI_RX_SAMPLE_DLY_RSD_BITS 0x000000ff -#define SSI_RX_SAMPLE_DLY_RSD_MSB 7 -#define SSI_RX_SAMPLE_DLY_RSD_LSB 0 +#define SSI_RX_SAMPLE_DLY_RSD_RESET _u(0x00) +#define SSI_RX_SAMPLE_DLY_RSD_BITS _u(0x000000ff) +#define SSI_RX_SAMPLE_DLY_RSD_MSB _u(7) +#define SSI_RX_SAMPLE_DLY_RSD_LSB _u(0) #define SSI_RX_SAMPLE_DLY_RSD_ACCESS "RW" // ============================================================================= // Register : SSI_SPI_CTRLR0 // Description : SPI control -#define SSI_SPI_CTRLR0_OFFSET 0x000000f4 -#define SSI_SPI_CTRLR0_BITS 0xff07fb3f -#define SSI_SPI_CTRLR0_RESET 0x03000000 +#define SSI_SPI_CTRLR0_OFFSET _u(0x000000f4) +#define SSI_SPI_CTRLR0_BITS _u(0xff07fb3f) +#define SSI_SPI_CTRLR0_RESET _u(0x03000000) // ----------------------------------------------------------------------------- // Field : SSI_SPI_CTRLR0_XIP_CMD // Description : SPI Command to send in XIP mode (INST_L = 8-bit) or to append // to Address (INST_L = 0-bit) -#define SSI_SPI_CTRLR0_XIP_CMD_RESET 0x03 -#define SSI_SPI_CTRLR0_XIP_CMD_BITS 0xff000000 -#define SSI_SPI_CTRLR0_XIP_CMD_MSB 31 -#define SSI_SPI_CTRLR0_XIP_CMD_LSB 24 +#define SSI_SPI_CTRLR0_XIP_CMD_RESET _u(0x03) +#define SSI_SPI_CTRLR0_XIP_CMD_BITS _u(0xff000000) +#define SSI_SPI_CTRLR0_XIP_CMD_MSB _u(31) +#define SSI_SPI_CTRLR0_XIP_CMD_LSB _u(24) #define SSI_SPI_CTRLR0_XIP_CMD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_SPI_CTRLR0_SPI_RXDS_EN // Description : Read data strobe enable -#define SSI_SPI_CTRLR0_SPI_RXDS_EN_RESET 0x0 -#define SSI_SPI_CTRLR0_SPI_RXDS_EN_BITS 0x00040000 -#define SSI_SPI_CTRLR0_SPI_RXDS_EN_MSB 18 -#define SSI_SPI_CTRLR0_SPI_RXDS_EN_LSB 18 +#define SSI_SPI_CTRLR0_SPI_RXDS_EN_RESET _u(0x0) +#define SSI_SPI_CTRLR0_SPI_RXDS_EN_BITS _u(0x00040000) +#define SSI_SPI_CTRLR0_SPI_RXDS_EN_MSB _u(18) +#define SSI_SPI_CTRLR0_SPI_RXDS_EN_LSB _u(18) #define SSI_SPI_CTRLR0_SPI_RXDS_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_SPI_CTRLR0_INST_DDR_EN // Description : Instruction DDR transfer enable -#define SSI_SPI_CTRLR0_INST_DDR_EN_RESET 0x0 -#define SSI_SPI_CTRLR0_INST_DDR_EN_BITS 0x00020000 -#define SSI_SPI_CTRLR0_INST_DDR_EN_MSB 17 -#define SSI_SPI_CTRLR0_INST_DDR_EN_LSB 17 +#define SSI_SPI_CTRLR0_INST_DDR_EN_RESET _u(0x0) +#define SSI_SPI_CTRLR0_INST_DDR_EN_BITS _u(0x00020000) +#define SSI_SPI_CTRLR0_INST_DDR_EN_MSB _u(17) +#define SSI_SPI_CTRLR0_INST_DDR_EN_LSB _u(17) #define SSI_SPI_CTRLR0_INST_DDR_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_SPI_CTRLR0_SPI_DDR_EN // Description : SPI DDR transfer enable -#define SSI_SPI_CTRLR0_SPI_DDR_EN_RESET 0x0 -#define SSI_SPI_CTRLR0_SPI_DDR_EN_BITS 0x00010000 -#define SSI_SPI_CTRLR0_SPI_DDR_EN_MSB 16 -#define SSI_SPI_CTRLR0_SPI_DDR_EN_LSB 16 +#define SSI_SPI_CTRLR0_SPI_DDR_EN_RESET _u(0x0) +#define SSI_SPI_CTRLR0_SPI_DDR_EN_BITS _u(0x00010000) +#define SSI_SPI_CTRLR0_SPI_DDR_EN_MSB _u(16) +#define SSI_SPI_CTRLR0_SPI_DDR_EN_LSB _u(16) #define SSI_SPI_CTRLR0_SPI_DDR_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_SPI_CTRLR0_WAIT_CYCLES // Description : Wait cycles between control frame transmit and data reception // (in SCLK cycles) -#define SSI_SPI_CTRLR0_WAIT_CYCLES_RESET 0x00 -#define SSI_SPI_CTRLR0_WAIT_CYCLES_BITS 0x0000f800 -#define SSI_SPI_CTRLR0_WAIT_CYCLES_MSB 15 -#define SSI_SPI_CTRLR0_WAIT_CYCLES_LSB 11 +#define SSI_SPI_CTRLR0_WAIT_CYCLES_RESET _u(0x00) +#define SSI_SPI_CTRLR0_WAIT_CYCLES_BITS _u(0x0000f800) +#define SSI_SPI_CTRLR0_WAIT_CYCLES_MSB _u(15) +#define SSI_SPI_CTRLR0_WAIT_CYCLES_LSB _u(11) #define SSI_SPI_CTRLR0_WAIT_CYCLES_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_SPI_CTRLR0_INST_L @@ -758,22 +758,22 @@ // 0x1 -> 4-bit instruction // 0x2 -> 8-bit instruction // 0x3 -> 16-bit instruction -#define SSI_SPI_CTRLR0_INST_L_RESET 0x0 -#define SSI_SPI_CTRLR0_INST_L_BITS 0x00000300 -#define SSI_SPI_CTRLR0_INST_L_MSB 9 -#define SSI_SPI_CTRLR0_INST_L_LSB 8 +#define SSI_SPI_CTRLR0_INST_L_RESET _u(0x0) +#define SSI_SPI_CTRLR0_INST_L_BITS _u(0x00000300) +#define SSI_SPI_CTRLR0_INST_L_MSB _u(9) +#define SSI_SPI_CTRLR0_INST_L_LSB _u(8) #define SSI_SPI_CTRLR0_INST_L_ACCESS "RW" -#define SSI_SPI_CTRLR0_INST_L_VALUE_NONE 0x0 -#define SSI_SPI_CTRLR0_INST_L_VALUE_4B 0x1 -#define SSI_SPI_CTRLR0_INST_L_VALUE_8B 0x2 -#define SSI_SPI_CTRLR0_INST_L_VALUE_16B 0x3 +#define SSI_SPI_CTRLR0_INST_L_VALUE_NONE _u(0x0) +#define SSI_SPI_CTRLR0_INST_L_VALUE_4B _u(0x1) +#define SSI_SPI_CTRLR0_INST_L_VALUE_8B _u(0x2) +#define SSI_SPI_CTRLR0_INST_L_VALUE_16B _u(0x3) // ----------------------------------------------------------------------------- // Field : SSI_SPI_CTRLR0_ADDR_L // Description : Address length (0b-60b in 4b increments) -#define SSI_SPI_CTRLR0_ADDR_L_RESET 0x0 -#define SSI_SPI_CTRLR0_ADDR_L_BITS 0x0000003c -#define SSI_SPI_CTRLR0_ADDR_L_MSB 5 -#define SSI_SPI_CTRLR0_ADDR_L_LSB 2 +#define SSI_SPI_CTRLR0_ADDR_L_RESET _u(0x0) +#define SSI_SPI_CTRLR0_ADDR_L_BITS _u(0x0000003c) +#define SSI_SPI_CTRLR0_ADDR_L_MSB _u(5) +#define SSI_SPI_CTRLR0_ADDR_L_LSB _u(2) #define SSI_SPI_CTRLR0_ADDR_L_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SSI_SPI_CTRLR0_TRANS_TYPE @@ -783,27 +783,27 @@ // specified by FRF // 0x2 -> Command and address both in format specified by FRF // (e.g. Dual-SPI) -#define SSI_SPI_CTRLR0_TRANS_TYPE_RESET 0x0 -#define SSI_SPI_CTRLR0_TRANS_TYPE_BITS 0x00000003 -#define SSI_SPI_CTRLR0_TRANS_TYPE_MSB 1 -#define SSI_SPI_CTRLR0_TRANS_TYPE_LSB 0 +#define SSI_SPI_CTRLR0_TRANS_TYPE_RESET _u(0x0) +#define SSI_SPI_CTRLR0_TRANS_TYPE_BITS _u(0x00000003) +#define SSI_SPI_CTRLR0_TRANS_TYPE_MSB _u(1) +#define SSI_SPI_CTRLR0_TRANS_TYPE_LSB _u(0) #define SSI_SPI_CTRLR0_TRANS_TYPE_ACCESS "RW" -#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A 0x0 -#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A 0x1 -#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A 0x2 +#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A _u(0x0) +#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A _u(0x1) +#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A _u(0x2) // ============================================================================= // Register : SSI_TXD_DRIVE_EDGE // Description : TX drive edge -#define SSI_TXD_DRIVE_EDGE_OFFSET 0x000000f8 -#define SSI_TXD_DRIVE_EDGE_BITS 0x000000ff -#define SSI_TXD_DRIVE_EDGE_RESET 0x00000000 +#define SSI_TXD_DRIVE_EDGE_OFFSET _u(0x000000f8) +#define SSI_TXD_DRIVE_EDGE_BITS _u(0x000000ff) +#define SSI_TXD_DRIVE_EDGE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SSI_TXD_DRIVE_EDGE_TDE // Description : TXD drive edge -#define SSI_TXD_DRIVE_EDGE_TDE_RESET 0x00 -#define SSI_TXD_DRIVE_EDGE_TDE_BITS 0x000000ff -#define SSI_TXD_DRIVE_EDGE_TDE_MSB 7 -#define SSI_TXD_DRIVE_EDGE_TDE_LSB 0 +#define SSI_TXD_DRIVE_EDGE_TDE_RESET _u(0x00) +#define SSI_TXD_DRIVE_EDGE_TDE_BITS _u(0x000000ff) +#define SSI_TXD_DRIVE_EDGE_TDE_MSB _u(7) +#define SSI_TXD_DRIVE_EDGE_TDE_LSB _u(0) #define SSI_TXD_DRIVE_EDGE_TDE_ACCESS "RW" // ============================================================================= #endif // HARDWARE_REGS_SSI_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/syscfg.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/syscfg.h index c1bcaf9dc..2bf09e26f 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/syscfg.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/syscfg.h @@ -15,38 +15,38 @@ // Register : SYSCFG_PROC0_NMI_MASK // Description : Processor core 0 NMI source mask // Set a bit high to enable NMI from that IRQ -#define SYSCFG_PROC0_NMI_MASK_OFFSET 0x00000000 -#define SYSCFG_PROC0_NMI_MASK_BITS 0xffffffff -#define SYSCFG_PROC0_NMI_MASK_RESET 0x00000000 -#define SYSCFG_PROC0_NMI_MASK_MSB 31 -#define SYSCFG_PROC0_NMI_MASK_LSB 0 +#define SYSCFG_PROC0_NMI_MASK_OFFSET _u(0x00000000) +#define SYSCFG_PROC0_NMI_MASK_BITS _u(0xffffffff) +#define SYSCFG_PROC0_NMI_MASK_RESET _u(0x00000000) +#define SYSCFG_PROC0_NMI_MASK_MSB _u(31) +#define SYSCFG_PROC0_NMI_MASK_LSB _u(0) #define SYSCFG_PROC0_NMI_MASK_ACCESS "RW" // ============================================================================= // Register : SYSCFG_PROC1_NMI_MASK // Description : Processor core 1 NMI source mask // Set a bit high to enable NMI from that IRQ -#define SYSCFG_PROC1_NMI_MASK_OFFSET 0x00000004 -#define SYSCFG_PROC1_NMI_MASK_BITS 0xffffffff -#define SYSCFG_PROC1_NMI_MASK_RESET 0x00000000 -#define SYSCFG_PROC1_NMI_MASK_MSB 31 -#define SYSCFG_PROC1_NMI_MASK_LSB 0 +#define SYSCFG_PROC1_NMI_MASK_OFFSET _u(0x00000004) +#define SYSCFG_PROC1_NMI_MASK_BITS _u(0xffffffff) +#define SYSCFG_PROC1_NMI_MASK_RESET _u(0x00000000) +#define SYSCFG_PROC1_NMI_MASK_MSB _u(31) +#define SYSCFG_PROC1_NMI_MASK_LSB _u(0) #define SYSCFG_PROC1_NMI_MASK_ACCESS "RW" // ============================================================================= // Register : SYSCFG_PROC_CONFIG // Description : Configuration for processors -#define SYSCFG_PROC_CONFIG_OFFSET 0x00000008 -#define SYSCFG_PROC_CONFIG_BITS 0xff000003 -#define SYSCFG_PROC_CONFIG_RESET 0x10000000 +#define SYSCFG_PROC_CONFIG_OFFSET _u(0x00000008) +#define SYSCFG_PROC_CONFIG_BITS _u(0xff000003) +#define SYSCFG_PROC_CONFIG_RESET _u(0x10000000) // ----------------------------------------------------------------------------- // Field : SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID // Description : Configure proc1 DAP instance ID. // Recommend that this is NOT changed until you require debug // access in multi-chip environment // WARNING: do not set to 15 as this is reserved for RescueDP -#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_RESET 0x1 -#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_BITS 0xf0000000 -#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_MSB 31 -#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_LSB 28 +#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_RESET _u(0x1) +#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_BITS _u(0xf0000000) +#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_MSB _u(31) +#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_LSB _u(28) #define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID @@ -54,26 +54,26 @@ // Recommend that this is NOT changed until you require debug // access in multi-chip environment // WARNING: do not set to 15 as this is reserved for RescueDP -#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_RESET 0x0 -#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_BITS 0x0f000000 -#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_MSB 27 -#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_LSB 24 +#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_RESET _u(0x0) +#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_BITS _u(0x0f000000) +#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_MSB _u(27) +#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_LSB _u(24) #define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_PROC_CONFIG_PROC1_HALTED // Description : Indication that proc1 has halted -#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET 0x0 -#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS 0x00000002 -#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB 1 -#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB 1 +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET _u(0x0) +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS _u(0x00000002) +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB _u(1) +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB _u(1) #define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SYSCFG_PROC_CONFIG_PROC0_HALTED // Description : Indication that proc0 has halted -#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET 0x0 -#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS 0x00000001 -#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB 0 -#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB 0 +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET _u(0x0) +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS _u(0x00000001) +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB _u(0) +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB _u(0) #define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO" // ============================================================================= // Register : SYSCFG_PROC_IN_SYNC_BYPASS @@ -86,11 +86,11 @@ // If you're feeling brave, you can bypass to save two cycles of // input // latency. This register applies to GPIO 0...29. -#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET 0x0000000c -#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS 0x3fffffff -#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET 0x00000000 -#define SYSCFG_PROC_IN_SYNC_BYPASS_MSB 29 -#define SYSCFG_PROC_IN_SYNC_BYPASS_LSB 0 +#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET _u(0x0000000c) +#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS _u(0x3fffffff) +#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET _u(0x00000000) +#define SYSCFG_PROC_IN_SYNC_BYPASS_MSB _u(29) +#define SYSCFG_PROC_IN_SYNC_BYPASS_LSB _u(0) #define SYSCFG_PROC_IN_SYNC_BYPASS_ACCESS "RW" // ============================================================================= // Register : SYSCFG_PROC_IN_SYNC_BYPASS_HI @@ -103,155 +103,155 @@ // If you're feeling brave, you can bypass to save two cycles of // input // latency. This register applies to GPIO 30...35 (the QSPI IOs). -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET 0x00000010 -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS 0x0000003f -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET 0x00000000 -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_MSB 5 -#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_LSB 0 +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET _u(0x00000010) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS _u(0x0000003f) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET _u(0x00000000) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_MSB _u(5) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_LSB _u(0) #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_ACCESS "RW" // ============================================================================= // Register : SYSCFG_DBGFORCE // Description : Directly control the SWD debug port of either processor -#define SYSCFG_DBGFORCE_OFFSET 0x00000014 -#define SYSCFG_DBGFORCE_BITS 0x000000ff -#define SYSCFG_DBGFORCE_RESET 0x00000066 +#define SYSCFG_DBGFORCE_OFFSET _u(0x00000014) +#define SYSCFG_DBGFORCE_BITS _u(0x000000ff) +#define SYSCFG_DBGFORCE_RESET _u(0x00000066) // ----------------------------------------------------------------------------- // Field : SYSCFG_DBGFORCE_PROC1_ATTACH // Description : Attach processor 1 debug port to syscfg controls, and // disconnect it from external SWD pads. -#define SYSCFG_DBGFORCE_PROC1_ATTACH_RESET 0x0 -#define SYSCFG_DBGFORCE_PROC1_ATTACH_BITS 0x00000080 -#define SYSCFG_DBGFORCE_PROC1_ATTACH_MSB 7 -#define SYSCFG_DBGFORCE_PROC1_ATTACH_LSB 7 +#define SYSCFG_DBGFORCE_PROC1_ATTACH_RESET _u(0x0) +#define SYSCFG_DBGFORCE_PROC1_ATTACH_BITS _u(0x00000080) +#define SYSCFG_DBGFORCE_PROC1_ATTACH_MSB _u(7) +#define SYSCFG_DBGFORCE_PROC1_ATTACH_LSB _u(7) #define SYSCFG_DBGFORCE_PROC1_ATTACH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_DBGFORCE_PROC1_SWCLK // Description : Directly drive processor 1 SWCLK, if PROC1_ATTACH is set -#define SYSCFG_DBGFORCE_PROC1_SWCLK_RESET 0x1 -#define SYSCFG_DBGFORCE_PROC1_SWCLK_BITS 0x00000040 -#define SYSCFG_DBGFORCE_PROC1_SWCLK_MSB 6 -#define SYSCFG_DBGFORCE_PROC1_SWCLK_LSB 6 +#define SYSCFG_DBGFORCE_PROC1_SWCLK_RESET _u(0x1) +#define SYSCFG_DBGFORCE_PROC1_SWCLK_BITS _u(0x00000040) +#define SYSCFG_DBGFORCE_PROC1_SWCLK_MSB _u(6) +#define SYSCFG_DBGFORCE_PROC1_SWCLK_LSB _u(6) #define SYSCFG_DBGFORCE_PROC1_SWCLK_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_DBGFORCE_PROC1_SWDI // Description : Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set -#define SYSCFG_DBGFORCE_PROC1_SWDI_RESET 0x1 -#define SYSCFG_DBGFORCE_PROC1_SWDI_BITS 0x00000020 -#define SYSCFG_DBGFORCE_PROC1_SWDI_MSB 5 -#define SYSCFG_DBGFORCE_PROC1_SWDI_LSB 5 +#define SYSCFG_DBGFORCE_PROC1_SWDI_RESET _u(0x1) +#define SYSCFG_DBGFORCE_PROC1_SWDI_BITS _u(0x00000020) +#define SYSCFG_DBGFORCE_PROC1_SWDI_MSB _u(5) +#define SYSCFG_DBGFORCE_PROC1_SWDI_LSB _u(5) #define SYSCFG_DBGFORCE_PROC1_SWDI_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_DBGFORCE_PROC1_SWDO // Description : Observe the value of processor 1 SWDIO output. #define SYSCFG_DBGFORCE_PROC1_SWDO_RESET "-" -#define SYSCFG_DBGFORCE_PROC1_SWDO_BITS 0x00000010 -#define SYSCFG_DBGFORCE_PROC1_SWDO_MSB 4 -#define SYSCFG_DBGFORCE_PROC1_SWDO_LSB 4 +#define SYSCFG_DBGFORCE_PROC1_SWDO_BITS _u(0x00000010) +#define SYSCFG_DBGFORCE_PROC1_SWDO_MSB _u(4) +#define SYSCFG_DBGFORCE_PROC1_SWDO_LSB _u(4) #define SYSCFG_DBGFORCE_PROC1_SWDO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SYSCFG_DBGFORCE_PROC0_ATTACH // Description : Attach processor 0 debug port to syscfg controls, and // disconnect it from external SWD pads. -#define SYSCFG_DBGFORCE_PROC0_ATTACH_RESET 0x0 -#define SYSCFG_DBGFORCE_PROC0_ATTACH_BITS 0x00000008 -#define SYSCFG_DBGFORCE_PROC0_ATTACH_MSB 3 -#define SYSCFG_DBGFORCE_PROC0_ATTACH_LSB 3 +#define SYSCFG_DBGFORCE_PROC0_ATTACH_RESET _u(0x0) +#define SYSCFG_DBGFORCE_PROC0_ATTACH_BITS _u(0x00000008) +#define SYSCFG_DBGFORCE_PROC0_ATTACH_MSB _u(3) +#define SYSCFG_DBGFORCE_PROC0_ATTACH_LSB _u(3) #define SYSCFG_DBGFORCE_PROC0_ATTACH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_DBGFORCE_PROC0_SWCLK // Description : Directly drive processor 0 SWCLK, if PROC0_ATTACH is set -#define SYSCFG_DBGFORCE_PROC0_SWCLK_RESET 0x1 -#define SYSCFG_DBGFORCE_PROC0_SWCLK_BITS 0x00000004 -#define SYSCFG_DBGFORCE_PROC0_SWCLK_MSB 2 -#define SYSCFG_DBGFORCE_PROC0_SWCLK_LSB 2 +#define SYSCFG_DBGFORCE_PROC0_SWCLK_RESET _u(0x1) +#define SYSCFG_DBGFORCE_PROC0_SWCLK_BITS _u(0x00000004) +#define SYSCFG_DBGFORCE_PROC0_SWCLK_MSB _u(2) +#define SYSCFG_DBGFORCE_PROC0_SWCLK_LSB _u(2) #define SYSCFG_DBGFORCE_PROC0_SWCLK_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_DBGFORCE_PROC0_SWDI // Description : Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set -#define SYSCFG_DBGFORCE_PROC0_SWDI_RESET 0x1 -#define SYSCFG_DBGFORCE_PROC0_SWDI_BITS 0x00000002 -#define SYSCFG_DBGFORCE_PROC0_SWDI_MSB 1 -#define SYSCFG_DBGFORCE_PROC0_SWDI_LSB 1 +#define SYSCFG_DBGFORCE_PROC0_SWDI_RESET _u(0x1) +#define SYSCFG_DBGFORCE_PROC0_SWDI_BITS _u(0x00000002) +#define SYSCFG_DBGFORCE_PROC0_SWDI_MSB _u(1) +#define SYSCFG_DBGFORCE_PROC0_SWDI_LSB _u(1) #define SYSCFG_DBGFORCE_PROC0_SWDI_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_DBGFORCE_PROC0_SWDO // Description : Observe the value of processor 0 SWDIO output. #define SYSCFG_DBGFORCE_PROC0_SWDO_RESET "-" -#define SYSCFG_DBGFORCE_PROC0_SWDO_BITS 0x00000001 -#define SYSCFG_DBGFORCE_PROC0_SWDO_MSB 0 -#define SYSCFG_DBGFORCE_PROC0_SWDO_LSB 0 +#define SYSCFG_DBGFORCE_PROC0_SWDO_BITS _u(0x00000001) +#define SYSCFG_DBGFORCE_PROC0_SWDO_MSB _u(0) +#define SYSCFG_DBGFORCE_PROC0_SWDO_LSB _u(0) #define SYSCFG_DBGFORCE_PROC0_SWDO_ACCESS "RO" // ============================================================================= // Register : SYSCFG_MEMPOWERDOWN // Description : Control power downs to memories. Set high to power down // memories. // Use with extreme caution -#define SYSCFG_MEMPOWERDOWN_OFFSET 0x00000018 -#define SYSCFG_MEMPOWERDOWN_BITS 0x000000ff -#define SYSCFG_MEMPOWERDOWN_RESET 0x00000000 +#define SYSCFG_MEMPOWERDOWN_OFFSET _u(0x00000018) +#define SYSCFG_MEMPOWERDOWN_BITS _u(0x000000ff) +#define SYSCFG_MEMPOWERDOWN_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_ROM // Description : None -#define SYSCFG_MEMPOWERDOWN_ROM_RESET 0x0 -#define SYSCFG_MEMPOWERDOWN_ROM_BITS 0x00000080 -#define SYSCFG_MEMPOWERDOWN_ROM_MSB 7 -#define SYSCFG_MEMPOWERDOWN_ROM_LSB 7 +#define SYSCFG_MEMPOWERDOWN_ROM_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_ROM_BITS _u(0x00000080) +#define SYSCFG_MEMPOWERDOWN_ROM_MSB _u(7) +#define SYSCFG_MEMPOWERDOWN_ROM_LSB _u(7) #define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_USB // Description : None -#define SYSCFG_MEMPOWERDOWN_USB_RESET 0x0 -#define SYSCFG_MEMPOWERDOWN_USB_BITS 0x00000040 -#define SYSCFG_MEMPOWERDOWN_USB_MSB 6 -#define SYSCFG_MEMPOWERDOWN_USB_LSB 6 +#define SYSCFG_MEMPOWERDOWN_USB_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_USB_BITS _u(0x00000040) +#define SYSCFG_MEMPOWERDOWN_USB_MSB _u(6) +#define SYSCFG_MEMPOWERDOWN_USB_LSB _u(6) #define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM5 // Description : None -#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET 0x0 -#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS 0x00000020 -#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB 5 -#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB 5 +#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS _u(0x00000020) +#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB _u(5) +#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB _u(5) #define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM4 // Description : None -#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET 0x0 -#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS 0x00000010 -#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB 4 -#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB 4 +#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS _u(0x00000010) +#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB _u(4) +#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB _u(4) #define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM3 // Description : None -#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET 0x0 -#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS 0x00000008 -#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB 3 -#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB 3 +#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS _u(0x00000008) +#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB _u(3) +#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB _u(3) #define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM2 // Description : None -#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET 0x0 -#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS 0x00000004 -#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB 2 -#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB 2 +#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS _u(0x00000004) +#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB _u(2) +#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB _u(2) #define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM1 // Description : None -#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET 0x0 -#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS 0x00000002 -#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB 1 -#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB 1 +#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS _u(0x00000002) +#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB _u(1) +#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB _u(1) #define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM0 // Description : None -#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET 0x0 -#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS 0x00000001 -#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB 0 -#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB 0 +#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS _u(0x00000001) +#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB _u(0) +#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB _u(0) #define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW" // ============================================================================= #endif // HARDWARE_REGS_SYSCFG_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sysinfo.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sysinfo.h index 7a460374c..2a46658e2 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sysinfo.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/sysinfo.h @@ -14,64 +14,64 @@ // ============================================================================= // Register : SYSINFO_CHIP_ID // Description : JEDEC JEP-106 compliant chip identifier. -#define SYSINFO_CHIP_ID_OFFSET 0x00000000 -#define SYSINFO_CHIP_ID_BITS 0xffffffff -#define SYSINFO_CHIP_ID_RESET 0x00000000 +#define SYSINFO_CHIP_ID_OFFSET _u(0x00000000) +#define SYSINFO_CHIP_ID_BITS _u(0xffffffff) +#define SYSINFO_CHIP_ID_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SYSINFO_CHIP_ID_REVISION // Description : None #define SYSINFO_CHIP_ID_REVISION_RESET "-" -#define SYSINFO_CHIP_ID_REVISION_BITS 0xf0000000 -#define SYSINFO_CHIP_ID_REVISION_MSB 31 -#define SYSINFO_CHIP_ID_REVISION_LSB 28 +#define SYSINFO_CHIP_ID_REVISION_BITS _u(0xf0000000) +#define SYSINFO_CHIP_ID_REVISION_MSB _u(31) +#define SYSINFO_CHIP_ID_REVISION_LSB _u(28) #define SYSINFO_CHIP_ID_REVISION_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SYSINFO_CHIP_ID_PART // Description : None #define SYSINFO_CHIP_ID_PART_RESET "-" -#define SYSINFO_CHIP_ID_PART_BITS 0x0ffff000 -#define SYSINFO_CHIP_ID_PART_MSB 27 -#define SYSINFO_CHIP_ID_PART_LSB 12 +#define SYSINFO_CHIP_ID_PART_BITS _u(0x0ffff000) +#define SYSINFO_CHIP_ID_PART_MSB _u(27) +#define SYSINFO_CHIP_ID_PART_LSB _u(12) #define SYSINFO_CHIP_ID_PART_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SYSINFO_CHIP_ID_MANUFACTURER // Description : None #define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-" -#define SYSINFO_CHIP_ID_MANUFACTURER_BITS 0x00000fff -#define SYSINFO_CHIP_ID_MANUFACTURER_MSB 11 -#define SYSINFO_CHIP_ID_MANUFACTURER_LSB 0 +#define SYSINFO_CHIP_ID_MANUFACTURER_BITS _u(0x00000fff) +#define SYSINFO_CHIP_ID_MANUFACTURER_MSB _u(11) +#define SYSINFO_CHIP_ID_MANUFACTURER_LSB _u(0) #define SYSINFO_CHIP_ID_MANUFACTURER_ACCESS "RO" // ============================================================================= // Register : SYSINFO_PLATFORM // Description : Platform register. Allows software to know what environment it // is running in. -#define SYSINFO_PLATFORM_OFFSET 0x00000004 -#define SYSINFO_PLATFORM_BITS 0x00000003 -#define SYSINFO_PLATFORM_RESET 0x00000000 +#define SYSINFO_PLATFORM_OFFSET _u(0x00000004) +#define SYSINFO_PLATFORM_BITS _u(0x00000003) +#define SYSINFO_PLATFORM_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SYSINFO_PLATFORM_ASIC // Description : None -#define SYSINFO_PLATFORM_ASIC_RESET 0x0 -#define SYSINFO_PLATFORM_ASIC_BITS 0x00000002 -#define SYSINFO_PLATFORM_ASIC_MSB 1 -#define SYSINFO_PLATFORM_ASIC_LSB 1 +#define SYSINFO_PLATFORM_ASIC_RESET _u(0x0) +#define SYSINFO_PLATFORM_ASIC_BITS _u(0x00000002) +#define SYSINFO_PLATFORM_ASIC_MSB _u(1) +#define SYSINFO_PLATFORM_ASIC_LSB _u(1) #define SYSINFO_PLATFORM_ASIC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SYSINFO_PLATFORM_FPGA // Description : None -#define SYSINFO_PLATFORM_FPGA_RESET 0x0 -#define SYSINFO_PLATFORM_FPGA_BITS 0x00000001 -#define SYSINFO_PLATFORM_FPGA_MSB 0 -#define SYSINFO_PLATFORM_FPGA_LSB 0 +#define SYSINFO_PLATFORM_FPGA_RESET _u(0x0) +#define SYSINFO_PLATFORM_FPGA_BITS _u(0x00000001) +#define SYSINFO_PLATFORM_FPGA_MSB _u(0) +#define SYSINFO_PLATFORM_FPGA_LSB _u(0) #define SYSINFO_PLATFORM_FPGA_ACCESS "RO" // ============================================================================= // Register : SYSINFO_GITREF_RP2040 // Description : Git hash of the chip source. Used to identify chip version. -#define SYSINFO_GITREF_RP2040_OFFSET 0x00000040 -#define SYSINFO_GITREF_RP2040_BITS 0xffffffff +#define SYSINFO_GITREF_RP2040_OFFSET _u(0x00000040) +#define SYSINFO_GITREF_RP2040_BITS _u(0xffffffff) #define SYSINFO_GITREF_RP2040_RESET "-" -#define SYSINFO_GITREF_RP2040_MSB 31 -#define SYSINFO_GITREF_RP2040_LSB 0 +#define SYSINFO_GITREF_RP2040_MSB _u(31) +#define SYSINFO_GITREF_RP2040_LSB _u(0) #define SYSINFO_GITREF_RP2040_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_SYSINFO_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/tbman.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/tbman.h index 6bf9b2959..4f8f64132 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/tbman.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/tbman.h @@ -15,24 +15,24 @@ // ============================================================================= // Register : TBMAN_PLATFORM // Description : Indicates the type of platform in use -#define TBMAN_PLATFORM_OFFSET 0x00000000 -#define TBMAN_PLATFORM_BITS 0x00000003 -#define TBMAN_PLATFORM_RESET 0x00000005 +#define TBMAN_PLATFORM_OFFSET _u(0x00000000) +#define TBMAN_PLATFORM_BITS _u(0x00000003) +#define TBMAN_PLATFORM_RESET _u(0x00000005) // ----------------------------------------------------------------------------- // Field : TBMAN_PLATFORM_FPGA // Description : Indicates the platform is an FPGA -#define TBMAN_PLATFORM_FPGA_RESET 0x0 -#define TBMAN_PLATFORM_FPGA_BITS 0x00000002 -#define TBMAN_PLATFORM_FPGA_MSB 1 -#define TBMAN_PLATFORM_FPGA_LSB 1 +#define TBMAN_PLATFORM_FPGA_RESET _u(0x0) +#define TBMAN_PLATFORM_FPGA_BITS _u(0x00000002) +#define TBMAN_PLATFORM_FPGA_MSB _u(1) +#define TBMAN_PLATFORM_FPGA_LSB _u(1) #define TBMAN_PLATFORM_FPGA_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TBMAN_PLATFORM_ASIC // Description : Indicates the platform is an ASIC -#define TBMAN_PLATFORM_ASIC_RESET 0x1 -#define TBMAN_PLATFORM_ASIC_BITS 0x00000001 -#define TBMAN_PLATFORM_ASIC_MSB 0 -#define TBMAN_PLATFORM_ASIC_LSB 0 +#define TBMAN_PLATFORM_ASIC_RESET _u(0x1) +#define TBMAN_PLATFORM_ASIC_BITS _u(0x00000001) +#define TBMAN_PLATFORM_ASIC_MSB _u(0) +#define TBMAN_PLATFORM_ASIC_LSB _u(0) #define TBMAN_PLATFORM_ASIC_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_TBMAN_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/timer.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/timer.h index a2209b690..c3ef0c5a1 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/timer.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/timer.h @@ -31,40 +31,40 @@ // Register : TIMER_TIMEHW // Description : Write to bits 63:32 of time // always write timelw before timehw -#define TIMER_TIMEHW_OFFSET 0x00000000 -#define TIMER_TIMEHW_BITS 0xffffffff -#define TIMER_TIMEHW_RESET 0x00000000 -#define TIMER_TIMEHW_MSB 31 -#define TIMER_TIMEHW_LSB 0 +#define TIMER_TIMEHW_OFFSET _u(0x00000000) +#define TIMER_TIMEHW_BITS _u(0xffffffff) +#define TIMER_TIMEHW_RESET _u(0x00000000) +#define TIMER_TIMEHW_MSB _u(31) +#define TIMER_TIMEHW_LSB _u(0) #define TIMER_TIMEHW_ACCESS "WF" // ============================================================================= // Register : TIMER_TIMELW // Description : Write to bits 31:0 of time // writes do not get copied to time until timehw is written -#define TIMER_TIMELW_OFFSET 0x00000004 -#define TIMER_TIMELW_BITS 0xffffffff -#define TIMER_TIMELW_RESET 0x00000000 -#define TIMER_TIMELW_MSB 31 -#define TIMER_TIMELW_LSB 0 +#define TIMER_TIMELW_OFFSET _u(0x00000004) +#define TIMER_TIMELW_BITS _u(0xffffffff) +#define TIMER_TIMELW_RESET _u(0x00000000) +#define TIMER_TIMELW_MSB _u(31) +#define TIMER_TIMELW_LSB _u(0) #define TIMER_TIMELW_ACCESS "WF" // ============================================================================= // Register : TIMER_TIMEHR // Description : Read from bits 63:32 of time // always read timelr before timehr -#define TIMER_TIMEHR_OFFSET 0x00000008 -#define TIMER_TIMEHR_BITS 0xffffffff -#define TIMER_TIMEHR_RESET 0x00000000 -#define TIMER_TIMEHR_MSB 31 -#define TIMER_TIMEHR_LSB 0 +#define TIMER_TIMEHR_OFFSET _u(0x00000008) +#define TIMER_TIMEHR_BITS _u(0xffffffff) +#define TIMER_TIMEHR_RESET _u(0x00000000) +#define TIMER_TIMEHR_MSB _u(31) +#define TIMER_TIMEHR_LSB _u(0) #define TIMER_TIMEHR_ACCESS "RO" // ============================================================================= // Register : TIMER_TIMELR // Description : Read from bits 31:0 of time -#define TIMER_TIMELR_OFFSET 0x0000000c -#define TIMER_TIMELR_BITS 0xffffffff -#define TIMER_TIMELR_RESET 0x00000000 -#define TIMER_TIMELR_MSB 31 -#define TIMER_TIMELR_LSB 0 +#define TIMER_TIMELR_OFFSET _u(0x0000000c) +#define TIMER_TIMELR_BITS _u(0xffffffff) +#define TIMER_TIMELR_RESET _u(0x00000000) +#define TIMER_TIMELR_MSB _u(31) +#define TIMER_TIMELR_LSB _u(0) #define TIMER_TIMELR_ACCESS "RO" // ============================================================================= // Register : TIMER_ALARM0 @@ -72,11 +72,11 @@ // Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. // The alarm will disarm itself once it fires, and can // be disarmed early using the ARMED status register. -#define TIMER_ALARM0_OFFSET 0x00000010 -#define TIMER_ALARM0_BITS 0xffffffff -#define TIMER_ALARM0_RESET 0x00000000 -#define TIMER_ALARM0_MSB 31 -#define TIMER_ALARM0_LSB 0 +#define TIMER_ALARM0_OFFSET _u(0x00000010) +#define TIMER_ALARM0_BITS _u(0xffffffff) +#define TIMER_ALARM0_RESET _u(0x00000000) +#define TIMER_ALARM0_MSB _u(31) +#define TIMER_ALARM0_LSB _u(0) #define TIMER_ALARM0_ACCESS "RW" // ============================================================================= // Register : TIMER_ALARM1 @@ -84,11 +84,11 @@ // Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. // The alarm will disarm itself once it fires, and can // be disarmed early using the ARMED status register. -#define TIMER_ALARM1_OFFSET 0x00000014 -#define TIMER_ALARM1_BITS 0xffffffff -#define TIMER_ALARM1_RESET 0x00000000 -#define TIMER_ALARM1_MSB 31 -#define TIMER_ALARM1_LSB 0 +#define TIMER_ALARM1_OFFSET _u(0x00000014) +#define TIMER_ALARM1_BITS _u(0xffffffff) +#define TIMER_ALARM1_RESET _u(0x00000000) +#define TIMER_ALARM1_MSB _u(31) +#define TIMER_ALARM1_LSB _u(0) #define TIMER_ALARM1_ACCESS "RW" // ============================================================================= // Register : TIMER_ALARM2 @@ -96,11 +96,11 @@ // Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. // The alarm will disarm itself once it fires, and can // be disarmed early using the ARMED status register. -#define TIMER_ALARM2_OFFSET 0x00000018 -#define TIMER_ALARM2_BITS 0xffffffff -#define TIMER_ALARM2_RESET 0x00000000 -#define TIMER_ALARM2_MSB 31 -#define TIMER_ALARM2_LSB 0 +#define TIMER_ALARM2_OFFSET _u(0x00000018) +#define TIMER_ALARM2_BITS _u(0xffffffff) +#define TIMER_ALARM2_RESET _u(0x00000000) +#define TIMER_ALARM2_MSB _u(31) +#define TIMER_ALARM2_LSB _u(0) #define TIMER_ALARM2_ACCESS "RW" // ============================================================================= // Register : TIMER_ALARM3 @@ -108,11 +108,11 @@ // Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. // The alarm will disarm itself once it fires, and can // be disarmed early using the ARMED status register. -#define TIMER_ALARM3_OFFSET 0x0000001c -#define TIMER_ALARM3_BITS 0xffffffff -#define TIMER_ALARM3_RESET 0x00000000 -#define TIMER_ALARM3_MSB 31 -#define TIMER_ALARM3_LSB 0 +#define TIMER_ALARM3_OFFSET _u(0x0000001c) +#define TIMER_ALARM3_BITS _u(0xffffffff) +#define TIMER_ALARM3_RESET _u(0x00000000) +#define TIMER_ALARM3_MSB _u(31) +#define TIMER_ALARM3_LSB _u(0) #define TIMER_ALARM3_ACCESS "RW" // ============================================================================= // Register : TIMER_ARMED @@ -120,213 +120,213 @@ // A write to the corresponding ALARMx register arms the alarm. // Alarms automatically disarm upon firing, but writing ones here // will disarm immediately without waiting to fire. -#define TIMER_ARMED_OFFSET 0x00000020 -#define TIMER_ARMED_BITS 0x0000000f -#define TIMER_ARMED_RESET 0x00000000 -#define TIMER_ARMED_MSB 3 -#define TIMER_ARMED_LSB 0 +#define TIMER_ARMED_OFFSET _u(0x00000020) +#define TIMER_ARMED_BITS _u(0x0000000f) +#define TIMER_ARMED_RESET _u(0x00000000) +#define TIMER_ARMED_MSB _u(3) +#define TIMER_ARMED_LSB _u(0) #define TIMER_ARMED_ACCESS "WC" // ============================================================================= // Register : TIMER_TIMERAWH // Description : Raw read from bits 63:32 of time (no side effects) -#define TIMER_TIMERAWH_OFFSET 0x00000024 -#define TIMER_TIMERAWH_BITS 0xffffffff -#define TIMER_TIMERAWH_RESET 0x00000000 -#define TIMER_TIMERAWH_MSB 31 -#define TIMER_TIMERAWH_LSB 0 +#define TIMER_TIMERAWH_OFFSET _u(0x00000024) +#define TIMER_TIMERAWH_BITS _u(0xffffffff) +#define TIMER_TIMERAWH_RESET _u(0x00000000) +#define TIMER_TIMERAWH_MSB _u(31) +#define TIMER_TIMERAWH_LSB _u(0) #define TIMER_TIMERAWH_ACCESS "RO" // ============================================================================= // Register : TIMER_TIMERAWL // Description : Raw read from bits 31:0 of time (no side effects) -#define TIMER_TIMERAWL_OFFSET 0x00000028 -#define TIMER_TIMERAWL_BITS 0xffffffff -#define TIMER_TIMERAWL_RESET 0x00000000 -#define TIMER_TIMERAWL_MSB 31 -#define TIMER_TIMERAWL_LSB 0 +#define TIMER_TIMERAWL_OFFSET _u(0x00000028) +#define TIMER_TIMERAWL_BITS _u(0xffffffff) +#define TIMER_TIMERAWL_RESET _u(0x00000000) +#define TIMER_TIMERAWL_MSB _u(31) +#define TIMER_TIMERAWL_LSB _u(0) #define TIMER_TIMERAWL_ACCESS "RO" // ============================================================================= // Register : TIMER_DBGPAUSE // Description : Set bits high to enable pause when the corresponding debug // ports are active -#define TIMER_DBGPAUSE_OFFSET 0x0000002c -#define TIMER_DBGPAUSE_BITS 0x00000006 -#define TIMER_DBGPAUSE_RESET 0x00000007 +#define TIMER_DBGPAUSE_OFFSET _u(0x0000002c) +#define TIMER_DBGPAUSE_BITS _u(0x00000006) +#define TIMER_DBGPAUSE_RESET _u(0x00000007) // ----------------------------------------------------------------------------- // Field : TIMER_DBGPAUSE_DBG1 // Description : Pause when processor 1 is in debug mode -#define TIMER_DBGPAUSE_DBG1_RESET 0x1 -#define TIMER_DBGPAUSE_DBG1_BITS 0x00000004 -#define TIMER_DBGPAUSE_DBG1_MSB 2 -#define TIMER_DBGPAUSE_DBG1_LSB 2 +#define TIMER_DBGPAUSE_DBG1_RESET _u(0x1) +#define TIMER_DBGPAUSE_DBG1_BITS _u(0x00000004) +#define TIMER_DBGPAUSE_DBG1_MSB _u(2) +#define TIMER_DBGPAUSE_DBG1_LSB _u(2) #define TIMER_DBGPAUSE_DBG1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_DBGPAUSE_DBG0 // Description : Pause when processor 0 is in debug mode -#define TIMER_DBGPAUSE_DBG0_RESET 0x1 -#define TIMER_DBGPAUSE_DBG0_BITS 0x00000002 -#define TIMER_DBGPAUSE_DBG0_MSB 1 -#define TIMER_DBGPAUSE_DBG0_LSB 1 +#define TIMER_DBGPAUSE_DBG0_RESET _u(0x1) +#define TIMER_DBGPAUSE_DBG0_BITS _u(0x00000002) +#define TIMER_DBGPAUSE_DBG0_MSB _u(1) +#define TIMER_DBGPAUSE_DBG0_LSB _u(1) #define TIMER_DBGPAUSE_DBG0_ACCESS "RW" // ============================================================================= // Register : TIMER_PAUSE // Description : Set high to pause the timer -#define TIMER_PAUSE_OFFSET 0x00000030 -#define TIMER_PAUSE_BITS 0x00000001 -#define TIMER_PAUSE_RESET 0x00000000 -#define TIMER_PAUSE_MSB 0 -#define TIMER_PAUSE_LSB 0 +#define TIMER_PAUSE_OFFSET _u(0x00000030) +#define TIMER_PAUSE_BITS _u(0x00000001) +#define TIMER_PAUSE_RESET _u(0x00000000) +#define TIMER_PAUSE_MSB _u(0) +#define TIMER_PAUSE_LSB _u(0) #define TIMER_PAUSE_ACCESS "RW" // ============================================================================= // Register : TIMER_INTR // Description : Raw Interrupts -#define TIMER_INTR_OFFSET 0x00000034 -#define TIMER_INTR_BITS 0x0000000f -#define TIMER_INTR_RESET 0x00000000 +#define TIMER_INTR_OFFSET _u(0x00000034) +#define TIMER_INTR_BITS _u(0x0000000f) +#define TIMER_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TIMER_INTR_ALARM_3 // Description : None -#define TIMER_INTR_ALARM_3_RESET 0x0 -#define TIMER_INTR_ALARM_3_BITS 0x00000008 -#define TIMER_INTR_ALARM_3_MSB 3 -#define TIMER_INTR_ALARM_3_LSB 3 +#define TIMER_INTR_ALARM_3_RESET _u(0x0) +#define TIMER_INTR_ALARM_3_BITS _u(0x00000008) +#define TIMER_INTR_ALARM_3_MSB _u(3) +#define TIMER_INTR_ALARM_3_LSB _u(3) #define TIMER_INTR_ALARM_3_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : TIMER_INTR_ALARM_2 // Description : None -#define TIMER_INTR_ALARM_2_RESET 0x0 -#define TIMER_INTR_ALARM_2_BITS 0x00000004 -#define TIMER_INTR_ALARM_2_MSB 2 -#define TIMER_INTR_ALARM_2_LSB 2 +#define TIMER_INTR_ALARM_2_RESET _u(0x0) +#define TIMER_INTR_ALARM_2_BITS _u(0x00000004) +#define TIMER_INTR_ALARM_2_MSB _u(2) +#define TIMER_INTR_ALARM_2_LSB _u(2) #define TIMER_INTR_ALARM_2_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : TIMER_INTR_ALARM_1 // Description : None -#define TIMER_INTR_ALARM_1_RESET 0x0 -#define TIMER_INTR_ALARM_1_BITS 0x00000002 -#define TIMER_INTR_ALARM_1_MSB 1 -#define TIMER_INTR_ALARM_1_LSB 1 +#define TIMER_INTR_ALARM_1_RESET _u(0x0) +#define TIMER_INTR_ALARM_1_BITS _u(0x00000002) +#define TIMER_INTR_ALARM_1_MSB _u(1) +#define TIMER_INTR_ALARM_1_LSB _u(1) #define TIMER_INTR_ALARM_1_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : TIMER_INTR_ALARM_0 // Description : None -#define TIMER_INTR_ALARM_0_RESET 0x0 -#define TIMER_INTR_ALARM_0_BITS 0x00000001 -#define TIMER_INTR_ALARM_0_MSB 0 -#define TIMER_INTR_ALARM_0_LSB 0 +#define TIMER_INTR_ALARM_0_RESET _u(0x0) +#define TIMER_INTR_ALARM_0_BITS _u(0x00000001) +#define TIMER_INTR_ALARM_0_MSB _u(0) +#define TIMER_INTR_ALARM_0_LSB _u(0) #define TIMER_INTR_ALARM_0_ACCESS "WC" // ============================================================================= // Register : TIMER_INTE // Description : Interrupt Enable -#define TIMER_INTE_OFFSET 0x00000038 -#define TIMER_INTE_BITS 0x0000000f -#define TIMER_INTE_RESET 0x00000000 +#define TIMER_INTE_OFFSET _u(0x00000038) +#define TIMER_INTE_BITS _u(0x0000000f) +#define TIMER_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TIMER_INTE_ALARM_3 // Description : None -#define TIMER_INTE_ALARM_3_RESET 0x0 -#define TIMER_INTE_ALARM_3_BITS 0x00000008 -#define TIMER_INTE_ALARM_3_MSB 3 -#define TIMER_INTE_ALARM_3_LSB 3 +#define TIMER_INTE_ALARM_3_RESET _u(0x0) +#define TIMER_INTE_ALARM_3_BITS _u(0x00000008) +#define TIMER_INTE_ALARM_3_MSB _u(3) +#define TIMER_INTE_ALARM_3_LSB _u(3) #define TIMER_INTE_ALARM_3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTE_ALARM_2 // Description : None -#define TIMER_INTE_ALARM_2_RESET 0x0 -#define TIMER_INTE_ALARM_2_BITS 0x00000004 -#define TIMER_INTE_ALARM_2_MSB 2 -#define TIMER_INTE_ALARM_2_LSB 2 +#define TIMER_INTE_ALARM_2_RESET _u(0x0) +#define TIMER_INTE_ALARM_2_BITS _u(0x00000004) +#define TIMER_INTE_ALARM_2_MSB _u(2) +#define TIMER_INTE_ALARM_2_LSB _u(2) #define TIMER_INTE_ALARM_2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTE_ALARM_1 // Description : None -#define TIMER_INTE_ALARM_1_RESET 0x0 -#define TIMER_INTE_ALARM_1_BITS 0x00000002 -#define TIMER_INTE_ALARM_1_MSB 1 -#define TIMER_INTE_ALARM_1_LSB 1 +#define TIMER_INTE_ALARM_1_RESET _u(0x0) +#define TIMER_INTE_ALARM_1_BITS _u(0x00000002) +#define TIMER_INTE_ALARM_1_MSB _u(1) +#define TIMER_INTE_ALARM_1_LSB _u(1) #define TIMER_INTE_ALARM_1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTE_ALARM_0 // Description : None -#define TIMER_INTE_ALARM_0_RESET 0x0 -#define TIMER_INTE_ALARM_0_BITS 0x00000001 -#define TIMER_INTE_ALARM_0_MSB 0 -#define TIMER_INTE_ALARM_0_LSB 0 +#define TIMER_INTE_ALARM_0_RESET _u(0x0) +#define TIMER_INTE_ALARM_0_BITS _u(0x00000001) +#define TIMER_INTE_ALARM_0_MSB _u(0) +#define TIMER_INTE_ALARM_0_LSB _u(0) #define TIMER_INTE_ALARM_0_ACCESS "RW" // ============================================================================= // Register : TIMER_INTF // Description : Interrupt Force -#define TIMER_INTF_OFFSET 0x0000003c -#define TIMER_INTF_BITS 0x0000000f -#define TIMER_INTF_RESET 0x00000000 +#define TIMER_INTF_OFFSET _u(0x0000003c) +#define TIMER_INTF_BITS _u(0x0000000f) +#define TIMER_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TIMER_INTF_ALARM_3 // Description : None -#define TIMER_INTF_ALARM_3_RESET 0x0 -#define TIMER_INTF_ALARM_3_BITS 0x00000008 -#define TIMER_INTF_ALARM_3_MSB 3 -#define TIMER_INTF_ALARM_3_LSB 3 +#define TIMER_INTF_ALARM_3_RESET _u(0x0) +#define TIMER_INTF_ALARM_3_BITS _u(0x00000008) +#define TIMER_INTF_ALARM_3_MSB _u(3) +#define TIMER_INTF_ALARM_3_LSB _u(3) #define TIMER_INTF_ALARM_3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTF_ALARM_2 // Description : None -#define TIMER_INTF_ALARM_2_RESET 0x0 -#define TIMER_INTF_ALARM_2_BITS 0x00000004 -#define TIMER_INTF_ALARM_2_MSB 2 -#define TIMER_INTF_ALARM_2_LSB 2 +#define TIMER_INTF_ALARM_2_RESET _u(0x0) +#define TIMER_INTF_ALARM_2_BITS _u(0x00000004) +#define TIMER_INTF_ALARM_2_MSB _u(2) +#define TIMER_INTF_ALARM_2_LSB _u(2) #define TIMER_INTF_ALARM_2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTF_ALARM_1 // Description : None -#define TIMER_INTF_ALARM_1_RESET 0x0 -#define TIMER_INTF_ALARM_1_BITS 0x00000002 -#define TIMER_INTF_ALARM_1_MSB 1 -#define TIMER_INTF_ALARM_1_LSB 1 +#define TIMER_INTF_ALARM_1_RESET _u(0x0) +#define TIMER_INTF_ALARM_1_BITS _u(0x00000002) +#define TIMER_INTF_ALARM_1_MSB _u(1) +#define TIMER_INTF_ALARM_1_LSB _u(1) #define TIMER_INTF_ALARM_1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTF_ALARM_0 // Description : None -#define TIMER_INTF_ALARM_0_RESET 0x0 -#define TIMER_INTF_ALARM_0_BITS 0x00000001 -#define TIMER_INTF_ALARM_0_MSB 0 -#define TIMER_INTF_ALARM_0_LSB 0 +#define TIMER_INTF_ALARM_0_RESET _u(0x0) +#define TIMER_INTF_ALARM_0_BITS _u(0x00000001) +#define TIMER_INTF_ALARM_0_MSB _u(0) +#define TIMER_INTF_ALARM_0_LSB _u(0) #define TIMER_INTF_ALARM_0_ACCESS "RW" // ============================================================================= // Register : TIMER_INTS // Description : Interrupt status after masking & forcing -#define TIMER_INTS_OFFSET 0x00000040 -#define TIMER_INTS_BITS 0x0000000f -#define TIMER_INTS_RESET 0x00000000 +#define TIMER_INTS_OFFSET _u(0x00000040) +#define TIMER_INTS_BITS _u(0x0000000f) +#define TIMER_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TIMER_INTS_ALARM_3 // Description : None -#define TIMER_INTS_ALARM_3_RESET 0x0 -#define TIMER_INTS_ALARM_3_BITS 0x00000008 -#define TIMER_INTS_ALARM_3_MSB 3 -#define TIMER_INTS_ALARM_3_LSB 3 +#define TIMER_INTS_ALARM_3_RESET _u(0x0) +#define TIMER_INTS_ALARM_3_BITS _u(0x00000008) +#define TIMER_INTS_ALARM_3_MSB _u(3) +#define TIMER_INTS_ALARM_3_LSB _u(3) #define TIMER_INTS_ALARM_3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TIMER_INTS_ALARM_2 // Description : None -#define TIMER_INTS_ALARM_2_RESET 0x0 -#define TIMER_INTS_ALARM_2_BITS 0x00000004 -#define TIMER_INTS_ALARM_2_MSB 2 -#define TIMER_INTS_ALARM_2_LSB 2 +#define TIMER_INTS_ALARM_2_RESET _u(0x0) +#define TIMER_INTS_ALARM_2_BITS _u(0x00000004) +#define TIMER_INTS_ALARM_2_MSB _u(2) +#define TIMER_INTS_ALARM_2_LSB _u(2) #define TIMER_INTS_ALARM_2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TIMER_INTS_ALARM_1 // Description : None -#define TIMER_INTS_ALARM_1_RESET 0x0 -#define TIMER_INTS_ALARM_1_BITS 0x00000002 -#define TIMER_INTS_ALARM_1_MSB 1 -#define TIMER_INTS_ALARM_1_LSB 1 +#define TIMER_INTS_ALARM_1_RESET _u(0x0) +#define TIMER_INTS_ALARM_1_BITS _u(0x00000002) +#define TIMER_INTS_ALARM_1_MSB _u(1) +#define TIMER_INTS_ALARM_1_LSB _u(1) #define TIMER_INTS_ALARM_1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TIMER_INTS_ALARM_0 // Description : None -#define TIMER_INTS_ALARM_0_RESET 0x0 -#define TIMER_INTS_ALARM_0_BITS 0x00000001 -#define TIMER_INTS_ALARM_0_MSB 0 -#define TIMER_INTS_ALARM_0_LSB 0 +#define TIMER_INTS_ALARM_0_RESET _u(0x0) +#define TIMER_INTS_ALARM_0_BITS _u(0x00000001) +#define TIMER_INTS_ALARM_0_MSB _u(0) +#define TIMER_INTS_ALARM_0_LSB _u(0) #define TIMER_INTS_ALARM_0_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_TIMER_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/uart.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/uart.h index 8fde5d197..409f59821 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/uart.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/uart.h @@ -14,9 +14,9 @@ // ============================================================================= // Register : UART_UARTDR // Description : Data Register, UARTDR -#define UART_UARTDR_OFFSET 0x00000000 -#define UART_UARTDR_BITS 0x00000fff -#define UART_UARTDR_RESET 0x00000000 +#define UART_UARTDR_OFFSET _u(0x00000000) +#define UART_UARTDR_BITS _u(0x00000fff) +#define UART_UARTDR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTDR_OE // Description : Overrun error. This bit is set to 1 if data is received and the @@ -24,9 +24,9 @@ // is an empty space in the FIFO and a new character can be // written to it. #define UART_UARTDR_OE_RESET "-" -#define UART_UARTDR_OE_BITS 0x00000800 -#define UART_UARTDR_OE_MSB 11 -#define UART_UARTDR_OE_LSB 11 +#define UART_UARTDR_OE_BITS _u(0x00000800) +#define UART_UARTDR_OE_MSB _u(11) +#define UART_UARTDR_OE_LSB _u(11) #define UART_UARTDR_OE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTDR_BE @@ -40,9 +40,9 @@ // goes to a 1 (marking state), and the next valid start bit is // received. #define UART_UARTDR_BE_RESET "-" -#define UART_UARTDR_BE_BITS 0x00000400 -#define UART_UARTDR_BE_MSB 10 -#define UART_UARTDR_BE_LSB 10 +#define UART_UARTDR_BE_BITS _u(0x00000400) +#define UART_UARTDR_BE_MSB _u(10) +#define UART_UARTDR_BE_LSB _u(10) #define UART_UARTDR_BE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTDR_PE @@ -52,9 +52,9 @@ // FIFO mode, this error is associated with the character at the // top of the FIFO. #define UART_UARTDR_PE_RESET "-" -#define UART_UARTDR_PE_BITS 0x00000200 -#define UART_UARTDR_PE_MSB 9 -#define UART_UARTDR_PE_LSB 9 +#define UART_UARTDR_PE_BITS _u(0x00000200) +#define UART_UARTDR_PE_MSB _u(9) +#define UART_UARTDR_PE_LSB _u(9) #define UART_UARTDR_PE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTDR_FE @@ -63,24 +63,24 @@ // 1). In FIFO mode, this error is associated with the character // at the top of the FIFO. #define UART_UARTDR_FE_RESET "-" -#define UART_UARTDR_FE_BITS 0x00000100 -#define UART_UARTDR_FE_MSB 8 -#define UART_UARTDR_FE_LSB 8 +#define UART_UARTDR_FE_BITS _u(0x00000100) +#define UART_UARTDR_FE_MSB _u(8) +#define UART_UARTDR_FE_LSB _u(8) #define UART_UARTDR_FE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTDR_DATA // Description : Receive (read) data character. Transmit (write) data character. #define UART_UARTDR_DATA_RESET "-" -#define UART_UARTDR_DATA_BITS 0x000000ff -#define UART_UARTDR_DATA_MSB 7 -#define UART_UARTDR_DATA_LSB 0 +#define UART_UARTDR_DATA_BITS _u(0x000000ff) +#define UART_UARTDR_DATA_MSB _u(7) +#define UART_UARTDR_DATA_LSB _u(0) #define UART_UARTDR_DATA_ACCESS "RWF" // ============================================================================= // Register : UART_UARTRSR // Description : Receive Status Register/Error Clear Register, UARTRSR/UARTECR -#define UART_UARTRSR_OFFSET 0x00000004 -#define UART_UARTRSR_BITS 0x0000000f -#define UART_UARTRSR_RESET 0x00000000 +#define UART_UARTRSR_OFFSET _u(0x00000004) +#define UART_UARTRSR_BITS _u(0x0000000f) +#define UART_UARTRSR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTRSR_OE // Description : Overrun error. This bit is set to 1 if data is received and the @@ -89,10 +89,10 @@ // written when the FIFO is full, only the contents of the shift // register are overwritten. The CPU must now read the data, to // empty the FIFO. -#define UART_UARTRSR_OE_RESET 0x0 -#define UART_UARTRSR_OE_BITS 0x00000008 -#define UART_UARTRSR_OE_MSB 3 -#define UART_UARTRSR_OE_LSB 3 +#define UART_UARTRSR_OE_RESET _u(0x0) +#define UART_UARTRSR_OE_BITS _u(0x00000008) +#define UART_UARTRSR_OE_MSB _u(3) +#define UART_UARTRSR_OE_LSB _u(3) #define UART_UARTRSR_OE_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTRSR_BE @@ -106,10 +106,10 @@ // next character is only enabled after the receive data input // goes to a 1 (marking state) and the next valid start bit is // received. -#define UART_UARTRSR_BE_RESET 0x0 -#define UART_UARTRSR_BE_BITS 0x00000004 -#define UART_UARTRSR_BE_MSB 2 -#define UART_UARTRSR_BE_LSB 2 +#define UART_UARTRSR_BE_RESET _u(0x0) +#define UART_UARTRSR_BE_BITS _u(0x00000004) +#define UART_UARTRSR_BE_MSB _u(2) +#define UART_UARTRSR_BE_LSB _u(2) #define UART_UARTRSR_BE_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTRSR_PE @@ -118,10 +118,10 @@ // EPS and SPS bits in the Line Control Register, UARTLCR_H. This // bit is cleared to 0 by a write to UARTECR. In FIFO mode, this // error is associated with the character at the top of the FIFO. -#define UART_UARTRSR_PE_RESET 0x0 -#define UART_UARTRSR_PE_BITS 0x00000002 -#define UART_UARTRSR_PE_MSB 1 -#define UART_UARTRSR_PE_LSB 1 +#define UART_UARTRSR_PE_RESET _u(0x0) +#define UART_UARTRSR_PE_BITS _u(0x00000002) +#define UART_UARTRSR_PE_MSB _u(1) +#define UART_UARTRSR_PE_LSB _u(1) #define UART_UARTRSR_PE_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTRSR_FE @@ -130,26 +130,26 @@ // 1). This bit is cleared to 0 by a write to UARTECR. In FIFO // mode, this error is associated with the character at the top of // the FIFO. -#define UART_UARTRSR_FE_RESET 0x0 -#define UART_UARTRSR_FE_BITS 0x00000001 -#define UART_UARTRSR_FE_MSB 0 -#define UART_UARTRSR_FE_LSB 0 +#define UART_UARTRSR_FE_RESET _u(0x0) +#define UART_UARTRSR_FE_BITS _u(0x00000001) +#define UART_UARTRSR_FE_MSB _u(0) +#define UART_UARTRSR_FE_LSB _u(0) #define UART_UARTRSR_FE_ACCESS "WC" // ============================================================================= // Register : UART_UARTFR // Description : Flag Register, UARTFR -#define UART_UARTFR_OFFSET 0x00000018 -#define UART_UARTFR_BITS 0x000001ff -#define UART_UARTFR_RESET 0x00000090 +#define UART_UARTFR_OFFSET _u(0x00000018) +#define UART_UARTFR_BITS _u(0x000001ff) +#define UART_UARTFR_RESET _u(0x00000090) // ----------------------------------------------------------------------------- // Field : UART_UARTFR_RI // Description : Ring indicator. This bit is the complement of the UART ring // indicator, nUARTRI, modem status input. That is, the bit is 1 // when nUARTRI is LOW. #define UART_UARTFR_RI_RESET "-" -#define UART_UARTFR_RI_BITS 0x00000100 -#define UART_UARTFR_RI_MSB 8 -#define UART_UARTFR_RI_LSB 8 +#define UART_UARTFR_RI_BITS _u(0x00000100) +#define UART_UARTFR_RI_MSB _u(8) +#define UART_UARTFR_RI_LSB _u(8) #define UART_UARTFR_RI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTFR_TXFE @@ -159,10 +159,10 @@ // holding register is empty. If the FIFO is enabled, the TXFE bit // is set when the transmit FIFO is empty. This bit does not // indicate if there is data in the transmit shift register. -#define UART_UARTFR_TXFE_RESET 0x1 -#define UART_UARTFR_TXFE_BITS 0x00000080 -#define UART_UARTFR_TXFE_MSB 7 -#define UART_UARTFR_TXFE_LSB 7 +#define UART_UARTFR_TXFE_RESET _u(0x1) +#define UART_UARTFR_TXFE_BITS _u(0x00000080) +#define UART_UARTFR_TXFE_MSB _u(7) +#define UART_UARTFR_TXFE_LSB _u(7) #define UART_UARTFR_TXFE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTFR_RXFF @@ -171,10 +171,10 @@ // disabled, this bit is set when the receive holding register is // full. If the FIFO is enabled, the RXFF bit is set when the // receive FIFO is full. -#define UART_UARTFR_RXFF_RESET 0x0 -#define UART_UARTFR_RXFF_BITS 0x00000040 -#define UART_UARTFR_RXFF_MSB 6 -#define UART_UARTFR_RXFF_LSB 6 +#define UART_UARTFR_RXFF_RESET _u(0x0) +#define UART_UARTFR_RXFF_BITS _u(0x00000040) +#define UART_UARTFR_RXFF_MSB _u(6) +#define UART_UARTFR_RXFF_LSB _u(6) #define UART_UARTFR_RXFF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTFR_TXFF @@ -183,10 +183,10 @@ // disabled, this bit is set when the transmit holding register is // full. If the FIFO is enabled, the TXFF bit is set when the // transmit FIFO is full. -#define UART_UARTFR_TXFF_RESET 0x0 -#define UART_UARTFR_TXFF_BITS 0x00000020 -#define UART_UARTFR_TXFF_MSB 5 -#define UART_UARTFR_TXFF_LSB 5 +#define UART_UARTFR_TXFF_RESET _u(0x0) +#define UART_UARTFR_TXFF_BITS _u(0x00000020) +#define UART_UARTFR_TXFF_MSB _u(5) +#define UART_UARTFR_TXFF_LSB _u(5) #define UART_UARTFR_TXFF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTFR_RXFE @@ -195,10 +195,10 @@ // disabled, this bit is set when the receive holding register is // empty. If the FIFO is enabled, the RXFE bit is set when the // receive FIFO is empty. -#define UART_UARTFR_RXFE_RESET 0x1 -#define UART_UARTFR_RXFE_BITS 0x00000010 -#define UART_UARTFR_RXFE_MSB 4 -#define UART_UARTFR_RXFE_LSB 4 +#define UART_UARTFR_RXFE_RESET _u(0x1) +#define UART_UARTFR_RXFE_BITS _u(0x00000010) +#define UART_UARTFR_RXFE_MSB _u(4) +#define UART_UARTFR_RXFE_LSB _u(4) #define UART_UARTFR_RXFE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTFR_BUSY @@ -207,10 +207,10 @@ // byte, including all the stop bits, has been sent from the shift // register. This bit is set as soon as the transmit FIFO becomes // non-empty, regardless of whether the UART is enabled or not. -#define UART_UARTFR_BUSY_RESET 0x0 -#define UART_UARTFR_BUSY_BITS 0x00000008 -#define UART_UARTFR_BUSY_MSB 3 -#define UART_UARTFR_BUSY_LSB 3 +#define UART_UARTFR_BUSY_RESET _u(0x0) +#define UART_UARTFR_BUSY_BITS _u(0x00000008) +#define UART_UARTFR_BUSY_MSB _u(3) +#define UART_UARTFR_BUSY_LSB _u(3) #define UART_UARTFR_BUSY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTFR_DCD @@ -218,9 +218,9 @@ // data carrier detect, nUARTDCD, modem status input. That is, the // bit is 1 when nUARTDCD is LOW. #define UART_UARTFR_DCD_RESET "-" -#define UART_UARTFR_DCD_BITS 0x00000004 -#define UART_UARTFR_DCD_MSB 2 -#define UART_UARTFR_DCD_LSB 2 +#define UART_UARTFR_DCD_BITS _u(0x00000004) +#define UART_UARTFR_DCD_MSB _u(2) +#define UART_UARTFR_DCD_LSB _u(2) #define UART_UARTFR_DCD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTFR_DSR @@ -228,9 +228,9 @@ // ready, nUARTDSR, modem status input. That is, the bit is 1 when // nUARTDSR is LOW. #define UART_UARTFR_DSR_RESET "-" -#define UART_UARTFR_DSR_BITS 0x00000002 -#define UART_UARTFR_DSR_MSB 1 -#define UART_UARTFR_DSR_LSB 1 +#define UART_UARTFR_DSR_BITS _u(0x00000002) +#define UART_UARTFR_DSR_MSB _u(1) +#define UART_UARTFR_DSR_LSB _u(1) #define UART_UARTFR_DSR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTFR_CTS @@ -238,61 +238,61 @@ // send, nUARTCTS, modem status input. That is, the bit is 1 when // nUARTCTS is LOW. #define UART_UARTFR_CTS_RESET "-" -#define UART_UARTFR_CTS_BITS 0x00000001 -#define UART_UARTFR_CTS_MSB 0 -#define UART_UARTFR_CTS_LSB 0 +#define UART_UARTFR_CTS_BITS _u(0x00000001) +#define UART_UARTFR_CTS_MSB _u(0) +#define UART_UARTFR_CTS_LSB _u(0) #define UART_UARTFR_CTS_ACCESS "RO" // ============================================================================= // Register : UART_UARTILPR // Description : IrDA Low-Power Counter Register, UARTILPR -#define UART_UARTILPR_OFFSET 0x00000020 -#define UART_UARTILPR_BITS 0x000000ff -#define UART_UARTILPR_RESET 0x00000000 +#define UART_UARTILPR_OFFSET _u(0x00000020) +#define UART_UARTILPR_BITS _u(0x000000ff) +#define UART_UARTILPR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTILPR_ILPDVSR // Description : 8-bit low-power divisor value. These bits are cleared to 0 at // reset. -#define UART_UARTILPR_ILPDVSR_RESET 0x00 -#define UART_UARTILPR_ILPDVSR_BITS 0x000000ff -#define UART_UARTILPR_ILPDVSR_MSB 7 -#define UART_UARTILPR_ILPDVSR_LSB 0 +#define UART_UARTILPR_ILPDVSR_RESET _u(0x00) +#define UART_UARTILPR_ILPDVSR_BITS _u(0x000000ff) +#define UART_UARTILPR_ILPDVSR_MSB _u(7) +#define UART_UARTILPR_ILPDVSR_LSB _u(0) #define UART_UARTILPR_ILPDVSR_ACCESS "RW" // ============================================================================= // Register : UART_UARTIBRD // Description : Integer Baud Rate Register, UARTIBRD -#define UART_UARTIBRD_OFFSET 0x00000024 -#define UART_UARTIBRD_BITS 0x0000ffff -#define UART_UARTIBRD_RESET 0x00000000 +#define UART_UARTIBRD_OFFSET _u(0x00000024) +#define UART_UARTIBRD_BITS _u(0x0000ffff) +#define UART_UARTIBRD_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTIBRD_BAUD_DIVINT // Description : The integer baud rate divisor. These bits are cleared to 0 on // reset. -#define UART_UARTIBRD_BAUD_DIVINT_RESET 0x0000 -#define UART_UARTIBRD_BAUD_DIVINT_BITS 0x0000ffff -#define UART_UARTIBRD_BAUD_DIVINT_MSB 15 -#define UART_UARTIBRD_BAUD_DIVINT_LSB 0 +#define UART_UARTIBRD_BAUD_DIVINT_RESET _u(0x0000) +#define UART_UARTIBRD_BAUD_DIVINT_BITS _u(0x0000ffff) +#define UART_UARTIBRD_BAUD_DIVINT_MSB _u(15) +#define UART_UARTIBRD_BAUD_DIVINT_LSB _u(0) #define UART_UARTIBRD_BAUD_DIVINT_ACCESS "RW" // ============================================================================= // Register : UART_UARTFBRD // Description : Fractional Baud Rate Register, UARTFBRD -#define UART_UARTFBRD_OFFSET 0x00000028 -#define UART_UARTFBRD_BITS 0x0000003f -#define UART_UARTFBRD_RESET 0x00000000 +#define UART_UARTFBRD_OFFSET _u(0x00000028) +#define UART_UARTFBRD_BITS _u(0x0000003f) +#define UART_UARTFBRD_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTFBRD_BAUD_DIVFRAC // Description : The fractional baud rate divisor. These bits are cleared to 0 // on reset. -#define UART_UARTFBRD_BAUD_DIVFRAC_RESET 0x00 -#define UART_UARTFBRD_BAUD_DIVFRAC_BITS 0x0000003f -#define UART_UARTFBRD_BAUD_DIVFRAC_MSB 5 -#define UART_UARTFBRD_BAUD_DIVFRAC_LSB 0 +#define UART_UARTFBRD_BAUD_DIVFRAC_RESET _u(0x00) +#define UART_UARTFBRD_BAUD_DIVFRAC_BITS _u(0x0000003f) +#define UART_UARTFBRD_BAUD_DIVFRAC_MSB _u(5) +#define UART_UARTFBRD_BAUD_DIVFRAC_LSB _u(0) #define UART_UARTFBRD_BAUD_DIVFRAC_ACCESS "RW" // ============================================================================= // Register : UART_UARTLCR_H // Description : Line Control Register, UARTLCR_H -#define UART_UARTLCR_H_OFFSET 0x0000002c -#define UART_UARTLCR_H_BITS 0x000000ff -#define UART_UARTLCR_H_RESET 0x00000000 +#define UART_UARTLCR_H_OFFSET _u(0x0000002c) +#define UART_UARTLCR_H_BITS _u(0x000000ff) +#define UART_UARTLCR_H_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTLCR_H_SPS // Description : Stick parity select. 0 = stick parity is disabled 1 = either: * @@ -300,40 +300,40 @@ // checked as a 1 * if the EPS bit is 1 then the parity bit is // transmitted and checked as a 0. This bit has no effect when the // PEN bit disables parity checking and generation. -#define UART_UARTLCR_H_SPS_RESET 0x0 -#define UART_UARTLCR_H_SPS_BITS 0x00000080 -#define UART_UARTLCR_H_SPS_MSB 7 -#define UART_UARTLCR_H_SPS_LSB 7 +#define UART_UARTLCR_H_SPS_RESET _u(0x0) +#define UART_UARTLCR_H_SPS_BITS _u(0x00000080) +#define UART_UARTLCR_H_SPS_MSB _u(7) +#define UART_UARTLCR_H_SPS_LSB _u(7) #define UART_UARTLCR_H_SPS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTLCR_H_WLEN // Description : Word length. These bits indicate the number of data bits // transmitted or received in a frame as follows: b11 = 8 bits b10 // = 7 bits b01 = 6 bits b00 = 5 bits. -#define UART_UARTLCR_H_WLEN_RESET 0x0 -#define UART_UARTLCR_H_WLEN_BITS 0x00000060 -#define UART_UARTLCR_H_WLEN_MSB 6 -#define UART_UARTLCR_H_WLEN_LSB 5 +#define UART_UARTLCR_H_WLEN_RESET _u(0x0) +#define UART_UARTLCR_H_WLEN_BITS _u(0x00000060) +#define UART_UARTLCR_H_WLEN_MSB _u(6) +#define UART_UARTLCR_H_WLEN_LSB _u(5) #define UART_UARTLCR_H_WLEN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTLCR_H_FEN // Description : Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, // the FIFOs become 1-byte-deep holding registers 1 = transmit and // receive FIFO buffers are enabled (FIFO mode). -#define UART_UARTLCR_H_FEN_RESET 0x0 -#define UART_UARTLCR_H_FEN_BITS 0x00000010 -#define UART_UARTLCR_H_FEN_MSB 4 -#define UART_UARTLCR_H_FEN_LSB 4 +#define UART_UARTLCR_H_FEN_RESET _u(0x0) +#define UART_UARTLCR_H_FEN_BITS _u(0x00000010) +#define UART_UARTLCR_H_FEN_MSB _u(4) +#define UART_UARTLCR_H_FEN_LSB _u(4) #define UART_UARTLCR_H_FEN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTLCR_H_STP2 // Description : Two stop bits select. If this bit is set to 1, two stop bits // are transmitted at the end of the frame. The receive logic does // not check for two stop bits being received. -#define UART_UARTLCR_H_STP2_RESET 0x0 -#define UART_UARTLCR_H_STP2_BITS 0x00000008 -#define UART_UARTLCR_H_STP2_MSB 3 -#define UART_UARTLCR_H_STP2_LSB 3 +#define UART_UARTLCR_H_STP2_RESET _u(0x0) +#define UART_UARTLCR_H_STP2_BITS _u(0x00000008) +#define UART_UARTLCR_H_STP2_MSB _u(3) +#define UART_UARTLCR_H_STP2_LSB _u(3) #define UART_UARTLCR_H_STP2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTLCR_H_EPS @@ -344,20 +344,20 @@ // an even number of 1s in the data and parity bits. This bit has // no effect when the PEN bit disables parity checking and // generation. -#define UART_UARTLCR_H_EPS_RESET 0x0 -#define UART_UARTLCR_H_EPS_BITS 0x00000004 -#define UART_UARTLCR_H_EPS_MSB 2 -#define UART_UARTLCR_H_EPS_LSB 2 +#define UART_UARTLCR_H_EPS_RESET _u(0x0) +#define UART_UARTLCR_H_EPS_BITS _u(0x00000004) +#define UART_UARTLCR_H_EPS_MSB _u(2) +#define UART_UARTLCR_H_EPS_LSB _u(2) #define UART_UARTLCR_H_EPS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTLCR_H_PEN // Description : Parity enable: 0 = parity is disabled and no parity bit added // to the data frame 1 = parity checking and generation is // enabled. -#define UART_UARTLCR_H_PEN_RESET 0x0 -#define UART_UARTLCR_H_PEN_BITS 0x00000002 -#define UART_UARTLCR_H_PEN_MSB 1 -#define UART_UARTLCR_H_PEN_LSB 1 +#define UART_UARTLCR_H_PEN_RESET _u(0x0) +#define UART_UARTLCR_H_PEN_BITS _u(0x00000002) +#define UART_UARTLCR_H_PEN_MSB _u(1) +#define UART_UARTLCR_H_PEN_LSB _u(1) #define UART_UARTLCR_H_PEN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTLCR_H_BRK @@ -366,46 +366,46 @@ // the current character. For the proper execution of the break // command, the software must set this bit for at least two // complete frames. For normal use, this bit must be cleared to 0. -#define UART_UARTLCR_H_BRK_RESET 0x0 -#define UART_UARTLCR_H_BRK_BITS 0x00000001 -#define UART_UARTLCR_H_BRK_MSB 0 -#define UART_UARTLCR_H_BRK_LSB 0 +#define UART_UARTLCR_H_BRK_RESET _u(0x0) +#define UART_UARTLCR_H_BRK_BITS _u(0x00000001) +#define UART_UARTLCR_H_BRK_MSB _u(0) +#define UART_UARTLCR_H_BRK_LSB _u(0) #define UART_UARTLCR_H_BRK_ACCESS "RW" // ============================================================================= // Register : UART_UARTCR // Description : Control Register, UARTCR -#define UART_UARTCR_OFFSET 0x00000030 -#define UART_UARTCR_BITS 0x0000ff87 -#define UART_UARTCR_RESET 0x00000300 +#define UART_UARTCR_OFFSET _u(0x00000030) +#define UART_UARTCR_BITS _u(0x0000ff87) +#define UART_UARTCR_RESET _u(0x00000300) // ----------------------------------------------------------------------------- // Field : UART_UARTCR_CTSEN // Description : CTS hardware flow control enable. If this bit is set to 1, CTS // hardware flow control is enabled. Data is only transmitted when // the nUARTCTS signal is asserted. -#define UART_UARTCR_CTSEN_RESET 0x0 -#define UART_UARTCR_CTSEN_BITS 0x00008000 -#define UART_UARTCR_CTSEN_MSB 15 -#define UART_UARTCR_CTSEN_LSB 15 +#define UART_UARTCR_CTSEN_RESET _u(0x0) +#define UART_UARTCR_CTSEN_BITS _u(0x00008000) +#define UART_UARTCR_CTSEN_MSB _u(15) +#define UART_UARTCR_CTSEN_LSB _u(15) #define UART_UARTCR_CTSEN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_RTSEN // Description : RTS hardware flow control enable. If this bit is set to 1, RTS // hardware flow control is enabled. Data is only requested when // there is space in the receive FIFO for it to be received. -#define UART_UARTCR_RTSEN_RESET 0x0 -#define UART_UARTCR_RTSEN_BITS 0x00004000 -#define UART_UARTCR_RTSEN_MSB 14 -#define UART_UARTCR_RTSEN_LSB 14 +#define UART_UARTCR_RTSEN_RESET _u(0x0) +#define UART_UARTCR_RTSEN_BITS _u(0x00004000) +#define UART_UARTCR_RTSEN_MSB _u(14) +#define UART_UARTCR_RTSEN_LSB _u(14) #define UART_UARTCR_RTSEN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_OUT2 // Description : This bit is the complement of the UART Out2 (nUARTOut2) modem // status output. That is, when the bit is programmed to a 1, the // output is 0. For DTE this can be used as Ring Indicator (RI). -#define UART_UARTCR_OUT2_RESET 0x0 -#define UART_UARTCR_OUT2_BITS 0x00002000 -#define UART_UARTCR_OUT2_MSB 13 -#define UART_UARTCR_OUT2_LSB 13 +#define UART_UARTCR_OUT2_RESET _u(0x0) +#define UART_UARTCR_OUT2_BITS _u(0x00002000) +#define UART_UARTCR_OUT2_MSB _u(13) +#define UART_UARTCR_OUT2_LSB _u(13) #define UART_UARTCR_OUT2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_OUT1 @@ -413,30 +413,30 @@ // status output. That is, when the bit is programmed to a 1 the // output is 0. For DTE this can be used as Data Carrier Detect // (DCD). -#define UART_UARTCR_OUT1_RESET 0x0 -#define UART_UARTCR_OUT1_BITS 0x00001000 -#define UART_UARTCR_OUT1_MSB 12 -#define UART_UARTCR_OUT1_LSB 12 +#define UART_UARTCR_OUT1_RESET _u(0x0) +#define UART_UARTCR_OUT1_BITS _u(0x00001000) +#define UART_UARTCR_OUT1_MSB _u(12) +#define UART_UARTCR_OUT1_LSB _u(12) #define UART_UARTCR_OUT1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_RTS // Description : Request to send. This bit is the complement of the UART request // to send, nUARTRTS, modem status output. That is, when the bit // is programmed to a 1 then nUARTRTS is LOW. -#define UART_UARTCR_RTS_RESET 0x0 -#define UART_UARTCR_RTS_BITS 0x00000800 -#define UART_UARTCR_RTS_MSB 11 -#define UART_UARTCR_RTS_LSB 11 +#define UART_UARTCR_RTS_RESET _u(0x0) +#define UART_UARTCR_RTS_BITS _u(0x00000800) +#define UART_UARTCR_RTS_MSB _u(11) +#define UART_UARTCR_RTS_LSB _u(11) #define UART_UARTCR_RTS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_DTR // Description : Data transmit ready. This bit is the complement of the UART // data transmit ready, nUARTDTR, modem status output. That is, // when the bit is programmed to a 1 then nUARTDTR is LOW. -#define UART_UARTCR_DTR_RESET 0x0 -#define UART_UARTCR_DTR_BITS 0x00000400 -#define UART_UARTCR_DTR_MSB 10 -#define UART_UARTCR_DTR_LSB 10 +#define UART_UARTCR_DTR_RESET _u(0x0) +#define UART_UARTCR_DTR_BITS _u(0x00000400) +#define UART_UARTCR_DTR_MSB _u(10) +#define UART_UARTCR_DTR_LSB _u(10) #define UART_UARTCR_DTR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_RXE @@ -445,10 +445,10 @@ // signals or SIR signals depending on the setting of the SIREN // bit. When the UART is disabled in the middle of reception, it // completes the current character before stopping. -#define UART_UARTCR_RXE_RESET 0x1 -#define UART_UARTCR_RXE_BITS 0x00000200 -#define UART_UARTCR_RXE_MSB 9 -#define UART_UARTCR_RXE_LSB 9 +#define UART_UARTCR_RXE_RESET _u(0x1) +#define UART_UARTCR_RXE_BITS _u(0x00000200) +#define UART_UARTCR_RXE_MSB _u(9) +#define UART_UARTCR_RXE_LSB _u(9) #define UART_UARTCR_RXE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_TXE @@ -458,10 +458,10 @@ // SIREN bit. When the UART is disabled in the middle of // transmission, it completes the current character before // stopping. -#define UART_UARTCR_TXE_RESET 0x1 -#define UART_UARTCR_TXE_BITS 0x00000100 -#define UART_UARTCR_TXE_MSB 8 -#define UART_UARTCR_TXE_LSB 8 +#define UART_UARTCR_TXE_RESET _u(0x1) +#define UART_UARTCR_TXE_BITS _u(0x00000100) +#define UART_UARTCR_TXE_MSB _u(8) +#define UART_UARTCR_TXE_LSB _u(8) #define UART_UARTCR_TXE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_LBE @@ -479,10 +479,10 @@ // mode or UART mode, when this bit is set, the modem outputs are // also fed through to the modem inputs. This bit is cleared to 0 // on reset, to disable loopback. -#define UART_UARTCR_LBE_RESET 0x0 -#define UART_UARTCR_LBE_BITS 0x00000080 -#define UART_UARTCR_LBE_MSB 7 -#define UART_UARTCR_LBE_LSB 7 +#define UART_UARTCR_LBE_RESET _u(0x0) +#define UART_UARTCR_LBE_BITS _u(0x00000080) +#define UART_UARTCR_LBE_MSB _u(7) +#define UART_UARTCR_LBE_LSB _u(7) #define UART_UARTCR_LBE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_SIRLP @@ -494,10 +494,10 @@ // the IrLPBaud16 input signal, regardless of the selected bit // rate. Setting this bit uses less power, but might reduce // transmission distances. -#define UART_UARTCR_SIRLP_RESET 0x0 -#define UART_UARTCR_SIRLP_BITS 0x00000004 -#define UART_UARTCR_SIRLP_MSB 2 -#define UART_UARTCR_SIRLP_LSB 2 +#define UART_UARTCR_SIRLP_RESET _u(0x0) +#define UART_UARTCR_SIRLP_BITS _u(0x00000004) +#define UART_UARTCR_SIRLP_MSB _u(2) +#define UART_UARTCR_SIRLP_LSB _u(2) #define UART_UARTCR_SIRLP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_SIREN @@ -508,10 +508,10 @@ // HIGH, in the marking state. Signal transitions on UARTRXD or // modem status inputs have no effect. This bit has no effect if // the UARTEN bit disables the UART. -#define UART_UARTCR_SIREN_RESET 0x0 -#define UART_UARTCR_SIREN_BITS 0x00000002 -#define UART_UARTCR_SIREN_MSB 1 -#define UART_UARTCR_SIREN_LSB 1 +#define UART_UARTCR_SIREN_RESET _u(0x0) +#define UART_UARTCR_SIREN_BITS _u(0x00000002) +#define UART_UARTCR_SIREN_MSB _u(1) +#define UART_UARTCR_SIREN_LSB _u(1) #define UART_UARTCR_SIREN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTCR_UARTEN @@ -520,17 +520,17 @@ // current character before stopping. 1 = the UART is enabled. // Data transmission and reception occurs for either UART signals // or SIR signals depending on the setting of the SIREN bit. -#define UART_UARTCR_UARTEN_RESET 0x0 -#define UART_UARTCR_UARTEN_BITS 0x00000001 -#define UART_UARTCR_UARTEN_MSB 0 -#define UART_UARTCR_UARTEN_LSB 0 +#define UART_UARTCR_UARTEN_RESET _u(0x0) +#define UART_UARTCR_UARTEN_BITS _u(0x00000001) +#define UART_UARTCR_UARTEN_MSB _u(0) +#define UART_UARTCR_UARTEN_LSB _u(0) #define UART_UARTCR_UARTEN_ACCESS "RW" // ============================================================================= // Register : UART_UARTIFLS // Description : Interrupt FIFO Level Select Register, UARTIFLS -#define UART_UARTIFLS_OFFSET 0x00000034 -#define UART_UARTIFLS_BITS 0x0000003f -#define UART_UARTIFLS_RESET 0x00000012 +#define UART_UARTIFLS_OFFSET _u(0x00000034) +#define UART_UARTIFLS_BITS _u(0x0000003f) +#define UART_UARTIFLS_RESET _u(0x00000012) // ----------------------------------------------------------------------------- // Field : UART_UARTIFLS_RXIFLSEL // Description : Receive interrupt FIFO level select. The trigger points for the @@ -539,10 +539,10 @@ // Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes // >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full // b101-b111 = reserved. -#define UART_UARTIFLS_RXIFLSEL_RESET 0x2 -#define UART_UARTIFLS_RXIFLSEL_BITS 0x00000038 -#define UART_UARTIFLS_RXIFLSEL_MSB 5 -#define UART_UARTIFLS_RXIFLSEL_LSB 3 +#define UART_UARTIFLS_RXIFLSEL_RESET _u(0x2) +#define UART_UARTIFLS_RXIFLSEL_BITS _u(0x00000038) +#define UART_UARTIFLS_RXIFLSEL_MSB _u(5) +#define UART_UARTIFLS_RXIFLSEL_LSB _u(3) #define UART_UARTIFLS_RXIFLSEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIFLS_TXIFLSEL @@ -552,597 +552,597 @@ // full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit // FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / // 8 full b101-b111 = reserved. -#define UART_UARTIFLS_TXIFLSEL_RESET 0x2 -#define UART_UARTIFLS_TXIFLSEL_BITS 0x00000007 -#define UART_UARTIFLS_TXIFLSEL_MSB 2 -#define UART_UARTIFLS_TXIFLSEL_LSB 0 +#define UART_UARTIFLS_TXIFLSEL_RESET _u(0x2) +#define UART_UARTIFLS_TXIFLSEL_BITS _u(0x00000007) +#define UART_UARTIFLS_TXIFLSEL_MSB _u(2) +#define UART_UARTIFLS_TXIFLSEL_LSB _u(0) #define UART_UARTIFLS_TXIFLSEL_ACCESS "RW" // ============================================================================= // Register : UART_UARTIMSC // Description : Interrupt Mask Set/Clear Register, UARTIMSC -#define UART_UARTIMSC_OFFSET 0x00000038 -#define UART_UARTIMSC_BITS 0x000007ff -#define UART_UARTIMSC_RESET 0x00000000 +#define UART_UARTIMSC_OFFSET _u(0x00000038) +#define UART_UARTIMSC_BITS _u(0x000007ff) +#define UART_UARTIMSC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_OEIM // Description : Overrun error interrupt mask. A read returns the current mask // for the UARTOEINTR interrupt. On a write of 1, the mask of the // UARTOEINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_OEIM_RESET 0x0 -#define UART_UARTIMSC_OEIM_BITS 0x00000400 -#define UART_UARTIMSC_OEIM_MSB 10 -#define UART_UARTIMSC_OEIM_LSB 10 +#define UART_UARTIMSC_OEIM_RESET _u(0x0) +#define UART_UARTIMSC_OEIM_BITS _u(0x00000400) +#define UART_UARTIMSC_OEIM_MSB _u(10) +#define UART_UARTIMSC_OEIM_LSB _u(10) #define UART_UARTIMSC_OEIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_BEIM // Description : Break error interrupt mask. A read returns the current mask for // the UARTBEINTR interrupt. On a write of 1, the mask of the // UARTBEINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_BEIM_RESET 0x0 -#define UART_UARTIMSC_BEIM_BITS 0x00000200 -#define UART_UARTIMSC_BEIM_MSB 9 -#define UART_UARTIMSC_BEIM_LSB 9 +#define UART_UARTIMSC_BEIM_RESET _u(0x0) +#define UART_UARTIMSC_BEIM_BITS _u(0x00000200) +#define UART_UARTIMSC_BEIM_MSB _u(9) +#define UART_UARTIMSC_BEIM_LSB _u(9) #define UART_UARTIMSC_BEIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_PEIM // Description : Parity error interrupt mask. A read returns the current mask // for the UARTPEINTR interrupt. On a write of 1, the mask of the // UARTPEINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_PEIM_RESET 0x0 -#define UART_UARTIMSC_PEIM_BITS 0x00000100 -#define UART_UARTIMSC_PEIM_MSB 8 -#define UART_UARTIMSC_PEIM_LSB 8 +#define UART_UARTIMSC_PEIM_RESET _u(0x0) +#define UART_UARTIMSC_PEIM_BITS _u(0x00000100) +#define UART_UARTIMSC_PEIM_MSB _u(8) +#define UART_UARTIMSC_PEIM_LSB _u(8) #define UART_UARTIMSC_PEIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_FEIM // Description : Framing error interrupt mask. A read returns the current mask // for the UARTFEINTR interrupt. On a write of 1, the mask of the // UARTFEINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_FEIM_RESET 0x0 -#define UART_UARTIMSC_FEIM_BITS 0x00000080 -#define UART_UARTIMSC_FEIM_MSB 7 -#define UART_UARTIMSC_FEIM_LSB 7 +#define UART_UARTIMSC_FEIM_RESET _u(0x0) +#define UART_UARTIMSC_FEIM_BITS _u(0x00000080) +#define UART_UARTIMSC_FEIM_MSB _u(7) +#define UART_UARTIMSC_FEIM_LSB _u(7) #define UART_UARTIMSC_FEIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_RTIM // Description : Receive timeout interrupt mask. A read returns the current mask // for the UARTRTINTR interrupt. On a write of 1, the mask of the // UARTRTINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_RTIM_RESET 0x0 -#define UART_UARTIMSC_RTIM_BITS 0x00000040 -#define UART_UARTIMSC_RTIM_MSB 6 -#define UART_UARTIMSC_RTIM_LSB 6 +#define UART_UARTIMSC_RTIM_RESET _u(0x0) +#define UART_UARTIMSC_RTIM_BITS _u(0x00000040) +#define UART_UARTIMSC_RTIM_MSB _u(6) +#define UART_UARTIMSC_RTIM_LSB _u(6) #define UART_UARTIMSC_RTIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_TXIM // Description : Transmit interrupt mask. A read returns the current mask for // the UARTTXINTR interrupt. On a write of 1, the mask of the // UARTTXINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_TXIM_RESET 0x0 -#define UART_UARTIMSC_TXIM_BITS 0x00000020 -#define UART_UARTIMSC_TXIM_MSB 5 -#define UART_UARTIMSC_TXIM_LSB 5 +#define UART_UARTIMSC_TXIM_RESET _u(0x0) +#define UART_UARTIMSC_TXIM_BITS _u(0x00000020) +#define UART_UARTIMSC_TXIM_MSB _u(5) +#define UART_UARTIMSC_TXIM_LSB _u(5) #define UART_UARTIMSC_TXIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_RXIM // Description : Receive interrupt mask. A read returns the current mask for the // UARTRXINTR interrupt. On a write of 1, the mask of the // UARTRXINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_RXIM_RESET 0x0 -#define UART_UARTIMSC_RXIM_BITS 0x00000010 -#define UART_UARTIMSC_RXIM_MSB 4 -#define UART_UARTIMSC_RXIM_LSB 4 +#define UART_UARTIMSC_RXIM_RESET _u(0x0) +#define UART_UARTIMSC_RXIM_BITS _u(0x00000010) +#define UART_UARTIMSC_RXIM_MSB _u(4) +#define UART_UARTIMSC_RXIM_LSB _u(4) #define UART_UARTIMSC_RXIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_DSRMIM // Description : nUARTDSR modem interrupt mask. A read returns the current mask // for the UARTDSRINTR interrupt. On a write of 1, the mask of the // UARTDSRINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_DSRMIM_RESET 0x0 -#define UART_UARTIMSC_DSRMIM_BITS 0x00000008 -#define UART_UARTIMSC_DSRMIM_MSB 3 -#define UART_UARTIMSC_DSRMIM_LSB 3 +#define UART_UARTIMSC_DSRMIM_RESET _u(0x0) +#define UART_UARTIMSC_DSRMIM_BITS _u(0x00000008) +#define UART_UARTIMSC_DSRMIM_MSB _u(3) +#define UART_UARTIMSC_DSRMIM_LSB _u(3) #define UART_UARTIMSC_DSRMIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_DCDMIM // Description : nUARTDCD modem interrupt mask. A read returns the current mask // for the UARTDCDINTR interrupt. On a write of 1, the mask of the // UARTDCDINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_DCDMIM_RESET 0x0 -#define UART_UARTIMSC_DCDMIM_BITS 0x00000004 -#define UART_UARTIMSC_DCDMIM_MSB 2 -#define UART_UARTIMSC_DCDMIM_LSB 2 +#define UART_UARTIMSC_DCDMIM_RESET _u(0x0) +#define UART_UARTIMSC_DCDMIM_BITS _u(0x00000004) +#define UART_UARTIMSC_DCDMIM_MSB _u(2) +#define UART_UARTIMSC_DCDMIM_LSB _u(2) #define UART_UARTIMSC_DCDMIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_CTSMIM // Description : nUARTCTS modem interrupt mask. A read returns the current mask // for the UARTCTSINTR interrupt. On a write of 1, the mask of the // UARTCTSINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_CTSMIM_RESET 0x0 -#define UART_UARTIMSC_CTSMIM_BITS 0x00000002 -#define UART_UARTIMSC_CTSMIM_MSB 1 -#define UART_UARTIMSC_CTSMIM_LSB 1 +#define UART_UARTIMSC_CTSMIM_RESET _u(0x0) +#define UART_UARTIMSC_CTSMIM_BITS _u(0x00000002) +#define UART_UARTIMSC_CTSMIM_MSB _u(1) +#define UART_UARTIMSC_CTSMIM_LSB _u(1) #define UART_UARTIMSC_CTSMIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTIMSC_RIMIM // Description : nUARTRI modem interrupt mask. A read returns the current mask // for the UARTRIINTR interrupt. On a write of 1, the mask of the // UARTRIINTR interrupt is set. A write of 0 clears the mask. -#define UART_UARTIMSC_RIMIM_RESET 0x0 -#define UART_UARTIMSC_RIMIM_BITS 0x00000001 -#define UART_UARTIMSC_RIMIM_MSB 0 -#define UART_UARTIMSC_RIMIM_LSB 0 +#define UART_UARTIMSC_RIMIM_RESET _u(0x0) +#define UART_UARTIMSC_RIMIM_BITS _u(0x00000001) +#define UART_UARTIMSC_RIMIM_MSB _u(0) +#define UART_UARTIMSC_RIMIM_LSB _u(0) #define UART_UARTIMSC_RIMIM_ACCESS "RW" // ============================================================================= // Register : UART_UARTRIS // Description : Raw Interrupt Status Register, UARTRIS -#define UART_UARTRIS_OFFSET 0x0000003c -#define UART_UARTRIS_BITS 0x000007ff -#define UART_UARTRIS_RESET 0x00000000 +#define UART_UARTRIS_OFFSET _u(0x0000003c) +#define UART_UARTRIS_BITS _u(0x000007ff) +#define UART_UARTRIS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_OERIS // Description : Overrun error interrupt status. Returns the raw interrupt state // of the UARTOEINTR interrupt. -#define UART_UARTRIS_OERIS_RESET 0x0 -#define UART_UARTRIS_OERIS_BITS 0x00000400 -#define UART_UARTRIS_OERIS_MSB 10 -#define UART_UARTRIS_OERIS_LSB 10 +#define UART_UARTRIS_OERIS_RESET _u(0x0) +#define UART_UARTRIS_OERIS_BITS _u(0x00000400) +#define UART_UARTRIS_OERIS_MSB _u(10) +#define UART_UARTRIS_OERIS_LSB _u(10) #define UART_UARTRIS_OERIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_BERIS // Description : Break error interrupt status. Returns the raw interrupt state // of the UARTBEINTR interrupt. -#define UART_UARTRIS_BERIS_RESET 0x0 -#define UART_UARTRIS_BERIS_BITS 0x00000200 -#define UART_UARTRIS_BERIS_MSB 9 -#define UART_UARTRIS_BERIS_LSB 9 +#define UART_UARTRIS_BERIS_RESET _u(0x0) +#define UART_UARTRIS_BERIS_BITS _u(0x00000200) +#define UART_UARTRIS_BERIS_MSB _u(9) +#define UART_UARTRIS_BERIS_LSB _u(9) #define UART_UARTRIS_BERIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_PERIS // Description : Parity error interrupt status. Returns the raw interrupt state // of the UARTPEINTR interrupt. -#define UART_UARTRIS_PERIS_RESET 0x0 -#define UART_UARTRIS_PERIS_BITS 0x00000100 -#define UART_UARTRIS_PERIS_MSB 8 -#define UART_UARTRIS_PERIS_LSB 8 +#define UART_UARTRIS_PERIS_RESET _u(0x0) +#define UART_UARTRIS_PERIS_BITS _u(0x00000100) +#define UART_UARTRIS_PERIS_MSB _u(8) +#define UART_UARTRIS_PERIS_LSB _u(8) #define UART_UARTRIS_PERIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_FERIS // Description : Framing error interrupt status. Returns the raw interrupt state // of the UARTFEINTR interrupt. -#define UART_UARTRIS_FERIS_RESET 0x0 -#define UART_UARTRIS_FERIS_BITS 0x00000080 -#define UART_UARTRIS_FERIS_MSB 7 -#define UART_UARTRIS_FERIS_LSB 7 +#define UART_UARTRIS_FERIS_RESET _u(0x0) +#define UART_UARTRIS_FERIS_BITS _u(0x00000080) +#define UART_UARTRIS_FERIS_MSB _u(7) +#define UART_UARTRIS_FERIS_LSB _u(7) #define UART_UARTRIS_FERIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_RTRIS // Description : Receive timeout interrupt status. Returns the raw interrupt // state of the UARTRTINTR interrupt. a -#define UART_UARTRIS_RTRIS_RESET 0x0 -#define UART_UARTRIS_RTRIS_BITS 0x00000040 -#define UART_UARTRIS_RTRIS_MSB 6 -#define UART_UARTRIS_RTRIS_LSB 6 +#define UART_UARTRIS_RTRIS_RESET _u(0x0) +#define UART_UARTRIS_RTRIS_BITS _u(0x00000040) +#define UART_UARTRIS_RTRIS_MSB _u(6) +#define UART_UARTRIS_RTRIS_LSB _u(6) #define UART_UARTRIS_RTRIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_TXRIS // Description : Transmit interrupt status. Returns the raw interrupt state of // the UARTTXINTR interrupt. -#define UART_UARTRIS_TXRIS_RESET 0x0 -#define UART_UARTRIS_TXRIS_BITS 0x00000020 -#define UART_UARTRIS_TXRIS_MSB 5 -#define UART_UARTRIS_TXRIS_LSB 5 +#define UART_UARTRIS_TXRIS_RESET _u(0x0) +#define UART_UARTRIS_TXRIS_BITS _u(0x00000020) +#define UART_UARTRIS_TXRIS_MSB _u(5) +#define UART_UARTRIS_TXRIS_LSB _u(5) #define UART_UARTRIS_TXRIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_RXRIS // Description : Receive interrupt status. Returns the raw interrupt state of // the UARTRXINTR interrupt. -#define UART_UARTRIS_RXRIS_RESET 0x0 -#define UART_UARTRIS_RXRIS_BITS 0x00000010 -#define UART_UARTRIS_RXRIS_MSB 4 -#define UART_UARTRIS_RXRIS_LSB 4 +#define UART_UARTRIS_RXRIS_RESET _u(0x0) +#define UART_UARTRIS_RXRIS_BITS _u(0x00000010) +#define UART_UARTRIS_RXRIS_MSB _u(4) +#define UART_UARTRIS_RXRIS_LSB _u(4) #define UART_UARTRIS_RXRIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_DSRRMIS // Description : nUARTDSR modem interrupt status. Returns the raw interrupt // state of the UARTDSRINTR interrupt. #define UART_UARTRIS_DSRRMIS_RESET "-" -#define UART_UARTRIS_DSRRMIS_BITS 0x00000008 -#define UART_UARTRIS_DSRRMIS_MSB 3 -#define UART_UARTRIS_DSRRMIS_LSB 3 +#define UART_UARTRIS_DSRRMIS_BITS _u(0x00000008) +#define UART_UARTRIS_DSRRMIS_MSB _u(3) +#define UART_UARTRIS_DSRRMIS_LSB _u(3) #define UART_UARTRIS_DSRRMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_DCDRMIS // Description : nUARTDCD modem interrupt status. Returns the raw interrupt // state of the UARTDCDINTR interrupt. #define UART_UARTRIS_DCDRMIS_RESET "-" -#define UART_UARTRIS_DCDRMIS_BITS 0x00000004 -#define UART_UARTRIS_DCDRMIS_MSB 2 -#define UART_UARTRIS_DCDRMIS_LSB 2 +#define UART_UARTRIS_DCDRMIS_BITS _u(0x00000004) +#define UART_UARTRIS_DCDRMIS_MSB _u(2) +#define UART_UARTRIS_DCDRMIS_LSB _u(2) #define UART_UARTRIS_DCDRMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_CTSRMIS // Description : nUARTCTS modem interrupt status. Returns the raw interrupt // state of the UARTCTSINTR interrupt. #define UART_UARTRIS_CTSRMIS_RESET "-" -#define UART_UARTRIS_CTSRMIS_BITS 0x00000002 -#define UART_UARTRIS_CTSRMIS_MSB 1 -#define UART_UARTRIS_CTSRMIS_LSB 1 +#define UART_UARTRIS_CTSRMIS_BITS _u(0x00000002) +#define UART_UARTRIS_CTSRMIS_MSB _u(1) +#define UART_UARTRIS_CTSRMIS_LSB _u(1) #define UART_UARTRIS_CTSRMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTRIS_RIRMIS // Description : nUARTRI modem interrupt status. Returns the raw interrupt state // of the UARTRIINTR interrupt. #define UART_UARTRIS_RIRMIS_RESET "-" -#define UART_UARTRIS_RIRMIS_BITS 0x00000001 -#define UART_UARTRIS_RIRMIS_MSB 0 -#define UART_UARTRIS_RIRMIS_LSB 0 +#define UART_UARTRIS_RIRMIS_BITS _u(0x00000001) +#define UART_UARTRIS_RIRMIS_MSB _u(0) +#define UART_UARTRIS_RIRMIS_LSB _u(0) #define UART_UARTRIS_RIRMIS_ACCESS "RO" // ============================================================================= // Register : UART_UARTMIS // Description : Masked Interrupt Status Register, UARTMIS -#define UART_UARTMIS_OFFSET 0x00000040 -#define UART_UARTMIS_BITS 0x000007ff -#define UART_UARTMIS_RESET 0x00000000 +#define UART_UARTMIS_OFFSET _u(0x00000040) +#define UART_UARTMIS_BITS _u(0x000007ff) +#define UART_UARTMIS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_OEMIS // Description : Overrun error masked interrupt status. Returns the masked // interrupt state of the UARTOEINTR interrupt. -#define UART_UARTMIS_OEMIS_RESET 0x0 -#define UART_UARTMIS_OEMIS_BITS 0x00000400 -#define UART_UARTMIS_OEMIS_MSB 10 -#define UART_UARTMIS_OEMIS_LSB 10 +#define UART_UARTMIS_OEMIS_RESET _u(0x0) +#define UART_UARTMIS_OEMIS_BITS _u(0x00000400) +#define UART_UARTMIS_OEMIS_MSB _u(10) +#define UART_UARTMIS_OEMIS_LSB _u(10) #define UART_UARTMIS_OEMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_BEMIS // Description : Break error masked interrupt status. Returns the masked // interrupt state of the UARTBEINTR interrupt. -#define UART_UARTMIS_BEMIS_RESET 0x0 -#define UART_UARTMIS_BEMIS_BITS 0x00000200 -#define UART_UARTMIS_BEMIS_MSB 9 -#define UART_UARTMIS_BEMIS_LSB 9 +#define UART_UARTMIS_BEMIS_RESET _u(0x0) +#define UART_UARTMIS_BEMIS_BITS _u(0x00000200) +#define UART_UARTMIS_BEMIS_MSB _u(9) +#define UART_UARTMIS_BEMIS_LSB _u(9) #define UART_UARTMIS_BEMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_PEMIS // Description : Parity error masked interrupt status. Returns the masked // interrupt state of the UARTPEINTR interrupt. -#define UART_UARTMIS_PEMIS_RESET 0x0 -#define UART_UARTMIS_PEMIS_BITS 0x00000100 -#define UART_UARTMIS_PEMIS_MSB 8 -#define UART_UARTMIS_PEMIS_LSB 8 +#define UART_UARTMIS_PEMIS_RESET _u(0x0) +#define UART_UARTMIS_PEMIS_BITS _u(0x00000100) +#define UART_UARTMIS_PEMIS_MSB _u(8) +#define UART_UARTMIS_PEMIS_LSB _u(8) #define UART_UARTMIS_PEMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_FEMIS // Description : Framing error masked interrupt status. Returns the masked // interrupt state of the UARTFEINTR interrupt. -#define UART_UARTMIS_FEMIS_RESET 0x0 -#define UART_UARTMIS_FEMIS_BITS 0x00000080 -#define UART_UARTMIS_FEMIS_MSB 7 -#define UART_UARTMIS_FEMIS_LSB 7 +#define UART_UARTMIS_FEMIS_RESET _u(0x0) +#define UART_UARTMIS_FEMIS_BITS _u(0x00000080) +#define UART_UARTMIS_FEMIS_MSB _u(7) +#define UART_UARTMIS_FEMIS_LSB _u(7) #define UART_UARTMIS_FEMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_RTMIS // Description : Receive timeout masked interrupt status. Returns the masked // interrupt state of the UARTRTINTR interrupt. -#define UART_UARTMIS_RTMIS_RESET 0x0 -#define UART_UARTMIS_RTMIS_BITS 0x00000040 -#define UART_UARTMIS_RTMIS_MSB 6 -#define UART_UARTMIS_RTMIS_LSB 6 +#define UART_UARTMIS_RTMIS_RESET _u(0x0) +#define UART_UARTMIS_RTMIS_BITS _u(0x00000040) +#define UART_UARTMIS_RTMIS_MSB _u(6) +#define UART_UARTMIS_RTMIS_LSB _u(6) #define UART_UARTMIS_RTMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_TXMIS // Description : Transmit masked interrupt status. Returns the masked interrupt // state of the UARTTXINTR interrupt. -#define UART_UARTMIS_TXMIS_RESET 0x0 -#define UART_UARTMIS_TXMIS_BITS 0x00000020 -#define UART_UARTMIS_TXMIS_MSB 5 -#define UART_UARTMIS_TXMIS_LSB 5 +#define UART_UARTMIS_TXMIS_RESET _u(0x0) +#define UART_UARTMIS_TXMIS_BITS _u(0x00000020) +#define UART_UARTMIS_TXMIS_MSB _u(5) +#define UART_UARTMIS_TXMIS_LSB _u(5) #define UART_UARTMIS_TXMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_RXMIS // Description : Receive masked interrupt status. Returns the masked interrupt // state of the UARTRXINTR interrupt. -#define UART_UARTMIS_RXMIS_RESET 0x0 -#define UART_UARTMIS_RXMIS_BITS 0x00000010 -#define UART_UARTMIS_RXMIS_MSB 4 -#define UART_UARTMIS_RXMIS_LSB 4 +#define UART_UARTMIS_RXMIS_RESET _u(0x0) +#define UART_UARTMIS_RXMIS_BITS _u(0x00000010) +#define UART_UARTMIS_RXMIS_MSB _u(4) +#define UART_UARTMIS_RXMIS_LSB _u(4) #define UART_UARTMIS_RXMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_DSRMMIS // Description : nUARTDSR modem masked interrupt status. Returns the masked // interrupt state of the UARTDSRINTR interrupt. #define UART_UARTMIS_DSRMMIS_RESET "-" -#define UART_UARTMIS_DSRMMIS_BITS 0x00000008 -#define UART_UARTMIS_DSRMMIS_MSB 3 -#define UART_UARTMIS_DSRMMIS_LSB 3 +#define UART_UARTMIS_DSRMMIS_BITS _u(0x00000008) +#define UART_UARTMIS_DSRMMIS_MSB _u(3) +#define UART_UARTMIS_DSRMMIS_LSB _u(3) #define UART_UARTMIS_DSRMMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_DCDMMIS // Description : nUARTDCD modem masked interrupt status. Returns the masked // interrupt state of the UARTDCDINTR interrupt. #define UART_UARTMIS_DCDMMIS_RESET "-" -#define UART_UARTMIS_DCDMMIS_BITS 0x00000004 -#define UART_UARTMIS_DCDMMIS_MSB 2 -#define UART_UARTMIS_DCDMMIS_LSB 2 +#define UART_UARTMIS_DCDMMIS_BITS _u(0x00000004) +#define UART_UARTMIS_DCDMMIS_MSB _u(2) +#define UART_UARTMIS_DCDMMIS_LSB _u(2) #define UART_UARTMIS_DCDMMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_CTSMMIS // Description : nUARTCTS modem masked interrupt status. Returns the masked // interrupt state of the UARTCTSINTR interrupt. #define UART_UARTMIS_CTSMMIS_RESET "-" -#define UART_UARTMIS_CTSMMIS_BITS 0x00000002 -#define UART_UARTMIS_CTSMMIS_MSB 1 -#define UART_UARTMIS_CTSMMIS_LSB 1 +#define UART_UARTMIS_CTSMMIS_BITS _u(0x00000002) +#define UART_UARTMIS_CTSMMIS_MSB _u(1) +#define UART_UARTMIS_CTSMMIS_LSB _u(1) #define UART_UARTMIS_CTSMMIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTMIS_RIMMIS // Description : nUARTRI modem masked interrupt status. Returns the masked // interrupt state of the UARTRIINTR interrupt. #define UART_UARTMIS_RIMMIS_RESET "-" -#define UART_UARTMIS_RIMMIS_BITS 0x00000001 -#define UART_UARTMIS_RIMMIS_MSB 0 -#define UART_UARTMIS_RIMMIS_LSB 0 +#define UART_UARTMIS_RIMMIS_BITS _u(0x00000001) +#define UART_UARTMIS_RIMMIS_MSB _u(0) +#define UART_UARTMIS_RIMMIS_LSB _u(0) #define UART_UARTMIS_RIMMIS_ACCESS "RO" // ============================================================================= // Register : UART_UARTICR // Description : Interrupt Clear Register, UARTICR -#define UART_UARTICR_OFFSET 0x00000044 -#define UART_UARTICR_BITS 0x000007ff -#define UART_UARTICR_RESET 0x00000000 +#define UART_UARTICR_OFFSET _u(0x00000044) +#define UART_UARTICR_BITS _u(0x000007ff) +#define UART_UARTICR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTICR_OEIC // Description : Overrun error interrupt clear. Clears the UARTOEINTR interrupt. #define UART_UARTICR_OEIC_RESET "-" -#define UART_UARTICR_OEIC_BITS 0x00000400 -#define UART_UARTICR_OEIC_MSB 10 -#define UART_UARTICR_OEIC_LSB 10 +#define UART_UARTICR_OEIC_BITS _u(0x00000400) +#define UART_UARTICR_OEIC_MSB _u(10) +#define UART_UARTICR_OEIC_LSB _u(10) #define UART_UARTICR_OEIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTICR_BEIC // Description : Break error interrupt clear. Clears the UARTBEINTR interrupt. #define UART_UARTICR_BEIC_RESET "-" -#define UART_UARTICR_BEIC_BITS 0x00000200 -#define UART_UARTICR_BEIC_MSB 9 -#define UART_UARTICR_BEIC_LSB 9 +#define UART_UARTICR_BEIC_BITS _u(0x00000200) +#define UART_UARTICR_BEIC_MSB _u(9) +#define UART_UARTICR_BEIC_LSB _u(9) #define UART_UARTICR_BEIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTICR_PEIC // Description : Parity error interrupt clear. Clears the UARTPEINTR interrupt. #define UART_UARTICR_PEIC_RESET "-" -#define UART_UARTICR_PEIC_BITS 0x00000100 -#define UART_UARTICR_PEIC_MSB 8 -#define UART_UARTICR_PEIC_LSB 8 +#define UART_UARTICR_PEIC_BITS _u(0x00000100) +#define UART_UARTICR_PEIC_MSB _u(8) +#define UART_UARTICR_PEIC_LSB _u(8) #define UART_UARTICR_PEIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTICR_FEIC // Description : Framing error interrupt clear. Clears the UARTFEINTR interrupt. #define UART_UARTICR_FEIC_RESET "-" -#define UART_UARTICR_FEIC_BITS 0x00000080 -#define UART_UARTICR_FEIC_MSB 7 -#define UART_UARTICR_FEIC_LSB 7 +#define UART_UARTICR_FEIC_BITS _u(0x00000080) +#define UART_UARTICR_FEIC_MSB _u(7) +#define UART_UARTICR_FEIC_LSB _u(7) #define UART_UARTICR_FEIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTICR_RTIC // Description : Receive timeout interrupt clear. Clears the UARTRTINTR // interrupt. #define UART_UARTICR_RTIC_RESET "-" -#define UART_UARTICR_RTIC_BITS 0x00000040 -#define UART_UARTICR_RTIC_MSB 6 -#define UART_UARTICR_RTIC_LSB 6 +#define UART_UARTICR_RTIC_BITS _u(0x00000040) +#define UART_UARTICR_RTIC_MSB _u(6) +#define UART_UARTICR_RTIC_LSB _u(6) #define UART_UARTICR_RTIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTICR_TXIC // Description : Transmit interrupt clear. Clears the UARTTXINTR interrupt. #define UART_UARTICR_TXIC_RESET "-" -#define UART_UARTICR_TXIC_BITS 0x00000020 -#define UART_UARTICR_TXIC_MSB 5 -#define UART_UARTICR_TXIC_LSB 5 +#define UART_UARTICR_TXIC_BITS _u(0x00000020) +#define UART_UARTICR_TXIC_MSB _u(5) +#define UART_UARTICR_TXIC_LSB _u(5) #define UART_UARTICR_TXIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTICR_RXIC // Description : Receive interrupt clear. Clears the UARTRXINTR interrupt. #define UART_UARTICR_RXIC_RESET "-" -#define UART_UARTICR_RXIC_BITS 0x00000010 -#define UART_UARTICR_RXIC_MSB 4 -#define UART_UARTICR_RXIC_LSB 4 +#define UART_UARTICR_RXIC_BITS _u(0x00000010) +#define UART_UARTICR_RXIC_MSB _u(4) +#define UART_UARTICR_RXIC_LSB _u(4) #define UART_UARTICR_RXIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTICR_DSRMIC // Description : nUARTDSR modem interrupt clear. Clears the UARTDSRINTR // interrupt. #define UART_UARTICR_DSRMIC_RESET "-" -#define UART_UARTICR_DSRMIC_BITS 0x00000008 -#define UART_UARTICR_DSRMIC_MSB 3 -#define UART_UARTICR_DSRMIC_LSB 3 +#define UART_UARTICR_DSRMIC_BITS _u(0x00000008) +#define UART_UARTICR_DSRMIC_MSB _u(3) +#define UART_UARTICR_DSRMIC_LSB _u(3) #define UART_UARTICR_DSRMIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTICR_DCDMIC // Description : nUARTDCD modem interrupt clear. Clears the UARTDCDINTR // interrupt. #define UART_UARTICR_DCDMIC_RESET "-" -#define UART_UARTICR_DCDMIC_BITS 0x00000004 -#define UART_UARTICR_DCDMIC_MSB 2 -#define UART_UARTICR_DCDMIC_LSB 2 +#define UART_UARTICR_DCDMIC_BITS _u(0x00000004) +#define UART_UARTICR_DCDMIC_MSB _u(2) +#define UART_UARTICR_DCDMIC_LSB _u(2) #define UART_UARTICR_DCDMIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTICR_CTSMIC // Description : nUARTCTS modem interrupt clear. Clears the UARTCTSINTR // interrupt. #define UART_UARTICR_CTSMIC_RESET "-" -#define UART_UARTICR_CTSMIC_BITS 0x00000002 -#define UART_UARTICR_CTSMIC_MSB 1 -#define UART_UARTICR_CTSMIC_LSB 1 +#define UART_UARTICR_CTSMIC_BITS _u(0x00000002) +#define UART_UARTICR_CTSMIC_MSB _u(1) +#define UART_UARTICR_CTSMIC_LSB _u(1) #define UART_UARTICR_CTSMIC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : UART_UARTICR_RIMIC // Description : nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. #define UART_UARTICR_RIMIC_RESET "-" -#define UART_UARTICR_RIMIC_BITS 0x00000001 -#define UART_UARTICR_RIMIC_MSB 0 -#define UART_UARTICR_RIMIC_LSB 0 +#define UART_UARTICR_RIMIC_BITS _u(0x00000001) +#define UART_UARTICR_RIMIC_MSB _u(0) +#define UART_UARTICR_RIMIC_LSB _u(0) #define UART_UARTICR_RIMIC_ACCESS "WC" // ============================================================================= // Register : UART_UARTDMACR // Description : DMA Control Register, UARTDMACR -#define UART_UARTDMACR_OFFSET 0x00000048 -#define UART_UARTDMACR_BITS 0x00000007 -#define UART_UARTDMACR_RESET 0x00000000 +#define UART_UARTDMACR_OFFSET _u(0x00000048) +#define UART_UARTDMACR_BITS _u(0x00000007) +#define UART_UARTDMACR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTDMACR_DMAONERR // Description : DMA on error. If this bit is set to 1, the DMA receive request // outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the // UART error interrupt is asserted. -#define UART_UARTDMACR_DMAONERR_RESET 0x0 -#define UART_UARTDMACR_DMAONERR_BITS 0x00000004 -#define UART_UARTDMACR_DMAONERR_MSB 2 -#define UART_UARTDMACR_DMAONERR_LSB 2 +#define UART_UARTDMACR_DMAONERR_RESET _u(0x0) +#define UART_UARTDMACR_DMAONERR_BITS _u(0x00000004) +#define UART_UARTDMACR_DMAONERR_MSB _u(2) +#define UART_UARTDMACR_DMAONERR_LSB _u(2) #define UART_UARTDMACR_DMAONERR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTDMACR_TXDMAE // Description : Transmit DMA enable. If this bit is set to 1, DMA for the // transmit FIFO is enabled. -#define UART_UARTDMACR_TXDMAE_RESET 0x0 -#define UART_UARTDMACR_TXDMAE_BITS 0x00000002 -#define UART_UARTDMACR_TXDMAE_MSB 1 -#define UART_UARTDMACR_TXDMAE_LSB 1 +#define UART_UARTDMACR_TXDMAE_RESET _u(0x0) +#define UART_UARTDMACR_TXDMAE_BITS _u(0x00000002) +#define UART_UARTDMACR_TXDMAE_MSB _u(1) +#define UART_UARTDMACR_TXDMAE_LSB _u(1) #define UART_UARTDMACR_TXDMAE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : UART_UARTDMACR_RXDMAE // Description : Receive DMA enable. If this bit is set to 1, DMA for the // receive FIFO is enabled. -#define UART_UARTDMACR_RXDMAE_RESET 0x0 -#define UART_UARTDMACR_RXDMAE_BITS 0x00000001 -#define UART_UARTDMACR_RXDMAE_MSB 0 -#define UART_UARTDMACR_RXDMAE_LSB 0 +#define UART_UARTDMACR_RXDMAE_RESET _u(0x0) +#define UART_UARTDMACR_RXDMAE_BITS _u(0x00000001) +#define UART_UARTDMACR_RXDMAE_MSB _u(0) +#define UART_UARTDMACR_RXDMAE_LSB _u(0) #define UART_UARTDMACR_RXDMAE_ACCESS "RW" // ============================================================================= // Register : UART_UARTPERIPHID0 // Description : UARTPeriphID0 Register -#define UART_UARTPERIPHID0_OFFSET 0x00000fe0 -#define UART_UARTPERIPHID0_BITS 0x000000ff -#define UART_UARTPERIPHID0_RESET 0x00000011 +#define UART_UARTPERIPHID0_OFFSET _u(0x00000fe0) +#define UART_UARTPERIPHID0_BITS _u(0x000000ff) +#define UART_UARTPERIPHID0_RESET _u(0x00000011) // ----------------------------------------------------------------------------- // Field : UART_UARTPERIPHID0_PARTNUMBER0 // Description : These bits read back as 0x11 -#define UART_UARTPERIPHID0_PARTNUMBER0_RESET 0x11 -#define UART_UARTPERIPHID0_PARTNUMBER0_BITS 0x000000ff -#define UART_UARTPERIPHID0_PARTNUMBER0_MSB 7 -#define UART_UARTPERIPHID0_PARTNUMBER0_LSB 0 +#define UART_UARTPERIPHID0_PARTNUMBER0_RESET _u(0x11) +#define UART_UARTPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff) +#define UART_UARTPERIPHID0_PARTNUMBER0_MSB _u(7) +#define UART_UARTPERIPHID0_PARTNUMBER0_LSB _u(0) #define UART_UARTPERIPHID0_PARTNUMBER0_ACCESS "RO" // ============================================================================= // Register : UART_UARTPERIPHID1 // Description : UARTPeriphID1 Register -#define UART_UARTPERIPHID1_OFFSET 0x00000fe4 -#define UART_UARTPERIPHID1_BITS 0x000000ff -#define UART_UARTPERIPHID1_RESET 0x00000010 +#define UART_UARTPERIPHID1_OFFSET _u(0x00000fe4) +#define UART_UARTPERIPHID1_BITS _u(0x000000ff) +#define UART_UARTPERIPHID1_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : UART_UARTPERIPHID1_DESIGNER0 // Description : These bits read back as 0x1 -#define UART_UARTPERIPHID1_DESIGNER0_RESET 0x1 -#define UART_UARTPERIPHID1_DESIGNER0_BITS 0x000000f0 -#define UART_UARTPERIPHID1_DESIGNER0_MSB 7 -#define UART_UARTPERIPHID1_DESIGNER0_LSB 4 +#define UART_UARTPERIPHID1_DESIGNER0_RESET _u(0x1) +#define UART_UARTPERIPHID1_DESIGNER0_BITS _u(0x000000f0) +#define UART_UARTPERIPHID1_DESIGNER0_MSB _u(7) +#define UART_UARTPERIPHID1_DESIGNER0_LSB _u(4) #define UART_UARTPERIPHID1_DESIGNER0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTPERIPHID1_PARTNUMBER1 // Description : These bits read back as 0x0 -#define UART_UARTPERIPHID1_PARTNUMBER1_RESET 0x0 -#define UART_UARTPERIPHID1_PARTNUMBER1_BITS 0x0000000f -#define UART_UARTPERIPHID1_PARTNUMBER1_MSB 3 -#define UART_UARTPERIPHID1_PARTNUMBER1_LSB 0 +#define UART_UARTPERIPHID1_PARTNUMBER1_RESET _u(0x0) +#define UART_UARTPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f) +#define UART_UARTPERIPHID1_PARTNUMBER1_MSB _u(3) +#define UART_UARTPERIPHID1_PARTNUMBER1_LSB _u(0) #define UART_UARTPERIPHID1_PARTNUMBER1_ACCESS "RO" // ============================================================================= // Register : UART_UARTPERIPHID2 // Description : UARTPeriphID2 Register -#define UART_UARTPERIPHID2_OFFSET 0x00000fe8 -#define UART_UARTPERIPHID2_BITS 0x000000ff -#define UART_UARTPERIPHID2_RESET 0x00000034 +#define UART_UARTPERIPHID2_OFFSET _u(0x00000fe8) +#define UART_UARTPERIPHID2_BITS _u(0x000000ff) +#define UART_UARTPERIPHID2_RESET _u(0x00000034) // ----------------------------------------------------------------------------- // Field : UART_UARTPERIPHID2_REVISION // Description : This field depends on the revision of the UART: r1p0 0x0 r1p1 // 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 -#define UART_UARTPERIPHID2_REVISION_RESET 0x3 -#define UART_UARTPERIPHID2_REVISION_BITS 0x000000f0 -#define UART_UARTPERIPHID2_REVISION_MSB 7 -#define UART_UARTPERIPHID2_REVISION_LSB 4 +#define UART_UARTPERIPHID2_REVISION_RESET _u(0x3) +#define UART_UARTPERIPHID2_REVISION_BITS _u(0x000000f0) +#define UART_UARTPERIPHID2_REVISION_MSB _u(7) +#define UART_UARTPERIPHID2_REVISION_LSB _u(4) #define UART_UARTPERIPHID2_REVISION_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : UART_UARTPERIPHID2_DESIGNER1 // Description : These bits read back as 0x4 -#define UART_UARTPERIPHID2_DESIGNER1_RESET 0x4 -#define UART_UARTPERIPHID2_DESIGNER1_BITS 0x0000000f -#define UART_UARTPERIPHID2_DESIGNER1_MSB 3 -#define UART_UARTPERIPHID2_DESIGNER1_LSB 0 +#define UART_UARTPERIPHID2_DESIGNER1_RESET _u(0x4) +#define UART_UARTPERIPHID2_DESIGNER1_BITS _u(0x0000000f) +#define UART_UARTPERIPHID2_DESIGNER1_MSB _u(3) +#define UART_UARTPERIPHID2_DESIGNER1_LSB _u(0) #define UART_UARTPERIPHID2_DESIGNER1_ACCESS "RO" // ============================================================================= // Register : UART_UARTPERIPHID3 // Description : UARTPeriphID3 Register -#define UART_UARTPERIPHID3_OFFSET 0x00000fec -#define UART_UARTPERIPHID3_BITS 0x000000ff -#define UART_UARTPERIPHID3_RESET 0x00000000 +#define UART_UARTPERIPHID3_OFFSET _u(0x00000fec) +#define UART_UARTPERIPHID3_BITS _u(0x000000ff) +#define UART_UARTPERIPHID3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : UART_UARTPERIPHID3_CONFIGURATION // Description : These bits read back as 0x00 -#define UART_UARTPERIPHID3_CONFIGURATION_RESET 0x00 -#define UART_UARTPERIPHID3_CONFIGURATION_BITS 0x000000ff -#define UART_UARTPERIPHID3_CONFIGURATION_MSB 7 -#define UART_UARTPERIPHID3_CONFIGURATION_LSB 0 +#define UART_UARTPERIPHID3_CONFIGURATION_RESET _u(0x00) +#define UART_UARTPERIPHID3_CONFIGURATION_BITS _u(0x000000ff) +#define UART_UARTPERIPHID3_CONFIGURATION_MSB _u(7) +#define UART_UARTPERIPHID3_CONFIGURATION_LSB _u(0) #define UART_UARTPERIPHID3_CONFIGURATION_ACCESS "RO" // ============================================================================= // Register : UART_UARTPCELLID0 // Description : UARTPCellID0 Register -#define UART_UARTPCELLID0_OFFSET 0x00000ff0 -#define UART_UARTPCELLID0_BITS 0x000000ff -#define UART_UARTPCELLID0_RESET 0x0000000d +#define UART_UARTPCELLID0_OFFSET _u(0x00000ff0) +#define UART_UARTPCELLID0_BITS _u(0x000000ff) +#define UART_UARTPCELLID0_RESET _u(0x0000000d) // ----------------------------------------------------------------------------- // Field : UART_UARTPCELLID0_UARTPCELLID0 // Description : These bits read back as 0x0D -#define UART_UARTPCELLID0_UARTPCELLID0_RESET 0x0d -#define UART_UARTPCELLID0_UARTPCELLID0_BITS 0x000000ff -#define UART_UARTPCELLID0_UARTPCELLID0_MSB 7 -#define UART_UARTPCELLID0_UARTPCELLID0_LSB 0 +#define UART_UARTPCELLID0_UARTPCELLID0_RESET _u(0x0d) +#define UART_UARTPCELLID0_UARTPCELLID0_BITS _u(0x000000ff) +#define UART_UARTPCELLID0_UARTPCELLID0_MSB _u(7) +#define UART_UARTPCELLID0_UARTPCELLID0_LSB _u(0) #define UART_UARTPCELLID0_UARTPCELLID0_ACCESS "RO" // ============================================================================= // Register : UART_UARTPCELLID1 // Description : UARTPCellID1 Register -#define UART_UARTPCELLID1_OFFSET 0x00000ff4 -#define UART_UARTPCELLID1_BITS 0x000000ff -#define UART_UARTPCELLID1_RESET 0x000000f0 +#define UART_UARTPCELLID1_OFFSET _u(0x00000ff4) +#define UART_UARTPCELLID1_BITS _u(0x000000ff) +#define UART_UARTPCELLID1_RESET _u(0x000000f0) // ----------------------------------------------------------------------------- // Field : UART_UARTPCELLID1_UARTPCELLID1 // Description : These bits read back as 0xF0 -#define UART_UARTPCELLID1_UARTPCELLID1_RESET 0xf0 -#define UART_UARTPCELLID1_UARTPCELLID1_BITS 0x000000ff -#define UART_UARTPCELLID1_UARTPCELLID1_MSB 7 -#define UART_UARTPCELLID1_UARTPCELLID1_LSB 0 +#define UART_UARTPCELLID1_UARTPCELLID1_RESET _u(0xf0) +#define UART_UARTPCELLID1_UARTPCELLID1_BITS _u(0x000000ff) +#define UART_UARTPCELLID1_UARTPCELLID1_MSB _u(7) +#define UART_UARTPCELLID1_UARTPCELLID1_LSB _u(0) #define UART_UARTPCELLID1_UARTPCELLID1_ACCESS "RO" // ============================================================================= // Register : UART_UARTPCELLID2 // Description : UARTPCellID2 Register -#define UART_UARTPCELLID2_OFFSET 0x00000ff8 -#define UART_UARTPCELLID2_BITS 0x000000ff -#define UART_UARTPCELLID2_RESET 0x00000005 +#define UART_UARTPCELLID2_OFFSET _u(0x00000ff8) +#define UART_UARTPCELLID2_BITS _u(0x000000ff) +#define UART_UARTPCELLID2_RESET _u(0x00000005) // ----------------------------------------------------------------------------- // Field : UART_UARTPCELLID2_UARTPCELLID2 // Description : These bits read back as 0x05 -#define UART_UARTPCELLID2_UARTPCELLID2_RESET 0x05 -#define UART_UARTPCELLID2_UARTPCELLID2_BITS 0x000000ff -#define UART_UARTPCELLID2_UARTPCELLID2_MSB 7 -#define UART_UARTPCELLID2_UARTPCELLID2_LSB 0 +#define UART_UARTPCELLID2_UARTPCELLID2_RESET _u(0x05) +#define UART_UARTPCELLID2_UARTPCELLID2_BITS _u(0x000000ff) +#define UART_UARTPCELLID2_UARTPCELLID2_MSB _u(7) +#define UART_UARTPCELLID2_UARTPCELLID2_LSB _u(0) #define UART_UARTPCELLID2_UARTPCELLID2_ACCESS "RO" // ============================================================================= // Register : UART_UARTPCELLID3 // Description : UARTPCellID3 Register -#define UART_UARTPCELLID3_OFFSET 0x00000ffc -#define UART_UARTPCELLID3_BITS 0x000000ff -#define UART_UARTPCELLID3_RESET 0x000000b1 +#define UART_UARTPCELLID3_OFFSET _u(0x00000ffc) +#define UART_UARTPCELLID3_BITS _u(0x000000ff) +#define UART_UARTPCELLID3_RESET _u(0x000000b1) // ----------------------------------------------------------------------------- // Field : UART_UARTPCELLID3_UARTPCELLID3 // Description : These bits read back as 0xB1 -#define UART_UARTPCELLID3_UARTPCELLID3_RESET 0xb1 -#define UART_UARTPCELLID3_UARTPCELLID3_BITS 0x000000ff -#define UART_UARTPCELLID3_UARTPCELLID3_MSB 7 -#define UART_UARTPCELLID3_UARTPCELLID3_LSB 0 +#define UART_UARTPCELLID3_UARTPCELLID3_RESET _u(0xb1) +#define UART_UARTPCELLID3_UARTPCELLID3_BITS _u(0x000000ff) +#define UART_UARTPCELLID3_UARTPCELLID3_MSB _u(7) +#define UART_UARTPCELLID3_UARTPCELLID3_LSB _u(0) #define UART_UARTPCELLID3_UARTPCELLID3_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_UART_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb.h index 6693205f9..552cd11a8 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb.h @@ -14,881 +14,881 @@ // ============================================================================= // Register : USB_ADDR_ENDP // Description : Device address and endpoint control -#define USB_ADDR_ENDP_OFFSET 0x00000000 -#define USB_ADDR_ENDP_BITS 0x000f007f -#define USB_ADDR_ENDP_RESET 0x00000000 +#define USB_ADDR_ENDP_OFFSET _u(0x00000000) +#define USB_ADDR_ENDP_BITS _u(0x000f007f) +#define USB_ADDR_ENDP_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP_ENDPOINT // Description : Device endpoint to send data to. Only valid for HOST mode. -#define USB_ADDR_ENDP_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP_ADDRESS // Description : In device mode, the address that the device should respond to. // Set in response to a SET_ADDR setup packet from the host. In // host mode set to the address of the device to communicate with. -#define USB_ADDR_ENDP_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP_ADDRESS_MSB 6 -#define USB_ADDR_ENDP_ADDRESS_LSB 0 +#define USB_ADDR_ENDP_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP1 // Description : Interrupt endpoint 1. Only valid for HOST mode. -#define USB_ADDR_ENDP1_OFFSET 0x00000004 -#define USB_ADDR_ENDP1_BITS 0x060f007f -#define USB_ADDR_ENDP1_RESET 0x00000000 +#define USB_ADDR_ENDP1_OFFSET _u(0x00000004) +#define USB_ADDR_ENDP1_BITS _u(0x060f007f) +#define USB_ADDR_ENDP1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP1_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP1_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP1_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP1_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP1_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP1_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP1_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP1_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP1_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP1_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP1_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP1_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP1_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP1_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP1_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP1_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP1_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP1_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP1_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP1_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP1_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP1_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP1_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP1_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP1_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP1_ADDRESS // Description : Device address -#define USB_ADDR_ENDP1_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP1_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP1_ADDRESS_MSB 6 -#define USB_ADDR_ENDP1_ADDRESS_LSB 0 +#define USB_ADDR_ENDP1_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP1_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP1_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP1_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP1_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP2 // Description : Interrupt endpoint 2. Only valid for HOST mode. -#define USB_ADDR_ENDP2_OFFSET 0x00000008 -#define USB_ADDR_ENDP2_BITS 0x060f007f -#define USB_ADDR_ENDP2_RESET 0x00000000 +#define USB_ADDR_ENDP2_OFFSET _u(0x00000008) +#define USB_ADDR_ENDP2_BITS _u(0x060f007f) +#define USB_ADDR_ENDP2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP2_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP2_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP2_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP2_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP2_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP2_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP2_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP2_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP2_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP2_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP2_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP2_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP2_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP2_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP2_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP2_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP2_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP2_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP2_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP2_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP2_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP2_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP2_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP2_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP2_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP2_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP2_ADDRESS // Description : Device address -#define USB_ADDR_ENDP2_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP2_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP2_ADDRESS_MSB 6 -#define USB_ADDR_ENDP2_ADDRESS_LSB 0 +#define USB_ADDR_ENDP2_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP2_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP2_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP2_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP2_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP3 // Description : Interrupt endpoint 3. Only valid for HOST mode. -#define USB_ADDR_ENDP3_OFFSET 0x0000000c -#define USB_ADDR_ENDP3_BITS 0x060f007f -#define USB_ADDR_ENDP3_RESET 0x00000000 +#define USB_ADDR_ENDP3_OFFSET _u(0x0000000c) +#define USB_ADDR_ENDP3_BITS _u(0x060f007f) +#define USB_ADDR_ENDP3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP3_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP3_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP3_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP3_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP3_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP3_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP3_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP3_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP3_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP3_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP3_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP3_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP3_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP3_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP3_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP3_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP3_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP3_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP3_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP3_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP3_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP3_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP3_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP3_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP3_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP3_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP3_ADDRESS // Description : Device address -#define USB_ADDR_ENDP3_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP3_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP3_ADDRESS_MSB 6 -#define USB_ADDR_ENDP3_ADDRESS_LSB 0 +#define USB_ADDR_ENDP3_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP3_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP3_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP3_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP3_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP4 // Description : Interrupt endpoint 4. Only valid for HOST mode. -#define USB_ADDR_ENDP4_OFFSET 0x00000010 -#define USB_ADDR_ENDP4_BITS 0x060f007f -#define USB_ADDR_ENDP4_RESET 0x00000000 +#define USB_ADDR_ENDP4_OFFSET _u(0x00000010) +#define USB_ADDR_ENDP4_BITS _u(0x060f007f) +#define USB_ADDR_ENDP4_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP4_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP4_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP4_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP4_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP4_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP4_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP4_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP4_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP4_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP4_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP4_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP4_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP4_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP4_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP4_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP4_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP4_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP4_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP4_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP4_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP4_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP4_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP4_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP4_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP4_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP4_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP4_ADDRESS // Description : Device address -#define USB_ADDR_ENDP4_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP4_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP4_ADDRESS_MSB 6 -#define USB_ADDR_ENDP4_ADDRESS_LSB 0 +#define USB_ADDR_ENDP4_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP4_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP4_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP4_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP4_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP5 // Description : Interrupt endpoint 5. Only valid for HOST mode. -#define USB_ADDR_ENDP5_OFFSET 0x00000014 -#define USB_ADDR_ENDP5_BITS 0x060f007f -#define USB_ADDR_ENDP5_RESET 0x00000000 +#define USB_ADDR_ENDP5_OFFSET _u(0x00000014) +#define USB_ADDR_ENDP5_BITS _u(0x060f007f) +#define USB_ADDR_ENDP5_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP5_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP5_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP5_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP5_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP5_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP5_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP5_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP5_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP5_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP5_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP5_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP5_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP5_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP5_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP5_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP5_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP5_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP5_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP5_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP5_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP5_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP5_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP5_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP5_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP5_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP5_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP5_ADDRESS // Description : Device address -#define USB_ADDR_ENDP5_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP5_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP5_ADDRESS_MSB 6 -#define USB_ADDR_ENDP5_ADDRESS_LSB 0 +#define USB_ADDR_ENDP5_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP5_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP5_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP5_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP5_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP6 // Description : Interrupt endpoint 6. Only valid for HOST mode. -#define USB_ADDR_ENDP6_OFFSET 0x00000018 -#define USB_ADDR_ENDP6_BITS 0x060f007f -#define USB_ADDR_ENDP6_RESET 0x00000000 +#define USB_ADDR_ENDP6_OFFSET _u(0x00000018) +#define USB_ADDR_ENDP6_BITS _u(0x060f007f) +#define USB_ADDR_ENDP6_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP6_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP6_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP6_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP6_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP6_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP6_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP6_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP6_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP6_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP6_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP6_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP6_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP6_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP6_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP6_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP6_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP6_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP6_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP6_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP6_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP6_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP6_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP6_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP6_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP6_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP6_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP6_ADDRESS // Description : Device address -#define USB_ADDR_ENDP6_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP6_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP6_ADDRESS_MSB 6 -#define USB_ADDR_ENDP6_ADDRESS_LSB 0 +#define USB_ADDR_ENDP6_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP6_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP6_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP6_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP6_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP7 // Description : Interrupt endpoint 7. Only valid for HOST mode. -#define USB_ADDR_ENDP7_OFFSET 0x0000001c -#define USB_ADDR_ENDP7_BITS 0x060f007f -#define USB_ADDR_ENDP7_RESET 0x00000000 +#define USB_ADDR_ENDP7_OFFSET _u(0x0000001c) +#define USB_ADDR_ENDP7_BITS _u(0x060f007f) +#define USB_ADDR_ENDP7_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP7_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP7_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP7_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP7_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP7_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP7_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP7_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP7_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP7_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP7_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP7_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP7_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP7_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP7_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP7_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP7_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP7_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP7_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP7_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP7_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP7_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP7_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP7_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP7_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP7_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP7_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP7_ADDRESS // Description : Device address -#define USB_ADDR_ENDP7_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP7_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP7_ADDRESS_MSB 6 -#define USB_ADDR_ENDP7_ADDRESS_LSB 0 +#define USB_ADDR_ENDP7_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP7_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP7_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP7_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP7_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP8 // Description : Interrupt endpoint 8. Only valid for HOST mode. -#define USB_ADDR_ENDP8_OFFSET 0x00000020 -#define USB_ADDR_ENDP8_BITS 0x060f007f -#define USB_ADDR_ENDP8_RESET 0x00000000 +#define USB_ADDR_ENDP8_OFFSET _u(0x00000020) +#define USB_ADDR_ENDP8_BITS _u(0x060f007f) +#define USB_ADDR_ENDP8_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP8_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP8_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP8_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP8_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP8_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP8_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP8_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP8_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP8_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP8_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP8_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP8_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP8_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP8_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP8_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP8_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP8_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP8_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP8_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP8_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP8_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP8_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP8_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP8_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP8_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP8_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP8_ADDRESS // Description : Device address -#define USB_ADDR_ENDP8_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP8_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP8_ADDRESS_MSB 6 -#define USB_ADDR_ENDP8_ADDRESS_LSB 0 +#define USB_ADDR_ENDP8_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP8_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP8_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP8_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP8_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP9 // Description : Interrupt endpoint 9. Only valid for HOST mode. -#define USB_ADDR_ENDP9_OFFSET 0x00000024 -#define USB_ADDR_ENDP9_BITS 0x060f007f -#define USB_ADDR_ENDP9_RESET 0x00000000 +#define USB_ADDR_ENDP9_OFFSET _u(0x00000024) +#define USB_ADDR_ENDP9_BITS _u(0x060f007f) +#define USB_ADDR_ENDP9_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP9_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP9_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP9_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP9_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP9_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP9_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP9_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP9_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP9_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP9_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP9_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP9_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP9_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP9_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP9_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP9_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP9_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP9_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP9_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP9_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP9_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP9_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP9_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP9_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP9_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP9_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP9_ADDRESS // Description : Device address -#define USB_ADDR_ENDP9_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP9_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP9_ADDRESS_MSB 6 -#define USB_ADDR_ENDP9_ADDRESS_LSB 0 +#define USB_ADDR_ENDP9_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP9_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP9_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP9_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP9_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP10 // Description : Interrupt endpoint 10. Only valid for HOST mode. -#define USB_ADDR_ENDP10_OFFSET 0x00000028 -#define USB_ADDR_ENDP10_BITS 0x060f007f -#define USB_ADDR_ENDP10_RESET 0x00000000 +#define USB_ADDR_ENDP10_OFFSET _u(0x00000028) +#define USB_ADDR_ENDP10_BITS _u(0x060f007f) +#define USB_ADDR_ENDP10_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP10_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP10_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP10_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP10_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP10_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP10_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP10_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP10_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP10_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP10_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP10_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP10_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP10_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP10_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP10_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP10_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP10_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP10_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP10_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP10_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP10_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP10_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP10_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP10_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP10_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP10_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP10_ADDRESS // Description : Device address -#define USB_ADDR_ENDP10_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP10_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP10_ADDRESS_MSB 6 -#define USB_ADDR_ENDP10_ADDRESS_LSB 0 +#define USB_ADDR_ENDP10_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP10_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP10_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP10_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP10_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP11 // Description : Interrupt endpoint 11. Only valid for HOST mode. -#define USB_ADDR_ENDP11_OFFSET 0x0000002c -#define USB_ADDR_ENDP11_BITS 0x060f007f -#define USB_ADDR_ENDP11_RESET 0x00000000 +#define USB_ADDR_ENDP11_OFFSET _u(0x0000002c) +#define USB_ADDR_ENDP11_BITS _u(0x060f007f) +#define USB_ADDR_ENDP11_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP11_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP11_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP11_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP11_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP11_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP11_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP11_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP11_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP11_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP11_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP11_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP11_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP11_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP11_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP11_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP11_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP11_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP11_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP11_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP11_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP11_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP11_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP11_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP11_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP11_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP11_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP11_ADDRESS // Description : Device address -#define USB_ADDR_ENDP11_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP11_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP11_ADDRESS_MSB 6 -#define USB_ADDR_ENDP11_ADDRESS_LSB 0 +#define USB_ADDR_ENDP11_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP11_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP11_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP11_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP11_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP12 // Description : Interrupt endpoint 12. Only valid for HOST mode. -#define USB_ADDR_ENDP12_OFFSET 0x00000030 -#define USB_ADDR_ENDP12_BITS 0x060f007f -#define USB_ADDR_ENDP12_RESET 0x00000000 +#define USB_ADDR_ENDP12_OFFSET _u(0x00000030) +#define USB_ADDR_ENDP12_BITS _u(0x060f007f) +#define USB_ADDR_ENDP12_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP12_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP12_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP12_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP12_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP12_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP12_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP12_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP12_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP12_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP12_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP12_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP12_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP12_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP12_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP12_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP12_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP12_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP12_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP12_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP12_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP12_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP12_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP12_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP12_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP12_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP12_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP12_ADDRESS // Description : Device address -#define USB_ADDR_ENDP12_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP12_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP12_ADDRESS_MSB 6 -#define USB_ADDR_ENDP12_ADDRESS_LSB 0 +#define USB_ADDR_ENDP12_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP12_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP12_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP12_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP12_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP13 // Description : Interrupt endpoint 13. Only valid for HOST mode. -#define USB_ADDR_ENDP13_OFFSET 0x00000034 -#define USB_ADDR_ENDP13_BITS 0x060f007f -#define USB_ADDR_ENDP13_RESET 0x00000000 +#define USB_ADDR_ENDP13_OFFSET _u(0x00000034) +#define USB_ADDR_ENDP13_BITS _u(0x060f007f) +#define USB_ADDR_ENDP13_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP13_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP13_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP13_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP13_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP13_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP13_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP13_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP13_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP13_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP13_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP13_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP13_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP13_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP13_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP13_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP13_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP13_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP13_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP13_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP13_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP13_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP13_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP13_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP13_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP13_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP13_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP13_ADDRESS // Description : Device address -#define USB_ADDR_ENDP13_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP13_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP13_ADDRESS_MSB 6 -#define USB_ADDR_ENDP13_ADDRESS_LSB 0 +#define USB_ADDR_ENDP13_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP13_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP13_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP13_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP13_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP14 // Description : Interrupt endpoint 14. Only valid for HOST mode. -#define USB_ADDR_ENDP14_OFFSET 0x00000038 -#define USB_ADDR_ENDP14_BITS 0x060f007f -#define USB_ADDR_ENDP14_RESET 0x00000000 +#define USB_ADDR_ENDP14_OFFSET _u(0x00000038) +#define USB_ADDR_ENDP14_BITS _u(0x060f007f) +#define USB_ADDR_ENDP14_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP14_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP14_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP14_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP14_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP14_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP14_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP14_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP14_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP14_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP14_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP14_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP14_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP14_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP14_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP14_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP14_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP14_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP14_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP14_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP14_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP14_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP14_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP14_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP14_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP14_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP14_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP14_ADDRESS // Description : Device address -#define USB_ADDR_ENDP14_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP14_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP14_ADDRESS_MSB 6 -#define USB_ADDR_ENDP14_ADDRESS_LSB 0 +#define USB_ADDR_ENDP14_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP14_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP14_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP14_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP14_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_ADDR_ENDP15 // Description : Interrupt endpoint 15. Only valid for HOST mode. -#define USB_ADDR_ENDP15_OFFSET 0x0000003c -#define USB_ADDR_ENDP15_BITS 0x060f007f -#define USB_ADDR_ENDP15_RESET 0x00000000 +#define USB_ADDR_ENDP15_OFFSET _u(0x0000003c) +#define USB_ADDR_ENDP15_BITS _u(0x060f007f) +#define USB_ADDR_ENDP15_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP15_INTEP_PREAMBLE // Description : Interrupt EP requires preamble (is a low speed device on a full // speed hub) -#define USB_ADDR_ENDP15_INTEP_PREAMBLE_RESET 0x0 -#define USB_ADDR_ENDP15_INTEP_PREAMBLE_BITS 0x04000000 -#define USB_ADDR_ENDP15_INTEP_PREAMBLE_MSB 26 -#define USB_ADDR_ENDP15_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_LSB _u(26) #define USB_ADDR_ENDP15_INTEP_PREAMBLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP15_INTEP_DIR // Description : Direction of the interrupt endpoint. In=0, Out=1 -#define USB_ADDR_ENDP15_INTEP_DIR_RESET 0x0 -#define USB_ADDR_ENDP15_INTEP_DIR_BITS 0x02000000 -#define USB_ADDR_ENDP15_INTEP_DIR_MSB 25 -#define USB_ADDR_ENDP15_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP15_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP15_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP15_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP15_INTEP_DIR_LSB _u(25) #define USB_ADDR_ENDP15_INTEP_DIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP15_ENDPOINT // Description : Endpoint number of the interrupt endpoint -#define USB_ADDR_ENDP15_ENDPOINT_RESET 0x0 -#define USB_ADDR_ENDP15_ENDPOINT_BITS 0x000f0000 -#define USB_ADDR_ENDP15_ENDPOINT_MSB 19 -#define USB_ADDR_ENDP15_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP15_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP15_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP15_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP15_ENDPOINT_LSB _u(16) #define USB_ADDR_ENDP15_ENDPOINT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_ADDR_ENDP15_ADDRESS // Description : Device address -#define USB_ADDR_ENDP15_ADDRESS_RESET 0x00 -#define USB_ADDR_ENDP15_ADDRESS_BITS 0x0000007f -#define USB_ADDR_ENDP15_ADDRESS_MSB 6 -#define USB_ADDR_ENDP15_ADDRESS_LSB 0 +#define USB_ADDR_ENDP15_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP15_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP15_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP15_ADDRESS_LSB _u(0) #define USB_ADDR_ENDP15_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_MAIN_CTRL // Description : Main control register -#define USB_MAIN_CTRL_OFFSET 0x00000040 -#define USB_MAIN_CTRL_BITS 0x80000003 -#define USB_MAIN_CTRL_RESET 0x00000000 +#define USB_MAIN_CTRL_OFFSET _u(0x00000040) +#define USB_MAIN_CTRL_BITS _u(0x80000003) +#define USB_MAIN_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_MAIN_CTRL_SIM_TIMING // Description : Reduced timings for simulation -#define USB_MAIN_CTRL_SIM_TIMING_RESET 0x0 -#define USB_MAIN_CTRL_SIM_TIMING_BITS 0x80000000 -#define USB_MAIN_CTRL_SIM_TIMING_MSB 31 -#define USB_MAIN_CTRL_SIM_TIMING_LSB 31 +#define USB_MAIN_CTRL_SIM_TIMING_RESET _u(0x0) +#define USB_MAIN_CTRL_SIM_TIMING_BITS _u(0x80000000) +#define USB_MAIN_CTRL_SIM_TIMING_MSB _u(31) +#define USB_MAIN_CTRL_SIM_TIMING_LSB _u(31) #define USB_MAIN_CTRL_SIM_TIMING_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_MAIN_CTRL_HOST_NDEVICE // Description : Device mode = 0, Host mode = 1 -#define USB_MAIN_CTRL_HOST_NDEVICE_RESET 0x0 -#define USB_MAIN_CTRL_HOST_NDEVICE_BITS 0x00000002 -#define USB_MAIN_CTRL_HOST_NDEVICE_MSB 1 -#define USB_MAIN_CTRL_HOST_NDEVICE_LSB 1 +#define USB_MAIN_CTRL_HOST_NDEVICE_RESET _u(0x0) +#define USB_MAIN_CTRL_HOST_NDEVICE_BITS _u(0x00000002) +#define USB_MAIN_CTRL_HOST_NDEVICE_MSB _u(1) +#define USB_MAIN_CTRL_HOST_NDEVICE_LSB _u(1) #define USB_MAIN_CTRL_HOST_NDEVICE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_MAIN_CTRL_CONTROLLER_EN // Description : Enable controller -#define USB_MAIN_CTRL_CONTROLLER_EN_RESET 0x0 -#define USB_MAIN_CTRL_CONTROLLER_EN_BITS 0x00000001 -#define USB_MAIN_CTRL_CONTROLLER_EN_MSB 0 -#define USB_MAIN_CTRL_CONTROLLER_EN_LSB 0 +#define USB_MAIN_CTRL_CONTROLLER_EN_RESET _u(0x0) +#define USB_MAIN_CTRL_CONTROLLER_EN_BITS _u(0x00000001) +#define USB_MAIN_CTRL_CONTROLLER_EN_MSB _u(0) +#define USB_MAIN_CTRL_CONTROLLER_EN_LSB _u(0) #define USB_MAIN_CTRL_CONTROLLER_EN_ACCESS "RW" // ============================================================================= // Register : USB_SOF_WR // Description : Set the SOF (Start of Frame) frame number in the host // controller. The SOF packet is sent every 1ms and the host will // increment the frame number by 1 each time. -#define USB_SOF_WR_OFFSET 0x00000044 -#define USB_SOF_WR_BITS 0x000007ff -#define USB_SOF_WR_RESET 0x00000000 +#define USB_SOF_WR_OFFSET _u(0x00000044) +#define USB_SOF_WR_BITS _u(0x000007ff) +#define USB_SOF_WR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_SOF_WR_COUNT // Description : None -#define USB_SOF_WR_COUNT_RESET 0x000 -#define USB_SOF_WR_COUNT_BITS 0x000007ff -#define USB_SOF_WR_COUNT_MSB 10 -#define USB_SOF_WR_COUNT_LSB 0 +#define USB_SOF_WR_COUNT_RESET _u(0x000) +#define USB_SOF_WR_COUNT_BITS _u(0x000007ff) +#define USB_SOF_WR_COUNT_MSB _u(10) +#define USB_SOF_WR_COUNT_LSB _u(0) #define USB_SOF_WR_COUNT_ACCESS "WF" // ============================================================================= // Register : USB_SOF_RD // Description : Read the last SOF (Start of Frame) frame number seen. In device // mode the last SOF received from the host. In host mode the last // SOF sent by the host. -#define USB_SOF_RD_OFFSET 0x00000048 -#define USB_SOF_RD_BITS 0x000007ff -#define USB_SOF_RD_RESET 0x00000000 +#define USB_SOF_RD_OFFSET _u(0x00000048) +#define USB_SOF_RD_BITS _u(0x000007ff) +#define USB_SOF_RD_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_SOF_RD_COUNT // Description : None -#define USB_SOF_RD_COUNT_RESET 0x000 -#define USB_SOF_RD_COUNT_BITS 0x000007ff -#define USB_SOF_RD_COUNT_MSB 10 -#define USB_SOF_RD_COUNT_LSB 0 +#define USB_SOF_RD_COUNT_RESET _u(0x000) +#define USB_SOF_RD_COUNT_BITS _u(0x000007ff) +#define USB_SOF_RD_COUNT_MSB _u(10) +#define USB_SOF_RD_COUNT_LSB _u(0) #define USB_SOF_RD_COUNT_ACCESS "RO" // ============================================================================= // Register : USB_SIE_CTRL // Description : SIE control register -#define USB_SIE_CTRL_OFFSET 0x0000004c -#define USB_SIE_CTRL_BITS 0xff07bf5f -#define USB_SIE_CTRL_RESET 0x00000000 +#define USB_SIE_CTRL_OFFSET _u(0x0000004c) +#define USB_SIE_CTRL_BITS _u(0xff07bf5f) +#define USB_SIE_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_EP0_INT_STALL // Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL -#define USB_SIE_CTRL_EP0_INT_STALL_RESET 0x0 -#define USB_SIE_CTRL_EP0_INT_STALL_BITS 0x80000000 -#define USB_SIE_CTRL_EP0_INT_STALL_MSB 31 -#define USB_SIE_CTRL_EP0_INT_STALL_LSB 31 +#define USB_SIE_CTRL_EP0_INT_STALL_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_INT_STALL_BITS _u(0x80000000) +#define USB_SIE_CTRL_EP0_INT_STALL_MSB _u(31) +#define USB_SIE_CTRL_EP0_INT_STALL_LSB _u(31) #define USB_SIE_CTRL_EP0_INT_STALL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_EP0_DOUBLE_BUF // Description : Device: EP0 single buffered = 0, double buffered = 1 -#define USB_SIE_CTRL_EP0_DOUBLE_BUF_RESET 0x0 -#define USB_SIE_CTRL_EP0_DOUBLE_BUF_BITS 0x40000000 -#define USB_SIE_CTRL_EP0_DOUBLE_BUF_MSB 30 -#define USB_SIE_CTRL_EP0_DOUBLE_BUF_LSB 30 +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_BITS _u(0x40000000) +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_MSB _u(30) +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_LSB _u(30) #define USB_SIE_CTRL_EP0_DOUBLE_BUF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_EP0_INT_1BUF // Description : Device: Set bit in BUFF_STATUS for every buffer completed on // EP0 -#define USB_SIE_CTRL_EP0_INT_1BUF_RESET 0x0 -#define USB_SIE_CTRL_EP0_INT_1BUF_BITS 0x20000000 -#define USB_SIE_CTRL_EP0_INT_1BUF_MSB 29 -#define USB_SIE_CTRL_EP0_INT_1BUF_LSB 29 +#define USB_SIE_CTRL_EP0_INT_1BUF_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_INT_1BUF_BITS _u(0x20000000) +#define USB_SIE_CTRL_EP0_INT_1BUF_MSB _u(29) +#define USB_SIE_CTRL_EP0_INT_1BUF_LSB _u(29) #define USB_SIE_CTRL_EP0_INT_1BUF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_EP0_INT_2BUF // Description : Device: Set bit in BUFF_STATUS for every 2 buffers completed on // EP0 -#define USB_SIE_CTRL_EP0_INT_2BUF_RESET 0x0 -#define USB_SIE_CTRL_EP0_INT_2BUF_BITS 0x10000000 -#define USB_SIE_CTRL_EP0_INT_2BUF_MSB 28 -#define USB_SIE_CTRL_EP0_INT_2BUF_LSB 28 +#define USB_SIE_CTRL_EP0_INT_2BUF_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_INT_2BUF_BITS _u(0x10000000) +#define USB_SIE_CTRL_EP0_INT_2BUF_MSB _u(28) +#define USB_SIE_CTRL_EP0_INT_2BUF_LSB _u(28) #define USB_SIE_CTRL_EP0_INT_2BUF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_EP0_INT_NAK // Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK -#define USB_SIE_CTRL_EP0_INT_NAK_RESET 0x0 -#define USB_SIE_CTRL_EP0_INT_NAK_BITS 0x08000000 -#define USB_SIE_CTRL_EP0_INT_NAK_MSB 27 -#define USB_SIE_CTRL_EP0_INT_NAK_LSB 27 +#define USB_SIE_CTRL_EP0_INT_NAK_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_INT_NAK_BITS _u(0x08000000) +#define USB_SIE_CTRL_EP0_INT_NAK_MSB _u(27) +#define USB_SIE_CTRL_EP0_INT_NAK_LSB _u(27) #define USB_SIE_CTRL_EP0_INT_NAK_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_DIRECT_EN // Description : Direct bus drive enable -#define USB_SIE_CTRL_DIRECT_EN_RESET 0x0 -#define USB_SIE_CTRL_DIRECT_EN_BITS 0x04000000 -#define USB_SIE_CTRL_DIRECT_EN_MSB 26 -#define USB_SIE_CTRL_DIRECT_EN_LSB 26 +#define USB_SIE_CTRL_DIRECT_EN_RESET _u(0x0) +#define USB_SIE_CTRL_DIRECT_EN_BITS _u(0x04000000) +#define USB_SIE_CTRL_DIRECT_EN_MSB _u(26) +#define USB_SIE_CTRL_DIRECT_EN_LSB _u(26) #define USB_SIE_CTRL_DIRECT_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_DIRECT_DP // Description : Direct control of DP -#define USB_SIE_CTRL_DIRECT_DP_RESET 0x0 -#define USB_SIE_CTRL_DIRECT_DP_BITS 0x02000000 -#define USB_SIE_CTRL_DIRECT_DP_MSB 25 -#define USB_SIE_CTRL_DIRECT_DP_LSB 25 +#define USB_SIE_CTRL_DIRECT_DP_RESET _u(0x0) +#define USB_SIE_CTRL_DIRECT_DP_BITS _u(0x02000000) +#define USB_SIE_CTRL_DIRECT_DP_MSB _u(25) +#define USB_SIE_CTRL_DIRECT_DP_LSB _u(25) #define USB_SIE_CTRL_DIRECT_DP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_DIRECT_DM // Description : Direct control of DM -#define USB_SIE_CTRL_DIRECT_DM_RESET 0x0 -#define USB_SIE_CTRL_DIRECT_DM_BITS 0x01000000 -#define USB_SIE_CTRL_DIRECT_DM_MSB 24 -#define USB_SIE_CTRL_DIRECT_DM_LSB 24 +#define USB_SIE_CTRL_DIRECT_DM_RESET _u(0x0) +#define USB_SIE_CTRL_DIRECT_DM_BITS _u(0x01000000) +#define USB_SIE_CTRL_DIRECT_DM_MSB _u(24) +#define USB_SIE_CTRL_DIRECT_DM_LSB _u(24) #define USB_SIE_CTRL_DIRECT_DM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_TRANSCEIVER_PD // Description : Power down bus transceiver -#define USB_SIE_CTRL_TRANSCEIVER_PD_RESET 0x0 -#define USB_SIE_CTRL_TRANSCEIVER_PD_BITS 0x00040000 -#define USB_SIE_CTRL_TRANSCEIVER_PD_MSB 18 -#define USB_SIE_CTRL_TRANSCEIVER_PD_LSB 18 +#define USB_SIE_CTRL_TRANSCEIVER_PD_RESET _u(0x0) +#define USB_SIE_CTRL_TRANSCEIVER_PD_BITS _u(0x00040000) +#define USB_SIE_CTRL_TRANSCEIVER_PD_MSB _u(18) +#define USB_SIE_CTRL_TRANSCEIVER_PD_LSB _u(18) #define USB_SIE_CTRL_TRANSCEIVER_PD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_RPU_OPT // Description : Device: Pull-up strength (0=1K2, 1=2k3) -#define USB_SIE_CTRL_RPU_OPT_RESET 0x0 -#define USB_SIE_CTRL_RPU_OPT_BITS 0x00020000 -#define USB_SIE_CTRL_RPU_OPT_MSB 17 -#define USB_SIE_CTRL_RPU_OPT_LSB 17 +#define USB_SIE_CTRL_RPU_OPT_RESET _u(0x0) +#define USB_SIE_CTRL_RPU_OPT_BITS _u(0x00020000) +#define USB_SIE_CTRL_RPU_OPT_MSB _u(17) +#define USB_SIE_CTRL_RPU_OPT_LSB _u(17) #define USB_SIE_CTRL_RPU_OPT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_PULLUP_EN // Description : Device: Enable pull up resistor -#define USB_SIE_CTRL_PULLUP_EN_RESET 0x0 -#define USB_SIE_CTRL_PULLUP_EN_BITS 0x00010000 -#define USB_SIE_CTRL_PULLUP_EN_MSB 16 -#define USB_SIE_CTRL_PULLUP_EN_LSB 16 +#define USB_SIE_CTRL_PULLUP_EN_RESET _u(0x0) +#define USB_SIE_CTRL_PULLUP_EN_BITS _u(0x00010000) +#define USB_SIE_CTRL_PULLUP_EN_MSB _u(16) +#define USB_SIE_CTRL_PULLUP_EN_LSB _u(16) #define USB_SIE_CTRL_PULLUP_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_PULLDOWN_EN // Description : Host: Enable pull down resistors -#define USB_SIE_CTRL_PULLDOWN_EN_RESET 0x0 -#define USB_SIE_CTRL_PULLDOWN_EN_BITS 0x00008000 -#define USB_SIE_CTRL_PULLDOWN_EN_MSB 15 -#define USB_SIE_CTRL_PULLDOWN_EN_LSB 15 +#define USB_SIE_CTRL_PULLDOWN_EN_RESET _u(0x0) +#define USB_SIE_CTRL_PULLDOWN_EN_BITS _u(0x00008000) +#define USB_SIE_CTRL_PULLDOWN_EN_MSB _u(15) +#define USB_SIE_CTRL_PULLDOWN_EN_LSB _u(15) #define USB_SIE_CTRL_PULLDOWN_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_RESET_BUS // Description : Host: Reset bus -#define USB_SIE_CTRL_RESET_BUS_RESET 0x0 -#define USB_SIE_CTRL_RESET_BUS_BITS 0x00002000 -#define USB_SIE_CTRL_RESET_BUS_MSB 13 -#define USB_SIE_CTRL_RESET_BUS_LSB 13 +#define USB_SIE_CTRL_RESET_BUS_RESET _u(0x0) +#define USB_SIE_CTRL_RESET_BUS_BITS _u(0x00002000) +#define USB_SIE_CTRL_RESET_BUS_MSB _u(13) +#define USB_SIE_CTRL_RESET_BUS_LSB _u(13) #define USB_SIE_CTRL_RESET_BUS_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_RESUME // Description : Device: Remote wakeup. Device can initiate its own resume after // suspend. -#define USB_SIE_CTRL_RESUME_RESET 0x0 -#define USB_SIE_CTRL_RESUME_BITS 0x00001000 -#define USB_SIE_CTRL_RESUME_MSB 12 -#define USB_SIE_CTRL_RESUME_LSB 12 +#define USB_SIE_CTRL_RESUME_RESET _u(0x0) +#define USB_SIE_CTRL_RESUME_BITS _u(0x00001000) +#define USB_SIE_CTRL_RESUME_MSB _u(12) +#define USB_SIE_CTRL_RESUME_LSB _u(12) #define USB_SIE_CTRL_RESUME_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_VBUS_EN // Description : Host: Enable VBUS -#define USB_SIE_CTRL_VBUS_EN_RESET 0x0 -#define USB_SIE_CTRL_VBUS_EN_BITS 0x00000800 -#define USB_SIE_CTRL_VBUS_EN_MSB 11 -#define USB_SIE_CTRL_VBUS_EN_LSB 11 +#define USB_SIE_CTRL_VBUS_EN_RESET _u(0x0) +#define USB_SIE_CTRL_VBUS_EN_BITS _u(0x00000800) +#define USB_SIE_CTRL_VBUS_EN_MSB _u(11) +#define USB_SIE_CTRL_VBUS_EN_LSB _u(11) #define USB_SIE_CTRL_VBUS_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_KEEP_ALIVE_EN // Description : Host: Enable keep alive packet (for low speed bus) -#define USB_SIE_CTRL_KEEP_ALIVE_EN_RESET 0x0 -#define USB_SIE_CTRL_KEEP_ALIVE_EN_BITS 0x00000400 -#define USB_SIE_CTRL_KEEP_ALIVE_EN_MSB 10 -#define USB_SIE_CTRL_KEEP_ALIVE_EN_LSB 10 +#define USB_SIE_CTRL_KEEP_ALIVE_EN_RESET _u(0x0) +#define USB_SIE_CTRL_KEEP_ALIVE_EN_BITS _u(0x00000400) +#define USB_SIE_CTRL_KEEP_ALIVE_EN_MSB _u(10) +#define USB_SIE_CTRL_KEEP_ALIVE_EN_LSB _u(10) #define USB_SIE_CTRL_KEEP_ALIVE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_SOF_EN // Description : Host: Enable SOF generation (for full speed bus) -#define USB_SIE_CTRL_SOF_EN_RESET 0x0 -#define USB_SIE_CTRL_SOF_EN_BITS 0x00000200 -#define USB_SIE_CTRL_SOF_EN_MSB 9 -#define USB_SIE_CTRL_SOF_EN_LSB 9 +#define USB_SIE_CTRL_SOF_EN_RESET _u(0x0) +#define USB_SIE_CTRL_SOF_EN_BITS _u(0x00000200) +#define USB_SIE_CTRL_SOF_EN_MSB _u(9) +#define USB_SIE_CTRL_SOF_EN_LSB _u(9) #define USB_SIE_CTRL_SOF_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_SOF_SYNC // Description : Host: Delay packet(s) until after SOF -#define USB_SIE_CTRL_SOF_SYNC_RESET 0x0 -#define USB_SIE_CTRL_SOF_SYNC_BITS 0x00000100 -#define USB_SIE_CTRL_SOF_SYNC_MSB 8 -#define USB_SIE_CTRL_SOF_SYNC_LSB 8 +#define USB_SIE_CTRL_SOF_SYNC_RESET _u(0x0) +#define USB_SIE_CTRL_SOF_SYNC_BITS _u(0x00000100) +#define USB_SIE_CTRL_SOF_SYNC_MSB _u(8) +#define USB_SIE_CTRL_SOF_SYNC_LSB _u(8) #define USB_SIE_CTRL_SOF_SYNC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_PREAMBLE_EN // Description : Host: Preable enable for LS device on FS hub -#define USB_SIE_CTRL_PREAMBLE_EN_RESET 0x0 -#define USB_SIE_CTRL_PREAMBLE_EN_BITS 0x00000040 -#define USB_SIE_CTRL_PREAMBLE_EN_MSB 6 -#define USB_SIE_CTRL_PREAMBLE_EN_LSB 6 +#define USB_SIE_CTRL_PREAMBLE_EN_RESET _u(0x0) +#define USB_SIE_CTRL_PREAMBLE_EN_BITS _u(0x00000040) +#define USB_SIE_CTRL_PREAMBLE_EN_MSB _u(6) +#define USB_SIE_CTRL_PREAMBLE_EN_LSB _u(6) #define USB_SIE_CTRL_PREAMBLE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_STOP_TRANS // Description : Host: Stop transaction -#define USB_SIE_CTRL_STOP_TRANS_RESET 0x0 -#define USB_SIE_CTRL_STOP_TRANS_BITS 0x00000010 -#define USB_SIE_CTRL_STOP_TRANS_MSB 4 -#define USB_SIE_CTRL_STOP_TRANS_LSB 4 +#define USB_SIE_CTRL_STOP_TRANS_RESET _u(0x0) +#define USB_SIE_CTRL_STOP_TRANS_BITS _u(0x00000010) +#define USB_SIE_CTRL_STOP_TRANS_MSB _u(4) +#define USB_SIE_CTRL_STOP_TRANS_LSB _u(4) #define USB_SIE_CTRL_STOP_TRANS_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_RECEIVE_DATA // Description : Host: Receive transaction (IN to host) -#define USB_SIE_CTRL_RECEIVE_DATA_RESET 0x0 -#define USB_SIE_CTRL_RECEIVE_DATA_BITS 0x00000008 -#define USB_SIE_CTRL_RECEIVE_DATA_MSB 3 -#define USB_SIE_CTRL_RECEIVE_DATA_LSB 3 +#define USB_SIE_CTRL_RECEIVE_DATA_RESET _u(0x0) +#define USB_SIE_CTRL_RECEIVE_DATA_BITS _u(0x00000008) +#define USB_SIE_CTRL_RECEIVE_DATA_MSB _u(3) +#define USB_SIE_CTRL_RECEIVE_DATA_LSB _u(3) #define USB_SIE_CTRL_RECEIVE_DATA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_SEND_DATA // Description : Host: Send transaction (OUT from host) -#define USB_SIE_CTRL_SEND_DATA_RESET 0x0 -#define USB_SIE_CTRL_SEND_DATA_BITS 0x00000004 -#define USB_SIE_CTRL_SEND_DATA_MSB 2 -#define USB_SIE_CTRL_SEND_DATA_LSB 2 +#define USB_SIE_CTRL_SEND_DATA_RESET _u(0x0) +#define USB_SIE_CTRL_SEND_DATA_BITS _u(0x00000004) +#define USB_SIE_CTRL_SEND_DATA_MSB _u(2) +#define USB_SIE_CTRL_SEND_DATA_LSB _u(2) #define USB_SIE_CTRL_SEND_DATA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_SEND_SETUP // Description : Host: Send Setup packet -#define USB_SIE_CTRL_SEND_SETUP_RESET 0x0 -#define USB_SIE_CTRL_SEND_SETUP_BITS 0x00000002 -#define USB_SIE_CTRL_SEND_SETUP_MSB 1 -#define USB_SIE_CTRL_SEND_SETUP_LSB 1 +#define USB_SIE_CTRL_SEND_SETUP_RESET _u(0x0) +#define USB_SIE_CTRL_SEND_SETUP_BITS _u(0x00000002) +#define USB_SIE_CTRL_SEND_SETUP_MSB _u(1) +#define USB_SIE_CTRL_SEND_SETUP_LSB _u(1) #define USB_SIE_CTRL_SEND_SETUP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_SIE_CTRL_START_TRANS // Description : Host: Start transaction -#define USB_SIE_CTRL_START_TRANS_RESET 0x0 -#define USB_SIE_CTRL_START_TRANS_BITS 0x00000001 -#define USB_SIE_CTRL_START_TRANS_MSB 0 -#define USB_SIE_CTRL_START_TRANS_LSB 0 +#define USB_SIE_CTRL_START_TRANS_RESET _u(0x0) +#define USB_SIE_CTRL_START_TRANS_BITS _u(0x00000001) +#define USB_SIE_CTRL_START_TRANS_MSB _u(0) +#define USB_SIE_CTRL_START_TRANS_LSB _u(0) #define USB_SIE_CTRL_START_TRANS_ACCESS "SC" // ============================================================================= // Register : USB_SIE_STATUS // Description : SIE status register -#define USB_SIE_STATUS_OFFSET 0x00000050 -#define USB_SIE_STATUS_BITS 0xff0f0f1d -#define USB_SIE_STATUS_RESET 0x00000000 +#define USB_SIE_STATUS_OFFSET _u(0x00000050) +#define USB_SIE_STATUS_BITS _u(0xff0f0f1d) +#define USB_SIE_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_DATA_SEQ_ERROR // Description : Data Sequence Error. @@ -905,76 +905,76 @@ // conditions: // // * An IN packet from the device has the wrong data PID -#define USB_SIE_STATUS_DATA_SEQ_ERROR_RESET 0x0 -#define USB_SIE_STATUS_DATA_SEQ_ERROR_BITS 0x80000000 -#define USB_SIE_STATUS_DATA_SEQ_ERROR_MSB 31 -#define USB_SIE_STATUS_DATA_SEQ_ERROR_LSB 31 +#define USB_SIE_STATUS_DATA_SEQ_ERROR_RESET _u(0x0) +#define USB_SIE_STATUS_DATA_SEQ_ERROR_BITS _u(0x80000000) +#define USB_SIE_STATUS_DATA_SEQ_ERROR_MSB _u(31) +#define USB_SIE_STATUS_DATA_SEQ_ERROR_LSB _u(31) #define USB_SIE_STATUS_DATA_SEQ_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_ACK_REC // Description : ACK received. Raised by both host and device. -#define USB_SIE_STATUS_ACK_REC_RESET 0x0 -#define USB_SIE_STATUS_ACK_REC_BITS 0x40000000 -#define USB_SIE_STATUS_ACK_REC_MSB 30 -#define USB_SIE_STATUS_ACK_REC_LSB 30 +#define USB_SIE_STATUS_ACK_REC_RESET _u(0x0) +#define USB_SIE_STATUS_ACK_REC_BITS _u(0x40000000) +#define USB_SIE_STATUS_ACK_REC_MSB _u(30) +#define USB_SIE_STATUS_ACK_REC_LSB _u(30) #define USB_SIE_STATUS_ACK_REC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_STALL_REC // Description : Host: STALL received -#define USB_SIE_STATUS_STALL_REC_RESET 0x0 -#define USB_SIE_STATUS_STALL_REC_BITS 0x20000000 -#define USB_SIE_STATUS_STALL_REC_MSB 29 -#define USB_SIE_STATUS_STALL_REC_LSB 29 +#define USB_SIE_STATUS_STALL_REC_RESET _u(0x0) +#define USB_SIE_STATUS_STALL_REC_BITS _u(0x20000000) +#define USB_SIE_STATUS_STALL_REC_MSB _u(29) +#define USB_SIE_STATUS_STALL_REC_LSB _u(29) #define USB_SIE_STATUS_STALL_REC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_NAK_REC // Description : Host: NAK received -#define USB_SIE_STATUS_NAK_REC_RESET 0x0 -#define USB_SIE_STATUS_NAK_REC_BITS 0x10000000 -#define USB_SIE_STATUS_NAK_REC_MSB 28 -#define USB_SIE_STATUS_NAK_REC_LSB 28 +#define USB_SIE_STATUS_NAK_REC_RESET _u(0x0) +#define USB_SIE_STATUS_NAK_REC_BITS _u(0x10000000) +#define USB_SIE_STATUS_NAK_REC_MSB _u(28) +#define USB_SIE_STATUS_NAK_REC_LSB _u(28) #define USB_SIE_STATUS_NAK_REC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_RX_TIMEOUT // Description : RX timeout is raised by both the host and device if an ACK is // not received in the maximum time specified by the USB spec. -#define USB_SIE_STATUS_RX_TIMEOUT_RESET 0x0 -#define USB_SIE_STATUS_RX_TIMEOUT_BITS 0x08000000 -#define USB_SIE_STATUS_RX_TIMEOUT_MSB 27 -#define USB_SIE_STATUS_RX_TIMEOUT_LSB 27 +#define USB_SIE_STATUS_RX_TIMEOUT_RESET _u(0x0) +#define USB_SIE_STATUS_RX_TIMEOUT_BITS _u(0x08000000) +#define USB_SIE_STATUS_RX_TIMEOUT_MSB _u(27) +#define USB_SIE_STATUS_RX_TIMEOUT_LSB _u(27) #define USB_SIE_STATUS_RX_TIMEOUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_RX_OVERFLOW // Description : RX overflow is raised by the Serial RX engine if the incoming // data is too fast. -#define USB_SIE_STATUS_RX_OVERFLOW_RESET 0x0 -#define USB_SIE_STATUS_RX_OVERFLOW_BITS 0x04000000 -#define USB_SIE_STATUS_RX_OVERFLOW_MSB 26 -#define USB_SIE_STATUS_RX_OVERFLOW_LSB 26 +#define USB_SIE_STATUS_RX_OVERFLOW_RESET _u(0x0) +#define USB_SIE_STATUS_RX_OVERFLOW_BITS _u(0x04000000) +#define USB_SIE_STATUS_RX_OVERFLOW_MSB _u(26) +#define USB_SIE_STATUS_RX_OVERFLOW_LSB _u(26) #define USB_SIE_STATUS_RX_OVERFLOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_BIT_STUFF_ERROR // Description : Bit Stuff Error. Raised by the Serial RX engine. -#define USB_SIE_STATUS_BIT_STUFF_ERROR_RESET 0x0 -#define USB_SIE_STATUS_BIT_STUFF_ERROR_BITS 0x02000000 -#define USB_SIE_STATUS_BIT_STUFF_ERROR_MSB 25 -#define USB_SIE_STATUS_BIT_STUFF_ERROR_LSB 25 +#define USB_SIE_STATUS_BIT_STUFF_ERROR_RESET _u(0x0) +#define USB_SIE_STATUS_BIT_STUFF_ERROR_BITS _u(0x02000000) +#define USB_SIE_STATUS_BIT_STUFF_ERROR_MSB _u(25) +#define USB_SIE_STATUS_BIT_STUFF_ERROR_LSB _u(25) #define USB_SIE_STATUS_BIT_STUFF_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_CRC_ERROR // Description : CRC Error. Raised by the Serial RX engine. -#define USB_SIE_STATUS_CRC_ERROR_RESET 0x0 -#define USB_SIE_STATUS_CRC_ERROR_BITS 0x01000000 -#define USB_SIE_STATUS_CRC_ERROR_MSB 24 -#define USB_SIE_STATUS_CRC_ERROR_LSB 24 +#define USB_SIE_STATUS_CRC_ERROR_RESET _u(0x0) +#define USB_SIE_STATUS_CRC_ERROR_BITS _u(0x01000000) +#define USB_SIE_STATUS_CRC_ERROR_MSB _u(24) +#define USB_SIE_STATUS_CRC_ERROR_LSB _u(24) #define USB_SIE_STATUS_CRC_ERROR_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_BUS_RESET // Description : Device: bus reset received -#define USB_SIE_STATUS_BUS_RESET_RESET 0x0 -#define USB_SIE_STATUS_BUS_RESET_BITS 0x00080000 -#define USB_SIE_STATUS_BUS_RESET_MSB 19 -#define USB_SIE_STATUS_BUS_RESET_LSB 19 +#define USB_SIE_STATUS_BUS_RESET_RESET _u(0x0) +#define USB_SIE_STATUS_BUS_RESET_BITS _u(0x00080000) +#define USB_SIE_STATUS_BUS_RESET_MSB _u(19) +#define USB_SIE_STATUS_BUS_RESET_LSB _u(19) #define USB_SIE_STATUS_BUS_RESET_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_TRANS_COMPLETE @@ -992,91 +992,91 @@ // `LAST_BUFF` bit is set in the buffer control register * An IN // packet is received with zero length * An OUT packet is sent and // the `LAST_BUFF` bit is set -#define USB_SIE_STATUS_TRANS_COMPLETE_RESET 0x0 -#define USB_SIE_STATUS_TRANS_COMPLETE_BITS 0x00040000 -#define USB_SIE_STATUS_TRANS_COMPLETE_MSB 18 -#define USB_SIE_STATUS_TRANS_COMPLETE_LSB 18 +#define USB_SIE_STATUS_TRANS_COMPLETE_RESET _u(0x0) +#define USB_SIE_STATUS_TRANS_COMPLETE_BITS _u(0x00040000) +#define USB_SIE_STATUS_TRANS_COMPLETE_MSB _u(18) +#define USB_SIE_STATUS_TRANS_COMPLETE_LSB _u(18) #define USB_SIE_STATUS_TRANS_COMPLETE_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_SETUP_REC // Description : Device: Setup packet received -#define USB_SIE_STATUS_SETUP_REC_RESET 0x0 -#define USB_SIE_STATUS_SETUP_REC_BITS 0x00020000 -#define USB_SIE_STATUS_SETUP_REC_MSB 17 -#define USB_SIE_STATUS_SETUP_REC_LSB 17 +#define USB_SIE_STATUS_SETUP_REC_RESET _u(0x0) +#define USB_SIE_STATUS_SETUP_REC_BITS _u(0x00020000) +#define USB_SIE_STATUS_SETUP_REC_MSB _u(17) +#define USB_SIE_STATUS_SETUP_REC_LSB _u(17) #define USB_SIE_STATUS_SETUP_REC_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_CONNECTED // Description : Device: connected -#define USB_SIE_STATUS_CONNECTED_RESET 0x0 -#define USB_SIE_STATUS_CONNECTED_BITS 0x00010000 -#define USB_SIE_STATUS_CONNECTED_MSB 16 -#define USB_SIE_STATUS_CONNECTED_LSB 16 -#define USB_SIE_STATUS_CONNECTED_ACCESS "RO" +#define USB_SIE_STATUS_CONNECTED_RESET _u(0x0) +#define USB_SIE_STATUS_CONNECTED_BITS _u(0x00010000) +#define USB_SIE_STATUS_CONNECTED_MSB _u(16) +#define USB_SIE_STATUS_CONNECTED_LSB _u(16) +#define USB_SIE_STATUS_CONNECTED_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_RESUME // Description : Host: Device has initiated a remote resume. Device: host has // initiated a resume. -#define USB_SIE_STATUS_RESUME_RESET 0x0 -#define USB_SIE_STATUS_RESUME_BITS 0x00000800 -#define USB_SIE_STATUS_RESUME_MSB 11 -#define USB_SIE_STATUS_RESUME_LSB 11 +#define USB_SIE_STATUS_RESUME_RESET _u(0x0) +#define USB_SIE_STATUS_RESUME_BITS _u(0x00000800) +#define USB_SIE_STATUS_RESUME_MSB _u(11) +#define USB_SIE_STATUS_RESUME_LSB _u(11) #define USB_SIE_STATUS_RESUME_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_VBUS_OVER_CURR // Description : VBUS over current detected -#define USB_SIE_STATUS_VBUS_OVER_CURR_RESET 0x0 -#define USB_SIE_STATUS_VBUS_OVER_CURR_BITS 0x00000400 -#define USB_SIE_STATUS_VBUS_OVER_CURR_MSB 10 -#define USB_SIE_STATUS_VBUS_OVER_CURR_LSB 10 +#define USB_SIE_STATUS_VBUS_OVER_CURR_RESET _u(0x0) +#define USB_SIE_STATUS_VBUS_OVER_CURR_BITS _u(0x00000400) +#define USB_SIE_STATUS_VBUS_OVER_CURR_MSB _u(10) +#define USB_SIE_STATUS_VBUS_OVER_CURR_LSB _u(10) #define USB_SIE_STATUS_VBUS_OVER_CURR_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_SPEED // Description : Host: device speed. Disconnected = 00, LS = 01, FS = 10 -#define USB_SIE_STATUS_SPEED_RESET 0x0 -#define USB_SIE_STATUS_SPEED_BITS 0x00000300 -#define USB_SIE_STATUS_SPEED_MSB 9 -#define USB_SIE_STATUS_SPEED_LSB 8 -#define USB_SIE_STATUS_SPEED_ACCESS "RO" +#define USB_SIE_STATUS_SPEED_RESET _u(0x0) +#define USB_SIE_STATUS_SPEED_BITS _u(0x00000300) +#define USB_SIE_STATUS_SPEED_MSB _u(9) +#define USB_SIE_STATUS_SPEED_LSB _u(8) +#define USB_SIE_STATUS_SPEED_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_SUSPENDED // Description : Bus in suspended state. Valid for device and host. Host and // device will go into suspend if neither Keep Alive / SOF frames // are enabled. -#define USB_SIE_STATUS_SUSPENDED_RESET 0x0 -#define USB_SIE_STATUS_SUSPENDED_BITS 0x00000010 -#define USB_SIE_STATUS_SUSPENDED_MSB 4 -#define USB_SIE_STATUS_SUSPENDED_LSB 4 -#define USB_SIE_STATUS_SUSPENDED_ACCESS "RO" +#define USB_SIE_STATUS_SUSPENDED_RESET _u(0x0) +#define USB_SIE_STATUS_SUSPENDED_BITS _u(0x00000010) +#define USB_SIE_STATUS_SUSPENDED_MSB _u(4) +#define USB_SIE_STATUS_SUSPENDED_LSB _u(4) +#define USB_SIE_STATUS_SUSPENDED_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_LINE_STATE // Description : USB bus line state -#define USB_SIE_STATUS_LINE_STATE_RESET 0x0 -#define USB_SIE_STATUS_LINE_STATE_BITS 0x0000000c -#define USB_SIE_STATUS_LINE_STATE_MSB 3 -#define USB_SIE_STATUS_LINE_STATE_LSB 2 +#define USB_SIE_STATUS_LINE_STATE_RESET _u(0x0) +#define USB_SIE_STATUS_LINE_STATE_BITS _u(0x0000000c) +#define USB_SIE_STATUS_LINE_STATE_MSB _u(3) +#define USB_SIE_STATUS_LINE_STATE_LSB _u(2) #define USB_SIE_STATUS_LINE_STATE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_VBUS_DETECTED // Description : Device: VBUS Detected -#define USB_SIE_STATUS_VBUS_DETECTED_RESET 0x0 -#define USB_SIE_STATUS_VBUS_DETECTED_BITS 0x00000001 -#define USB_SIE_STATUS_VBUS_DETECTED_MSB 0 -#define USB_SIE_STATUS_VBUS_DETECTED_LSB 0 +#define USB_SIE_STATUS_VBUS_DETECTED_RESET _u(0x0) +#define USB_SIE_STATUS_VBUS_DETECTED_BITS _u(0x00000001) +#define USB_SIE_STATUS_VBUS_DETECTED_MSB _u(0) +#define USB_SIE_STATUS_VBUS_DETECTED_LSB _u(0) #define USB_SIE_STATUS_VBUS_DETECTED_ACCESS "RO" // ============================================================================= // Register : USB_INT_EP_CTRL // Description : interrupt endpoint control register -#define USB_INT_EP_CTRL_OFFSET 0x00000054 -#define USB_INT_EP_CTRL_BITS 0x0000fffe -#define USB_INT_EP_CTRL_RESET 0x00000000 +#define USB_INT_EP_CTRL_OFFSET _u(0x00000054) +#define USB_INT_EP_CTRL_BITS _u(0x0000fffe) +#define USB_INT_EP_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_INT_EP_CTRL_INT_EP_ACTIVE // Description : Host: Enable interrupt endpoint 1 -> 15 -#define USB_INT_EP_CTRL_INT_EP_ACTIVE_RESET 0x0000 -#define USB_INT_EP_CTRL_INT_EP_ACTIVE_BITS 0x0000fffe -#define USB_INT_EP_CTRL_INT_EP_ACTIVE_MSB 15 -#define USB_INT_EP_CTRL_INT_EP_ACTIVE_LSB 1 +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_RESET _u(0x0000) +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_BITS _u(0x0000fffe) +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_MSB _u(15) +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_LSB _u(1) #define USB_INT_EP_CTRL_INT_EP_ACTIVE_ACCESS "RW" // ============================================================================= // Register : USB_BUFF_STATUS @@ -1085,529 +1085,529 @@ // enabled). It is possible for 2 buffers to be completed, so // clearing the buffer status bit may instantly re set it on the // next clock cycle. -#define USB_BUFF_STATUS_OFFSET 0x00000058 -#define USB_BUFF_STATUS_BITS 0xffffffff -#define USB_BUFF_STATUS_RESET 0x00000000 +#define USB_BUFF_STATUS_OFFSET _u(0x00000058) +#define USB_BUFF_STATUS_BITS _u(0xffffffff) +#define USB_BUFF_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP15_OUT // Description : None -#define USB_BUFF_STATUS_EP15_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP15_OUT_BITS 0x80000000 -#define USB_BUFF_STATUS_EP15_OUT_MSB 31 -#define USB_BUFF_STATUS_EP15_OUT_LSB 31 -#define USB_BUFF_STATUS_EP15_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP15_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP15_OUT_BITS _u(0x80000000) +#define USB_BUFF_STATUS_EP15_OUT_MSB _u(31) +#define USB_BUFF_STATUS_EP15_OUT_LSB _u(31) +#define USB_BUFF_STATUS_EP15_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP15_IN // Description : None -#define USB_BUFF_STATUS_EP15_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP15_IN_BITS 0x40000000 -#define USB_BUFF_STATUS_EP15_IN_MSB 30 -#define USB_BUFF_STATUS_EP15_IN_LSB 30 -#define USB_BUFF_STATUS_EP15_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP15_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP15_IN_BITS _u(0x40000000) +#define USB_BUFF_STATUS_EP15_IN_MSB _u(30) +#define USB_BUFF_STATUS_EP15_IN_LSB _u(30) +#define USB_BUFF_STATUS_EP15_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP14_OUT // Description : None -#define USB_BUFF_STATUS_EP14_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP14_OUT_BITS 0x20000000 -#define USB_BUFF_STATUS_EP14_OUT_MSB 29 -#define USB_BUFF_STATUS_EP14_OUT_LSB 29 -#define USB_BUFF_STATUS_EP14_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP14_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP14_OUT_BITS _u(0x20000000) +#define USB_BUFF_STATUS_EP14_OUT_MSB _u(29) +#define USB_BUFF_STATUS_EP14_OUT_LSB _u(29) +#define USB_BUFF_STATUS_EP14_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP14_IN // Description : None -#define USB_BUFF_STATUS_EP14_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP14_IN_BITS 0x10000000 -#define USB_BUFF_STATUS_EP14_IN_MSB 28 -#define USB_BUFF_STATUS_EP14_IN_LSB 28 -#define USB_BUFF_STATUS_EP14_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP14_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP14_IN_BITS _u(0x10000000) +#define USB_BUFF_STATUS_EP14_IN_MSB _u(28) +#define USB_BUFF_STATUS_EP14_IN_LSB _u(28) +#define USB_BUFF_STATUS_EP14_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP13_OUT // Description : None -#define USB_BUFF_STATUS_EP13_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP13_OUT_BITS 0x08000000 -#define USB_BUFF_STATUS_EP13_OUT_MSB 27 -#define USB_BUFF_STATUS_EP13_OUT_LSB 27 -#define USB_BUFF_STATUS_EP13_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP13_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP13_OUT_BITS _u(0x08000000) +#define USB_BUFF_STATUS_EP13_OUT_MSB _u(27) +#define USB_BUFF_STATUS_EP13_OUT_LSB _u(27) +#define USB_BUFF_STATUS_EP13_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP13_IN // Description : None -#define USB_BUFF_STATUS_EP13_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP13_IN_BITS 0x04000000 -#define USB_BUFF_STATUS_EP13_IN_MSB 26 -#define USB_BUFF_STATUS_EP13_IN_LSB 26 -#define USB_BUFF_STATUS_EP13_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP13_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP13_IN_BITS _u(0x04000000) +#define USB_BUFF_STATUS_EP13_IN_MSB _u(26) +#define USB_BUFF_STATUS_EP13_IN_LSB _u(26) +#define USB_BUFF_STATUS_EP13_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP12_OUT // Description : None -#define USB_BUFF_STATUS_EP12_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP12_OUT_BITS 0x02000000 -#define USB_BUFF_STATUS_EP12_OUT_MSB 25 -#define USB_BUFF_STATUS_EP12_OUT_LSB 25 -#define USB_BUFF_STATUS_EP12_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP12_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP12_OUT_BITS _u(0x02000000) +#define USB_BUFF_STATUS_EP12_OUT_MSB _u(25) +#define USB_BUFF_STATUS_EP12_OUT_LSB _u(25) +#define USB_BUFF_STATUS_EP12_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP12_IN // Description : None -#define USB_BUFF_STATUS_EP12_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP12_IN_BITS 0x01000000 -#define USB_BUFF_STATUS_EP12_IN_MSB 24 -#define USB_BUFF_STATUS_EP12_IN_LSB 24 -#define USB_BUFF_STATUS_EP12_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP12_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP12_IN_BITS _u(0x01000000) +#define USB_BUFF_STATUS_EP12_IN_MSB _u(24) +#define USB_BUFF_STATUS_EP12_IN_LSB _u(24) +#define USB_BUFF_STATUS_EP12_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP11_OUT // Description : None -#define USB_BUFF_STATUS_EP11_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP11_OUT_BITS 0x00800000 -#define USB_BUFF_STATUS_EP11_OUT_MSB 23 -#define USB_BUFF_STATUS_EP11_OUT_LSB 23 -#define USB_BUFF_STATUS_EP11_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP11_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP11_OUT_BITS _u(0x00800000) +#define USB_BUFF_STATUS_EP11_OUT_MSB _u(23) +#define USB_BUFF_STATUS_EP11_OUT_LSB _u(23) +#define USB_BUFF_STATUS_EP11_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP11_IN // Description : None -#define USB_BUFF_STATUS_EP11_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP11_IN_BITS 0x00400000 -#define USB_BUFF_STATUS_EP11_IN_MSB 22 -#define USB_BUFF_STATUS_EP11_IN_LSB 22 -#define USB_BUFF_STATUS_EP11_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP11_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP11_IN_BITS _u(0x00400000) +#define USB_BUFF_STATUS_EP11_IN_MSB _u(22) +#define USB_BUFF_STATUS_EP11_IN_LSB _u(22) +#define USB_BUFF_STATUS_EP11_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP10_OUT // Description : None -#define USB_BUFF_STATUS_EP10_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP10_OUT_BITS 0x00200000 -#define USB_BUFF_STATUS_EP10_OUT_MSB 21 -#define USB_BUFF_STATUS_EP10_OUT_LSB 21 -#define USB_BUFF_STATUS_EP10_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP10_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP10_OUT_BITS _u(0x00200000) +#define USB_BUFF_STATUS_EP10_OUT_MSB _u(21) +#define USB_BUFF_STATUS_EP10_OUT_LSB _u(21) +#define USB_BUFF_STATUS_EP10_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP10_IN // Description : None -#define USB_BUFF_STATUS_EP10_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP10_IN_BITS 0x00100000 -#define USB_BUFF_STATUS_EP10_IN_MSB 20 -#define USB_BUFF_STATUS_EP10_IN_LSB 20 -#define USB_BUFF_STATUS_EP10_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP10_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP10_IN_BITS _u(0x00100000) +#define USB_BUFF_STATUS_EP10_IN_MSB _u(20) +#define USB_BUFF_STATUS_EP10_IN_LSB _u(20) +#define USB_BUFF_STATUS_EP10_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP9_OUT // Description : None -#define USB_BUFF_STATUS_EP9_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP9_OUT_BITS 0x00080000 -#define USB_BUFF_STATUS_EP9_OUT_MSB 19 -#define USB_BUFF_STATUS_EP9_OUT_LSB 19 -#define USB_BUFF_STATUS_EP9_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP9_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP9_OUT_BITS _u(0x00080000) +#define USB_BUFF_STATUS_EP9_OUT_MSB _u(19) +#define USB_BUFF_STATUS_EP9_OUT_LSB _u(19) +#define USB_BUFF_STATUS_EP9_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP9_IN // Description : None -#define USB_BUFF_STATUS_EP9_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP9_IN_BITS 0x00040000 -#define USB_BUFF_STATUS_EP9_IN_MSB 18 -#define USB_BUFF_STATUS_EP9_IN_LSB 18 -#define USB_BUFF_STATUS_EP9_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP9_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP9_IN_BITS _u(0x00040000) +#define USB_BUFF_STATUS_EP9_IN_MSB _u(18) +#define USB_BUFF_STATUS_EP9_IN_LSB _u(18) +#define USB_BUFF_STATUS_EP9_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP8_OUT // Description : None -#define USB_BUFF_STATUS_EP8_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP8_OUT_BITS 0x00020000 -#define USB_BUFF_STATUS_EP8_OUT_MSB 17 -#define USB_BUFF_STATUS_EP8_OUT_LSB 17 -#define USB_BUFF_STATUS_EP8_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP8_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP8_OUT_BITS _u(0x00020000) +#define USB_BUFF_STATUS_EP8_OUT_MSB _u(17) +#define USB_BUFF_STATUS_EP8_OUT_LSB _u(17) +#define USB_BUFF_STATUS_EP8_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP8_IN // Description : None -#define USB_BUFF_STATUS_EP8_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP8_IN_BITS 0x00010000 -#define USB_BUFF_STATUS_EP8_IN_MSB 16 -#define USB_BUFF_STATUS_EP8_IN_LSB 16 -#define USB_BUFF_STATUS_EP8_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP8_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP8_IN_BITS _u(0x00010000) +#define USB_BUFF_STATUS_EP8_IN_MSB _u(16) +#define USB_BUFF_STATUS_EP8_IN_LSB _u(16) +#define USB_BUFF_STATUS_EP8_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP7_OUT // Description : None -#define USB_BUFF_STATUS_EP7_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP7_OUT_BITS 0x00008000 -#define USB_BUFF_STATUS_EP7_OUT_MSB 15 -#define USB_BUFF_STATUS_EP7_OUT_LSB 15 -#define USB_BUFF_STATUS_EP7_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP7_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP7_OUT_BITS _u(0x00008000) +#define USB_BUFF_STATUS_EP7_OUT_MSB _u(15) +#define USB_BUFF_STATUS_EP7_OUT_LSB _u(15) +#define USB_BUFF_STATUS_EP7_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP7_IN // Description : None -#define USB_BUFF_STATUS_EP7_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP7_IN_BITS 0x00004000 -#define USB_BUFF_STATUS_EP7_IN_MSB 14 -#define USB_BUFF_STATUS_EP7_IN_LSB 14 -#define USB_BUFF_STATUS_EP7_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP7_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP7_IN_BITS _u(0x00004000) +#define USB_BUFF_STATUS_EP7_IN_MSB _u(14) +#define USB_BUFF_STATUS_EP7_IN_LSB _u(14) +#define USB_BUFF_STATUS_EP7_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP6_OUT // Description : None -#define USB_BUFF_STATUS_EP6_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP6_OUT_BITS 0x00002000 -#define USB_BUFF_STATUS_EP6_OUT_MSB 13 -#define USB_BUFF_STATUS_EP6_OUT_LSB 13 -#define USB_BUFF_STATUS_EP6_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP6_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP6_OUT_BITS _u(0x00002000) +#define USB_BUFF_STATUS_EP6_OUT_MSB _u(13) +#define USB_BUFF_STATUS_EP6_OUT_LSB _u(13) +#define USB_BUFF_STATUS_EP6_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP6_IN // Description : None -#define USB_BUFF_STATUS_EP6_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP6_IN_BITS 0x00001000 -#define USB_BUFF_STATUS_EP6_IN_MSB 12 -#define USB_BUFF_STATUS_EP6_IN_LSB 12 -#define USB_BUFF_STATUS_EP6_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP6_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP6_IN_BITS _u(0x00001000) +#define USB_BUFF_STATUS_EP6_IN_MSB _u(12) +#define USB_BUFF_STATUS_EP6_IN_LSB _u(12) +#define USB_BUFF_STATUS_EP6_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP5_OUT // Description : None -#define USB_BUFF_STATUS_EP5_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP5_OUT_BITS 0x00000800 -#define USB_BUFF_STATUS_EP5_OUT_MSB 11 -#define USB_BUFF_STATUS_EP5_OUT_LSB 11 -#define USB_BUFF_STATUS_EP5_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP5_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP5_OUT_BITS _u(0x00000800) +#define USB_BUFF_STATUS_EP5_OUT_MSB _u(11) +#define USB_BUFF_STATUS_EP5_OUT_LSB _u(11) +#define USB_BUFF_STATUS_EP5_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP5_IN // Description : None -#define USB_BUFF_STATUS_EP5_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP5_IN_BITS 0x00000400 -#define USB_BUFF_STATUS_EP5_IN_MSB 10 -#define USB_BUFF_STATUS_EP5_IN_LSB 10 -#define USB_BUFF_STATUS_EP5_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP5_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP5_IN_BITS _u(0x00000400) +#define USB_BUFF_STATUS_EP5_IN_MSB _u(10) +#define USB_BUFF_STATUS_EP5_IN_LSB _u(10) +#define USB_BUFF_STATUS_EP5_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP4_OUT // Description : None -#define USB_BUFF_STATUS_EP4_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP4_OUT_BITS 0x00000200 -#define USB_BUFF_STATUS_EP4_OUT_MSB 9 -#define USB_BUFF_STATUS_EP4_OUT_LSB 9 -#define USB_BUFF_STATUS_EP4_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP4_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP4_OUT_BITS _u(0x00000200) +#define USB_BUFF_STATUS_EP4_OUT_MSB _u(9) +#define USB_BUFF_STATUS_EP4_OUT_LSB _u(9) +#define USB_BUFF_STATUS_EP4_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP4_IN // Description : None -#define USB_BUFF_STATUS_EP4_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP4_IN_BITS 0x00000100 -#define USB_BUFF_STATUS_EP4_IN_MSB 8 -#define USB_BUFF_STATUS_EP4_IN_LSB 8 -#define USB_BUFF_STATUS_EP4_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP4_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP4_IN_BITS _u(0x00000100) +#define USB_BUFF_STATUS_EP4_IN_MSB _u(8) +#define USB_BUFF_STATUS_EP4_IN_LSB _u(8) +#define USB_BUFF_STATUS_EP4_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP3_OUT // Description : None -#define USB_BUFF_STATUS_EP3_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP3_OUT_BITS 0x00000080 -#define USB_BUFF_STATUS_EP3_OUT_MSB 7 -#define USB_BUFF_STATUS_EP3_OUT_LSB 7 -#define USB_BUFF_STATUS_EP3_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP3_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP3_OUT_BITS _u(0x00000080) +#define USB_BUFF_STATUS_EP3_OUT_MSB _u(7) +#define USB_BUFF_STATUS_EP3_OUT_LSB _u(7) +#define USB_BUFF_STATUS_EP3_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP3_IN // Description : None -#define USB_BUFF_STATUS_EP3_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP3_IN_BITS 0x00000040 -#define USB_BUFF_STATUS_EP3_IN_MSB 6 -#define USB_BUFF_STATUS_EP3_IN_LSB 6 -#define USB_BUFF_STATUS_EP3_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP3_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP3_IN_BITS _u(0x00000040) +#define USB_BUFF_STATUS_EP3_IN_MSB _u(6) +#define USB_BUFF_STATUS_EP3_IN_LSB _u(6) +#define USB_BUFF_STATUS_EP3_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP2_OUT // Description : None -#define USB_BUFF_STATUS_EP2_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP2_OUT_BITS 0x00000020 -#define USB_BUFF_STATUS_EP2_OUT_MSB 5 -#define USB_BUFF_STATUS_EP2_OUT_LSB 5 -#define USB_BUFF_STATUS_EP2_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP2_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP2_OUT_BITS _u(0x00000020) +#define USB_BUFF_STATUS_EP2_OUT_MSB _u(5) +#define USB_BUFF_STATUS_EP2_OUT_LSB _u(5) +#define USB_BUFF_STATUS_EP2_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP2_IN // Description : None -#define USB_BUFF_STATUS_EP2_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP2_IN_BITS 0x00000010 -#define USB_BUFF_STATUS_EP2_IN_MSB 4 -#define USB_BUFF_STATUS_EP2_IN_LSB 4 -#define USB_BUFF_STATUS_EP2_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP2_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP2_IN_BITS _u(0x00000010) +#define USB_BUFF_STATUS_EP2_IN_MSB _u(4) +#define USB_BUFF_STATUS_EP2_IN_LSB _u(4) +#define USB_BUFF_STATUS_EP2_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP1_OUT // Description : None -#define USB_BUFF_STATUS_EP1_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP1_OUT_BITS 0x00000008 -#define USB_BUFF_STATUS_EP1_OUT_MSB 3 -#define USB_BUFF_STATUS_EP1_OUT_LSB 3 -#define USB_BUFF_STATUS_EP1_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP1_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP1_OUT_BITS _u(0x00000008) +#define USB_BUFF_STATUS_EP1_OUT_MSB _u(3) +#define USB_BUFF_STATUS_EP1_OUT_LSB _u(3) +#define USB_BUFF_STATUS_EP1_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP1_IN // Description : None -#define USB_BUFF_STATUS_EP1_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP1_IN_BITS 0x00000004 -#define USB_BUFF_STATUS_EP1_IN_MSB 2 -#define USB_BUFF_STATUS_EP1_IN_LSB 2 -#define USB_BUFF_STATUS_EP1_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP1_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP1_IN_BITS _u(0x00000004) +#define USB_BUFF_STATUS_EP1_IN_MSB _u(2) +#define USB_BUFF_STATUS_EP1_IN_LSB _u(2) +#define USB_BUFF_STATUS_EP1_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP0_OUT // Description : None -#define USB_BUFF_STATUS_EP0_OUT_RESET 0x0 -#define USB_BUFF_STATUS_EP0_OUT_BITS 0x00000002 -#define USB_BUFF_STATUS_EP0_OUT_MSB 1 -#define USB_BUFF_STATUS_EP0_OUT_LSB 1 -#define USB_BUFF_STATUS_EP0_OUT_ACCESS "RO" +#define USB_BUFF_STATUS_EP0_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP0_OUT_BITS _u(0x00000002) +#define USB_BUFF_STATUS_EP0_OUT_MSB _u(1) +#define USB_BUFF_STATUS_EP0_OUT_LSB _u(1) +#define USB_BUFF_STATUS_EP0_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP0_IN // Description : None -#define USB_BUFF_STATUS_EP0_IN_RESET 0x0 -#define USB_BUFF_STATUS_EP0_IN_BITS 0x00000001 -#define USB_BUFF_STATUS_EP0_IN_MSB 0 -#define USB_BUFF_STATUS_EP0_IN_LSB 0 -#define USB_BUFF_STATUS_EP0_IN_ACCESS "RO" +#define USB_BUFF_STATUS_EP0_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP0_IN_BITS _u(0x00000001) +#define USB_BUFF_STATUS_EP0_IN_MSB _u(0) +#define USB_BUFF_STATUS_EP0_IN_LSB _u(0) +#define USB_BUFF_STATUS_EP0_IN_ACCESS "WC" // ============================================================================= // Register : USB_BUFF_CPU_SHOULD_HANDLE // Description : Which of the double buffers should be handled. Only valid if // using an interrupt per buffer (i.e. not per 2 buffers). Not // valid for host interrupt endpoint polling because they are only // single buffered. -#define USB_BUFF_CPU_SHOULD_HANDLE_OFFSET 0x0000005c -#define USB_BUFF_CPU_SHOULD_HANDLE_BITS 0xffffffff -#define USB_BUFF_CPU_SHOULD_HANDLE_RESET 0x00000000 +#define USB_BUFF_CPU_SHOULD_HANDLE_OFFSET _u(0x0000005c) +#define USB_BUFF_CPU_SHOULD_HANDLE_BITS _u(0xffffffff) +#define USB_BUFF_CPU_SHOULD_HANDLE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_BITS 0x80000000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_MSB 31 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_LSB 31 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_BITS _u(0x80000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_MSB _u(31) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_LSB _u(31) #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_BITS 0x40000000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_MSB 30 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_LSB 30 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_BITS _u(0x40000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_MSB _u(30) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_LSB _u(30) #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_BITS 0x20000000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_MSB 29 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_LSB 29 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_BITS _u(0x20000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_MSB _u(29) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_LSB _u(29) #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_BITS 0x10000000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_MSB 28 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_LSB 28 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_BITS _u(0x10000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_MSB _u(28) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_LSB _u(28) #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_BITS 0x08000000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_MSB 27 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_LSB 27 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_BITS _u(0x08000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_MSB _u(27) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_LSB _u(27) #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_BITS 0x04000000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_MSB 26 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_LSB 26 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_BITS _u(0x04000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_MSB _u(26) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_LSB _u(26) #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_BITS 0x02000000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_MSB 25 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_LSB 25 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_BITS _u(0x02000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_MSB _u(25) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_LSB _u(25) #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_BITS 0x01000000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_MSB 24 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_LSB 24 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_BITS _u(0x01000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_MSB _u(24) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_LSB _u(24) #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_BITS 0x00800000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_MSB 23 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_LSB 23 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_BITS _u(0x00800000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_MSB _u(23) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_LSB _u(23) #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_BITS 0x00400000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_MSB 22 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_LSB 22 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_BITS _u(0x00400000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_MSB _u(22) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_LSB _u(22) #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_BITS 0x00200000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_MSB 21 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_LSB 21 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_BITS _u(0x00200000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_MSB _u(21) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_LSB _u(21) #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_BITS 0x00100000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_MSB 20 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_LSB 20 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_BITS _u(0x00100000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_MSB _u(20) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_LSB _u(20) #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_BITS 0x00080000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_MSB 19 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_LSB 19 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_BITS _u(0x00080000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_MSB _u(19) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_LSB _u(19) #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_BITS 0x00040000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_MSB 18 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_LSB 18 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_BITS _u(0x00040000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_MSB _u(18) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_LSB _u(18) #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_BITS 0x00020000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_MSB 17 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_LSB 17 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_BITS _u(0x00020000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_MSB _u(17) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_LSB _u(17) #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_BITS 0x00010000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_MSB 16 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_LSB 16 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_BITS _u(0x00010000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_MSB _u(16) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_LSB _u(16) #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_BITS 0x00008000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_MSB 15 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_LSB 15 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_BITS _u(0x00008000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_MSB _u(15) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_LSB _u(15) #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_BITS 0x00004000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_MSB 14 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_LSB 14 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_BITS _u(0x00004000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_MSB _u(14) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_LSB _u(14) #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_BITS 0x00002000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_MSB 13 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_LSB 13 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_BITS _u(0x00002000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_MSB _u(13) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_LSB _u(13) #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_BITS 0x00001000 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_MSB 12 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_LSB 12 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_BITS _u(0x00001000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_MSB _u(12) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_LSB _u(12) #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_BITS 0x00000800 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_MSB 11 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_LSB 11 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_BITS _u(0x00000800) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_MSB _u(11) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_LSB _u(11) #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_BITS 0x00000400 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_MSB 10 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_LSB 10 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_BITS _u(0x00000400) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_MSB _u(10) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_LSB _u(10) #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_BITS 0x00000200 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_MSB 9 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_LSB 9 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_BITS _u(0x00000200) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_MSB _u(9) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_LSB _u(9) #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_BITS 0x00000100 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_MSB 8 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_LSB 8 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_BITS _u(0x00000100) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_MSB _u(8) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_LSB _u(8) #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_BITS 0x00000080 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_MSB 7 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_LSB 7 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_BITS _u(0x00000080) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_MSB _u(7) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_LSB _u(7) #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_BITS 0x00000040 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_MSB 6 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_LSB 6 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_BITS _u(0x00000040) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_MSB _u(6) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_LSB _u(6) #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_BITS 0x00000020 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_MSB 5 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_LSB 5 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_BITS _u(0x00000020) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_MSB _u(5) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_LSB _u(5) #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_BITS 0x00000010 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_MSB 4 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_LSB 4 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_BITS _u(0x00000010) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_MSB _u(4) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_LSB _u(4) #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_BITS 0x00000008 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_MSB 3 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_LSB 3 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_BITS _u(0x00000008) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_MSB _u(3) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_LSB _u(3) #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_BITS 0x00000004 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_MSB 2 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_LSB 2 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_BITS _u(0x00000004) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_MSB _u(2) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_LSB _u(2) #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_BITS 0x00000002 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_MSB 1 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_LSB 1 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_BITS _u(0x00000002) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_MSB _u(1) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_LSB _u(1) #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN // Description : None -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_RESET 0x0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_BITS 0x00000001 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_MSB 0 -#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_LSB 0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_BITS _u(0x00000001) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_MSB _u(0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_LSB _u(0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_ACCESS "RO" // ============================================================================= // Register : USB_EP_ABORT @@ -1616,528 +1616,528 @@ // NAK will be sent for every access to the endpoint until this // bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set // when it is safe to modify the buffer control register. -#define USB_EP_ABORT_OFFSET 0x00000060 -#define USB_EP_ABORT_BITS 0xffffffff -#define USB_EP_ABORT_RESET 0x00000000 +#define USB_EP_ABORT_OFFSET _u(0x00000060) +#define USB_EP_ABORT_BITS _u(0xffffffff) +#define USB_EP_ABORT_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP15_OUT // Description : None -#define USB_EP_ABORT_EP15_OUT_RESET 0x0 -#define USB_EP_ABORT_EP15_OUT_BITS 0x80000000 -#define USB_EP_ABORT_EP15_OUT_MSB 31 -#define USB_EP_ABORT_EP15_OUT_LSB 31 +#define USB_EP_ABORT_EP15_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP15_OUT_BITS _u(0x80000000) +#define USB_EP_ABORT_EP15_OUT_MSB _u(31) +#define USB_EP_ABORT_EP15_OUT_LSB _u(31) #define USB_EP_ABORT_EP15_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP15_IN // Description : None -#define USB_EP_ABORT_EP15_IN_RESET 0x0 -#define USB_EP_ABORT_EP15_IN_BITS 0x40000000 -#define USB_EP_ABORT_EP15_IN_MSB 30 -#define USB_EP_ABORT_EP15_IN_LSB 30 +#define USB_EP_ABORT_EP15_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP15_IN_BITS _u(0x40000000) +#define USB_EP_ABORT_EP15_IN_MSB _u(30) +#define USB_EP_ABORT_EP15_IN_LSB _u(30) #define USB_EP_ABORT_EP15_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP14_OUT // Description : None -#define USB_EP_ABORT_EP14_OUT_RESET 0x0 -#define USB_EP_ABORT_EP14_OUT_BITS 0x20000000 -#define USB_EP_ABORT_EP14_OUT_MSB 29 -#define USB_EP_ABORT_EP14_OUT_LSB 29 +#define USB_EP_ABORT_EP14_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP14_OUT_BITS _u(0x20000000) +#define USB_EP_ABORT_EP14_OUT_MSB _u(29) +#define USB_EP_ABORT_EP14_OUT_LSB _u(29) #define USB_EP_ABORT_EP14_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP14_IN // Description : None -#define USB_EP_ABORT_EP14_IN_RESET 0x0 -#define USB_EP_ABORT_EP14_IN_BITS 0x10000000 -#define USB_EP_ABORT_EP14_IN_MSB 28 -#define USB_EP_ABORT_EP14_IN_LSB 28 +#define USB_EP_ABORT_EP14_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP14_IN_BITS _u(0x10000000) +#define USB_EP_ABORT_EP14_IN_MSB _u(28) +#define USB_EP_ABORT_EP14_IN_LSB _u(28) #define USB_EP_ABORT_EP14_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP13_OUT // Description : None -#define USB_EP_ABORT_EP13_OUT_RESET 0x0 -#define USB_EP_ABORT_EP13_OUT_BITS 0x08000000 -#define USB_EP_ABORT_EP13_OUT_MSB 27 -#define USB_EP_ABORT_EP13_OUT_LSB 27 +#define USB_EP_ABORT_EP13_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP13_OUT_BITS _u(0x08000000) +#define USB_EP_ABORT_EP13_OUT_MSB _u(27) +#define USB_EP_ABORT_EP13_OUT_LSB _u(27) #define USB_EP_ABORT_EP13_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP13_IN // Description : None -#define USB_EP_ABORT_EP13_IN_RESET 0x0 -#define USB_EP_ABORT_EP13_IN_BITS 0x04000000 -#define USB_EP_ABORT_EP13_IN_MSB 26 -#define USB_EP_ABORT_EP13_IN_LSB 26 +#define USB_EP_ABORT_EP13_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP13_IN_BITS _u(0x04000000) +#define USB_EP_ABORT_EP13_IN_MSB _u(26) +#define USB_EP_ABORT_EP13_IN_LSB _u(26) #define USB_EP_ABORT_EP13_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP12_OUT // Description : None -#define USB_EP_ABORT_EP12_OUT_RESET 0x0 -#define USB_EP_ABORT_EP12_OUT_BITS 0x02000000 -#define USB_EP_ABORT_EP12_OUT_MSB 25 -#define USB_EP_ABORT_EP12_OUT_LSB 25 +#define USB_EP_ABORT_EP12_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP12_OUT_BITS _u(0x02000000) +#define USB_EP_ABORT_EP12_OUT_MSB _u(25) +#define USB_EP_ABORT_EP12_OUT_LSB _u(25) #define USB_EP_ABORT_EP12_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP12_IN // Description : None -#define USB_EP_ABORT_EP12_IN_RESET 0x0 -#define USB_EP_ABORT_EP12_IN_BITS 0x01000000 -#define USB_EP_ABORT_EP12_IN_MSB 24 -#define USB_EP_ABORT_EP12_IN_LSB 24 +#define USB_EP_ABORT_EP12_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP12_IN_BITS _u(0x01000000) +#define USB_EP_ABORT_EP12_IN_MSB _u(24) +#define USB_EP_ABORT_EP12_IN_LSB _u(24) #define USB_EP_ABORT_EP12_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP11_OUT // Description : None -#define USB_EP_ABORT_EP11_OUT_RESET 0x0 -#define USB_EP_ABORT_EP11_OUT_BITS 0x00800000 -#define USB_EP_ABORT_EP11_OUT_MSB 23 -#define USB_EP_ABORT_EP11_OUT_LSB 23 +#define USB_EP_ABORT_EP11_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP11_OUT_BITS _u(0x00800000) +#define USB_EP_ABORT_EP11_OUT_MSB _u(23) +#define USB_EP_ABORT_EP11_OUT_LSB _u(23) #define USB_EP_ABORT_EP11_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP11_IN // Description : None -#define USB_EP_ABORT_EP11_IN_RESET 0x0 -#define USB_EP_ABORT_EP11_IN_BITS 0x00400000 -#define USB_EP_ABORT_EP11_IN_MSB 22 -#define USB_EP_ABORT_EP11_IN_LSB 22 +#define USB_EP_ABORT_EP11_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP11_IN_BITS _u(0x00400000) +#define USB_EP_ABORT_EP11_IN_MSB _u(22) +#define USB_EP_ABORT_EP11_IN_LSB _u(22) #define USB_EP_ABORT_EP11_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP10_OUT // Description : None -#define USB_EP_ABORT_EP10_OUT_RESET 0x0 -#define USB_EP_ABORT_EP10_OUT_BITS 0x00200000 -#define USB_EP_ABORT_EP10_OUT_MSB 21 -#define USB_EP_ABORT_EP10_OUT_LSB 21 +#define USB_EP_ABORT_EP10_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP10_OUT_BITS _u(0x00200000) +#define USB_EP_ABORT_EP10_OUT_MSB _u(21) +#define USB_EP_ABORT_EP10_OUT_LSB _u(21) #define USB_EP_ABORT_EP10_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP10_IN // Description : None -#define USB_EP_ABORT_EP10_IN_RESET 0x0 -#define USB_EP_ABORT_EP10_IN_BITS 0x00100000 -#define USB_EP_ABORT_EP10_IN_MSB 20 -#define USB_EP_ABORT_EP10_IN_LSB 20 +#define USB_EP_ABORT_EP10_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP10_IN_BITS _u(0x00100000) +#define USB_EP_ABORT_EP10_IN_MSB _u(20) +#define USB_EP_ABORT_EP10_IN_LSB _u(20) #define USB_EP_ABORT_EP10_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP9_OUT // Description : None -#define USB_EP_ABORT_EP9_OUT_RESET 0x0 -#define USB_EP_ABORT_EP9_OUT_BITS 0x00080000 -#define USB_EP_ABORT_EP9_OUT_MSB 19 -#define USB_EP_ABORT_EP9_OUT_LSB 19 +#define USB_EP_ABORT_EP9_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP9_OUT_BITS _u(0x00080000) +#define USB_EP_ABORT_EP9_OUT_MSB _u(19) +#define USB_EP_ABORT_EP9_OUT_LSB _u(19) #define USB_EP_ABORT_EP9_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP9_IN // Description : None -#define USB_EP_ABORT_EP9_IN_RESET 0x0 -#define USB_EP_ABORT_EP9_IN_BITS 0x00040000 -#define USB_EP_ABORT_EP9_IN_MSB 18 -#define USB_EP_ABORT_EP9_IN_LSB 18 +#define USB_EP_ABORT_EP9_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP9_IN_BITS _u(0x00040000) +#define USB_EP_ABORT_EP9_IN_MSB _u(18) +#define USB_EP_ABORT_EP9_IN_LSB _u(18) #define USB_EP_ABORT_EP9_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP8_OUT // Description : None -#define USB_EP_ABORT_EP8_OUT_RESET 0x0 -#define USB_EP_ABORT_EP8_OUT_BITS 0x00020000 -#define USB_EP_ABORT_EP8_OUT_MSB 17 -#define USB_EP_ABORT_EP8_OUT_LSB 17 +#define USB_EP_ABORT_EP8_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP8_OUT_BITS _u(0x00020000) +#define USB_EP_ABORT_EP8_OUT_MSB _u(17) +#define USB_EP_ABORT_EP8_OUT_LSB _u(17) #define USB_EP_ABORT_EP8_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP8_IN // Description : None -#define USB_EP_ABORT_EP8_IN_RESET 0x0 -#define USB_EP_ABORT_EP8_IN_BITS 0x00010000 -#define USB_EP_ABORT_EP8_IN_MSB 16 -#define USB_EP_ABORT_EP8_IN_LSB 16 +#define USB_EP_ABORT_EP8_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP8_IN_BITS _u(0x00010000) +#define USB_EP_ABORT_EP8_IN_MSB _u(16) +#define USB_EP_ABORT_EP8_IN_LSB _u(16) #define USB_EP_ABORT_EP8_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP7_OUT // Description : None -#define USB_EP_ABORT_EP7_OUT_RESET 0x0 -#define USB_EP_ABORT_EP7_OUT_BITS 0x00008000 -#define USB_EP_ABORT_EP7_OUT_MSB 15 -#define USB_EP_ABORT_EP7_OUT_LSB 15 +#define USB_EP_ABORT_EP7_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP7_OUT_BITS _u(0x00008000) +#define USB_EP_ABORT_EP7_OUT_MSB _u(15) +#define USB_EP_ABORT_EP7_OUT_LSB _u(15) #define USB_EP_ABORT_EP7_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP7_IN // Description : None -#define USB_EP_ABORT_EP7_IN_RESET 0x0 -#define USB_EP_ABORT_EP7_IN_BITS 0x00004000 -#define USB_EP_ABORT_EP7_IN_MSB 14 -#define USB_EP_ABORT_EP7_IN_LSB 14 +#define USB_EP_ABORT_EP7_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP7_IN_BITS _u(0x00004000) +#define USB_EP_ABORT_EP7_IN_MSB _u(14) +#define USB_EP_ABORT_EP7_IN_LSB _u(14) #define USB_EP_ABORT_EP7_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP6_OUT // Description : None -#define USB_EP_ABORT_EP6_OUT_RESET 0x0 -#define USB_EP_ABORT_EP6_OUT_BITS 0x00002000 -#define USB_EP_ABORT_EP6_OUT_MSB 13 -#define USB_EP_ABORT_EP6_OUT_LSB 13 +#define USB_EP_ABORT_EP6_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP6_OUT_BITS _u(0x00002000) +#define USB_EP_ABORT_EP6_OUT_MSB _u(13) +#define USB_EP_ABORT_EP6_OUT_LSB _u(13) #define USB_EP_ABORT_EP6_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP6_IN // Description : None -#define USB_EP_ABORT_EP6_IN_RESET 0x0 -#define USB_EP_ABORT_EP6_IN_BITS 0x00001000 -#define USB_EP_ABORT_EP6_IN_MSB 12 -#define USB_EP_ABORT_EP6_IN_LSB 12 +#define USB_EP_ABORT_EP6_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP6_IN_BITS _u(0x00001000) +#define USB_EP_ABORT_EP6_IN_MSB _u(12) +#define USB_EP_ABORT_EP6_IN_LSB _u(12) #define USB_EP_ABORT_EP6_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP5_OUT // Description : None -#define USB_EP_ABORT_EP5_OUT_RESET 0x0 -#define USB_EP_ABORT_EP5_OUT_BITS 0x00000800 -#define USB_EP_ABORT_EP5_OUT_MSB 11 -#define USB_EP_ABORT_EP5_OUT_LSB 11 +#define USB_EP_ABORT_EP5_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP5_OUT_BITS _u(0x00000800) +#define USB_EP_ABORT_EP5_OUT_MSB _u(11) +#define USB_EP_ABORT_EP5_OUT_LSB _u(11) #define USB_EP_ABORT_EP5_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP5_IN // Description : None -#define USB_EP_ABORT_EP5_IN_RESET 0x0 -#define USB_EP_ABORT_EP5_IN_BITS 0x00000400 -#define USB_EP_ABORT_EP5_IN_MSB 10 -#define USB_EP_ABORT_EP5_IN_LSB 10 +#define USB_EP_ABORT_EP5_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP5_IN_BITS _u(0x00000400) +#define USB_EP_ABORT_EP5_IN_MSB _u(10) +#define USB_EP_ABORT_EP5_IN_LSB _u(10) #define USB_EP_ABORT_EP5_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP4_OUT // Description : None -#define USB_EP_ABORT_EP4_OUT_RESET 0x0 -#define USB_EP_ABORT_EP4_OUT_BITS 0x00000200 -#define USB_EP_ABORT_EP4_OUT_MSB 9 -#define USB_EP_ABORT_EP4_OUT_LSB 9 +#define USB_EP_ABORT_EP4_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP4_OUT_BITS _u(0x00000200) +#define USB_EP_ABORT_EP4_OUT_MSB _u(9) +#define USB_EP_ABORT_EP4_OUT_LSB _u(9) #define USB_EP_ABORT_EP4_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP4_IN // Description : None -#define USB_EP_ABORT_EP4_IN_RESET 0x0 -#define USB_EP_ABORT_EP4_IN_BITS 0x00000100 -#define USB_EP_ABORT_EP4_IN_MSB 8 -#define USB_EP_ABORT_EP4_IN_LSB 8 +#define USB_EP_ABORT_EP4_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP4_IN_BITS _u(0x00000100) +#define USB_EP_ABORT_EP4_IN_MSB _u(8) +#define USB_EP_ABORT_EP4_IN_LSB _u(8) #define USB_EP_ABORT_EP4_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP3_OUT // Description : None -#define USB_EP_ABORT_EP3_OUT_RESET 0x0 -#define USB_EP_ABORT_EP3_OUT_BITS 0x00000080 -#define USB_EP_ABORT_EP3_OUT_MSB 7 -#define USB_EP_ABORT_EP3_OUT_LSB 7 +#define USB_EP_ABORT_EP3_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP3_OUT_BITS _u(0x00000080) +#define USB_EP_ABORT_EP3_OUT_MSB _u(7) +#define USB_EP_ABORT_EP3_OUT_LSB _u(7) #define USB_EP_ABORT_EP3_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP3_IN // Description : None -#define USB_EP_ABORT_EP3_IN_RESET 0x0 -#define USB_EP_ABORT_EP3_IN_BITS 0x00000040 -#define USB_EP_ABORT_EP3_IN_MSB 6 -#define USB_EP_ABORT_EP3_IN_LSB 6 +#define USB_EP_ABORT_EP3_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP3_IN_BITS _u(0x00000040) +#define USB_EP_ABORT_EP3_IN_MSB _u(6) +#define USB_EP_ABORT_EP3_IN_LSB _u(6) #define USB_EP_ABORT_EP3_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP2_OUT // Description : None -#define USB_EP_ABORT_EP2_OUT_RESET 0x0 -#define USB_EP_ABORT_EP2_OUT_BITS 0x00000020 -#define USB_EP_ABORT_EP2_OUT_MSB 5 -#define USB_EP_ABORT_EP2_OUT_LSB 5 +#define USB_EP_ABORT_EP2_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP2_OUT_BITS _u(0x00000020) +#define USB_EP_ABORT_EP2_OUT_MSB _u(5) +#define USB_EP_ABORT_EP2_OUT_LSB _u(5) #define USB_EP_ABORT_EP2_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP2_IN // Description : None -#define USB_EP_ABORT_EP2_IN_RESET 0x0 -#define USB_EP_ABORT_EP2_IN_BITS 0x00000010 -#define USB_EP_ABORT_EP2_IN_MSB 4 -#define USB_EP_ABORT_EP2_IN_LSB 4 +#define USB_EP_ABORT_EP2_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP2_IN_BITS _u(0x00000010) +#define USB_EP_ABORT_EP2_IN_MSB _u(4) +#define USB_EP_ABORT_EP2_IN_LSB _u(4) #define USB_EP_ABORT_EP2_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP1_OUT // Description : None -#define USB_EP_ABORT_EP1_OUT_RESET 0x0 -#define USB_EP_ABORT_EP1_OUT_BITS 0x00000008 -#define USB_EP_ABORT_EP1_OUT_MSB 3 -#define USB_EP_ABORT_EP1_OUT_LSB 3 +#define USB_EP_ABORT_EP1_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP1_OUT_BITS _u(0x00000008) +#define USB_EP_ABORT_EP1_OUT_MSB _u(3) +#define USB_EP_ABORT_EP1_OUT_LSB _u(3) #define USB_EP_ABORT_EP1_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP1_IN // Description : None -#define USB_EP_ABORT_EP1_IN_RESET 0x0 -#define USB_EP_ABORT_EP1_IN_BITS 0x00000004 -#define USB_EP_ABORT_EP1_IN_MSB 2 -#define USB_EP_ABORT_EP1_IN_LSB 2 +#define USB_EP_ABORT_EP1_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP1_IN_BITS _u(0x00000004) +#define USB_EP_ABORT_EP1_IN_MSB _u(2) +#define USB_EP_ABORT_EP1_IN_LSB _u(2) #define USB_EP_ABORT_EP1_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP0_OUT // Description : None -#define USB_EP_ABORT_EP0_OUT_RESET 0x0 -#define USB_EP_ABORT_EP0_OUT_BITS 0x00000002 -#define USB_EP_ABORT_EP0_OUT_MSB 1 -#define USB_EP_ABORT_EP0_OUT_LSB 1 +#define USB_EP_ABORT_EP0_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP0_OUT_BITS _u(0x00000002) +#define USB_EP_ABORT_EP0_OUT_MSB _u(1) +#define USB_EP_ABORT_EP0_OUT_LSB _u(1) #define USB_EP_ABORT_EP0_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP0_IN // Description : None -#define USB_EP_ABORT_EP0_IN_RESET 0x0 -#define USB_EP_ABORT_EP0_IN_BITS 0x00000001 -#define USB_EP_ABORT_EP0_IN_MSB 0 -#define USB_EP_ABORT_EP0_IN_LSB 0 +#define USB_EP_ABORT_EP0_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP0_IN_BITS _u(0x00000001) +#define USB_EP_ABORT_EP0_IN_MSB _u(0) +#define USB_EP_ABORT_EP0_IN_LSB _u(0) #define USB_EP_ABORT_EP0_IN_ACCESS "RW" // ============================================================================= // Register : USB_EP_ABORT_DONE // Description : Device only: Used in conjunction with `EP_ABORT`. Set once an // endpoint is idle so the programmer knows it is safe to modify // the buffer control register. -#define USB_EP_ABORT_DONE_OFFSET 0x00000064 -#define USB_EP_ABORT_DONE_BITS 0xffffffff -#define USB_EP_ABORT_DONE_RESET 0x00000000 +#define USB_EP_ABORT_DONE_OFFSET _u(0x00000064) +#define USB_EP_ABORT_DONE_BITS _u(0xffffffff) +#define USB_EP_ABORT_DONE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP15_OUT // Description : None -#define USB_EP_ABORT_DONE_EP15_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP15_OUT_BITS 0x80000000 -#define USB_EP_ABORT_DONE_EP15_OUT_MSB 31 -#define USB_EP_ABORT_DONE_EP15_OUT_LSB 31 +#define USB_EP_ABORT_DONE_EP15_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP15_OUT_BITS _u(0x80000000) +#define USB_EP_ABORT_DONE_EP15_OUT_MSB _u(31) +#define USB_EP_ABORT_DONE_EP15_OUT_LSB _u(31) #define USB_EP_ABORT_DONE_EP15_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP15_IN // Description : None -#define USB_EP_ABORT_DONE_EP15_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP15_IN_BITS 0x40000000 -#define USB_EP_ABORT_DONE_EP15_IN_MSB 30 -#define USB_EP_ABORT_DONE_EP15_IN_LSB 30 +#define USB_EP_ABORT_DONE_EP15_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP15_IN_BITS _u(0x40000000) +#define USB_EP_ABORT_DONE_EP15_IN_MSB _u(30) +#define USB_EP_ABORT_DONE_EP15_IN_LSB _u(30) #define USB_EP_ABORT_DONE_EP15_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP14_OUT // Description : None -#define USB_EP_ABORT_DONE_EP14_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP14_OUT_BITS 0x20000000 -#define USB_EP_ABORT_DONE_EP14_OUT_MSB 29 -#define USB_EP_ABORT_DONE_EP14_OUT_LSB 29 +#define USB_EP_ABORT_DONE_EP14_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP14_OUT_BITS _u(0x20000000) +#define USB_EP_ABORT_DONE_EP14_OUT_MSB _u(29) +#define USB_EP_ABORT_DONE_EP14_OUT_LSB _u(29) #define USB_EP_ABORT_DONE_EP14_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP14_IN // Description : None -#define USB_EP_ABORT_DONE_EP14_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP14_IN_BITS 0x10000000 -#define USB_EP_ABORT_DONE_EP14_IN_MSB 28 -#define USB_EP_ABORT_DONE_EP14_IN_LSB 28 +#define USB_EP_ABORT_DONE_EP14_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP14_IN_BITS _u(0x10000000) +#define USB_EP_ABORT_DONE_EP14_IN_MSB _u(28) +#define USB_EP_ABORT_DONE_EP14_IN_LSB _u(28) #define USB_EP_ABORT_DONE_EP14_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP13_OUT // Description : None -#define USB_EP_ABORT_DONE_EP13_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP13_OUT_BITS 0x08000000 -#define USB_EP_ABORT_DONE_EP13_OUT_MSB 27 -#define USB_EP_ABORT_DONE_EP13_OUT_LSB 27 +#define USB_EP_ABORT_DONE_EP13_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP13_OUT_BITS _u(0x08000000) +#define USB_EP_ABORT_DONE_EP13_OUT_MSB _u(27) +#define USB_EP_ABORT_DONE_EP13_OUT_LSB _u(27) #define USB_EP_ABORT_DONE_EP13_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP13_IN // Description : None -#define USB_EP_ABORT_DONE_EP13_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP13_IN_BITS 0x04000000 -#define USB_EP_ABORT_DONE_EP13_IN_MSB 26 -#define USB_EP_ABORT_DONE_EP13_IN_LSB 26 +#define USB_EP_ABORT_DONE_EP13_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP13_IN_BITS _u(0x04000000) +#define USB_EP_ABORT_DONE_EP13_IN_MSB _u(26) +#define USB_EP_ABORT_DONE_EP13_IN_LSB _u(26) #define USB_EP_ABORT_DONE_EP13_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP12_OUT // Description : None -#define USB_EP_ABORT_DONE_EP12_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP12_OUT_BITS 0x02000000 -#define USB_EP_ABORT_DONE_EP12_OUT_MSB 25 -#define USB_EP_ABORT_DONE_EP12_OUT_LSB 25 +#define USB_EP_ABORT_DONE_EP12_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP12_OUT_BITS _u(0x02000000) +#define USB_EP_ABORT_DONE_EP12_OUT_MSB _u(25) +#define USB_EP_ABORT_DONE_EP12_OUT_LSB _u(25) #define USB_EP_ABORT_DONE_EP12_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP12_IN // Description : None -#define USB_EP_ABORT_DONE_EP12_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP12_IN_BITS 0x01000000 -#define USB_EP_ABORT_DONE_EP12_IN_MSB 24 -#define USB_EP_ABORT_DONE_EP12_IN_LSB 24 +#define USB_EP_ABORT_DONE_EP12_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP12_IN_BITS _u(0x01000000) +#define USB_EP_ABORT_DONE_EP12_IN_MSB _u(24) +#define USB_EP_ABORT_DONE_EP12_IN_LSB _u(24) #define USB_EP_ABORT_DONE_EP12_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP11_OUT // Description : None -#define USB_EP_ABORT_DONE_EP11_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP11_OUT_BITS 0x00800000 -#define USB_EP_ABORT_DONE_EP11_OUT_MSB 23 -#define USB_EP_ABORT_DONE_EP11_OUT_LSB 23 +#define USB_EP_ABORT_DONE_EP11_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP11_OUT_BITS _u(0x00800000) +#define USB_EP_ABORT_DONE_EP11_OUT_MSB _u(23) +#define USB_EP_ABORT_DONE_EP11_OUT_LSB _u(23) #define USB_EP_ABORT_DONE_EP11_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP11_IN // Description : None -#define USB_EP_ABORT_DONE_EP11_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP11_IN_BITS 0x00400000 -#define USB_EP_ABORT_DONE_EP11_IN_MSB 22 -#define USB_EP_ABORT_DONE_EP11_IN_LSB 22 +#define USB_EP_ABORT_DONE_EP11_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP11_IN_BITS _u(0x00400000) +#define USB_EP_ABORT_DONE_EP11_IN_MSB _u(22) +#define USB_EP_ABORT_DONE_EP11_IN_LSB _u(22) #define USB_EP_ABORT_DONE_EP11_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP10_OUT // Description : None -#define USB_EP_ABORT_DONE_EP10_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP10_OUT_BITS 0x00200000 -#define USB_EP_ABORT_DONE_EP10_OUT_MSB 21 -#define USB_EP_ABORT_DONE_EP10_OUT_LSB 21 +#define USB_EP_ABORT_DONE_EP10_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP10_OUT_BITS _u(0x00200000) +#define USB_EP_ABORT_DONE_EP10_OUT_MSB _u(21) +#define USB_EP_ABORT_DONE_EP10_OUT_LSB _u(21) #define USB_EP_ABORT_DONE_EP10_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP10_IN // Description : None -#define USB_EP_ABORT_DONE_EP10_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP10_IN_BITS 0x00100000 -#define USB_EP_ABORT_DONE_EP10_IN_MSB 20 -#define USB_EP_ABORT_DONE_EP10_IN_LSB 20 +#define USB_EP_ABORT_DONE_EP10_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP10_IN_BITS _u(0x00100000) +#define USB_EP_ABORT_DONE_EP10_IN_MSB _u(20) +#define USB_EP_ABORT_DONE_EP10_IN_LSB _u(20) #define USB_EP_ABORT_DONE_EP10_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP9_OUT // Description : None -#define USB_EP_ABORT_DONE_EP9_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP9_OUT_BITS 0x00080000 -#define USB_EP_ABORT_DONE_EP9_OUT_MSB 19 -#define USB_EP_ABORT_DONE_EP9_OUT_LSB 19 +#define USB_EP_ABORT_DONE_EP9_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP9_OUT_BITS _u(0x00080000) +#define USB_EP_ABORT_DONE_EP9_OUT_MSB _u(19) +#define USB_EP_ABORT_DONE_EP9_OUT_LSB _u(19) #define USB_EP_ABORT_DONE_EP9_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP9_IN // Description : None -#define USB_EP_ABORT_DONE_EP9_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP9_IN_BITS 0x00040000 -#define USB_EP_ABORT_DONE_EP9_IN_MSB 18 -#define USB_EP_ABORT_DONE_EP9_IN_LSB 18 +#define USB_EP_ABORT_DONE_EP9_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP9_IN_BITS _u(0x00040000) +#define USB_EP_ABORT_DONE_EP9_IN_MSB _u(18) +#define USB_EP_ABORT_DONE_EP9_IN_LSB _u(18) #define USB_EP_ABORT_DONE_EP9_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP8_OUT // Description : None -#define USB_EP_ABORT_DONE_EP8_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP8_OUT_BITS 0x00020000 -#define USB_EP_ABORT_DONE_EP8_OUT_MSB 17 -#define USB_EP_ABORT_DONE_EP8_OUT_LSB 17 +#define USB_EP_ABORT_DONE_EP8_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP8_OUT_BITS _u(0x00020000) +#define USB_EP_ABORT_DONE_EP8_OUT_MSB _u(17) +#define USB_EP_ABORT_DONE_EP8_OUT_LSB _u(17) #define USB_EP_ABORT_DONE_EP8_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP8_IN // Description : None -#define USB_EP_ABORT_DONE_EP8_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP8_IN_BITS 0x00010000 -#define USB_EP_ABORT_DONE_EP8_IN_MSB 16 -#define USB_EP_ABORT_DONE_EP8_IN_LSB 16 +#define USB_EP_ABORT_DONE_EP8_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP8_IN_BITS _u(0x00010000) +#define USB_EP_ABORT_DONE_EP8_IN_MSB _u(16) +#define USB_EP_ABORT_DONE_EP8_IN_LSB _u(16) #define USB_EP_ABORT_DONE_EP8_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP7_OUT // Description : None -#define USB_EP_ABORT_DONE_EP7_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP7_OUT_BITS 0x00008000 -#define USB_EP_ABORT_DONE_EP7_OUT_MSB 15 -#define USB_EP_ABORT_DONE_EP7_OUT_LSB 15 +#define USB_EP_ABORT_DONE_EP7_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP7_OUT_BITS _u(0x00008000) +#define USB_EP_ABORT_DONE_EP7_OUT_MSB _u(15) +#define USB_EP_ABORT_DONE_EP7_OUT_LSB _u(15) #define USB_EP_ABORT_DONE_EP7_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP7_IN // Description : None -#define USB_EP_ABORT_DONE_EP7_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP7_IN_BITS 0x00004000 -#define USB_EP_ABORT_DONE_EP7_IN_MSB 14 -#define USB_EP_ABORT_DONE_EP7_IN_LSB 14 +#define USB_EP_ABORT_DONE_EP7_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP7_IN_BITS _u(0x00004000) +#define USB_EP_ABORT_DONE_EP7_IN_MSB _u(14) +#define USB_EP_ABORT_DONE_EP7_IN_LSB _u(14) #define USB_EP_ABORT_DONE_EP7_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP6_OUT // Description : None -#define USB_EP_ABORT_DONE_EP6_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP6_OUT_BITS 0x00002000 -#define USB_EP_ABORT_DONE_EP6_OUT_MSB 13 -#define USB_EP_ABORT_DONE_EP6_OUT_LSB 13 +#define USB_EP_ABORT_DONE_EP6_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP6_OUT_BITS _u(0x00002000) +#define USB_EP_ABORT_DONE_EP6_OUT_MSB _u(13) +#define USB_EP_ABORT_DONE_EP6_OUT_LSB _u(13) #define USB_EP_ABORT_DONE_EP6_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP6_IN // Description : None -#define USB_EP_ABORT_DONE_EP6_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP6_IN_BITS 0x00001000 -#define USB_EP_ABORT_DONE_EP6_IN_MSB 12 -#define USB_EP_ABORT_DONE_EP6_IN_LSB 12 +#define USB_EP_ABORT_DONE_EP6_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP6_IN_BITS _u(0x00001000) +#define USB_EP_ABORT_DONE_EP6_IN_MSB _u(12) +#define USB_EP_ABORT_DONE_EP6_IN_LSB _u(12) #define USB_EP_ABORT_DONE_EP6_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP5_OUT // Description : None -#define USB_EP_ABORT_DONE_EP5_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP5_OUT_BITS 0x00000800 -#define USB_EP_ABORT_DONE_EP5_OUT_MSB 11 -#define USB_EP_ABORT_DONE_EP5_OUT_LSB 11 +#define USB_EP_ABORT_DONE_EP5_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP5_OUT_BITS _u(0x00000800) +#define USB_EP_ABORT_DONE_EP5_OUT_MSB _u(11) +#define USB_EP_ABORT_DONE_EP5_OUT_LSB _u(11) #define USB_EP_ABORT_DONE_EP5_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP5_IN // Description : None -#define USB_EP_ABORT_DONE_EP5_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP5_IN_BITS 0x00000400 -#define USB_EP_ABORT_DONE_EP5_IN_MSB 10 -#define USB_EP_ABORT_DONE_EP5_IN_LSB 10 +#define USB_EP_ABORT_DONE_EP5_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP5_IN_BITS _u(0x00000400) +#define USB_EP_ABORT_DONE_EP5_IN_MSB _u(10) +#define USB_EP_ABORT_DONE_EP5_IN_LSB _u(10) #define USB_EP_ABORT_DONE_EP5_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP4_OUT // Description : None -#define USB_EP_ABORT_DONE_EP4_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP4_OUT_BITS 0x00000200 -#define USB_EP_ABORT_DONE_EP4_OUT_MSB 9 -#define USB_EP_ABORT_DONE_EP4_OUT_LSB 9 +#define USB_EP_ABORT_DONE_EP4_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP4_OUT_BITS _u(0x00000200) +#define USB_EP_ABORT_DONE_EP4_OUT_MSB _u(9) +#define USB_EP_ABORT_DONE_EP4_OUT_LSB _u(9) #define USB_EP_ABORT_DONE_EP4_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP4_IN // Description : None -#define USB_EP_ABORT_DONE_EP4_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP4_IN_BITS 0x00000100 -#define USB_EP_ABORT_DONE_EP4_IN_MSB 8 -#define USB_EP_ABORT_DONE_EP4_IN_LSB 8 +#define USB_EP_ABORT_DONE_EP4_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP4_IN_BITS _u(0x00000100) +#define USB_EP_ABORT_DONE_EP4_IN_MSB _u(8) +#define USB_EP_ABORT_DONE_EP4_IN_LSB _u(8) #define USB_EP_ABORT_DONE_EP4_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP3_OUT // Description : None -#define USB_EP_ABORT_DONE_EP3_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP3_OUT_BITS 0x00000080 -#define USB_EP_ABORT_DONE_EP3_OUT_MSB 7 -#define USB_EP_ABORT_DONE_EP3_OUT_LSB 7 +#define USB_EP_ABORT_DONE_EP3_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP3_OUT_BITS _u(0x00000080) +#define USB_EP_ABORT_DONE_EP3_OUT_MSB _u(7) +#define USB_EP_ABORT_DONE_EP3_OUT_LSB _u(7) #define USB_EP_ABORT_DONE_EP3_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP3_IN // Description : None -#define USB_EP_ABORT_DONE_EP3_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP3_IN_BITS 0x00000040 -#define USB_EP_ABORT_DONE_EP3_IN_MSB 6 -#define USB_EP_ABORT_DONE_EP3_IN_LSB 6 +#define USB_EP_ABORT_DONE_EP3_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP3_IN_BITS _u(0x00000040) +#define USB_EP_ABORT_DONE_EP3_IN_MSB _u(6) +#define USB_EP_ABORT_DONE_EP3_IN_LSB _u(6) #define USB_EP_ABORT_DONE_EP3_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP2_OUT // Description : None -#define USB_EP_ABORT_DONE_EP2_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP2_OUT_BITS 0x00000020 -#define USB_EP_ABORT_DONE_EP2_OUT_MSB 5 -#define USB_EP_ABORT_DONE_EP2_OUT_LSB 5 +#define USB_EP_ABORT_DONE_EP2_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP2_OUT_BITS _u(0x00000020) +#define USB_EP_ABORT_DONE_EP2_OUT_MSB _u(5) +#define USB_EP_ABORT_DONE_EP2_OUT_LSB _u(5) #define USB_EP_ABORT_DONE_EP2_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP2_IN // Description : None -#define USB_EP_ABORT_DONE_EP2_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP2_IN_BITS 0x00000010 -#define USB_EP_ABORT_DONE_EP2_IN_MSB 4 -#define USB_EP_ABORT_DONE_EP2_IN_LSB 4 +#define USB_EP_ABORT_DONE_EP2_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP2_IN_BITS _u(0x00000010) +#define USB_EP_ABORT_DONE_EP2_IN_MSB _u(4) +#define USB_EP_ABORT_DONE_EP2_IN_LSB _u(4) #define USB_EP_ABORT_DONE_EP2_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP1_OUT // Description : None -#define USB_EP_ABORT_DONE_EP1_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP1_OUT_BITS 0x00000008 -#define USB_EP_ABORT_DONE_EP1_OUT_MSB 3 -#define USB_EP_ABORT_DONE_EP1_OUT_LSB 3 +#define USB_EP_ABORT_DONE_EP1_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP1_OUT_BITS _u(0x00000008) +#define USB_EP_ABORT_DONE_EP1_OUT_MSB _u(3) +#define USB_EP_ABORT_DONE_EP1_OUT_LSB _u(3) #define USB_EP_ABORT_DONE_EP1_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP1_IN // Description : None -#define USB_EP_ABORT_DONE_EP1_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP1_IN_BITS 0x00000004 -#define USB_EP_ABORT_DONE_EP1_IN_MSB 2 -#define USB_EP_ABORT_DONE_EP1_IN_LSB 2 +#define USB_EP_ABORT_DONE_EP1_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP1_IN_BITS _u(0x00000004) +#define USB_EP_ABORT_DONE_EP1_IN_MSB _u(2) +#define USB_EP_ABORT_DONE_EP1_IN_LSB _u(2) #define USB_EP_ABORT_DONE_EP1_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP0_OUT // Description : None -#define USB_EP_ABORT_DONE_EP0_OUT_RESET 0x0 -#define USB_EP_ABORT_DONE_EP0_OUT_BITS 0x00000002 -#define USB_EP_ABORT_DONE_EP0_OUT_MSB 1 -#define USB_EP_ABORT_DONE_EP0_OUT_LSB 1 +#define USB_EP_ABORT_DONE_EP0_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP0_OUT_BITS _u(0x00000002) +#define USB_EP_ABORT_DONE_EP0_OUT_MSB _u(1) +#define USB_EP_ABORT_DONE_EP0_OUT_LSB _u(1) #define USB_EP_ABORT_DONE_EP0_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP0_IN // Description : None -#define USB_EP_ABORT_DONE_EP0_IN_RESET 0x0 -#define USB_EP_ABORT_DONE_EP0_IN_BITS 0x00000001 -#define USB_EP_ABORT_DONE_EP0_IN_MSB 0 -#define USB_EP_ABORT_DONE_EP0_IN_LSB 0 +#define USB_EP_ABORT_DONE_EP0_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP0_IN_BITS _u(0x00000001) +#define USB_EP_ABORT_DONE_EP0_IN_MSB _u(0) +#define USB_EP_ABORT_DONE_EP0_IN_LSB _u(0) #define USB_EP_ABORT_DONE_EP0_IN_ACCESS "WC" // ============================================================================= // Register : USB_EP_STALL_ARM @@ -2146,350 +2146,350 @@ // device controller clears these bits when a SETUP packet is // received because the USB spec requires that a STALL condition // is cleared when a SETUP packet is received. -#define USB_EP_STALL_ARM_OFFSET 0x00000068 -#define USB_EP_STALL_ARM_BITS 0x00000003 -#define USB_EP_STALL_ARM_RESET 0x00000000 +#define USB_EP_STALL_ARM_OFFSET _u(0x00000068) +#define USB_EP_STALL_ARM_BITS _u(0x00000003) +#define USB_EP_STALL_ARM_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_EP_STALL_ARM_EP0_OUT // Description : None -#define USB_EP_STALL_ARM_EP0_OUT_RESET 0x0 -#define USB_EP_STALL_ARM_EP0_OUT_BITS 0x00000002 -#define USB_EP_STALL_ARM_EP0_OUT_MSB 1 -#define USB_EP_STALL_ARM_EP0_OUT_LSB 1 +#define USB_EP_STALL_ARM_EP0_OUT_RESET _u(0x0) +#define USB_EP_STALL_ARM_EP0_OUT_BITS _u(0x00000002) +#define USB_EP_STALL_ARM_EP0_OUT_MSB _u(1) +#define USB_EP_STALL_ARM_EP0_OUT_LSB _u(1) #define USB_EP_STALL_ARM_EP0_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_STALL_ARM_EP0_IN // Description : None -#define USB_EP_STALL_ARM_EP0_IN_RESET 0x0 -#define USB_EP_STALL_ARM_EP0_IN_BITS 0x00000001 -#define USB_EP_STALL_ARM_EP0_IN_MSB 0 -#define USB_EP_STALL_ARM_EP0_IN_LSB 0 +#define USB_EP_STALL_ARM_EP0_IN_RESET _u(0x0) +#define USB_EP_STALL_ARM_EP0_IN_BITS _u(0x00000001) +#define USB_EP_STALL_ARM_EP0_IN_MSB _u(0) +#define USB_EP_STALL_ARM_EP0_IN_LSB _u(0) #define USB_EP_STALL_ARM_EP0_IN_ACCESS "RW" // ============================================================================= // Register : USB_NAK_POLL // Description : Used by the host controller. Sets the wait time in microseconds // before trying again if the device replies with a NAK. -#define USB_NAK_POLL_OFFSET 0x0000006c -#define USB_NAK_POLL_BITS 0x03ff03ff -#define USB_NAK_POLL_RESET 0x00100010 +#define USB_NAK_POLL_OFFSET _u(0x0000006c) +#define USB_NAK_POLL_BITS _u(0x03ff03ff) +#define USB_NAK_POLL_RESET _u(0x00100010) // ----------------------------------------------------------------------------- // Field : USB_NAK_POLL_DELAY_FS // Description : NAK polling interval for a full speed device -#define USB_NAK_POLL_DELAY_FS_RESET 0x010 -#define USB_NAK_POLL_DELAY_FS_BITS 0x03ff0000 -#define USB_NAK_POLL_DELAY_FS_MSB 25 -#define USB_NAK_POLL_DELAY_FS_LSB 16 +#define USB_NAK_POLL_DELAY_FS_RESET _u(0x010) +#define USB_NAK_POLL_DELAY_FS_BITS _u(0x03ff0000) +#define USB_NAK_POLL_DELAY_FS_MSB _u(25) +#define USB_NAK_POLL_DELAY_FS_LSB _u(16) #define USB_NAK_POLL_DELAY_FS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_NAK_POLL_DELAY_LS // Description : NAK polling interval for a low speed device -#define USB_NAK_POLL_DELAY_LS_RESET 0x010 -#define USB_NAK_POLL_DELAY_LS_BITS 0x000003ff -#define USB_NAK_POLL_DELAY_LS_MSB 9 -#define USB_NAK_POLL_DELAY_LS_LSB 0 +#define USB_NAK_POLL_DELAY_LS_RESET _u(0x010) +#define USB_NAK_POLL_DELAY_LS_BITS _u(0x000003ff) +#define USB_NAK_POLL_DELAY_LS_MSB _u(9) +#define USB_NAK_POLL_DELAY_LS_LSB _u(0) #define USB_NAK_POLL_DELAY_LS_ACCESS "RW" // ============================================================================= // Register : USB_EP_STATUS_STALL_NAK // Description : Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` // bits are set. For EP0 this comes from `SIE_CTRL`. For all other // endpoints it comes from the endpoint control register. -#define USB_EP_STATUS_STALL_NAK_OFFSET 0x00000070 -#define USB_EP_STATUS_STALL_NAK_BITS 0xffffffff -#define USB_EP_STATUS_STALL_NAK_RESET 0x00000000 +#define USB_EP_STATUS_STALL_NAK_OFFSET _u(0x00000070) +#define USB_EP_STATUS_STALL_NAK_BITS _u(0xffffffff) +#define USB_EP_STATUS_STALL_NAK_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP15_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP15_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP15_OUT_BITS 0x80000000 -#define USB_EP_STATUS_STALL_NAK_EP15_OUT_MSB 31 -#define USB_EP_STATUS_STALL_NAK_EP15_OUT_LSB 31 +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_BITS _u(0x80000000) +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_MSB _u(31) +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_LSB _u(31) #define USB_EP_STATUS_STALL_NAK_EP15_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP15_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP15_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP15_IN_BITS 0x40000000 -#define USB_EP_STATUS_STALL_NAK_EP15_IN_MSB 30 -#define USB_EP_STATUS_STALL_NAK_EP15_IN_LSB 30 +#define USB_EP_STATUS_STALL_NAK_EP15_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP15_IN_BITS _u(0x40000000) +#define USB_EP_STATUS_STALL_NAK_EP15_IN_MSB _u(30) +#define USB_EP_STATUS_STALL_NAK_EP15_IN_LSB _u(30) #define USB_EP_STATUS_STALL_NAK_EP15_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP14_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP14_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP14_OUT_BITS 0x20000000 -#define USB_EP_STATUS_STALL_NAK_EP14_OUT_MSB 29 -#define USB_EP_STATUS_STALL_NAK_EP14_OUT_LSB 29 +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_BITS _u(0x20000000) +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_MSB _u(29) +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_LSB _u(29) #define USB_EP_STATUS_STALL_NAK_EP14_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP14_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP14_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP14_IN_BITS 0x10000000 -#define USB_EP_STATUS_STALL_NAK_EP14_IN_MSB 28 -#define USB_EP_STATUS_STALL_NAK_EP14_IN_LSB 28 +#define USB_EP_STATUS_STALL_NAK_EP14_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP14_IN_BITS _u(0x10000000) +#define USB_EP_STATUS_STALL_NAK_EP14_IN_MSB _u(28) +#define USB_EP_STATUS_STALL_NAK_EP14_IN_LSB _u(28) #define USB_EP_STATUS_STALL_NAK_EP14_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP13_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP13_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP13_OUT_BITS 0x08000000 -#define USB_EP_STATUS_STALL_NAK_EP13_OUT_MSB 27 -#define USB_EP_STATUS_STALL_NAK_EP13_OUT_LSB 27 +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_BITS _u(0x08000000) +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_MSB _u(27) +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_LSB _u(27) #define USB_EP_STATUS_STALL_NAK_EP13_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP13_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP13_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP13_IN_BITS 0x04000000 -#define USB_EP_STATUS_STALL_NAK_EP13_IN_MSB 26 -#define USB_EP_STATUS_STALL_NAK_EP13_IN_LSB 26 +#define USB_EP_STATUS_STALL_NAK_EP13_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP13_IN_BITS _u(0x04000000) +#define USB_EP_STATUS_STALL_NAK_EP13_IN_MSB _u(26) +#define USB_EP_STATUS_STALL_NAK_EP13_IN_LSB _u(26) #define USB_EP_STATUS_STALL_NAK_EP13_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP12_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP12_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP12_OUT_BITS 0x02000000 -#define USB_EP_STATUS_STALL_NAK_EP12_OUT_MSB 25 -#define USB_EP_STATUS_STALL_NAK_EP12_OUT_LSB 25 +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_BITS _u(0x02000000) +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_MSB _u(25) +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_LSB _u(25) #define USB_EP_STATUS_STALL_NAK_EP12_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP12_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP12_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP12_IN_BITS 0x01000000 -#define USB_EP_STATUS_STALL_NAK_EP12_IN_MSB 24 -#define USB_EP_STATUS_STALL_NAK_EP12_IN_LSB 24 +#define USB_EP_STATUS_STALL_NAK_EP12_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP12_IN_BITS _u(0x01000000) +#define USB_EP_STATUS_STALL_NAK_EP12_IN_MSB _u(24) +#define USB_EP_STATUS_STALL_NAK_EP12_IN_LSB _u(24) #define USB_EP_STATUS_STALL_NAK_EP12_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP11_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP11_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP11_OUT_BITS 0x00800000 -#define USB_EP_STATUS_STALL_NAK_EP11_OUT_MSB 23 -#define USB_EP_STATUS_STALL_NAK_EP11_OUT_LSB 23 +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_BITS _u(0x00800000) +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_MSB _u(23) +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_LSB _u(23) #define USB_EP_STATUS_STALL_NAK_EP11_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP11_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP11_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP11_IN_BITS 0x00400000 -#define USB_EP_STATUS_STALL_NAK_EP11_IN_MSB 22 -#define USB_EP_STATUS_STALL_NAK_EP11_IN_LSB 22 +#define USB_EP_STATUS_STALL_NAK_EP11_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP11_IN_BITS _u(0x00400000) +#define USB_EP_STATUS_STALL_NAK_EP11_IN_MSB _u(22) +#define USB_EP_STATUS_STALL_NAK_EP11_IN_LSB _u(22) #define USB_EP_STATUS_STALL_NAK_EP11_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP10_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP10_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP10_OUT_BITS 0x00200000 -#define USB_EP_STATUS_STALL_NAK_EP10_OUT_MSB 21 -#define USB_EP_STATUS_STALL_NAK_EP10_OUT_LSB 21 +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_BITS _u(0x00200000) +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_MSB _u(21) +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_LSB _u(21) #define USB_EP_STATUS_STALL_NAK_EP10_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP10_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP10_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP10_IN_BITS 0x00100000 -#define USB_EP_STATUS_STALL_NAK_EP10_IN_MSB 20 -#define USB_EP_STATUS_STALL_NAK_EP10_IN_LSB 20 +#define USB_EP_STATUS_STALL_NAK_EP10_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP10_IN_BITS _u(0x00100000) +#define USB_EP_STATUS_STALL_NAK_EP10_IN_MSB _u(20) +#define USB_EP_STATUS_STALL_NAK_EP10_IN_LSB _u(20) #define USB_EP_STATUS_STALL_NAK_EP10_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP9_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP9_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP9_OUT_BITS 0x00080000 -#define USB_EP_STATUS_STALL_NAK_EP9_OUT_MSB 19 -#define USB_EP_STATUS_STALL_NAK_EP9_OUT_LSB 19 +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_BITS _u(0x00080000) +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_MSB _u(19) +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_LSB _u(19) #define USB_EP_STATUS_STALL_NAK_EP9_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP9_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP9_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP9_IN_BITS 0x00040000 -#define USB_EP_STATUS_STALL_NAK_EP9_IN_MSB 18 -#define USB_EP_STATUS_STALL_NAK_EP9_IN_LSB 18 +#define USB_EP_STATUS_STALL_NAK_EP9_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP9_IN_BITS _u(0x00040000) +#define USB_EP_STATUS_STALL_NAK_EP9_IN_MSB _u(18) +#define USB_EP_STATUS_STALL_NAK_EP9_IN_LSB _u(18) #define USB_EP_STATUS_STALL_NAK_EP9_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP8_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP8_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP8_OUT_BITS 0x00020000 -#define USB_EP_STATUS_STALL_NAK_EP8_OUT_MSB 17 -#define USB_EP_STATUS_STALL_NAK_EP8_OUT_LSB 17 +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_BITS _u(0x00020000) +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_MSB _u(17) +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_LSB _u(17) #define USB_EP_STATUS_STALL_NAK_EP8_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP8_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP8_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP8_IN_BITS 0x00010000 -#define USB_EP_STATUS_STALL_NAK_EP8_IN_MSB 16 -#define USB_EP_STATUS_STALL_NAK_EP8_IN_LSB 16 +#define USB_EP_STATUS_STALL_NAK_EP8_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP8_IN_BITS _u(0x00010000) +#define USB_EP_STATUS_STALL_NAK_EP8_IN_MSB _u(16) +#define USB_EP_STATUS_STALL_NAK_EP8_IN_LSB _u(16) #define USB_EP_STATUS_STALL_NAK_EP8_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP7_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP7_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP7_OUT_BITS 0x00008000 -#define USB_EP_STATUS_STALL_NAK_EP7_OUT_MSB 15 -#define USB_EP_STATUS_STALL_NAK_EP7_OUT_LSB 15 +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_BITS _u(0x00008000) +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_MSB _u(15) +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_LSB _u(15) #define USB_EP_STATUS_STALL_NAK_EP7_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP7_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP7_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP7_IN_BITS 0x00004000 -#define USB_EP_STATUS_STALL_NAK_EP7_IN_MSB 14 -#define USB_EP_STATUS_STALL_NAK_EP7_IN_LSB 14 +#define USB_EP_STATUS_STALL_NAK_EP7_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP7_IN_BITS _u(0x00004000) +#define USB_EP_STATUS_STALL_NAK_EP7_IN_MSB _u(14) +#define USB_EP_STATUS_STALL_NAK_EP7_IN_LSB _u(14) #define USB_EP_STATUS_STALL_NAK_EP7_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP6_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP6_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP6_OUT_BITS 0x00002000 -#define USB_EP_STATUS_STALL_NAK_EP6_OUT_MSB 13 -#define USB_EP_STATUS_STALL_NAK_EP6_OUT_LSB 13 +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_BITS _u(0x00002000) +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_MSB _u(13) +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_LSB _u(13) #define USB_EP_STATUS_STALL_NAK_EP6_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP6_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP6_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP6_IN_BITS 0x00001000 -#define USB_EP_STATUS_STALL_NAK_EP6_IN_MSB 12 -#define USB_EP_STATUS_STALL_NAK_EP6_IN_LSB 12 +#define USB_EP_STATUS_STALL_NAK_EP6_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP6_IN_BITS _u(0x00001000) +#define USB_EP_STATUS_STALL_NAK_EP6_IN_MSB _u(12) +#define USB_EP_STATUS_STALL_NAK_EP6_IN_LSB _u(12) #define USB_EP_STATUS_STALL_NAK_EP6_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP5_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP5_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP5_OUT_BITS 0x00000800 -#define USB_EP_STATUS_STALL_NAK_EP5_OUT_MSB 11 -#define USB_EP_STATUS_STALL_NAK_EP5_OUT_LSB 11 +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_BITS _u(0x00000800) +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_MSB _u(11) +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_LSB _u(11) #define USB_EP_STATUS_STALL_NAK_EP5_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP5_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP5_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP5_IN_BITS 0x00000400 -#define USB_EP_STATUS_STALL_NAK_EP5_IN_MSB 10 -#define USB_EP_STATUS_STALL_NAK_EP5_IN_LSB 10 +#define USB_EP_STATUS_STALL_NAK_EP5_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP5_IN_BITS _u(0x00000400) +#define USB_EP_STATUS_STALL_NAK_EP5_IN_MSB _u(10) +#define USB_EP_STATUS_STALL_NAK_EP5_IN_LSB _u(10) #define USB_EP_STATUS_STALL_NAK_EP5_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP4_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP4_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP4_OUT_BITS 0x00000200 -#define USB_EP_STATUS_STALL_NAK_EP4_OUT_MSB 9 -#define USB_EP_STATUS_STALL_NAK_EP4_OUT_LSB 9 +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_BITS _u(0x00000200) +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_MSB _u(9) +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_LSB _u(9) #define USB_EP_STATUS_STALL_NAK_EP4_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP4_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP4_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP4_IN_BITS 0x00000100 -#define USB_EP_STATUS_STALL_NAK_EP4_IN_MSB 8 -#define USB_EP_STATUS_STALL_NAK_EP4_IN_LSB 8 +#define USB_EP_STATUS_STALL_NAK_EP4_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP4_IN_BITS _u(0x00000100) +#define USB_EP_STATUS_STALL_NAK_EP4_IN_MSB _u(8) +#define USB_EP_STATUS_STALL_NAK_EP4_IN_LSB _u(8) #define USB_EP_STATUS_STALL_NAK_EP4_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP3_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP3_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP3_OUT_BITS 0x00000080 -#define USB_EP_STATUS_STALL_NAK_EP3_OUT_MSB 7 -#define USB_EP_STATUS_STALL_NAK_EP3_OUT_LSB 7 +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_BITS _u(0x00000080) +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_MSB _u(7) +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_LSB _u(7) #define USB_EP_STATUS_STALL_NAK_EP3_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP3_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP3_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP3_IN_BITS 0x00000040 -#define USB_EP_STATUS_STALL_NAK_EP3_IN_MSB 6 -#define USB_EP_STATUS_STALL_NAK_EP3_IN_LSB 6 +#define USB_EP_STATUS_STALL_NAK_EP3_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP3_IN_BITS _u(0x00000040) +#define USB_EP_STATUS_STALL_NAK_EP3_IN_MSB _u(6) +#define USB_EP_STATUS_STALL_NAK_EP3_IN_LSB _u(6) #define USB_EP_STATUS_STALL_NAK_EP3_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP2_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP2_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP2_OUT_BITS 0x00000020 -#define USB_EP_STATUS_STALL_NAK_EP2_OUT_MSB 5 -#define USB_EP_STATUS_STALL_NAK_EP2_OUT_LSB 5 +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_BITS _u(0x00000020) +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_MSB _u(5) +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_LSB _u(5) #define USB_EP_STATUS_STALL_NAK_EP2_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP2_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP2_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP2_IN_BITS 0x00000010 -#define USB_EP_STATUS_STALL_NAK_EP2_IN_MSB 4 -#define USB_EP_STATUS_STALL_NAK_EP2_IN_LSB 4 +#define USB_EP_STATUS_STALL_NAK_EP2_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP2_IN_BITS _u(0x00000010) +#define USB_EP_STATUS_STALL_NAK_EP2_IN_MSB _u(4) +#define USB_EP_STATUS_STALL_NAK_EP2_IN_LSB _u(4) #define USB_EP_STATUS_STALL_NAK_EP2_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP1_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP1_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP1_OUT_BITS 0x00000008 -#define USB_EP_STATUS_STALL_NAK_EP1_OUT_MSB 3 -#define USB_EP_STATUS_STALL_NAK_EP1_OUT_LSB 3 +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_BITS _u(0x00000008) +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_MSB _u(3) +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_LSB _u(3) #define USB_EP_STATUS_STALL_NAK_EP1_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP1_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP1_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP1_IN_BITS 0x00000004 -#define USB_EP_STATUS_STALL_NAK_EP1_IN_MSB 2 -#define USB_EP_STATUS_STALL_NAK_EP1_IN_LSB 2 +#define USB_EP_STATUS_STALL_NAK_EP1_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP1_IN_BITS _u(0x00000004) +#define USB_EP_STATUS_STALL_NAK_EP1_IN_MSB _u(2) +#define USB_EP_STATUS_STALL_NAK_EP1_IN_LSB _u(2) #define USB_EP_STATUS_STALL_NAK_EP1_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP0_OUT // Description : None -#define USB_EP_STATUS_STALL_NAK_EP0_OUT_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP0_OUT_BITS 0x00000002 -#define USB_EP_STATUS_STALL_NAK_EP0_OUT_MSB 1 -#define USB_EP_STATUS_STALL_NAK_EP0_OUT_LSB 1 +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_BITS _u(0x00000002) +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_MSB _u(1) +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_LSB _u(1) #define USB_EP_STATUS_STALL_NAK_EP0_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP0_IN // Description : None -#define USB_EP_STATUS_STALL_NAK_EP0_IN_RESET 0x0 -#define USB_EP_STATUS_STALL_NAK_EP0_IN_BITS 0x00000001 -#define USB_EP_STATUS_STALL_NAK_EP0_IN_MSB 0 -#define USB_EP_STATUS_STALL_NAK_EP0_IN_LSB 0 +#define USB_EP_STATUS_STALL_NAK_EP0_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP0_IN_BITS _u(0x00000001) +#define USB_EP_STATUS_STALL_NAK_EP0_IN_MSB _u(0) +#define USB_EP_STATUS_STALL_NAK_EP0_IN_LSB _u(0) #define USB_EP_STATUS_STALL_NAK_EP0_IN_ACCESS "WC" // ============================================================================= // Register : USB_USB_MUXING // Description : Where to connect the USB controller. Should be to_phy by // default. -#define USB_USB_MUXING_OFFSET 0x00000074 -#define USB_USB_MUXING_BITS 0x0000000f -#define USB_USB_MUXING_RESET 0x00000000 +#define USB_USB_MUXING_OFFSET _u(0x00000074) +#define USB_USB_MUXING_BITS _u(0x0000000f) +#define USB_USB_MUXING_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_USB_MUXING_SOFTCON // Description : None -#define USB_USB_MUXING_SOFTCON_RESET 0x0 -#define USB_USB_MUXING_SOFTCON_BITS 0x00000008 -#define USB_USB_MUXING_SOFTCON_MSB 3 -#define USB_USB_MUXING_SOFTCON_LSB 3 +#define USB_USB_MUXING_SOFTCON_RESET _u(0x0) +#define USB_USB_MUXING_SOFTCON_BITS _u(0x00000008) +#define USB_USB_MUXING_SOFTCON_MSB _u(3) +#define USB_USB_MUXING_SOFTCON_LSB _u(3) #define USB_USB_MUXING_SOFTCON_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_MUXING_TO_DIGITAL_PAD // Description : None -#define USB_USB_MUXING_TO_DIGITAL_PAD_RESET 0x0 -#define USB_USB_MUXING_TO_DIGITAL_PAD_BITS 0x00000004 -#define USB_USB_MUXING_TO_DIGITAL_PAD_MSB 2 -#define USB_USB_MUXING_TO_DIGITAL_PAD_LSB 2 +#define USB_USB_MUXING_TO_DIGITAL_PAD_RESET _u(0x0) +#define USB_USB_MUXING_TO_DIGITAL_PAD_BITS _u(0x00000004) +#define USB_USB_MUXING_TO_DIGITAL_PAD_MSB _u(2) +#define USB_USB_MUXING_TO_DIGITAL_PAD_LSB _u(2) #define USB_USB_MUXING_TO_DIGITAL_PAD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_MUXING_TO_EXTPHY // Description : None -#define USB_USB_MUXING_TO_EXTPHY_RESET 0x0 -#define USB_USB_MUXING_TO_EXTPHY_BITS 0x00000002 -#define USB_USB_MUXING_TO_EXTPHY_MSB 1 -#define USB_USB_MUXING_TO_EXTPHY_LSB 1 +#define USB_USB_MUXING_TO_EXTPHY_RESET _u(0x0) +#define USB_USB_MUXING_TO_EXTPHY_BITS _u(0x00000002) +#define USB_USB_MUXING_TO_EXTPHY_MSB _u(1) +#define USB_USB_MUXING_TO_EXTPHY_LSB _u(1) #define USB_USB_MUXING_TO_EXTPHY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_MUXING_TO_PHY // Description : None -#define USB_USB_MUXING_TO_PHY_RESET 0x0 -#define USB_USB_MUXING_TO_PHY_BITS 0x00000001 -#define USB_USB_MUXING_TO_PHY_MSB 0 -#define USB_USB_MUXING_TO_PHY_LSB 0 +#define USB_USB_MUXING_TO_PHY_RESET _u(0x0) +#define USB_USB_MUXING_TO_PHY_BITS _u(0x00000001) +#define USB_USB_MUXING_TO_PHY_MSB _u(0) +#define USB_USB_MUXING_TO_PHY_LSB _u(0) #define USB_USB_MUXING_TO_PHY_ACCESS "RW" // ============================================================================= // Register : USB_USB_PWR @@ -2497,167 +2497,167 @@ // signals are not hooked up to GPIO. Set the value of the // override and then the override enable to switch over to the // override value. -#define USB_USB_PWR_OFFSET 0x00000078 -#define USB_USB_PWR_BITS 0x0000003f -#define USB_USB_PWR_RESET 0x00000000 +#define USB_USB_PWR_OFFSET _u(0x00000078) +#define USB_USB_PWR_BITS _u(0x0000003f) +#define USB_USB_PWR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_OVERCURR_DETECT_EN // Description : None -#define USB_USB_PWR_OVERCURR_DETECT_EN_RESET 0x0 -#define USB_USB_PWR_OVERCURR_DETECT_EN_BITS 0x00000020 -#define USB_USB_PWR_OVERCURR_DETECT_EN_MSB 5 -#define USB_USB_PWR_OVERCURR_DETECT_EN_LSB 5 +#define USB_USB_PWR_OVERCURR_DETECT_EN_RESET _u(0x0) +#define USB_USB_PWR_OVERCURR_DETECT_EN_BITS _u(0x00000020) +#define USB_USB_PWR_OVERCURR_DETECT_EN_MSB _u(5) +#define USB_USB_PWR_OVERCURR_DETECT_EN_LSB _u(5) #define USB_USB_PWR_OVERCURR_DETECT_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_OVERCURR_DETECT // Description : None -#define USB_USB_PWR_OVERCURR_DETECT_RESET 0x0 -#define USB_USB_PWR_OVERCURR_DETECT_BITS 0x00000010 -#define USB_USB_PWR_OVERCURR_DETECT_MSB 4 -#define USB_USB_PWR_OVERCURR_DETECT_LSB 4 +#define USB_USB_PWR_OVERCURR_DETECT_RESET _u(0x0) +#define USB_USB_PWR_OVERCURR_DETECT_BITS _u(0x00000010) +#define USB_USB_PWR_OVERCURR_DETECT_MSB _u(4) +#define USB_USB_PWR_OVERCURR_DETECT_LSB _u(4) #define USB_USB_PWR_OVERCURR_DETECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN // Description : None -#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_RESET 0x0 -#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS 0x00000008 -#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_MSB 3 -#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_LSB 3 +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_RESET _u(0x0) +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS _u(0x00000008) +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_MSB _u(3) +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_LSB _u(3) #define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_VBUS_DETECT // Description : None -#define USB_USB_PWR_VBUS_DETECT_RESET 0x0 -#define USB_USB_PWR_VBUS_DETECT_BITS 0x00000004 -#define USB_USB_PWR_VBUS_DETECT_MSB 2 -#define USB_USB_PWR_VBUS_DETECT_LSB 2 +#define USB_USB_PWR_VBUS_DETECT_RESET _u(0x0) +#define USB_USB_PWR_VBUS_DETECT_BITS _u(0x00000004) +#define USB_USB_PWR_VBUS_DETECT_MSB _u(2) +#define USB_USB_PWR_VBUS_DETECT_LSB _u(2) #define USB_USB_PWR_VBUS_DETECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_VBUS_EN_OVERRIDE_EN // Description : None -#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_RESET 0x0 -#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_BITS 0x00000002 -#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_MSB 1 -#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_LSB 1 +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_RESET _u(0x0) +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_BITS _u(0x00000002) +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_MSB _u(1) +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_LSB _u(1) #define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_VBUS_EN // Description : None -#define USB_USB_PWR_VBUS_EN_RESET 0x0 -#define USB_USB_PWR_VBUS_EN_BITS 0x00000001 -#define USB_USB_PWR_VBUS_EN_MSB 0 -#define USB_USB_PWR_VBUS_EN_LSB 0 +#define USB_USB_PWR_VBUS_EN_RESET _u(0x0) +#define USB_USB_PWR_VBUS_EN_BITS _u(0x00000001) +#define USB_USB_PWR_VBUS_EN_MSB _u(0) +#define USB_USB_PWR_VBUS_EN_LSB _u(0) #define USB_USB_PWR_VBUS_EN_ACCESS "RW" // ============================================================================= // Register : USB_USBPHY_DIRECT // Description : This register allows for direct control of the USB phy. Use in // conjunction with usbphy_direct_override register to enable each // override bit. -#define USB_USBPHY_DIRECT_OFFSET 0x0000007c -#define USB_USBPHY_DIRECT_BITS 0x007fff77 -#define USB_USBPHY_DIRECT_RESET 0x00000000 +#define USB_USBPHY_DIRECT_OFFSET _u(0x0000007c) +#define USB_USBPHY_DIRECT_BITS _u(0x007fff77) +#define USB_USBPHY_DIRECT_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_OVV // Description : DM over voltage -#define USB_USBPHY_DIRECT_DM_OVV_RESET 0x0 -#define USB_USBPHY_DIRECT_DM_OVV_BITS 0x00400000 -#define USB_USBPHY_DIRECT_DM_OVV_MSB 22 -#define USB_USBPHY_DIRECT_DM_OVV_LSB 22 +#define USB_USBPHY_DIRECT_DM_OVV_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DM_OVV_BITS _u(0x00400000) +#define USB_USBPHY_DIRECT_DM_OVV_MSB _u(22) +#define USB_USBPHY_DIRECT_DM_OVV_LSB _u(22) #define USB_USBPHY_DIRECT_DM_OVV_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_OVV // Description : DP over voltage -#define USB_USBPHY_DIRECT_DP_OVV_RESET 0x0 -#define USB_USBPHY_DIRECT_DP_OVV_BITS 0x00200000 -#define USB_USBPHY_DIRECT_DP_OVV_MSB 21 -#define USB_USBPHY_DIRECT_DP_OVV_LSB 21 +#define USB_USBPHY_DIRECT_DP_OVV_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DP_OVV_BITS _u(0x00200000) +#define USB_USBPHY_DIRECT_DP_OVV_MSB _u(21) +#define USB_USBPHY_DIRECT_DP_OVV_LSB _u(21) #define USB_USBPHY_DIRECT_DP_OVV_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_OVCN // Description : DM overcurrent -#define USB_USBPHY_DIRECT_DM_OVCN_RESET 0x0 -#define USB_USBPHY_DIRECT_DM_OVCN_BITS 0x00100000 -#define USB_USBPHY_DIRECT_DM_OVCN_MSB 20 -#define USB_USBPHY_DIRECT_DM_OVCN_LSB 20 +#define USB_USBPHY_DIRECT_DM_OVCN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DM_OVCN_BITS _u(0x00100000) +#define USB_USBPHY_DIRECT_DM_OVCN_MSB _u(20) +#define USB_USBPHY_DIRECT_DM_OVCN_LSB _u(20) #define USB_USBPHY_DIRECT_DM_OVCN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_OVCN // Description : DP overcurrent -#define USB_USBPHY_DIRECT_DP_OVCN_RESET 0x0 -#define USB_USBPHY_DIRECT_DP_OVCN_BITS 0x00080000 -#define USB_USBPHY_DIRECT_DP_OVCN_MSB 19 -#define USB_USBPHY_DIRECT_DP_OVCN_LSB 19 +#define USB_USBPHY_DIRECT_DP_OVCN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DP_OVCN_BITS _u(0x00080000) +#define USB_USBPHY_DIRECT_DP_OVCN_MSB _u(19) +#define USB_USBPHY_DIRECT_DP_OVCN_LSB _u(19) #define USB_USBPHY_DIRECT_DP_OVCN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_RX_DM // Description : DPM pin state -#define USB_USBPHY_DIRECT_RX_DM_RESET 0x0 -#define USB_USBPHY_DIRECT_RX_DM_BITS 0x00040000 -#define USB_USBPHY_DIRECT_RX_DM_MSB 18 -#define USB_USBPHY_DIRECT_RX_DM_LSB 18 +#define USB_USBPHY_DIRECT_RX_DM_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_DM_BITS _u(0x00040000) +#define USB_USBPHY_DIRECT_RX_DM_MSB _u(18) +#define USB_USBPHY_DIRECT_RX_DM_LSB _u(18) #define USB_USBPHY_DIRECT_RX_DM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_RX_DP // Description : DPP pin state -#define USB_USBPHY_DIRECT_RX_DP_RESET 0x0 -#define USB_USBPHY_DIRECT_RX_DP_BITS 0x00020000 -#define USB_USBPHY_DIRECT_RX_DP_MSB 17 -#define USB_USBPHY_DIRECT_RX_DP_LSB 17 +#define USB_USBPHY_DIRECT_RX_DP_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_DP_BITS _u(0x00020000) +#define USB_USBPHY_DIRECT_RX_DP_MSB _u(17) +#define USB_USBPHY_DIRECT_RX_DP_LSB _u(17) #define USB_USBPHY_DIRECT_RX_DP_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_RX_DD // Description : Differential RX -#define USB_USBPHY_DIRECT_RX_DD_RESET 0x0 -#define USB_USBPHY_DIRECT_RX_DD_BITS 0x00010000 -#define USB_USBPHY_DIRECT_RX_DD_MSB 16 -#define USB_USBPHY_DIRECT_RX_DD_LSB 16 +#define USB_USBPHY_DIRECT_RX_DD_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_DD_BITS _u(0x00010000) +#define USB_USBPHY_DIRECT_RX_DD_MSB _u(16) +#define USB_USBPHY_DIRECT_RX_DD_LSB _u(16) #define USB_USBPHY_DIRECT_RX_DD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DIFFMODE // Description : TX_DIFFMODE=0: Single ended mode // TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE // ignored) -#define USB_USBPHY_DIRECT_TX_DIFFMODE_RESET 0x0 -#define USB_USBPHY_DIRECT_TX_DIFFMODE_BITS 0x00008000 -#define USB_USBPHY_DIRECT_TX_DIFFMODE_MSB 15 -#define USB_USBPHY_DIRECT_TX_DIFFMODE_LSB 15 +#define USB_USBPHY_DIRECT_TX_DIFFMODE_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_DIFFMODE_BITS _u(0x00008000) +#define USB_USBPHY_DIRECT_TX_DIFFMODE_MSB _u(15) +#define USB_USBPHY_DIRECT_TX_DIFFMODE_LSB _u(15) #define USB_USBPHY_DIRECT_TX_DIFFMODE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_FSSLEW // Description : TX_FSSLEW=0: Low speed slew rate // TX_FSSLEW=1: Full speed slew rate -#define USB_USBPHY_DIRECT_TX_FSSLEW_RESET 0x0 -#define USB_USBPHY_DIRECT_TX_FSSLEW_BITS 0x00004000 -#define USB_USBPHY_DIRECT_TX_FSSLEW_MSB 14 -#define USB_USBPHY_DIRECT_TX_FSSLEW_LSB 14 +#define USB_USBPHY_DIRECT_TX_FSSLEW_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_FSSLEW_BITS _u(0x00004000) +#define USB_USBPHY_DIRECT_TX_FSSLEW_MSB _u(14) +#define USB_USBPHY_DIRECT_TX_FSSLEW_LSB _u(14) #define USB_USBPHY_DIRECT_TX_FSSLEW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_PD // Description : TX power down override (if override enable is set). 1 = powered // down. -#define USB_USBPHY_DIRECT_TX_PD_RESET 0x0 -#define USB_USBPHY_DIRECT_TX_PD_BITS 0x00002000 -#define USB_USBPHY_DIRECT_TX_PD_MSB 13 -#define USB_USBPHY_DIRECT_TX_PD_LSB 13 +#define USB_USBPHY_DIRECT_TX_PD_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_PD_BITS _u(0x00002000) +#define USB_USBPHY_DIRECT_TX_PD_MSB _u(13) +#define USB_USBPHY_DIRECT_TX_PD_LSB _u(13) #define USB_USBPHY_DIRECT_TX_PD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_RX_PD // Description : RX power down override (if override enable is set). 1 = powered // down. -#define USB_USBPHY_DIRECT_RX_PD_RESET 0x0 -#define USB_USBPHY_DIRECT_RX_PD_BITS 0x00001000 -#define USB_USBPHY_DIRECT_RX_PD_MSB 12 -#define USB_USBPHY_DIRECT_RX_PD_LSB 12 +#define USB_USBPHY_DIRECT_RX_PD_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_PD_BITS _u(0x00001000) +#define USB_USBPHY_DIRECT_RX_PD_MSB _u(12) +#define USB_USBPHY_DIRECT_RX_PD_LSB _u(12) #define USB_USBPHY_DIRECT_RX_PD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DM // Description : Output data. TX_DIFFMODE=1, Ignored // TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. // DPM=TX_DM -#define USB_USBPHY_DIRECT_TX_DM_RESET 0x0 -#define USB_USBPHY_DIRECT_TX_DM_BITS 0x00000800 -#define USB_USBPHY_DIRECT_TX_DM_MSB 11 -#define USB_USBPHY_DIRECT_TX_DM_LSB 11 +#define USB_USBPHY_DIRECT_TX_DM_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_DM_BITS _u(0x00000800) +#define USB_USBPHY_DIRECT_TX_DM_MSB _u(11) +#define USB_USBPHY_DIRECT_TX_DM_LSB _u(11) #define USB_USBPHY_DIRECT_TX_DM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DP @@ -2665,20 +2665,20 @@ // TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP // If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. // DPP=TX_DP -#define USB_USBPHY_DIRECT_TX_DP_RESET 0x0 -#define USB_USBPHY_DIRECT_TX_DP_BITS 0x00000400 -#define USB_USBPHY_DIRECT_TX_DP_MSB 10 -#define USB_USBPHY_DIRECT_TX_DP_LSB 10 +#define USB_USBPHY_DIRECT_TX_DP_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_DP_BITS _u(0x00000400) +#define USB_USBPHY_DIRECT_TX_DP_MSB _u(10) +#define USB_USBPHY_DIRECT_TX_DP_LSB _u(10) #define USB_USBPHY_DIRECT_TX_DP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DM_OE // Description : Output enable. If TX_DIFFMODE=1, Ignored. // If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - // DPM driving -#define USB_USBPHY_DIRECT_TX_DM_OE_RESET 0x0 -#define USB_USBPHY_DIRECT_TX_DM_OE_BITS 0x00000200 -#define USB_USBPHY_DIRECT_TX_DM_OE_MSB 9 -#define USB_USBPHY_DIRECT_TX_DM_OE_LSB 9 +#define USB_USBPHY_DIRECT_TX_DM_OE_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_DM_OE_BITS _u(0x00000200) +#define USB_USBPHY_DIRECT_TX_DM_OE_MSB _u(9) +#define USB_USBPHY_DIRECT_TX_DM_OE_LSB _u(9) #define USB_USBPHY_DIRECT_TX_DM_OE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DP_OE @@ -2686,195 +2686,195 @@ // DPP/DPM in Hi-Z state; 1 - DPP/DPM driving // If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - // DPP driving -#define USB_USBPHY_DIRECT_TX_DP_OE_RESET 0x0 -#define USB_USBPHY_DIRECT_TX_DP_OE_BITS 0x00000100 -#define USB_USBPHY_DIRECT_TX_DP_OE_MSB 8 -#define USB_USBPHY_DIRECT_TX_DP_OE_LSB 8 +#define USB_USBPHY_DIRECT_TX_DP_OE_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_DP_OE_BITS _u(0x00000100) +#define USB_USBPHY_DIRECT_TX_DP_OE_MSB _u(8) +#define USB_USBPHY_DIRECT_TX_DP_OE_LSB _u(8) #define USB_USBPHY_DIRECT_TX_DP_OE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_PULLDN_EN // Description : DM pull down enable -#define USB_USBPHY_DIRECT_DM_PULLDN_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_DM_PULLDN_EN_BITS 0x00000040 -#define USB_USBPHY_DIRECT_DM_PULLDN_EN_MSB 6 -#define USB_USBPHY_DIRECT_DM_PULLDN_EN_LSB 6 +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_BITS _u(0x00000040) +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_MSB _u(6) +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_LSB _u(6) #define USB_USBPHY_DIRECT_DM_PULLDN_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_PULLUP_EN // Description : DM pull up enable -#define USB_USBPHY_DIRECT_DM_PULLUP_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_DM_PULLUP_EN_BITS 0x00000020 -#define USB_USBPHY_DIRECT_DM_PULLUP_EN_MSB 5 -#define USB_USBPHY_DIRECT_DM_PULLUP_EN_LSB 5 +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_BITS _u(0x00000020) +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_MSB _u(5) +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_LSB _u(5) #define USB_USBPHY_DIRECT_DM_PULLUP_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_PULLUP_HISEL // Description : Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - // Pull = Rpu1 + Rpu2 -#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_RESET 0x0 -#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_BITS 0x00000010 -#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_MSB 4 -#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_LSB 4 +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_BITS _u(0x00000010) +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_MSB _u(4) +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_LSB _u(4) #define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_PULLDN_EN // Description : DP pull down enable -#define USB_USBPHY_DIRECT_DP_PULLDN_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_DP_PULLDN_EN_BITS 0x00000004 -#define USB_USBPHY_DIRECT_DP_PULLDN_EN_MSB 2 -#define USB_USBPHY_DIRECT_DP_PULLDN_EN_LSB 2 +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_BITS _u(0x00000004) +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_MSB _u(2) +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_LSB _u(2) #define USB_USBPHY_DIRECT_DP_PULLDN_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_PULLUP_EN // Description : DP pull up enable -#define USB_USBPHY_DIRECT_DP_PULLUP_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS 0x00000002 -#define USB_USBPHY_DIRECT_DP_PULLUP_EN_MSB 1 -#define USB_USBPHY_DIRECT_DP_PULLUP_EN_LSB 1 +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS _u(0x00000002) +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_MSB _u(1) +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_LSB _u(1) #define USB_USBPHY_DIRECT_DP_PULLUP_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_PULLUP_HISEL // Description : Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - // Pull = Rpu1 + Rpu2 -#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_RESET 0x0 -#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_BITS 0x00000001 -#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_MSB 0 -#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_LSB 0 +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_BITS _u(0x00000001) +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_MSB _u(0) +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_LSB _u(0) #define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_ACCESS "RW" // ============================================================================= // Register : USB_USBPHY_DIRECT_OVERRIDE // Description : Override enable for each control in usbphy_direct -#define USB_USBPHY_DIRECT_OVERRIDE_OFFSET 0x00000080 -#define USB_USBPHY_DIRECT_OVERRIDE_BITS 0x00009fff -#define USB_USBPHY_DIRECT_OVERRIDE_RESET 0x00000000 +#define USB_USBPHY_DIRECT_OVERRIDE_OFFSET _u(0x00000080) +#define USB_USBPHY_DIRECT_OVERRIDE_BITS _u(0x00009fff) +#define USB_USBPHY_DIRECT_OVERRIDE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_BITS 0x00008000 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_MSB 15 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_LSB 15 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_BITS _u(0x00008000) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_MSB _u(15) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_LSB _u(15) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_BITS 0x00001000 -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_MSB 12 -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_LSB 12 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_BITS _u(0x00001000) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_MSB _u(12) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_LSB _u(12) #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_BITS 0x00000800 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_MSB 11 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_LSB 11 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_BITS _u(0x00000800) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_MSB _u(11) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_LSB _u(11) #define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_BITS 0x00000400 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_MSB 10 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_LSB 10 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_BITS _u(0x00000400) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_MSB _u(10) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_LSB _u(10) #define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_BITS 0x00000200 -#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_MSB 9 -#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_LSB 9 +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_BITS _u(0x00000200) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_MSB _u(9) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_LSB _u(9) #define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_BITS 0x00000100 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_MSB 8 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_LSB 8 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_BITS _u(0x00000100) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_MSB _u(8) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_LSB _u(8) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_BITS 0x00000080 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_MSB 7 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_LSB 7 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_BITS _u(0x00000080) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_MSB _u(7) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_LSB _u(7) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_BITS 0x00000040 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_MSB 6 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_LSB 6 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_BITS _u(0x00000040) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_MSB _u(6) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_LSB _u(6) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_BITS 0x00000020 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_MSB 5 -#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_LSB 5 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_BITS _u(0x00000020) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_MSB _u(5) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_LSB _u(5) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_BITS 0x00000010 -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_MSB 4 -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_LSB 4 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000010) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_MSB _u(4) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_LSB _u(4) #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_BITS 0x00000008 -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_MSB 3 -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_LSB 3 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000008) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_MSB _u(3) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_LSB _u(3) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS 0x00000004 -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_MSB 2 -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_LSB 2 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS _u(0x00000004) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_MSB _u(2) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_LSB _u(2) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_BITS 0x00000002 -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_MSB 1 -#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_LSB 1 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000002) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_MSB _u(1) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_LSB _u(1) #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN // Description : None -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_RESET 0x0 -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_BITS 0x00000001 -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_MSB 0 -#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_LSB 0 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000001) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_MSB _u(0) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_LSB _u(0) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW" // ============================================================================= // Register : USB_USBPHY_TRIM // Description : Used to adjust trim values of USB phy pull down resistors. -#define USB_USBPHY_TRIM_OFFSET 0x00000084 -#define USB_USBPHY_TRIM_BITS 0x00001f1f -#define USB_USBPHY_TRIM_RESET 0x00001f1f +#define USB_USBPHY_TRIM_OFFSET _u(0x00000084) +#define USB_USBPHY_TRIM_BITS _u(0x00001f1f) +#define USB_USBPHY_TRIM_RESET _u(0x00001f1f) // ----------------------------------------------------------------------------- // Field : USB_USBPHY_TRIM_DM_PULLDN_TRIM // Description : Value to drive to USB PHY // DM pulldown resistor trim control // Experimental data suggests that the reset value will work, but // this register allows adjustment if required -#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_RESET 0x1f -#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_BITS 0x00001f00 -#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_MSB 12 -#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_LSB 8 +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_RESET _u(0x1f) +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_BITS _u(0x00001f00) +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_MSB _u(12) +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_LSB _u(8) #define USB_USBPHY_TRIM_DM_PULLDN_TRIM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_TRIM_DP_PULLDN_TRIM @@ -2882,722 +2882,722 @@ // DP pulldown resistor trim control // Experimental data suggests that the reset value will work, but // this register allows adjustment if required -#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_RESET 0x1f -#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_BITS 0x0000001f -#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_MSB 4 -#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_LSB 0 +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_RESET _u(0x1f) +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_BITS _u(0x0000001f) +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_MSB _u(4) +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_LSB _u(0) #define USB_USBPHY_TRIM_DP_PULLDN_TRIM_ACCESS "RW" // ============================================================================= // Register : USB_INTR // Description : Raw Interrupts -#define USB_INTR_OFFSET 0x0000008c -#define USB_INTR_BITS 0x000fffff -#define USB_INTR_RESET 0x00000000 +#define USB_INTR_OFFSET _u(0x0000008c) +#define USB_INTR_BITS _u(0x000fffff) +#define USB_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_INTR_EP_STALL_NAK // Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by // clearing all bits in EP_STATUS_STALL_NAK. -#define USB_INTR_EP_STALL_NAK_RESET 0x0 -#define USB_INTR_EP_STALL_NAK_BITS 0x00080000 -#define USB_INTR_EP_STALL_NAK_MSB 19 -#define USB_INTR_EP_STALL_NAK_LSB 19 +#define USB_INTR_EP_STALL_NAK_RESET _u(0x0) +#define USB_INTR_EP_STALL_NAK_BITS _u(0x00080000) +#define USB_INTR_EP_STALL_NAK_MSB _u(19) +#define USB_INTR_EP_STALL_NAK_LSB _u(19) #define USB_INTR_EP_STALL_NAK_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_ABORT_DONE // Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all // bits in ABORT_DONE. -#define USB_INTR_ABORT_DONE_RESET 0x0 -#define USB_INTR_ABORT_DONE_BITS 0x00040000 -#define USB_INTR_ABORT_DONE_MSB 18 -#define USB_INTR_ABORT_DONE_LSB 18 +#define USB_INTR_ABORT_DONE_RESET _u(0x0) +#define USB_INTR_ABORT_DONE_BITS _u(0x00040000) +#define USB_INTR_ABORT_DONE_MSB _u(18) +#define USB_INTR_ABORT_DONE_LSB _u(18) #define USB_INTR_ABORT_DONE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_DEV_SOF // Description : Set every time the device receives a SOF (Start of Frame) // packet. Cleared by reading SOF_RD -#define USB_INTR_DEV_SOF_RESET 0x0 -#define USB_INTR_DEV_SOF_BITS 0x00020000 -#define USB_INTR_DEV_SOF_MSB 17 -#define USB_INTR_DEV_SOF_LSB 17 +#define USB_INTR_DEV_SOF_RESET _u(0x0) +#define USB_INTR_DEV_SOF_BITS _u(0x00020000) +#define USB_INTR_DEV_SOF_MSB _u(17) +#define USB_INTR_DEV_SOF_LSB _u(17) #define USB_INTR_DEV_SOF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_SETUP_REQ // Description : Device. Source: SIE_STATUS.SETUP_REC -#define USB_INTR_SETUP_REQ_RESET 0x0 -#define USB_INTR_SETUP_REQ_BITS 0x00010000 -#define USB_INTR_SETUP_REQ_MSB 16 -#define USB_INTR_SETUP_REQ_LSB 16 +#define USB_INTR_SETUP_REQ_RESET _u(0x0) +#define USB_INTR_SETUP_REQ_BITS _u(0x00010000) +#define USB_INTR_SETUP_REQ_MSB _u(16) +#define USB_INTR_SETUP_REQ_LSB _u(16) #define USB_INTR_SETUP_REQ_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_DEV_RESUME_FROM_HOST // Description : Set when the device receives a resume from the host. Cleared by // writing to SIE_STATUS.RESUME -#define USB_INTR_DEV_RESUME_FROM_HOST_RESET 0x0 -#define USB_INTR_DEV_RESUME_FROM_HOST_BITS 0x00008000 -#define USB_INTR_DEV_RESUME_FROM_HOST_MSB 15 -#define USB_INTR_DEV_RESUME_FROM_HOST_LSB 15 +#define USB_INTR_DEV_RESUME_FROM_HOST_RESET _u(0x0) +#define USB_INTR_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) +#define USB_INTR_DEV_RESUME_FROM_HOST_MSB _u(15) +#define USB_INTR_DEV_RESUME_FROM_HOST_LSB _u(15) #define USB_INTR_DEV_RESUME_FROM_HOST_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_DEV_SUSPEND // Description : Set when the device suspend state changes. Cleared by writing // to SIE_STATUS.SUSPENDED -#define USB_INTR_DEV_SUSPEND_RESET 0x0 -#define USB_INTR_DEV_SUSPEND_BITS 0x00004000 -#define USB_INTR_DEV_SUSPEND_MSB 14 -#define USB_INTR_DEV_SUSPEND_LSB 14 +#define USB_INTR_DEV_SUSPEND_RESET _u(0x0) +#define USB_INTR_DEV_SUSPEND_BITS _u(0x00004000) +#define USB_INTR_DEV_SUSPEND_MSB _u(14) +#define USB_INTR_DEV_SUSPEND_LSB _u(14) #define USB_INTR_DEV_SUSPEND_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_DEV_CONN_DIS // Description : Set when the device connection state changes. Cleared by // writing to SIE_STATUS.CONNECTED -#define USB_INTR_DEV_CONN_DIS_RESET 0x0 -#define USB_INTR_DEV_CONN_DIS_BITS 0x00002000 -#define USB_INTR_DEV_CONN_DIS_MSB 13 -#define USB_INTR_DEV_CONN_DIS_LSB 13 +#define USB_INTR_DEV_CONN_DIS_RESET _u(0x0) +#define USB_INTR_DEV_CONN_DIS_BITS _u(0x00002000) +#define USB_INTR_DEV_CONN_DIS_MSB _u(13) +#define USB_INTR_DEV_CONN_DIS_LSB _u(13) #define USB_INTR_DEV_CONN_DIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_BUS_RESET // Description : Source: SIE_STATUS.BUS_RESET -#define USB_INTR_BUS_RESET_RESET 0x0 -#define USB_INTR_BUS_RESET_BITS 0x00001000 -#define USB_INTR_BUS_RESET_MSB 12 -#define USB_INTR_BUS_RESET_LSB 12 +#define USB_INTR_BUS_RESET_RESET _u(0x0) +#define USB_INTR_BUS_RESET_BITS _u(0x00001000) +#define USB_INTR_BUS_RESET_MSB _u(12) +#define USB_INTR_BUS_RESET_LSB _u(12) #define USB_INTR_BUS_RESET_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECT -#define USB_INTR_VBUS_DETECT_RESET 0x0 -#define USB_INTR_VBUS_DETECT_BITS 0x00000800 -#define USB_INTR_VBUS_DETECT_MSB 11 -#define USB_INTR_VBUS_DETECT_LSB 11 +// Description : Source: SIE_STATUS.VBUS_DETECTED +#define USB_INTR_VBUS_DETECT_RESET _u(0x0) +#define USB_INTR_VBUS_DETECT_BITS _u(0x00000800) +#define USB_INTR_VBUS_DETECT_MSB _u(11) +#define USB_INTR_VBUS_DETECT_LSB _u(11) #define USB_INTR_VBUS_DETECT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_STALL // Description : Source: SIE_STATUS.STALL_REC -#define USB_INTR_STALL_RESET 0x0 -#define USB_INTR_STALL_BITS 0x00000400 -#define USB_INTR_STALL_MSB 10 -#define USB_INTR_STALL_LSB 10 +#define USB_INTR_STALL_RESET _u(0x0) +#define USB_INTR_STALL_BITS _u(0x00000400) +#define USB_INTR_STALL_MSB _u(10) +#define USB_INTR_STALL_LSB _u(10) #define USB_INTR_STALL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_ERROR_CRC // Description : Source: SIE_STATUS.CRC_ERROR -#define USB_INTR_ERROR_CRC_RESET 0x0 -#define USB_INTR_ERROR_CRC_BITS 0x00000200 -#define USB_INTR_ERROR_CRC_MSB 9 -#define USB_INTR_ERROR_CRC_LSB 9 +#define USB_INTR_ERROR_CRC_RESET _u(0x0) +#define USB_INTR_ERROR_CRC_BITS _u(0x00000200) +#define USB_INTR_ERROR_CRC_MSB _u(9) +#define USB_INTR_ERROR_CRC_LSB _u(9) #define USB_INTR_ERROR_CRC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_ERROR_BIT_STUFF // Description : Source: SIE_STATUS.BIT_STUFF_ERROR -#define USB_INTR_ERROR_BIT_STUFF_RESET 0x0 -#define USB_INTR_ERROR_BIT_STUFF_BITS 0x00000100 -#define USB_INTR_ERROR_BIT_STUFF_MSB 8 -#define USB_INTR_ERROR_BIT_STUFF_LSB 8 +#define USB_INTR_ERROR_BIT_STUFF_RESET _u(0x0) +#define USB_INTR_ERROR_BIT_STUFF_BITS _u(0x00000100) +#define USB_INTR_ERROR_BIT_STUFF_MSB _u(8) +#define USB_INTR_ERROR_BIT_STUFF_LSB _u(8) #define USB_INTR_ERROR_BIT_STUFF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_ERROR_RX_OVERFLOW // Description : Source: SIE_STATUS.RX_OVERFLOW -#define USB_INTR_ERROR_RX_OVERFLOW_RESET 0x0 -#define USB_INTR_ERROR_RX_OVERFLOW_BITS 0x00000080 -#define USB_INTR_ERROR_RX_OVERFLOW_MSB 7 -#define USB_INTR_ERROR_RX_OVERFLOW_LSB 7 +#define USB_INTR_ERROR_RX_OVERFLOW_RESET _u(0x0) +#define USB_INTR_ERROR_RX_OVERFLOW_BITS _u(0x00000080) +#define USB_INTR_ERROR_RX_OVERFLOW_MSB _u(7) +#define USB_INTR_ERROR_RX_OVERFLOW_LSB _u(7) #define USB_INTR_ERROR_RX_OVERFLOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_ERROR_RX_TIMEOUT // Description : Source: SIE_STATUS.RX_TIMEOUT -#define USB_INTR_ERROR_RX_TIMEOUT_RESET 0x0 -#define USB_INTR_ERROR_RX_TIMEOUT_BITS 0x00000040 -#define USB_INTR_ERROR_RX_TIMEOUT_MSB 6 -#define USB_INTR_ERROR_RX_TIMEOUT_LSB 6 +#define USB_INTR_ERROR_RX_TIMEOUT_RESET _u(0x0) +#define USB_INTR_ERROR_RX_TIMEOUT_BITS _u(0x00000040) +#define USB_INTR_ERROR_RX_TIMEOUT_MSB _u(6) +#define USB_INTR_ERROR_RX_TIMEOUT_LSB _u(6) #define USB_INTR_ERROR_RX_TIMEOUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_ERROR_DATA_SEQ // Description : Source: SIE_STATUS.DATA_SEQ_ERROR -#define USB_INTR_ERROR_DATA_SEQ_RESET 0x0 -#define USB_INTR_ERROR_DATA_SEQ_BITS 0x00000020 -#define USB_INTR_ERROR_DATA_SEQ_MSB 5 -#define USB_INTR_ERROR_DATA_SEQ_LSB 5 +#define USB_INTR_ERROR_DATA_SEQ_RESET _u(0x0) +#define USB_INTR_ERROR_DATA_SEQ_BITS _u(0x00000020) +#define USB_INTR_ERROR_DATA_SEQ_MSB _u(5) +#define USB_INTR_ERROR_DATA_SEQ_LSB _u(5) #define USB_INTR_ERROR_DATA_SEQ_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_BUFF_STATUS // Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing // all bits in BUFF_STATUS. -#define USB_INTR_BUFF_STATUS_RESET 0x0 -#define USB_INTR_BUFF_STATUS_BITS 0x00000010 -#define USB_INTR_BUFF_STATUS_MSB 4 -#define USB_INTR_BUFF_STATUS_LSB 4 +#define USB_INTR_BUFF_STATUS_RESET _u(0x0) +#define USB_INTR_BUFF_STATUS_BITS _u(0x00000010) +#define USB_INTR_BUFF_STATUS_MSB _u(4) +#define USB_INTR_BUFF_STATUS_LSB _u(4) #define USB_INTR_BUFF_STATUS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_TRANS_COMPLETE // Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by // writing to this bit. -#define USB_INTR_TRANS_COMPLETE_RESET 0x0 -#define USB_INTR_TRANS_COMPLETE_BITS 0x00000008 -#define USB_INTR_TRANS_COMPLETE_MSB 3 -#define USB_INTR_TRANS_COMPLETE_LSB 3 +#define USB_INTR_TRANS_COMPLETE_RESET _u(0x0) +#define USB_INTR_TRANS_COMPLETE_BITS _u(0x00000008) +#define USB_INTR_TRANS_COMPLETE_MSB _u(3) +#define USB_INTR_TRANS_COMPLETE_LSB _u(3) #define USB_INTR_TRANS_COMPLETE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_HOST_SOF // Description : Host: raised every time the host sends a SOF (Start of Frame). // Cleared by reading SOF_RD -#define USB_INTR_HOST_SOF_RESET 0x0 -#define USB_INTR_HOST_SOF_BITS 0x00000004 -#define USB_INTR_HOST_SOF_MSB 2 -#define USB_INTR_HOST_SOF_LSB 2 +#define USB_INTR_HOST_SOF_RESET _u(0x0) +#define USB_INTR_HOST_SOF_BITS _u(0x00000004) +#define USB_INTR_HOST_SOF_MSB _u(2) +#define USB_INTR_HOST_SOF_LSB _u(2) #define USB_INTR_HOST_SOF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_HOST_RESUME // Description : Host: raised when a device wakes up the host. Cleared by // writing to SIE_STATUS.RESUME -#define USB_INTR_HOST_RESUME_RESET 0x0 -#define USB_INTR_HOST_RESUME_BITS 0x00000002 -#define USB_INTR_HOST_RESUME_MSB 1 -#define USB_INTR_HOST_RESUME_LSB 1 +#define USB_INTR_HOST_RESUME_RESET _u(0x0) +#define USB_INTR_HOST_RESUME_BITS _u(0x00000002) +#define USB_INTR_HOST_RESUME_MSB _u(1) +#define USB_INTR_HOST_RESUME_LSB _u(1) #define USB_INTR_HOST_RESUME_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_HOST_CONN_DIS // Description : Host: raised when a device is connected or disconnected (i.e. // when SIE_STATUS.SPEED changes). Cleared by writing to // SIE_STATUS.SPEED -#define USB_INTR_HOST_CONN_DIS_RESET 0x0 -#define USB_INTR_HOST_CONN_DIS_BITS 0x00000001 -#define USB_INTR_HOST_CONN_DIS_MSB 0 -#define USB_INTR_HOST_CONN_DIS_LSB 0 +#define USB_INTR_HOST_CONN_DIS_RESET _u(0x0) +#define USB_INTR_HOST_CONN_DIS_BITS _u(0x00000001) +#define USB_INTR_HOST_CONN_DIS_MSB _u(0) +#define USB_INTR_HOST_CONN_DIS_LSB _u(0) #define USB_INTR_HOST_CONN_DIS_ACCESS "RO" // ============================================================================= // Register : USB_INTE // Description : Interrupt Enable -#define USB_INTE_OFFSET 0x00000090 -#define USB_INTE_BITS 0x000fffff -#define USB_INTE_RESET 0x00000000 +#define USB_INTE_OFFSET _u(0x00000090) +#define USB_INTE_BITS _u(0x000fffff) +#define USB_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_INTE_EP_STALL_NAK // Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by // clearing all bits in EP_STATUS_STALL_NAK. -#define USB_INTE_EP_STALL_NAK_RESET 0x0 -#define USB_INTE_EP_STALL_NAK_BITS 0x00080000 -#define USB_INTE_EP_STALL_NAK_MSB 19 -#define USB_INTE_EP_STALL_NAK_LSB 19 +#define USB_INTE_EP_STALL_NAK_RESET _u(0x0) +#define USB_INTE_EP_STALL_NAK_BITS _u(0x00080000) +#define USB_INTE_EP_STALL_NAK_MSB _u(19) +#define USB_INTE_EP_STALL_NAK_LSB _u(19) #define USB_INTE_EP_STALL_NAK_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_ABORT_DONE // Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all // bits in ABORT_DONE. -#define USB_INTE_ABORT_DONE_RESET 0x0 -#define USB_INTE_ABORT_DONE_BITS 0x00040000 -#define USB_INTE_ABORT_DONE_MSB 18 -#define USB_INTE_ABORT_DONE_LSB 18 +#define USB_INTE_ABORT_DONE_RESET _u(0x0) +#define USB_INTE_ABORT_DONE_BITS _u(0x00040000) +#define USB_INTE_ABORT_DONE_MSB _u(18) +#define USB_INTE_ABORT_DONE_LSB _u(18) #define USB_INTE_ABORT_DONE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_DEV_SOF // Description : Set every time the device receives a SOF (Start of Frame) // packet. Cleared by reading SOF_RD -#define USB_INTE_DEV_SOF_RESET 0x0 -#define USB_INTE_DEV_SOF_BITS 0x00020000 -#define USB_INTE_DEV_SOF_MSB 17 -#define USB_INTE_DEV_SOF_LSB 17 +#define USB_INTE_DEV_SOF_RESET _u(0x0) +#define USB_INTE_DEV_SOF_BITS _u(0x00020000) +#define USB_INTE_DEV_SOF_MSB _u(17) +#define USB_INTE_DEV_SOF_LSB _u(17) #define USB_INTE_DEV_SOF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_SETUP_REQ // Description : Device. Source: SIE_STATUS.SETUP_REC -#define USB_INTE_SETUP_REQ_RESET 0x0 -#define USB_INTE_SETUP_REQ_BITS 0x00010000 -#define USB_INTE_SETUP_REQ_MSB 16 -#define USB_INTE_SETUP_REQ_LSB 16 +#define USB_INTE_SETUP_REQ_RESET _u(0x0) +#define USB_INTE_SETUP_REQ_BITS _u(0x00010000) +#define USB_INTE_SETUP_REQ_MSB _u(16) +#define USB_INTE_SETUP_REQ_LSB _u(16) #define USB_INTE_SETUP_REQ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_DEV_RESUME_FROM_HOST // Description : Set when the device receives a resume from the host. Cleared by // writing to SIE_STATUS.RESUME -#define USB_INTE_DEV_RESUME_FROM_HOST_RESET 0x0 -#define USB_INTE_DEV_RESUME_FROM_HOST_BITS 0x00008000 -#define USB_INTE_DEV_RESUME_FROM_HOST_MSB 15 -#define USB_INTE_DEV_RESUME_FROM_HOST_LSB 15 +#define USB_INTE_DEV_RESUME_FROM_HOST_RESET _u(0x0) +#define USB_INTE_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) +#define USB_INTE_DEV_RESUME_FROM_HOST_MSB _u(15) +#define USB_INTE_DEV_RESUME_FROM_HOST_LSB _u(15) #define USB_INTE_DEV_RESUME_FROM_HOST_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_DEV_SUSPEND // Description : Set when the device suspend state changes. Cleared by writing // to SIE_STATUS.SUSPENDED -#define USB_INTE_DEV_SUSPEND_RESET 0x0 -#define USB_INTE_DEV_SUSPEND_BITS 0x00004000 -#define USB_INTE_DEV_SUSPEND_MSB 14 -#define USB_INTE_DEV_SUSPEND_LSB 14 +#define USB_INTE_DEV_SUSPEND_RESET _u(0x0) +#define USB_INTE_DEV_SUSPEND_BITS _u(0x00004000) +#define USB_INTE_DEV_SUSPEND_MSB _u(14) +#define USB_INTE_DEV_SUSPEND_LSB _u(14) #define USB_INTE_DEV_SUSPEND_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_DEV_CONN_DIS // Description : Set when the device connection state changes. Cleared by // writing to SIE_STATUS.CONNECTED -#define USB_INTE_DEV_CONN_DIS_RESET 0x0 -#define USB_INTE_DEV_CONN_DIS_BITS 0x00002000 -#define USB_INTE_DEV_CONN_DIS_MSB 13 -#define USB_INTE_DEV_CONN_DIS_LSB 13 +#define USB_INTE_DEV_CONN_DIS_RESET _u(0x0) +#define USB_INTE_DEV_CONN_DIS_BITS _u(0x00002000) +#define USB_INTE_DEV_CONN_DIS_MSB _u(13) +#define USB_INTE_DEV_CONN_DIS_LSB _u(13) #define USB_INTE_DEV_CONN_DIS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_BUS_RESET // Description : Source: SIE_STATUS.BUS_RESET -#define USB_INTE_BUS_RESET_RESET 0x0 -#define USB_INTE_BUS_RESET_BITS 0x00001000 -#define USB_INTE_BUS_RESET_MSB 12 -#define USB_INTE_BUS_RESET_LSB 12 +#define USB_INTE_BUS_RESET_RESET _u(0x0) +#define USB_INTE_BUS_RESET_BITS _u(0x00001000) +#define USB_INTE_BUS_RESET_MSB _u(12) +#define USB_INTE_BUS_RESET_LSB _u(12) #define USB_INTE_BUS_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECT -#define USB_INTE_VBUS_DETECT_RESET 0x0 -#define USB_INTE_VBUS_DETECT_BITS 0x00000800 -#define USB_INTE_VBUS_DETECT_MSB 11 -#define USB_INTE_VBUS_DETECT_LSB 11 +// Description : Source: SIE_STATUS.VBUS_DETECTED +#define USB_INTE_VBUS_DETECT_RESET _u(0x0) +#define USB_INTE_VBUS_DETECT_BITS _u(0x00000800) +#define USB_INTE_VBUS_DETECT_MSB _u(11) +#define USB_INTE_VBUS_DETECT_LSB _u(11) #define USB_INTE_VBUS_DETECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_STALL // Description : Source: SIE_STATUS.STALL_REC -#define USB_INTE_STALL_RESET 0x0 -#define USB_INTE_STALL_BITS 0x00000400 -#define USB_INTE_STALL_MSB 10 -#define USB_INTE_STALL_LSB 10 +#define USB_INTE_STALL_RESET _u(0x0) +#define USB_INTE_STALL_BITS _u(0x00000400) +#define USB_INTE_STALL_MSB _u(10) +#define USB_INTE_STALL_LSB _u(10) #define USB_INTE_STALL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_ERROR_CRC // Description : Source: SIE_STATUS.CRC_ERROR -#define USB_INTE_ERROR_CRC_RESET 0x0 -#define USB_INTE_ERROR_CRC_BITS 0x00000200 -#define USB_INTE_ERROR_CRC_MSB 9 -#define USB_INTE_ERROR_CRC_LSB 9 +#define USB_INTE_ERROR_CRC_RESET _u(0x0) +#define USB_INTE_ERROR_CRC_BITS _u(0x00000200) +#define USB_INTE_ERROR_CRC_MSB _u(9) +#define USB_INTE_ERROR_CRC_LSB _u(9) #define USB_INTE_ERROR_CRC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_ERROR_BIT_STUFF // Description : Source: SIE_STATUS.BIT_STUFF_ERROR -#define USB_INTE_ERROR_BIT_STUFF_RESET 0x0 -#define USB_INTE_ERROR_BIT_STUFF_BITS 0x00000100 -#define USB_INTE_ERROR_BIT_STUFF_MSB 8 -#define USB_INTE_ERROR_BIT_STUFF_LSB 8 +#define USB_INTE_ERROR_BIT_STUFF_RESET _u(0x0) +#define USB_INTE_ERROR_BIT_STUFF_BITS _u(0x00000100) +#define USB_INTE_ERROR_BIT_STUFF_MSB _u(8) +#define USB_INTE_ERROR_BIT_STUFF_LSB _u(8) #define USB_INTE_ERROR_BIT_STUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_ERROR_RX_OVERFLOW // Description : Source: SIE_STATUS.RX_OVERFLOW -#define USB_INTE_ERROR_RX_OVERFLOW_RESET 0x0 -#define USB_INTE_ERROR_RX_OVERFLOW_BITS 0x00000080 -#define USB_INTE_ERROR_RX_OVERFLOW_MSB 7 -#define USB_INTE_ERROR_RX_OVERFLOW_LSB 7 +#define USB_INTE_ERROR_RX_OVERFLOW_RESET _u(0x0) +#define USB_INTE_ERROR_RX_OVERFLOW_BITS _u(0x00000080) +#define USB_INTE_ERROR_RX_OVERFLOW_MSB _u(7) +#define USB_INTE_ERROR_RX_OVERFLOW_LSB _u(7) #define USB_INTE_ERROR_RX_OVERFLOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_ERROR_RX_TIMEOUT // Description : Source: SIE_STATUS.RX_TIMEOUT -#define USB_INTE_ERROR_RX_TIMEOUT_RESET 0x0 -#define USB_INTE_ERROR_RX_TIMEOUT_BITS 0x00000040 -#define USB_INTE_ERROR_RX_TIMEOUT_MSB 6 -#define USB_INTE_ERROR_RX_TIMEOUT_LSB 6 +#define USB_INTE_ERROR_RX_TIMEOUT_RESET _u(0x0) +#define USB_INTE_ERROR_RX_TIMEOUT_BITS _u(0x00000040) +#define USB_INTE_ERROR_RX_TIMEOUT_MSB _u(6) +#define USB_INTE_ERROR_RX_TIMEOUT_LSB _u(6) #define USB_INTE_ERROR_RX_TIMEOUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_ERROR_DATA_SEQ // Description : Source: SIE_STATUS.DATA_SEQ_ERROR -#define USB_INTE_ERROR_DATA_SEQ_RESET 0x0 -#define USB_INTE_ERROR_DATA_SEQ_BITS 0x00000020 -#define USB_INTE_ERROR_DATA_SEQ_MSB 5 -#define USB_INTE_ERROR_DATA_SEQ_LSB 5 +#define USB_INTE_ERROR_DATA_SEQ_RESET _u(0x0) +#define USB_INTE_ERROR_DATA_SEQ_BITS _u(0x00000020) +#define USB_INTE_ERROR_DATA_SEQ_MSB _u(5) +#define USB_INTE_ERROR_DATA_SEQ_LSB _u(5) #define USB_INTE_ERROR_DATA_SEQ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_BUFF_STATUS // Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing // all bits in BUFF_STATUS. -#define USB_INTE_BUFF_STATUS_RESET 0x0 -#define USB_INTE_BUFF_STATUS_BITS 0x00000010 -#define USB_INTE_BUFF_STATUS_MSB 4 -#define USB_INTE_BUFF_STATUS_LSB 4 +#define USB_INTE_BUFF_STATUS_RESET _u(0x0) +#define USB_INTE_BUFF_STATUS_BITS _u(0x00000010) +#define USB_INTE_BUFF_STATUS_MSB _u(4) +#define USB_INTE_BUFF_STATUS_LSB _u(4) #define USB_INTE_BUFF_STATUS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_TRANS_COMPLETE // Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by // writing to this bit. -#define USB_INTE_TRANS_COMPLETE_RESET 0x0 -#define USB_INTE_TRANS_COMPLETE_BITS 0x00000008 -#define USB_INTE_TRANS_COMPLETE_MSB 3 -#define USB_INTE_TRANS_COMPLETE_LSB 3 +#define USB_INTE_TRANS_COMPLETE_RESET _u(0x0) +#define USB_INTE_TRANS_COMPLETE_BITS _u(0x00000008) +#define USB_INTE_TRANS_COMPLETE_MSB _u(3) +#define USB_INTE_TRANS_COMPLETE_LSB _u(3) #define USB_INTE_TRANS_COMPLETE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_HOST_SOF // Description : Host: raised every time the host sends a SOF (Start of Frame). // Cleared by reading SOF_RD -#define USB_INTE_HOST_SOF_RESET 0x0 -#define USB_INTE_HOST_SOF_BITS 0x00000004 -#define USB_INTE_HOST_SOF_MSB 2 -#define USB_INTE_HOST_SOF_LSB 2 +#define USB_INTE_HOST_SOF_RESET _u(0x0) +#define USB_INTE_HOST_SOF_BITS _u(0x00000004) +#define USB_INTE_HOST_SOF_MSB _u(2) +#define USB_INTE_HOST_SOF_LSB _u(2) #define USB_INTE_HOST_SOF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_HOST_RESUME // Description : Host: raised when a device wakes up the host. Cleared by // writing to SIE_STATUS.RESUME -#define USB_INTE_HOST_RESUME_RESET 0x0 -#define USB_INTE_HOST_RESUME_BITS 0x00000002 -#define USB_INTE_HOST_RESUME_MSB 1 -#define USB_INTE_HOST_RESUME_LSB 1 +#define USB_INTE_HOST_RESUME_RESET _u(0x0) +#define USB_INTE_HOST_RESUME_BITS _u(0x00000002) +#define USB_INTE_HOST_RESUME_MSB _u(1) +#define USB_INTE_HOST_RESUME_LSB _u(1) #define USB_INTE_HOST_RESUME_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_HOST_CONN_DIS // Description : Host: raised when a device is connected or disconnected (i.e. // when SIE_STATUS.SPEED changes). Cleared by writing to // SIE_STATUS.SPEED -#define USB_INTE_HOST_CONN_DIS_RESET 0x0 -#define USB_INTE_HOST_CONN_DIS_BITS 0x00000001 -#define USB_INTE_HOST_CONN_DIS_MSB 0 -#define USB_INTE_HOST_CONN_DIS_LSB 0 +#define USB_INTE_HOST_CONN_DIS_RESET _u(0x0) +#define USB_INTE_HOST_CONN_DIS_BITS _u(0x00000001) +#define USB_INTE_HOST_CONN_DIS_MSB _u(0) +#define USB_INTE_HOST_CONN_DIS_LSB _u(0) #define USB_INTE_HOST_CONN_DIS_ACCESS "RW" // ============================================================================= // Register : USB_INTF // Description : Interrupt Force -#define USB_INTF_OFFSET 0x00000094 -#define USB_INTF_BITS 0x000fffff -#define USB_INTF_RESET 0x00000000 +#define USB_INTF_OFFSET _u(0x00000094) +#define USB_INTF_BITS _u(0x000fffff) +#define USB_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_INTF_EP_STALL_NAK // Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by // clearing all bits in EP_STATUS_STALL_NAK. -#define USB_INTF_EP_STALL_NAK_RESET 0x0 -#define USB_INTF_EP_STALL_NAK_BITS 0x00080000 -#define USB_INTF_EP_STALL_NAK_MSB 19 -#define USB_INTF_EP_STALL_NAK_LSB 19 +#define USB_INTF_EP_STALL_NAK_RESET _u(0x0) +#define USB_INTF_EP_STALL_NAK_BITS _u(0x00080000) +#define USB_INTF_EP_STALL_NAK_MSB _u(19) +#define USB_INTF_EP_STALL_NAK_LSB _u(19) #define USB_INTF_EP_STALL_NAK_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_ABORT_DONE // Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all // bits in ABORT_DONE. -#define USB_INTF_ABORT_DONE_RESET 0x0 -#define USB_INTF_ABORT_DONE_BITS 0x00040000 -#define USB_INTF_ABORT_DONE_MSB 18 -#define USB_INTF_ABORT_DONE_LSB 18 +#define USB_INTF_ABORT_DONE_RESET _u(0x0) +#define USB_INTF_ABORT_DONE_BITS _u(0x00040000) +#define USB_INTF_ABORT_DONE_MSB _u(18) +#define USB_INTF_ABORT_DONE_LSB _u(18) #define USB_INTF_ABORT_DONE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_DEV_SOF // Description : Set every time the device receives a SOF (Start of Frame) // packet. Cleared by reading SOF_RD -#define USB_INTF_DEV_SOF_RESET 0x0 -#define USB_INTF_DEV_SOF_BITS 0x00020000 -#define USB_INTF_DEV_SOF_MSB 17 -#define USB_INTF_DEV_SOF_LSB 17 +#define USB_INTF_DEV_SOF_RESET _u(0x0) +#define USB_INTF_DEV_SOF_BITS _u(0x00020000) +#define USB_INTF_DEV_SOF_MSB _u(17) +#define USB_INTF_DEV_SOF_LSB _u(17) #define USB_INTF_DEV_SOF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_SETUP_REQ // Description : Device. Source: SIE_STATUS.SETUP_REC -#define USB_INTF_SETUP_REQ_RESET 0x0 -#define USB_INTF_SETUP_REQ_BITS 0x00010000 -#define USB_INTF_SETUP_REQ_MSB 16 -#define USB_INTF_SETUP_REQ_LSB 16 +#define USB_INTF_SETUP_REQ_RESET _u(0x0) +#define USB_INTF_SETUP_REQ_BITS _u(0x00010000) +#define USB_INTF_SETUP_REQ_MSB _u(16) +#define USB_INTF_SETUP_REQ_LSB _u(16) #define USB_INTF_SETUP_REQ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_DEV_RESUME_FROM_HOST // Description : Set when the device receives a resume from the host. Cleared by // writing to SIE_STATUS.RESUME -#define USB_INTF_DEV_RESUME_FROM_HOST_RESET 0x0 -#define USB_INTF_DEV_RESUME_FROM_HOST_BITS 0x00008000 -#define USB_INTF_DEV_RESUME_FROM_HOST_MSB 15 -#define USB_INTF_DEV_RESUME_FROM_HOST_LSB 15 +#define USB_INTF_DEV_RESUME_FROM_HOST_RESET _u(0x0) +#define USB_INTF_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) +#define USB_INTF_DEV_RESUME_FROM_HOST_MSB _u(15) +#define USB_INTF_DEV_RESUME_FROM_HOST_LSB _u(15) #define USB_INTF_DEV_RESUME_FROM_HOST_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_DEV_SUSPEND // Description : Set when the device suspend state changes. Cleared by writing // to SIE_STATUS.SUSPENDED -#define USB_INTF_DEV_SUSPEND_RESET 0x0 -#define USB_INTF_DEV_SUSPEND_BITS 0x00004000 -#define USB_INTF_DEV_SUSPEND_MSB 14 -#define USB_INTF_DEV_SUSPEND_LSB 14 +#define USB_INTF_DEV_SUSPEND_RESET _u(0x0) +#define USB_INTF_DEV_SUSPEND_BITS _u(0x00004000) +#define USB_INTF_DEV_SUSPEND_MSB _u(14) +#define USB_INTF_DEV_SUSPEND_LSB _u(14) #define USB_INTF_DEV_SUSPEND_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_DEV_CONN_DIS // Description : Set when the device connection state changes. Cleared by // writing to SIE_STATUS.CONNECTED -#define USB_INTF_DEV_CONN_DIS_RESET 0x0 -#define USB_INTF_DEV_CONN_DIS_BITS 0x00002000 -#define USB_INTF_DEV_CONN_DIS_MSB 13 -#define USB_INTF_DEV_CONN_DIS_LSB 13 +#define USB_INTF_DEV_CONN_DIS_RESET _u(0x0) +#define USB_INTF_DEV_CONN_DIS_BITS _u(0x00002000) +#define USB_INTF_DEV_CONN_DIS_MSB _u(13) +#define USB_INTF_DEV_CONN_DIS_LSB _u(13) #define USB_INTF_DEV_CONN_DIS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_BUS_RESET // Description : Source: SIE_STATUS.BUS_RESET -#define USB_INTF_BUS_RESET_RESET 0x0 -#define USB_INTF_BUS_RESET_BITS 0x00001000 -#define USB_INTF_BUS_RESET_MSB 12 -#define USB_INTF_BUS_RESET_LSB 12 +#define USB_INTF_BUS_RESET_RESET _u(0x0) +#define USB_INTF_BUS_RESET_BITS _u(0x00001000) +#define USB_INTF_BUS_RESET_MSB _u(12) +#define USB_INTF_BUS_RESET_LSB _u(12) #define USB_INTF_BUS_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECT -#define USB_INTF_VBUS_DETECT_RESET 0x0 -#define USB_INTF_VBUS_DETECT_BITS 0x00000800 -#define USB_INTF_VBUS_DETECT_MSB 11 -#define USB_INTF_VBUS_DETECT_LSB 11 +// Description : Source: SIE_STATUS.VBUS_DETECTED +#define USB_INTF_VBUS_DETECT_RESET _u(0x0) +#define USB_INTF_VBUS_DETECT_BITS _u(0x00000800) +#define USB_INTF_VBUS_DETECT_MSB _u(11) +#define USB_INTF_VBUS_DETECT_LSB _u(11) #define USB_INTF_VBUS_DETECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_STALL // Description : Source: SIE_STATUS.STALL_REC -#define USB_INTF_STALL_RESET 0x0 -#define USB_INTF_STALL_BITS 0x00000400 -#define USB_INTF_STALL_MSB 10 -#define USB_INTF_STALL_LSB 10 +#define USB_INTF_STALL_RESET _u(0x0) +#define USB_INTF_STALL_BITS _u(0x00000400) +#define USB_INTF_STALL_MSB _u(10) +#define USB_INTF_STALL_LSB _u(10) #define USB_INTF_STALL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_ERROR_CRC // Description : Source: SIE_STATUS.CRC_ERROR -#define USB_INTF_ERROR_CRC_RESET 0x0 -#define USB_INTF_ERROR_CRC_BITS 0x00000200 -#define USB_INTF_ERROR_CRC_MSB 9 -#define USB_INTF_ERROR_CRC_LSB 9 +#define USB_INTF_ERROR_CRC_RESET _u(0x0) +#define USB_INTF_ERROR_CRC_BITS _u(0x00000200) +#define USB_INTF_ERROR_CRC_MSB _u(9) +#define USB_INTF_ERROR_CRC_LSB _u(9) #define USB_INTF_ERROR_CRC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_ERROR_BIT_STUFF // Description : Source: SIE_STATUS.BIT_STUFF_ERROR -#define USB_INTF_ERROR_BIT_STUFF_RESET 0x0 -#define USB_INTF_ERROR_BIT_STUFF_BITS 0x00000100 -#define USB_INTF_ERROR_BIT_STUFF_MSB 8 -#define USB_INTF_ERROR_BIT_STUFF_LSB 8 +#define USB_INTF_ERROR_BIT_STUFF_RESET _u(0x0) +#define USB_INTF_ERROR_BIT_STUFF_BITS _u(0x00000100) +#define USB_INTF_ERROR_BIT_STUFF_MSB _u(8) +#define USB_INTF_ERROR_BIT_STUFF_LSB _u(8) #define USB_INTF_ERROR_BIT_STUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_ERROR_RX_OVERFLOW // Description : Source: SIE_STATUS.RX_OVERFLOW -#define USB_INTF_ERROR_RX_OVERFLOW_RESET 0x0 -#define USB_INTF_ERROR_RX_OVERFLOW_BITS 0x00000080 -#define USB_INTF_ERROR_RX_OVERFLOW_MSB 7 -#define USB_INTF_ERROR_RX_OVERFLOW_LSB 7 +#define USB_INTF_ERROR_RX_OVERFLOW_RESET _u(0x0) +#define USB_INTF_ERROR_RX_OVERFLOW_BITS _u(0x00000080) +#define USB_INTF_ERROR_RX_OVERFLOW_MSB _u(7) +#define USB_INTF_ERROR_RX_OVERFLOW_LSB _u(7) #define USB_INTF_ERROR_RX_OVERFLOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_ERROR_RX_TIMEOUT // Description : Source: SIE_STATUS.RX_TIMEOUT -#define USB_INTF_ERROR_RX_TIMEOUT_RESET 0x0 -#define USB_INTF_ERROR_RX_TIMEOUT_BITS 0x00000040 -#define USB_INTF_ERROR_RX_TIMEOUT_MSB 6 -#define USB_INTF_ERROR_RX_TIMEOUT_LSB 6 +#define USB_INTF_ERROR_RX_TIMEOUT_RESET _u(0x0) +#define USB_INTF_ERROR_RX_TIMEOUT_BITS _u(0x00000040) +#define USB_INTF_ERROR_RX_TIMEOUT_MSB _u(6) +#define USB_INTF_ERROR_RX_TIMEOUT_LSB _u(6) #define USB_INTF_ERROR_RX_TIMEOUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_ERROR_DATA_SEQ // Description : Source: SIE_STATUS.DATA_SEQ_ERROR -#define USB_INTF_ERROR_DATA_SEQ_RESET 0x0 -#define USB_INTF_ERROR_DATA_SEQ_BITS 0x00000020 -#define USB_INTF_ERROR_DATA_SEQ_MSB 5 -#define USB_INTF_ERROR_DATA_SEQ_LSB 5 +#define USB_INTF_ERROR_DATA_SEQ_RESET _u(0x0) +#define USB_INTF_ERROR_DATA_SEQ_BITS _u(0x00000020) +#define USB_INTF_ERROR_DATA_SEQ_MSB _u(5) +#define USB_INTF_ERROR_DATA_SEQ_LSB _u(5) #define USB_INTF_ERROR_DATA_SEQ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_BUFF_STATUS // Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing // all bits in BUFF_STATUS. -#define USB_INTF_BUFF_STATUS_RESET 0x0 -#define USB_INTF_BUFF_STATUS_BITS 0x00000010 -#define USB_INTF_BUFF_STATUS_MSB 4 -#define USB_INTF_BUFF_STATUS_LSB 4 +#define USB_INTF_BUFF_STATUS_RESET _u(0x0) +#define USB_INTF_BUFF_STATUS_BITS _u(0x00000010) +#define USB_INTF_BUFF_STATUS_MSB _u(4) +#define USB_INTF_BUFF_STATUS_LSB _u(4) #define USB_INTF_BUFF_STATUS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_TRANS_COMPLETE // Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by // writing to this bit. -#define USB_INTF_TRANS_COMPLETE_RESET 0x0 -#define USB_INTF_TRANS_COMPLETE_BITS 0x00000008 -#define USB_INTF_TRANS_COMPLETE_MSB 3 -#define USB_INTF_TRANS_COMPLETE_LSB 3 +#define USB_INTF_TRANS_COMPLETE_RESET _u(0x0) +#define USB_INTF_TRANS_COMPLETE_BITS _u(0x00000008) +#define USB_INTF_TRANS_COMPLETE_MSB _u(3) +#define USB_INTF_TRANS_COMPLETE_LSB _u(3) #define USB_INTF_TRANS_COMPLETE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_HOST_SOF // Description : Host: raised every time the host sends a SOF (Start of Frame). // Cleared by reading SOF_RD -#define USB_INTF_HOST_SOF_RESET 0x0 -#define USB_INTF_HOST_SOF_BITS 0x00000004 -#define USB_INTF_HOST_SOF_MSB 2 -#define USB_INTF_HOST_SOF_LSB 2 +#define USB_INTF_HOST_SOF_RESET _u(0x0) +#define USB_INTF_HOST_SOF_BITS _u(0x00000004) +#define USB_INTF_HOST_SOF_MSB _u(2) +#define USB_INTF_HOST_SOF_LSB _u(2) #define USB_INTF_HOST_SOF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_HOST_RESUME // Description : Host: raised when a device wakes up the host. Cleared by // writing to SIE_STATUS.RESUME -#define USB_INTF_HOST_RESUME_RESET 0x0 -#define USB_INTF_HOST_RESUME_BITS 0x00000002 -#define USB_INTF_HOST_RESUME_MSB 1 -#define USB_INTF_HOST_RESUME_LSB 1 +#define USB_INTF_HOST_RESUME_RESET _u(0x0) +#define USB_INTF_HOST_RESUME_BITS _u(0x00000002) +#define USB_INTF_HOST_RESUME_MSB _u(1) +#define USB_INTF_HOST_RESUME_LSB _u(1) #define USB_INTF_HOST_RESUME_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_HOST_CONN_DIS // Description : Host: raised when a device is connected or disconnected (i.e. // when SIE_STATUS.SPEED changes). Cleared by writing to // SIE_STATUS.SPEED -#define USB_INTF_HOST_CONN_DIS_RESET 0x0 -#define USB_INTF_HOST_CONN_DIS_BITS 0x00000001 -#define USB_INTF_HOST_CONN_DIS_MSB 0 -#define USB_INTF_HOST_CONN_DIS_LSB 0 +#define USB_INTF_HOST_CONN_DIS_RESET _u(0x0) +#define USB_INTF_HOST_CONN_DIS_BITS _u(0x00000001) +#define USB_INTF_HOST_CONN_DIS_MSB _u(0) +#define USB_INTF_HOST_CONN_DIS_LSB _u(0) #define USB_INTF_HOST_CONN_DIS_ACCESS "RW" // ============================================================================= // Register : USB_INTS // Description : Interrupt status after masking & forcing -#define USB_INTS_OFFSET 0x00000098 -#define USB_INTS_BITS 0x000fffff -#define USB_INTS_RESET 0x00000000 +#define USB_INTS_OFFSET _u(0x00000098) +#define USB_INTS_BITS _u(0x000fffff) +#define USB_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_INTS_EP_STALL_NAK // Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by // clearing all bits in EP_STATUS_STALL_NAK. -#define USB_INTS_EP_STALL_NAK_RESET 0x0 -#define USB_INTS_EP_STALL_NAK_BITS 0x00080000 -#define USB_INTS_EP_STALL_NAK_MSB 19 -#define USB_INTS_EP_STALL_NAK_LSB 19 +#define USB_INTS_EP_STALL_NAK_RESET _u(0x0) +#define USB_INTS_EP_STALL_NAK_BITS _u(0x00080000) +#define USB_INTS_EP_STALL_NAK_MSB _u(19) +#define USB_INTS_EP_STALL_NAK_LSB _u(19) #define USB_INTS_EP_STALL_NAK_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_ABORT_DONE // Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all // bits in ABORT_DONE. -#define USB_INTS_ABORT_DONE_RESET 0x0 -#define USB_INTS_ABORT_DONE_BITS 0x00040000 -#define USB_INTS_ABORT_DONE_MSB 18 -#define USB_INTS_ABORT_DONE_LSB 18 +#define USB_INTS_ABORT_DONE_RESET _u(0x0) +#define USB_INTS_ABORT_DONE_BITS _u(0x00040000) +#define USB_INTS_ABORT_DONE_MSB _u(18) +#define USB_INTS_ABORT_DONE_LSB _u(18) #define USB_INTS_ABORT_DONE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_DEV_SOF // Description : Set every time the device receives a SOF (Start of Frame) // packet. Cleared by reading SOF_RD -#define USB_INTS_DEV_SOF_RESET 0x0 -#define USB_INTS_DEV_SOF_BITS 0x00020000 -#define USB_INTS_DEV_SOF_MSB 17 -#define USB_INTS_DEV_SOF_LSB 17 +#define USB_INTS_DEV_SOF_RESET _u(0x0) +#define USB_INTS_DEV_SOF_BITS _u(0x00020000) +#define USB_INTS_DEV_SOF_MSB _u(17) +#define USB_INTS_DEV_SOF_LSB _u(17) #define USB_INTS_DEV_SOF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_SETUP_REQ // Description : Device. Source: SIE_STATUS.SETUP_REC -#define USB_INTS_SETUP_REQ_RESET 0x0 -#define USB_INTS_SETUP_REQ_BITS 0x00010000 -#define USB_INTS_SETUP_REQ_MSB 16 -#define USB_INTS_SETUP_REQ_LSB 16 +#define USB_INTS_SETUP_REQ_RESET _u(0x0) +#define USB_INTS_SETUP_REQ_BITS _u(0x00010000) +#define USB_INTS_SETUP_REQ_MSB _u(16) +#define USB_INTS_SETUP_REQ_LSB _u(16) #define USB_INTS_SETUP_REQ_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_DEV_RESUME_FROM_HOST // Description : Set when the device receives a resume from the host. Cleared by // writing to SIE_STATUS.RESUME -#define USB_INTS_DEV_RESUME_FROM_HOST_RESET 0x0 -#define USB_INTS_DEV_RESUME_FROM_HOST_BITS 0x00008000 -#define USB_INTS_DEV_RESUME_FROM_HOST_MSB 15 -#define USB_INTS_DEV_RESUME_FROM_HOST_LSB 15 +#define USB_INTS_DEV_RESUME_FROM_HOST_RESET _u(0x0) +#define USB_INTS_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) +#define USB_INTS_DEV_RESUME_FROM_HOST_MSB _u(15) +#define USB_INTS_DEV_RESUME_FROM_HOST_LSB _u(15) #define USB_INTS_DEV_RESUME_FROM_HOST_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_DEV_SUSPEND // Description : Set when the device suspend state changes. Cleared by writing // to SIE_STATUS.SUSPENDED -#define USB_INTS_DEV_SUSPEND_RESET 0x0 -#define USB_INTS_DEV_SUSPEND_BITS 0x00004000 -#define USB_INTS_DEV_SUSPEND_MSB 14 -#define USB_INTS_DEV_SUSPEND_LSB 14 +#define USB_INTS_DEV_SUSPEND_RESET _u(0x0) +#define USB_INTS_DEV_SUSPEND_BITS _u(0x00004000) +#define USB_INTS_DEV_SUSPEND_MSB _u(14) +#define USB_INTS_DEV_SUSPEND_LSB _u(14) #define USB_INTS_DEV_SUSPEND_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_DEV_CONN_DIS // Description : Set when the device connection state changes. Cleared by // writing to SIE_STATUS.CONNECTED -#define USB_INTS_DEV_CONN_DIS_RESET 0x0 -#define USB_INTS_DEV_CONN_DIS_BITS 0x00002000 -#define USB_INTS_DEV_CONN_DIS_MSB 13 -#define USB_INTS_DEV_CONN_DIS_LSB 13 +#define USB_INTS_DEV_CONN_DIS_RESET _u(0x0) +#define USB_INTS_DEV_CONN_DIS_BITS _u(0x00002000) +#define USB_INTS_DEV_CONN_DIS_MSB _u(13) +#define USB_INTS_DEV_CONN_DIS_LSB _u(13) #define USB_INTS_DEV_CONN_DIS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_BUS_RESET // Description : Source: SIE_STATUS.BUS_RESET -#define USB_INTS_BUS_RESET_RESET 0x0 -#define USB_INTS_BUS_RESET_BITS 0x00001000 -#define USB_INTS_BUS_RESET_MSB 12 -#define USB_INTS_BUS_RESET_LSB 12 +#define USB_INTS_BUS_RESET_RESET _u(0x0) +#define USB_INTS_BUS_RESET_BITS _u(0x00001000) +#define USB_INTS_BUS_RESET_MSB _u(12) +#define USB_INTS_BUS_RESET_LSB _u(12) #define USB_INTS_BUS_RESET_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECT -#define USB_INTS_VBUS_DETECT_RESET 0x0 -#define USB_INTS_VBUS_DETECT_BITS 0x00000800 -#define USB_INTS_VBUS_DETECT_MSB 11 -#define USB_INTS_VBUS_DETECT_LSB 11 +// Description : Source: SIE_STATUS.VBUS_DETECTED +#define USB_INTS_VBUS_DETECT_RESET _u(0x0) +#define USB_INTS_VBUS_DETECT_BITS _u(0x00000800) +#define USB_INTS_VBUS_DETECT_MSB _u(11) +#define USB_INTS_VBUS_DETECT_LSB _u(11) #define USB_INTS_VBUS_DETECT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_STALL // Description : Source: SIE_STATUS.STALL_REC -#define USB_INTS_STALL_RESET 0x0 -#define USB_INTS_STALL_BITS 0x00000400 -#define USB_INTS_STALL_MSB 10 -#define USB_INTS_STALL_LSB 10 +#define USB_INTS_STALL_RESET _u(0x0) +#define USB_INTS_STALL_BITS _u(0x00000400) +#define USB_INTS_STALL_MSB _u(10) +#define USB_INTS_STALL_LSB _u(10) #define USB_INTS_STALL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_ERROR_CRC // Description : Source: SIE_STATUS.CRC_ERROR -#define USB_INTS_ERROR_CRC_RESET 0x0 -#define USB_INTS_ERROR_CRC_BITS 0x00000200 -#define USB_INTS_ERROR_CRC_MSB 9 -#define USB_INTS_ERROR_CRC_LSB 9 +#define USB_INTS_ERROR_CRC_RESET _u(0x0) +#define USB_INTS_ERROR_CRC_BITS _u(0x00000200) +#define USB_INTS_ERROR_CRC_MSB _u(9) +#define USB_INTS_ERROR_CRC_LSB _u(9) #define USB_INTS_ERROR_CRC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_ERROR_BIT_STUFF // Description : Source: SIE_STATUS.BIT_STUFF_ERROR -#define USB_INTS_ERROR_BIT_STUFF_RESET 0x0 -#define USB_INTS_ERROR_BIT_STUFF_BITS 0x00000100 -#define USB_INTS_ERROR_BIT_STUFF_MSB 8 -#define USB_INTS_ERROR_BIT_STUFF_LSB 8 +#define USB_INTS_ERROR_BIT_STUFF_RESET _u(0x0) +#define USB_INTS_ERROR_BIT_STUFF_BITS _u(0x00000100) +#define USB_INTS_ERROR_BIT_STUFF_MSB _u(8) +#define USB_INTS_ERROR_BIT_STUFF_LSB _u(8) #define USB_INTS_ERROR_BIT_STUFF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_ERROR_RX_OVERFLOW // Description : Source: SIE_STATUS.RX_OVERFLOW -#define USB_INTS_ERROR_RX_OVERFLOW_RESET 0x0 -#define USB_INTS_ERROR_RX_OVERFLOW_BITS 0x00000080 -#define USB_INTS_ERROR_RX_OVERFLOW_MSB 7 -#define USB_INTS_ERROR_RX_OVERFLOW_LSB 7 +#define USB_INTS_ERROR_RX_OVERFLOW_RESET _u(0x0) +#define USB_INTS_ERROR_RX_OVERFLOW_BITS _u(0x00000080) +#define USB_INTS_ERROR_RX_OVERFLOW_MSB _u(7) +#define USB_INTS_ERROR_RX_OVERFLOW_LSB _u(7) #define USB_INTS_ERROR_RX_OVERFLOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_ERROR_RX_TIMEOUT // Description : Source: SIE_STATUS.RX_TIMEOUT -#define USB_INTS_ERROR_RX_TIMEOUT_RESET 0x0 -#define USB_INTS_ERROR_RX_TIMEOUT_BITS 0x00000040 -#define USB_INTS_ERROR_RX_TIMEOUT_MSB 6 -#define USB_INTS_ERROR_RX_TIMEOUT_LSB 6 +#define USB_INTS_ERROR_RX_TIMEOUT_RESET _u(0x0) +#define USB_INTS_ERROR_RX_TIMEOUT_BITS _u(0x00000040) +#define USB_INTS_ERROR_RX_TIMEOUT_MSB _u(6) +#define USB_INTS_ERROR_RX_TIMEOUT_LSB _u(6) #define USB_INTS_ERROR_RX_TIMEOUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_ERROR_DATA_SEQ // Description : Source: SIE_STATUS.DATA_SEQ_ERROR -#define USB_INTS_ERROR_DATA_SEQ_RESET 0x0 -#define USB_INTS_ERROR_DATA_SEQ_BITS 0x00000020 -#define USB_INTS_ERROR_DATA_SEQ_MSB 5 -#define USB_INTS_ERROR_DATA_SEQ_LSB 5 +#define USB_INTS_ERROR_DATA_SEQ_RESET _u(0x0) +#define USB_INTS_ERROR_DATA_SEQ_BITS _u(0x00000020) +#define USB_INTS_ERROR_DATA_SEQ_MSB _u(5) +#define USB_INTS_ERROR_DATA_SEQ_LSB _u(5) #define USB_INTS_ERROR_DATA_SEQ_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_BUFF_STATUS // Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing // all bits in BUFF_STATUS. -#define USB_INTS_BUFF_STATUS_RESET 0x0 -#define USB_INTS_BUFF_STATUS_BITS 0x00000010 -#define USB_INTS_BUFF_STATUS_MSB 4 -#define USB_INTS_BUFF_STATUS_LSB 4 +#define USB_INTS_BUFF_STATUS_RESET _u(0x0) +#define USB_INTS_BUFF_STATUS_BITS _u(0x00000010) +#define USB_INTS_BUFF_STATUS_MSB _u(4) +#define USB_INTS_BUFF_STATUS_LSB _u(4) #define USB_INTS_BUFF_STATUS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_TRANS_COMPLETE // Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by // writing to this bit. -#define USB_INTS_TRANS_COMPLETE_RESET 0x0 -#define USB_INTS_TRANS_COMPLETE_BITS 0x00000008 -#define USB_INTS_TRANS_COMPLETE_MSB 3 -#define USB_INTS_TRANS_COMPLETE_LSB 3 +#define USB_INTS_TRANS_COMPLETE_RESET _u(0x0) +#define USB_INTS_TRANS_COMPLETE_BITS _u(0x00000008) +#define USB_INTS_TRANS_COMPLETE_MSB _u(3) +#define USB_INTS_TRANS_COMPLETE_LSB _u(3) #define USB_INTS_TRANS_COMPLETE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_HOST_SOF // Description : Host: raised every time the host sends a SOF (Start of Frame). // Cleared by reading SOF_RD -#define USB_INTS_HOST_SOF_RESET 0x0 -#define USB_INTS_HOST_SOF_BITS 0x00000004 -#define USB_INTS_HOST_SOF_MSB 2 -#define USB_INTS_HOST_SOF_LSB 2 +#define USB_INTS_HOST_SOF_RESET _u(0x0) +#define USB_INTS_HOST_SOF_BITS _u(0x00000004) +#define USB_INTS_HOST_SOF_MSB _u(2) +#define USB_INTS_HOST_SOF_LSB _u(2) #define USB_INTS_HOST_SOF_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_HOST_RESUME // Description : Host: raised when a device wakes up the host. Cleared by // writing to SIE_STATUS.RESUME -#define USB_INTS_HOST_RESUME_RESET 0x0 -#define USB_INTS_HOST_RESUME_BITS 0x00000002 -#define USB_INTS_HOST_RESUME_MSB 1 -#define USB_INTS_HOST_RESUME_LSB 1 +#define USB_INTS_HOST_RESUME_RESET _u(0x0) +#define USB_INTS_HOST_RESUME_BITS _u(0x00000002) +#define USB_INTS_HOST_RESUME_MSB _u(1) +#define USB_INTS_HOST_RESUME_LSB _u(1) #define USB_INTS_HOST_RESUME_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_HOST_CONN_DIS // Description : Host: raised when a device is connected or disconnected (i.e. // when SIE_STATUS.SPEED changes). Cleared by writing to // SIE_STATUS.SPEED -#define USB_INTS_HOST_CONN_DIS_RESET 0x0 -#define USB_INTS_HOST_CONN_DIS_BITS 0x00000001 -#define USB_INTS_HOST_CONN_DIS_MSB 0 -#define USB_INTS_HOST_CONN_DIS_LSB 0 +#define USB_INTS_HOST_CONN_DIS_RESET _u(0x0) +#define USB_INTS_HOST_CONN_DIS_BITS _u(0x00000001) +#define USB_INTS_HOST_CONN_DIS_MSB _u(0) +#define USB_INTS_HOST_CONN_DIS_LSB _u(0) #define USB_INTS_HOST_CONN_DIS_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_USB_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h new file mode 100644 index 000000000..fe65ffb1f --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h @@ -0,0 +1,6807 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : USB_DEVICE_DPRAM +// Version : 1 +// Bus type : ahbl +// Description : DPRAM layout for USB device. +// ============================================================================= +#ifndef HARDWARE_REGS_USB_DEVICE_DPRAM_DEFINED +#define HARDWARE_REGS_USB_DEVICE_DPRAM_DEFINED +// ============================================================================= +// Register : USB_DEVICE_DPRAM_SETUP_PACKET_LOW +// Description : Bytes 0-3 of the SETUP packet from the host. +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_OFFSET _u(0x00000000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE +// Description : None +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_BITS _u(0xffff0000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_MSB _u(31) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_LSB _u(16) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST +// Description : None +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_RESET _u(0x00) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_BITS _u(0x0000ff00) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_MSB _u(15) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_LSB _u(8) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE +// Description : None +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_RESET _u(0x00) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_BITS _u(0x000000ff) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_MSB _u(7) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_LSB _u(0) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH +// Description : Bytes 4-7 of the setup packet from the host. +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_OFFSET _u(0x00000004) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH +// Description : None +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_BITS _u(0xffff0000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_MSB _u(31) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_LSB _u(16) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX +// Description : None +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_MSB _u(15) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_LSB _u(0) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP1_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_OFFSET _u(0x00000008) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP1_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_OFFSET _u(0x0000000c) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP2_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_OFFSET _u(0x00000010) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP2_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_OFFSET _u(0x00000014) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP3_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_OFFSET _u(0x00000018) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP3_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_OFFSET _u(0x0000001c) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP4_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_OFFSET _u(0x00000020) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP4_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_OFFSET _u(0x00000024) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP5_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_OFFSET _u(0x00000028) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP5_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_OFFSET _u(0x0000002c) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP6_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_OFFSET _u(0x00000030) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP6_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_OFFSET _u(0x00000034) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP7_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_OFFSET _u(0x00000038) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP7_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_OFFSET _u(0x0000003c) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP8_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_OFFSET _u(0x00000040) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP8_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_OFFSET _u(0x00000044) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP9_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_OFFSET _u(0x00000048) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP9_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_OFFSET _u(0x0000004c) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP10_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_OFFSET _u(0x00000050) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP10_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_OFFSET _u(0x00000054) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP11_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_OFFSET _u(0x00000058) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP11_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_OFFSET _u(0x0000005c) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP12_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_OFFSET _u(0x00000060) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP12_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_OFFSET _u(0x00000064) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP13_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_OFFSET _u(0x00000068) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP13_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_OFFSET _u(0x0000006c) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP14_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_OFFSET _u(0x00000070) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP14_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_OFFSET _u(0x00000074) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP15_IN_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_OFFSET _u(0x00000078) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP15_OUT_CONTROL +// Description : None +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_OFFSET _u(0x0000007c) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE +// Description : 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_OFFSET _u(0x00000080) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_OFFSET _u(0x00000084) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_OFFSET _u(0x00000088) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_OFFSET _u(0x0000008c) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_OFFSET _u(0x00000090) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_OFFSET _u(0x00000094) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_OFFSET _u(0x00000098) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_OFFSET _u(0x0000009c) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_OFFSET _u(0x000000a0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_OFFSET _u(0x000000a4) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_OFFSET _u(0x000000a8) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_OFFSET _u(0x000000ac) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_OFFSET _u(0x000000b0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_OFFSET _u(0x000000b4) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_OFFSET _u(0x000000b8) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_OFFSET _u(0x000000bc) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_OFFSET _u(0x000000c0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_OFFSET _u(0x000000c4) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_OFFSET _u(0x000000c8) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_OFFSET _u(0x000000cc) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_OFFSET _u(0x000000d0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_OFFSET _u(0x000000d4) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS +// ET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_OFFSET _u(0x000000d8) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_OFFSET _u(0x000000dc) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS +// ET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_OFFSET _u(0x000000e0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_OFFSET _u(0x000000e4) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS +// ET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_OFFSET _u(0x000000e8) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_OFFSET _u(0x000000ec) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS +// ET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_OFFSET _u(0x000000f0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_OFFSET _u(0x000000f4) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS +// ET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_OFFSET _u(0x000000f8) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE +// T +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_OFFSET _u(0x000000fc) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS +// ET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_USB_DEVICE_DPRAM_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h index 34ca1ba5c..356ff568a 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h @@ -15,17 +15,17 @@ // ============================================================================= // Register : VREG_AND_CHIP_RESET_VREG // Description : Voltage regulator control and status -#define VREG_AND_CHIP_RESET_VREG_OFFSET 0x00000000 -#define VREG_AND_CHIP_RESET_VREG_BITS 0x000010f3 -#define VREG_AND_CHIP_RESET_VREG_RESET 0x000000b1 +#define VREG_AND_CHIP_RESET_VREG_OFFSET _u(0x00000000) +#define VREG_AND_CHIP_RESET_VREG_BITS _u(0x000010f3) +#define VREG_AND_CHIP_RESET_VREG_RESET _u(0x000000b1) // ----------------------------------------------------------------------------- // Field : VREG_AND_CHIP_RESET_VREG_ROK // Description : regulation status // 0=not in regulation, 1=in regulation -#define VREG_AND_CHIP_RESET_VREG_ROK_RESET 0x0 -#define VREG_AND_CHIP_RESET_VREG_ROK_BITS 0x00001000 -#define VREG_AND_CHIP_RESET_VREG_ROK_MSB 12 -#define VREG_AND_CHIP_RESET_VREG_ROK_LSB 12 +#define VREG_AND_CHIP_RESET_VREG_ROK_RESET _u(0x0) +#define VREG_AND_CHIP_RESET_VREG_ROK_BITS _u(0x00001000) +#define VREG_AND_CHIP_RESET_VREG_ROK_MSB _u(12) +#define VREG_AND_CHIP_RESET_VREG_ROK_LSB _u(12) #define VREG_AND_CHIP_RESET_VREG_ROK_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : VREG_AND_CHIP_RESET_VREG_VSEL @@ -41,35 +41,35 @@ // 1101 - 1.20V // 1110 - 1.25V // 1111 - 1.30V -#define VREG_AND_CHIP_RESET_VREG_VSEL_RESET 0xb -#define VREG_AND_CHIP_RESET_VREG_VSEL_BITS 0x000000f0 -#define VREG_AND_CHIP_RESET_VREG_VSEL_MSB 7 -#define VREG_AND_CHIP_RESET_VREG_VSEL_LSB 4 +#define VREG_AND_CHIP_RESET_VREG_VSEL_RESET _u(0xb) +#define VREG_AND_CHIP_RESET_VREG_VSEL_BITS _u(0x000000f0) +#define VREG_AND_CHIP_RESET_VREG_VSEL_MSB _u(7) +#define VREG_AND_CHIP_RESET_VREG_VSEL_LSB _u(4) #define VREG_AND_CHIP_RESET_VREG_VSEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : VREG_AND_CHIP_RESET_VREG_HIZ // Description : high impedance mode select // 0=not in high impedance mode, 1=in high impedance mode -#define VREG_AND_CHIP_RESET_VREG_HIZ_RESET 0x0 -#define VREG_AND_CHIP_RESET_VREG_HIZ_BITS 0x00000002 -#define VREG_AND_CHIP_RESET_VREG_HIZ_MSB 1 -#define VREG_AND_CHIP_RESET_VREG_HIZ_LSB 1 +#define VREG_AND_CHIP_RESET_VREG_HIZ_RESET _u(0x0) +#define VREG_AND_CHIP_RESET_VREG_HIZ_BITS _u(0x00000002) +#define VREG_AND_CHIP_RESET_VREG_HIZ_MSB _u(1) +#define VREG_AND_CHIP_RESET_VREG_HIZ_LSB _u(1) #define VREG_AND_CHIP_RESET_VREG_HIZ_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : VREG_AND_CHIP_RESET_VREG_EN // Description : enable // 0=not enabled, 1=enabled -#define VREG_AND_CHIP_RESET_VREG_EN_RESET 0x1 -#define VREG_AND_CHIP_RESET_VREG_EN_BITS 0x00000001 -#define VREG_AND_CHIP_RESET_VREG_EN_MSB 0 -#define VREG_AND_CHIP_RESET_VREG_EN_LSB 0 +#define VREG_AND_CHIP_RESET_VREG_EN_RESET _u(0x1) +#define VREG_AND_CHIP_RESET_VREG_EN_BITS _u(0x00000001) +#define VREG_AND_CHIP_RESET_VREG_EN_MSB _u(0) +#define VREG_AND_CHIP_RESET_VREG_EN_LSB _u(0) #define VREG_AND_CHIP_RESET_VREG_EN_ACCESS "RW" // ============================================================================= // Register : VREG_AND_CHIP_RESET_BOD // Description : brown-out detection control -#define VREG_AND_CHIP_RESET_BOD_OFFSET 0x00000004 -#define VREG_AND_CHIP_RESET_BOD_BITS 0x000000f1 -#define VREG_AND_CHIP_RESET_BOD_RESET 0x00000091 +#define VREG_AND_CHIP_RESET_BOD_OFFSET _u(0x00000004) +#define VREG_AND_CHIP_RESET_BOD_BITS _u(0x000000f1) +#define VREG_AND_CHIP_RESET_BOD_RESET _u(0x00000091) // ----------------------------------------------------------------------------- // Field : VREG_AND_CHIP_RESET_BOD_VSEL // Description : threshold select @@ -89,26 +89,26 @@ // 1101 - 1.032V // 1110 - 1.075V // 1111 - 1.118V -#define VREG_AND_CHIP_RESET_BOD_VSEL_RESET 0x9 -#define VREG_AND_CHIP_RESET_BOD_VSEL_BITS 0x000000f0 -#define VREG_AND_CHIP_RESET_BOD_VSEL_MSB 7 -#define VREG_AND_CHIP_RESET_BOD_VSEL_LSB 4 +#define VREG_AND_CHIP_RESET_BOD_VSEL_RESET _u(0x9) +#define VREG_AND_CHIP_RESET_BOD_VSEL_BITS _u(0x000000f0) +#define VREG_AND_CHIP_RESET_BOD_VSEL_MSB _u(7) +#define VREG_AND_CHIP_RESET_BOD_VSEL_LSB _u(4) #define VREG_AND_CHIP_RESET_BOD_VSEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : VREG_AND_CHIP_RESET_BOD_EN // Description : enable // 0=not enabled, 1=enabled -#define VREG_AND_CHIP_RESET_BOD_EN_RESET 0x1 -#define VREG_AND_CHIP_RESET_BOD_EN_BITS 0x00000001 -#define VREG_AND_CHIP_RESET_BOD_EN_MSB 0 -#define VREG_AND_CHIP_RESET_BOD_EN_LSB 0 +#define VREG_AND_CHIP_RESET_BOD_EN_RESET _u(0x1) +#define VREG_AND_CHIP_RESET_BOD_EN_BITS _u(0x00000001) +#define VREG_AND_CHIP_RESET_BOD_EN_MSB _u(0) +#define VREG_AND_CHIP_RESET_BOD_EN_LSB _u(0) #define VREG_AND_CHIP_RESET_BOD_EN_ACCESS "RW" // ============================================================================= // Register : VREG_AND_CHIP_RESET_CHIP_RESET // Description : Chip reset control and status -#define VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET 0x00000008 -#define VREG_AND_CHIP_RESET_CHIP_RESET_BITS 0x01110100 -#define VREG_AND_CHIP_RESET_CHIP_RESET_RESET 0x00000000 +#define VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET _u(0x00000008) +#define VREG_AND_CHIP_RESET_CHIP_RESET_BITS _u(0x01110100) +#define VREG_AND_CHIP_RESET_CHIP_RESET_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG // Description : This is set by psm_restart from the debugger. @@ -117,35 +117,35 @@ // boot lock-up. // In the safe mode the debugger can repair the boot code, clear // this flag then reboot the processor. -#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_RESET 0x0 -#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_BITS 0x01000000 -#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_MSB 24 -#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_LSB 24 +#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_RESET _u(0x0) +#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_BITS _u(0x01000000) +#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_MSB _u(24) +#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_LSB _u(24) #define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART // Description : Last reset was from the debug port -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_RESET 0x0 -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS 0x00100000 -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_MSB 20 -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB 20 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_RESET _u(0x0) +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS _u(0x00100000) +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_MSB _u(20) +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB _u(20) #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN // Description : Last reset was from the RUN pin -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_RESET 0x0 -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS 0x00010000 -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_MSB 16 -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB 16 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_RESET _u(0x0) +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS _u(0x00010000) +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_MSB _u(16) +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB _u(16) #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR // Description : Last reset was from the power-on reset or brown-out detection // blocks -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_RESET 0x0 -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS 0x00000100 -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_MSB 8 -#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB 8 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_RESET _u(0x0) +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS _u(0x00000100) +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_MSB _u(8) +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB _u(8) #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/watchdog.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/watchdog.h index f415c9c25..6a9853d40 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/watchdog.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/watchdog.h @@ -17,210 +17,210 @@ // The rst_wdsel register determines which subsystems are reset // when the watchdog is triggered. // The watchdog can be triggered in software. -#define WATCHDOG_CTRL_OFFSET 0x00000000 -#define WATCHDOG_CTRL_BITS 0xc7ffffff -#define WATCHDOG_CTRL_RESET 0x07000000 +#define WATCHDOG_CTRL_OFFSET _u(0x00000000) +#define WATCHDOG_CTRL_BITS _u(0xc7ffffff) +#define WATCHDOG_CTRL_RESET _u(0x07000000) // ----------------------------------------------------------------------------- // Field : WATCHDOG_CTRL_TRIGGER // Description : Trigger a watchdog reset -#define WATCHDOG_CTRL_TRIGGER_RESET 0x0 -#define WATCHDOG_CTRL_TRIGGER_BITS 0x80000000 -#define WATCHDOG_CTRL_TRIGGER_MSB 31 -#define WATCHDOG_CTRL_TRIGGER_LSB 31 +#define WATCHDOG_CTRL_TRIGGER_RESET _u(0x0) +#define WATCHDOG_CTRL_TRIGGER_BITS _u(0x80000000) +#define WATCHDOG_CTRL_TRIGGER_MSB _u(31) +#define WATCHDOG_CTRL_TRIGGER_LSB _u(31) #define WATCHDOG_CTRL_TRIGGER_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : WATCHDOG_CTRL_ENABLE // Description : When not enabled the watchdog timer is paused -#define WATCHDOG_CTRL_ENABLE_RESET 0x0 -#define WATCHDOG_CTRL_ENABLE_BITS 0x40000000 -#define WATCHDOG_CTRL_ENABLE_MSB 30 -#define WATCHDOG_CTRL_ENABLE_LSB 30 +#define WATCHDOG_CTRL_ENABLE_RESET _u(0x0) +#define WATCHDOG_CTRL_ENABLE_BITS _u(0x40000000) +#define WATCHDOG_CTRL_ENABLE_MSB _u(30) +#define WATCHDOG_CTRL_ENABLE_LSB _u(30) #define WATCHDOG_CTRL_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : WATCHDOG_CTRL_PAUSE_DBG1 // Description : Pause the watchdog timer when processor 1 is in debug mode -#define WATCHDOG_CTRL_PAUSE_DBG1_RESET 0x1 -#define WATCHDOG_CTRL_PAUSE_DBG1_BITS 0x04000000 -#define WATCHDOG_CTRL_PAUSE_DBG1_MSB 26 -#define WATCHDOG_CTRL_PAUSE_DBG1_LSB 26 +#define WATCHDOG_CTRL_PAUSE_DBG1_RESET _u(0x1) +#define WATCHDOG_CTRL_PAUSE_DBG1_BITS _u(0x04000000) +#define WATCHDOG_CTRL_PAUSE_DBG1_MSB _u(26) +#define WATCHDOG_CTRL_PAUSE_DBG1_LSB _u(26) #define WATCHDOG_CTRL_PAUSE_DBG1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : WATCHDOG_CTRL_PAUSE_DBG0 // Description : Pause the watchdog timer when processor 0 is in debug mode -#define WATCHDOG_CTRL_PAUSE_DBG0_RESET 0x1 -#define WATCHDOG_CTRL_PAUSE_DBG0_BITS 0x02000000 -#define WATCHDOG_CTRL_PAUSE_DBG0_MSB 25 -#define WATCHDOG_CTRL_PAUSE_DBG0_LSB 25 +#define WATCHDOG_CTRL_PAUSE_DBG0_RESET _u(0x1) +#define WATCHDOG_CTRL_PAUSE_DBG0_BITS _u(0x02000000) +#define WATCHDOG_CTRL_PAUSE_DBG0_MSB _u(25) +#define WATCHDOG_CTRL_PAUSE_DBG0_LSB _u(25) #define WATCHDOG_CTRL_PAUSE_DBG0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : WATCHDOG_CTRL_PAUSE_JTAG // Description : Pause the watchdog timer when JTAG is accessing the bus fabric -#define WATCHDOG_CTRL_PAUSE_JTAG_RESET 0x1 -#define WATCHDOG_CTRL_PAUSE_JTAG_BITS 0x01000000 -#define WATCHDOG_CTRL_PAUSE_JTAG_MSB 24 -#define WATCHDOG_CTRL_PAUSE_JTAG_LSB 24 +#define WATCHDOG_CTRL_PAUSE_JTAG_RESET _u(0x1) +#define WATCHDOG_CTRL_PAUSE_JTAG_BITS _u(0x01000000) +#define WATCHDOG_CTRL_PAUSE_JTAG_MSB _u(24) +#define WATCHDOG_CTRL_PAUSE_JTAG_LSB _u(24) #define WATCHDOG_CTRL_PAUSE_JTAG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : WATCHDOG_CTRL_TIME // Description : Indicates the number of ticks / 2 (see errata RP2040-E1) before // a watchdog reset will be triggered -#define WATCHDOG_CTRL_TIME_RESET 0x000000 -#define WATCHDOG_CTRL_TIME_BITS 0x00ffffff -#define WATCHDOG_CTRL_TIME_MSB 23 -#define WATCHDOG_CTRL_TIME_LSB 0 +#define WATCHDOG_CTRL_TIME_RESET _u(0x000000) +#define WATCHDOG_CTRL_TIME_BITS _u(0x00ffffff) +#define WATCHDOG_CTRL_TIME_MSB _u(23) +#define WATCHDOG_CTRL_TIME_LSB _u(0) #define WATCHDOG_CTRL_TIME_ACCESS "RO" // ============================================================================= // Register : WATCHDOG_LOAD // Description : Load the watchdog timer. The maximum setting is 0xffffff which // corresponds to 0xffffff / 2 ticks before triggering a watchdog // reset (see errata RP2040-E1). -#define WATCHDOG_LOAD_OFFSET 0x00000004 -#define WATCHDOG_LOAD_BITS 0x00ffffff -#define WATCHDOG_LOAD_RESET 0x00000000 -#define WATCHDOG_LOAD_MSB 23 -#define WATCHDOG_LOAD_LSB 0 +#define WATCHDOG_LOAD_OFFSET _u(0x00000004) +#define WATCHDOG_LOAD_BITS _u(0x00ffffff) +#define WATCHDOG_LOAD_RESET _u(0x00000000) +#define WATCHDOG_LOAD_MSB _u(23) +#define WATCHDOG_LOAD_LSB _u(0) #define WATCHDOG_LOAD_ACCESS "WF" // ============================================================================= // Register : WATCHDOG_REASON // Description : Logs the reason for the last reset. Both bits are zero for the // case of a hardware reset. -#define WATCHDOG_REASON_OFFSET 0x00000008 -#define WATCHDOG_REASON_BITS 0x00000003 -#define WATCHDOG_REASON_RESET 0x00000000 +#define WATCHDOG_REASON_OFFSET _u(0x00000008) +#define WATCHDOG_REASON_BITS _u(0x00000003) +#define WATCHDOG_REASON_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : WATCHDOG_REASON_FORCE // Description : None -#define WATCHDOG_REASON_FORCE_RESET 0x0 -#define WATCHDOG_REASON_FORCE_BITS 0x00000002 -#define WATCHDOG_REASON_FORCE_MSB 1 -#define WATCHDOG_REASON_FORCE_LSB 1 +#define WATCHDOG_REASON_FORCE_RESET _u(0x0) +#define WATCHDOG_REASON_FORCE_BITS _u(0x00000002) +#define WATCHDOG_REASON_FORCE_MSB _u(1) +#define WATCHDOG_REASON_FORCE_LSB _u(1) #define WATCHDOG_REASON_FORCE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : WATCHDOG_REASON_TIMER // Description : None -#define WATCHDOG_REASON_TIMER_RESET 0x0 -#define WATCHDOG_REASON_TIMER_BITS 0x00000001 -#define WATCHDOG_REASON_TIMER_MSB 0 -#define WATCHDOG_REASON_TIMER_LSB 0 +#define WATCHDOG_REASON_TIMER_RESET _u(0x0) +#define WATCHDOG_REASON_TIMER_BITS _u(0x00000001) +#define WATCHDOG_REASON_TIMER_MSB _u(0) +#define WATCHDOG_REASON_TIMER_LSB _u(0) #define WATCHDOG_REASON_TIMER_ACCESS "RO" // ============================================================================= // Register : WATCHDOG_SCRATCH0 // Description : Scratch register. Information persists through soft reset of // the chip. -#define WATCHDOG_SCRATCH0_OFFSET 0x0000000c -#define WATCHDOG_SCRATCH0_BITS 0xffffffff -#define WATCHDOG_SCRATCH0_RESET 0x00000000 -#define WATCHDOG_SCRATCH0_MSB 31 -#define WATCHDOG_SCRATCH0_LSB 0 +#define WATCHDOG_SCRATCH0_OFFSET _u(0x0000000c) +#define WATCHDOG_SCRATCH0_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH0_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH0_MSB _u(31) +#define WATCHDOG_SCRATCH0_LSB _u(0) #define WATCHDOG_SCRATCH0_ACCESS "RW" // ============================================================================= // Register : WATCHDOG_SCRATCH1 // Description : Scratch register. Information persists through soft reset of // the chip. -#define WATCHDOG_SCRATCH1_OFFSET 0x00000010 -#define WATCHDOG_SCRATCH1_BITS 0xffffffff -#define WATCHDOG_SCRATCH1_RESET 0x00000000 -#define WATCHDOG_SCRATCH1_MSB 31 -#define WATCHDOG_SCRATCH1_LSB 0 +#define WATCHDOG_SCRATCH1_OFFSET _u(0x00000010) +#define WATCHDOG_SCRATCH1_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH1_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH1_MSB _u(31) +#define WATCHDOG_SCRATCH1_LSB _u(0) #define WATCHDOG_SCRATCH1_ACCESS "RW" // ============================================================================= // Register : WATCHDOG_SCRATCH2 // Description : Scratch register. Information persists through soft reset of // the chip. -#define WATCHDOG_SCRATCH2_OFFSET 0x00000014 -#define WATCHDOG_SCRATCH2_BITS 0xffffffff -#define WATCHDOG_SCRATCH2_RESET 0x00000000 -#define WATCHDOG_SCRATCH2_MSB 31 -#define WATCHDOG_SCRATCH2_LSB 0 +#define WATCHDOG_SCRATCH2_OFFSET _u(0x00000014) +#define WATCHDOG_SCRATCH2_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH2_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH2_MSB _u(31) +#define WATCHDOG_SCRATCH2_LSB _u(0) #define WATCHDOG_SCRATCH2_ACCESS "RW" // ============================================================================= // Register : WATCHDOG_SCRATCH3 // Description : Scratch register. Information persists through soft reset of // the chip. -#define WATCHDOG_SCRATCH3_OFFSET 0x00000018 -#define WATCHDOG_SCRATCH3_BITS 0xffffffff -#define WATCHDOG_SCRATCH3_RESET 0x00000000 -#define WATCHDOG_SCRATCH3_MSB 31 -#define WATCHDOG_SCRATCH3_LSB 0 +#define WATCHDOG_SCRATCH3_OFFSET _u(0x00000018) +#define WATCHDOG_SCRATCH3_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH3_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH3_MSB _u(31) +#define WATCHDOG_SCRATCH3_LSB _u(0) #define WATCHDOG_SCRATCH3_ACCESS "RW" // ============================================================================= // Register : WATCHDOG_SCRATCH4 // Description : Scratch register. Information persists through soft reset of // the chip. -#define WATCHDOG_SCRATCH4_OFFSET 0x0000001c -#define WATCHDOG_SCRATCH4_BITS 0xffffffff -#define WATCHDOG_SCRATCH4_RESET 0x00000000 -#define WATCHDOG_SCRATCH4_MSB 31 -#define WATCHDOG_SCRATCH4_LSB 0 +#define WATCHDOG_SCRATCH4_OFFSET _u(0x0000001c) +#define WATCHDOG_SCRATCH4_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH4_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH4_MSB _u(31) +#define WATCHDOG_SCRATCH4_LSB _u(0) #define WATCHDOG_SCRATCH4_ACCESS "RW" // ============================================================================= // Register : WATCHDOG_SCRATCH5 // Description : Scratch register. Information persists through soft reset of // the chip. -#define WATCHDOG_SCRATCH5_OFFSET 0x00000020 -#define WATCHDOG_SCRATCH5_BITS 0xffffffff -#define WATCHDOG_SCRATCH5_RESET 0x00000000 -#define WATCHDOG_SCRATCH5_MSB 31 -#define WATCHDOG_SCRATCH5_LSB 0 +#define WATCHDOG_SCRATCH5_OFFSET _u(0x00000020) +#define WATCHDOG_SCRATCH5_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH5_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH5_MSB _u(31) +#define WATCHDOG_SCRATCH5_LSB _u(0) #define WATCHDOG_SCRATCH5_ACCESS "RW" // ============================================================================= // Register : WATCHDOG_SCRATCH6 // Description : Scratch register. Information persists through soft reset of // the chip. -#define WATCHDOG_SCRATCH6_OFFSET 0x00000024 -#define WATCHDOG_SCRATCH6_BITS 0xffffffff -#define WATCHDOG_SCRATCH6_RESET 0x00000000 -#define WATCHDOG_SCRATCH6_MSB 31 -#define WATCHDOG_SCRATCH6_LSB 0 +#define WATCHDOG_SCRATCH6_OFFSET _u(0x00000024) +#define WATCHDOG_SCRATCH6_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH6_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH6_MSB _u(31) +#define WATCHDOG_SCRATCH6_LSB _u(0) #define WATCHDOG_SCRATCH6_ACCESS "RW" // ============================================================================= // Register : WATCHDOG_SCRATCH7 // Description : Scratch register. Information persists through soft reset of // the chip. -#define WATCHDOG_SCRATCH7_OFFSET 0x00000028 -#define WATCHDOG_SCRATCH7_BITS 0xffffffff -#define WATCHDOG_SCRATCH7_RESET 0x00000000 -#define WATCHDOG_SCRATCH7_MSB 31 -#define WATCHDOG_SCRATCH7_LSB 0 +#define WATCHDOG_SCRATCH7_OFFSET _u(0x00000028) +#define WATCHDOG_SCRATCH7_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH7_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH7_MSB _u(31) +#define WATCHDOG_SCRATCH7_LSB _u(0) #define WATCHDOG_SCRATCH7_ACCESS "RW" // ============================================================================= // Register : WATCHDOG_TICK // Description : Controls the tick generator -#define WATCHDOG_TICK_OFFSET 0x0000002c -#define WATCHDOG_TICK_BITS 0x000fffff -#define WATCHDOG_TICK_RESET 0x00000200 +#define WATCHDOG_TICK_OFFSET _u(0x0000002c) +#define WATCHDOG_TICK_BITS _u(0x000fffff) +#define WATCHDOG_TICK_RESET _u(0x00000200) // ----------------------------------------------------------------------------- // Field : WATCHDOG_TICK_COUNT // Description : Count down timer: the remaining number clk_tick cycles before // the next tick is generated. #define WATCHDOG_TICK_COUNT_RESET "-" -#define WATCHDOG_TICK_COUNT_BITS 0x000ff800 -#define WATCHDOG_TICK_COUNT_MSB 19 -#define WATCHDOG_TICK_COUNT_LSB 11 +#define WATCHDOG_TICK_COUNT_BITS _u(0x000ff800) +#define WATCHDOG_TICK_COUNT_MSB _u(19) +#define WATCHDOG_TICK_COUNT_LSB _u(11) #define WATCHDOG_TICK_COUNT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : WATCHDOG_TICK_RUNNING // Description : Is the tick generator running? #define WATCHDOG_TICK_RUNNING_RESET "-" -#define WATCHDOG_TICK_RUNNING_BITS 0x00000400 -#define WATCHDOG_TICK_RUNNING_MSB 10 -#define WATCHDOG_TICK_RUNNING_LSB 10 +#define WATCHDOG_TICK_RUNNING_BITS _u(0x00000400) +#define WATCHDOG_TICK_RUNNING_MSB _u(10) +#define WATCHDOG_TICK_RUNNING_LSB _u(10) #define WATCHDOG_TICK_RUNNING_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : WATCHDOG_TICK_ENABLE // Description : start / stop tick generation -#define WATCHDOG_TICK_ENABLE_RESET 0x1 -#define WATCHDOG_TICK_ENABLE_BITS 0x00000200 -#define WATCHDOG_TICK_ENABLE_MSB 9 -#define WATCHDOG_TICK_ENABLE_LSB 9 +#define WATCHDOG_TICK_ENABLE_RESET _u(0x1) +#define WATCHDOG_TICK_ENABLE_BITS _u(0x00000200) +#define WATCHDOG_TICK_ENABLE_MSB _u(9) +#define WATCHDOG_TICK_ENABLE_LSB _u(9) #define WATCHDOG_TICK_ENABLE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : WATCHDOG_TICK_CYCLES // Description : Total number of clk_tick cycles before the next tick. -#define WATCHDOG_TICK_CYCLES_RESET 0x000 -#define WATCHDOG_TICK_CYCLES_BITS 0x000001ff -#define WATCHDOG_TICK_CYCLES_MSB 8 -#define WATCHDOG_TICK_CYCLES_LSB 0 +#define WATCHDOG_TICK_CYCLES_RESET _u(0x000) +#define WATCHDOG_TICK_CYCLES_BITS _u(0x000001ff) +#define WATCHDOG_TICK_CYCLES_MSB _u(8) +#define WATCHDOG_TICK_CYCLES_LSB _u(0) #define WATCHDOG_TICK_CYCLES_ACCESS "RW" // ============================================================================= #endif // HARDWARE_REGS_WATCHDOG_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xip.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xip.h index 59487e460..3964f6745 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xip.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xip.h @@ -14,9 +14,9 @@ // ============================================================================= // Register : XIP_CTRL // Description : Cache control -#define XIP_CTRL_OFFSET 0x00000000 -#define XIP_CTRL_BITS 0x0000000b -#define XIP_CTRL_RESET 0x00000003 +#define XIP_CTRL_OFFSET _u(0x00000000) +#define XIP_CTRL_BITS _u(0x0000000b) +#define XIP_CTRL_RESET _u(0x00000003) // ----------------------------------------------------------------------------- // Field : XIP_CTRL_POWER_DOWN // Description : When 1, the cache memories are powered down. They retain state, @@ -26,10 +26,10 @@ // be enabled when powered down. // Cache-as-SRAM accesses will produce a bus error response when // the cache is powered down. -#define XIP_CTRL_POWER_DOWN_RESET 0x0 -#define XIP_CTRL_POWER_DOWN_BITS 0x00000008 -#define XIP_CTRL_POWER_DOWN_MSB 3 -#define XIP_CTRL_POWER_DOWN_LSB 3 +#define XIP_CTRL_POWER_DOWN_RESET _u(0x0) +#define XIP_CTRL_POWER_DOWN_BITS _u(0x00000008) +#define XIP_CTRL_POWER_DOWN_MSB _u(3) +#define XIP_CTRL_POWER_DOWN_LSB _u(3) #define XIP_CTRL_POWER_DOWN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : XIP_CTRL_ERR_BADWRITE @@ -40,10 +40,10 @@ // In either case, writes to the 0x0 alias will deallocate on tag // match, // as usual. -#define XIP_CTRL_ERR_BADWRITE_RESET 0x1 -#define XIP_CTRL_ERR_BADWRITE_BITS 0x00000002 -#define XIP_CTRL_ERR_BADWRITE_MSB 1 -#define XIP_CTRL_ERR_BADWRITE_LSB 1 +#define XIP_CTRL_ERR_BADWRITE_RESET _u(0x1) +#define XIP_CTRL_ERR_BADWRITE_BITS _u(0x00000002) +#define XIP_CTRL_ERR_BADWRITE_MSB _u(1) +#define XIP_CTRL_ERR_BADWRITE_LSB _u(1) #define XIP_CTRL_ERR_BADWRITE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : XIP_CTRL_EN @@ -57,10 +57,10 @@ // If the cache is enabled, cache-as-SRAM accesses have no effect // on the // cache data RAM, and will produce a bus error response. -#define XIP_CTRL_EN_RESET 0x1 -#define XIP_CTRL_EN_BITS 0x00000001 -#define XIP_CTRL_EN_MSB 0 -#define XIP_CTRL_EN_LSB 0 +#define XIP_CTRL_EN_RESET _u(0x1) +#define XIP_CTRL_EN_BITS _u(0x00000001) +#define XIP_CTRL_EN_MSB _u(0) +#define XIP_CTRL_EN_LSB _u(0) #define XIP_CTRL_EN_ACCESS "RW" // ============================================================================= // Register : XIP_FLUSH @@ -70,45 +70,45 @@ // contents is not affected by flush or reset.) // Reading will hold the bus (stall the processor) until the flush // completes. Alternatively STAT can be polled until completion. -#define XIP_FLUSH_OFFSET 0x00000004 -#define XIP_FLUSH_BITS 0x00000001 -#define XIP_FLUSH_RESET 0x00000000 -#define XIP_FLUSH_MSB 0 -#define XIP_FLUSH_LSB 0 +#define XIP_FLUSH_OFFSET _u(0x00000004) +#define XIP_FLUSH_BITS _u(0x00000001) +#define XIP_FLUSH_RESET _u(0x00000000) +#define XIP_FLUSH_MSB _u(0) +#define XIP_FLUSH_LSB _u(0) #define XIP_FLUSH_ACCESS "SC" // ============================================================================= // Register : XIP_STAT // Description : Cache Status -#define XIP_STAT_OFFSET 0x00000008 -#define XIP_STAT_BITS 0x00000007 -#define XIP_STAT_RESET 0x00000002 +#define XIP_STAT_OFFSET _u(0x00000008) +#define XIP_STAT_BITS _u(0x00000007) +#define XIP_STAT_RESET _u(0x00000002) // ----------------------------------------------------------------------------- // Field : XIP_STAT_FIFO_FULL // Description : When 1, indicates the XIP streaming FIFO is completely full. // The streaming FIFO is 2 entries deep, so the full and empty // flag allow its level to be ascertained. -#define XIP_STAT_FIFO_FULL_RESET 0x0 -#define XIP_STAT_FIFO_FULL_BITS 0x00000004 -#define XIP_STAT_FIFO_FULL_MSB 2 -#define XIP_STAT_FIFO_FULL_LSB 2 +#define XIP_STAT_FIFO_FULL_RESET _u(0x0) +#define XIP_STAT_FIFO_FULL_BITS _u(0x00000004) +#define XIP_STAT_FIFO_FULL_MSB _u(2) +#define XIP_STAT_FIFO_FULL_LSB _u(2) #define XIP_STAT_FIFO_FULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : XIP_STAT_FIFO_EMPTY // Description : When 1, indicates the XIP streaming FIFO is completely empty. -#define XIP_STAT_FIFO_EMPTY_RESET 0x1 -#define XIP_STAT_FIFO_EMPTY_BITS 0x00000002 -#define XIP_STAT_FIFO_EMPTY_MSB 1 -#define XIP_STAT_FIFO_EMPTY_LSB 1 +#define XIP_STAT_FIFO_EMPTY_RESET _u(0x1) +#define XIP_STAT_FIFO_EMPTY_BITS _u(0x00000002) +#define XIP_STAT_FIFO_EMPTY_MSB _u(1) +#define XIP_STAT_FIFO_EMPTY_LSB _u(1) #define XIP_STAT_FIFO_EMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : XIP_STAT_FLUSH_READY // Description : Reads as 0 while a cache flush is in progress, and 1 otherwise. // The cache is flushed whenever the XIP block is reset, and also // when requested via the FLUSH register. -#define XIP_STAT_FLUSH_READY_RESET 0x0 -#define XIP_STAT_FLUSH_READY_BITS 0x00000001 -#define XIP_STAT_FLUSH_READY_MSB 0 -#define XIP_STAT_FLUSH_READY_LSB 0 +#define XIP_STAT_FLUSH_READY_RESET _u(0x0) +#define XIP_STAT_FLUSH_READY_BITS _u(0x00000001) +#define XIP_STAT_FLUSH_READY_MSB _u(0) +#define XIP_STAT_FLUSH_READY_LSB _u(0) #define XIP_STAT_FLUSH_READY_ACCESS "RO" // ============================================================================= // Register : XIP_CTR_HIT @@ -117,11 +117,11 @@ // hit, // i.e. when an XIP access is serviced directly from cached data. // Write any value to clear. -#define XIP_CTR_HIT_OFFSET 0x0000000c -#define XIP_CTR_HIT_BITS 0xffffffff -#define XIP_CTR_HIT_RESET 0x00000000 -#define XIP_CTR_HIT_MSB 31 -#define XIP_CTR_HIT_LSB 0 +#define XIP_CTR_HIT_OFFSET _u(0x0000000c) +#define XIP_CTR_HIT_BITS _u(0xffffffff) +#define XIP_CTR_HIT_RESET _u(0x00000000) +#define XIP_CTR_HIT_MSB _u(31) +#define XIP_CTR_HIT_LSB _u(0) #define XIP_CTR_HIT_ACCESS "WC" // ============================================================================= // Register : XIP_CTR_ACC @@ -131,11 +131,11 @@ // whether the cache is hit or not. This includes noncacheable // accesses. // Write any value to clear. -#define XIP_CTR_ACC_OFFSET 0x00000010 -#define XIP_CTR_ACC_BITS 0xffffffff -#define XIP_CTR_ACC_RESET 0x00000000 -#define XIP_CTR_ACC_MSB 31 -#define XIP_CTR_ACC_LSB 0 +#define XIP_CTR_ACC_OFFSET _u(0x00000010) +#define XIP_CTR_ACC_BITS _u(0xffffffff) +#define XIP_CTR_ACC_RESET _u(0x00000000) +#define XIP_CTR_ACC_MSB _u(31) +#define XIP_CTR_ACC_LSB _u(0) #define XIP_CTR_ACC_ACCESS "WC" // ============================================================================= // Register : XIP_STREAM_ADDR @@ -145,11 +145,11 @@ // Increments automatically after each flash access. // Write the initial access address here before starting a // streaming read. -#define XIP_STREAM_ADDR_OFFSET 0x00000014 -#define XIP_STREAM_ADDR_BITS 0xfffffffc -#define XIP_STREAM_ADDR_RESET 0x00000000 -#define XIP_STREAM_ADDR_MSB 31 -#define XIP_STREAM_ADDR_LSB 2 +#define XIP_STREAM_ADDR_OFFSET _u(0x00000014) +#define XIP_STREAM_ADDR_BITS _u(0xfffffffc) +#define XIP_STREAM_ADDR_RESET _u(0x00000000) +#define XIP_STREAM_ADDR_MSB _u(31) +#define XIP_STREAM_ADDR_LSB _u(2) #define XIP_STREAM_ADDR_ACCESS "RW" // ============================================================================= // Register : XIP_STREAM_CTR @@ -163,11 +163,11 @@ // in-flight // read, so that a new stream can immediately be started (after // draining the FIFO and reinitialising STREAM_ADDR) -#define XIP_STREAM_CTR_OFFSET 0x00000018 -#define XIP_STREAM_CTR_BITS 0x003fffff -#define XIP_STREAM_CTR_RESET 0x00000000 -#define XIP_STREAM_CTR_MSB 21 -#define XIP_STREAM_CTR_LSB 0 +#define XIP_STREAM_CTR_OFFSET _u(0x00000018) +#define XIP_STREAM_CTR_BITS _u(0x003fffff) +#define XIP_STREAM_CTR_RESET _u(0x00000000) +#define XIP_STREAM_CTR_MSB _u(21) +#define XIP_STREAM_CTR_LSB _u(0) #define XIP_STREAM_CTR_ACCESS "RW" // ============================================================================= // Register : XIP_STREAM_FIFO @@ -177,11 +177,11 @@ // This FIFO can also be accessed via the XIP_AUX slave, to avoid // exposing // the DMA to bus stalls caused by other XIP traffic. -#define XIP_STREAM_FIFO_OFFSET 0x0000001c -#define XIP_STREAM_FIFO_BITS 0xffffffff -#define XIP_STREAM_FIFO_RESET 0x00000000 -#define XIP_STREAM_FIFO_MSB 31 -#define XIP_STREAM_FIFO_LSB 0 +#define XIP_STREAM_FIFO_OFFSET _u(0x0000001c) +#define XIP_STREAM_FIFO_BITS _u(0xffffffff) +#define XIP_STREAM_FIFO_RESET _u(0x00000000) +#define XIP_STREAM_FIFO_MSB _u(31) +#define XIP_STREAM_FIFO_LSB _u(0) #define XIP_STREAM_FIFO_ACCESS "RF" // ============================================================================= #endif // HARDWARE_REGS_XIP_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xosc.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xosc.h index 89d036b86..ec84d3d90 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xosc.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_regs/include/hardware/regs/xosc.h @@ -14,9 +14,9 @@ // ============================================================================= // Register : XOSC_CTRL // Description : Crystal Oscillator Control -#define XOSC_CTRL_OFFSET 0x00000000 -#define XOSC_CTRL_BITS 0x00ffffff -#define XOSC_CTRL_RESET 0x00000000 +#define XOSC_CTRL_OFFSET _u(0x00000000) +#define XOSC_CTRL_BITS _u(0x00ffffff) +#define XOSC_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : XOSC_CTRL_ENABLE // Description : On power-up this field is initialised to DISABLE and the chip @@ -31,12 +31,12 @@ // 0xd1e -> DISABLE // 0xfab -> ENABLE #define XOSC_CTRL_ENABLE_RESET "-" -#define XOSC_CTRL_ENABLE_BITS 0x00fff000 -#define XOSC_CTRL_ENABLE_MSB 23 -#define XOSC_CTRL_ENABLE_LSB 12 +#define XOSC_CTRL_ENABLE_BITS _u(0x00fff000) +#define XOSC_CTRL_ENABLE_MSB _u(23) +#define XOSC_CTRL_ENABLE_LSB _u(12) #define XOSC_CTRL_ENABLE_ACCESS "RW" -#define XOSC_CTRL_ENABLE_VALUE_DISABLE 0xd1e -#define XOSC_CTRL_ENABLE_VALUE_ENABLE 0xfab +#define XOSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e) +#define XOSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab) // ----------------------------------------------------------------------------- // Field : XOSC_CTRL_FREQ_RANGE // Description : Frequency range. This resets to 0xAA0 and cannot be changed. @@ -45,45 +45,45 @@ // 0xaa2 -> RESERVED_2 // 0xaa3 -> RESERVED_3 #define XOSC_CTRL_FREQ_RANGE_RESET "-" -#define XOSC_CTRL_FREQ_RANGE_BITS 0x00000fff -#define XOSC_CTRL_FREQ_RANGE_MSB 11 -#define XOSC_CTRL_FREQ_RANGE_LSB 0 +#define XOSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff) +#define XOSC_CTRL_FREQ_RANGE_MSB _u(11) +#define XOSC_CTRL_FREQ_RANGE_LSB _u(0) #define XOSC_CTRL_FREQ_RANGE_ACCESS "RW" -#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ 0xaa0 -#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_1 0xaa1 -#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_2 0xaa2 -#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_3 0xaa3 +#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ _u(0xaa0) +#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_1 _u(0xaa1) +#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_2 _u(0xaa2) +#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_3 _u(0xaa3) // ============================================================================= // Register : XOSC_STATUS // Description : Crystal Oscillator Status -#define XOSC_STATUS_OFFSET 0x00000004 -#define XOSC_STATUS_BITS 0x81001003 -#define XOSC_STATUS_RESET 0x00000000 +#define XOSC_STATUS_OFFSET _u(0x00000004) +#define XOSC_STATUS_BITS _u(0x81001003) +#define XOSC_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : XOSC_STATUS_STABLE // Description : Oscillator is running and stable -#define XOSC_STATUS_STABLE_RESET 0x0 -#define XOSC_STATUS_STABLE_BITS 0x80000000 -#define XOSC_STATUS_STABLE_MSB 31 -#define XOSC_STATUS_STABLE_LSB 31 +#define XOSC_STATUS_STABLE_RESET _u(0x0) +#define XOSC_STATUS_STABLE_BITS _u(0x80000000) +#define XOSC_STATUS_STABLE_MSB _u(31) +#define XOSC_STATUS_STABLE_LSB _u(31) #define XOSC_STATUS_STABLE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : XOSC_STATUS_BADWRITE // Description : An invalid value has been written to CTRL_ENABLE or // CTRL_FREQ_RANGE or DORMANT -#define XOSC_STATUS_BADWRITE_RESET 0x0 -#define XOSC_STATUS_BADWRITE_BITS 0x01000000 -#define XOSC_STATUS_BADWRITE_MSB 24 -#define XOSC_STATUS_BADWRITE_LSB 24 +#define XOSC_STATUS_BADWRITE_RESET _u(0x0) +#define XOSC_STATUS_BADWRITE_BITS _u(0x01000000) +#define XOSC_STATUS_BADWRITE_MSB _u(24) +#define XOSC_STATUS_BADWRITE_LSB _u(24) #define XOSC_STATUS_BADWRITE_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : XOSC_STATUS_ENABLED // Description : Oscillator is enabled but not necessarily running and stable, // resets to 0 #define XOSC_STATUS_ENABLED_RESET "-" -#define XOSC_STATUS_ENABLED_BITS 0x00001000 -#define XOSC_STATUS_ENABLED_MSB 12 -#define XOSC_STATUS_ENABLED_LSB 12 +#define XOSC_STATUS_ENABLED_BITS _u(0x00001000) +#define XOSC_STATUS_ENABLED_MSB _u(12) +#define XOSC_STATUS_ENABLED_LSB _u(12) #define XOSC_STATUS_ENABLED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : XOSC_STATUS_FREQ_RANGE @@ -93,14 +93,14 @@ // 0x2 -> RESERVED_2 // 0x3 -> RESERVED_3 #define XOSC_STATUS_FREQ_RANGE_RESET "-" -#define XOSC_STATUS_FREQ_RANGE_BITS 0x00000003 -#define XOSC_STATUS_FREQ_RANGE_MSB 1 -#define XOSC_STATUS_FREQ_RANGE_LSB 0 +#define XOSC_STATUS_FREQ_RANGE_BITS _u(0x00000003) +#define XOSC_STATUS_FREQ_RANGE_MSB _u(1) +#define XOSC_STATUS_FREQ_RANGE_LSB _u(0) #define XOSC_STATUS_FREQ_RANGE_ACCESS "RO" -#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ 0x0 -#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_1 0x1 -#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_2 0x2 -#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_3 0x3 +#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ _u(0x0) +#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_1 _u(0x1) +#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_2 _u(0x2) +#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_3 _u(0x3) // ============================================================================= // Register : XOSC_DORMANT // Description : Crystal Oscillator pause control @@ -111,36 +111,37 @@ // WARNING: setup the irq before selecting dormant mode // 0x636f6d61 -> DORMANT // 0x77616b65 -> WAKE -#define XOSC_DORMANT_OFFSET 0x00000008 -#define XOSC_DORMANT_BITS 0xffffffff +#define XOSC_DORMANT_OFFSET _u(0x00000008) +#define XOSC_DORMANT_BITS _u(0xffffffff) #define XOSC_DORMANT_RESET "-" -#define XOSC_DORMANT_MSB 31 -#define XOSC_DORMANT_LSB 0 +#define XOSC_DORMANT_MSB _u(31) +#define XOSC_DORMANT_LSB _u(0) #define XOSC_DORMANT_ACCESS "RW" -#define XOSC_DORMANT_VALUE_DORMANT 0x636f6d61 -#define XOSC_DORMANT_VALUE_WAKE 0x77616b65 +#define XOSC_DORMANT_VALUE_DORMANT _u(0x636f6d61) +#define XOSC_DORMANT_VALUE_WAKE _u(0x77616b65) // ============================================================================= // Register : XOSC_STARTUP // Description : Controls the startup delay -#define XOSC_STARTUP_OFFSET 0x0000000c -#define XOSC_STARTUP_BITS 0x00103fff -#define XOSC_STARTUP_RESET 0x00000000 +#define XOSC_STARTUP_OFFSET _u(0x0000000c) +#define XOSC_STARTUP_BITS _u(0x00103fff) +#define XOSC_STARTUP_RESET _u(0x000000c4) // ----------------------------------------------------------------------------- // Field : XOSC_STARTUP_X4 // Description : Multiplies the startup_delay by 4. This is of little value to -// the user given that the delay can be programmed directly -#define XOSC_STARTUP_X4_RESET "-" -#define XOSC_STARTUP_X4_BITS 0x00100000 -#define XOSC_STARTUP_X4_MSB 20 -#define XOSC_STARTUP_X4_LSB 20 +// the user given that the delay can be programmed directly. +#define XOSC_STARTUP_X4_RESET _u(0x0) +#define XOSC_STARTUP_X4_BITS _u(0x00100000) +#define XOSC_STARTUP_X4_MSB _u(20) +#define XOSC_STARTUP_X4_LSB _u(20) #define XOSC_STARTUP_X4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : XOSC_STARTUP_DELAY -// Description : in multiples of 256*xtal_period -#define XOSC_STARTUP_DELAY_RESET "-" -#define XOSC_STARTUP_DELAY_BITS 0x00003fff -#define XOSC_STARTUP_DELAY_MSB 13 -#define XOSC_STARTUP_DELAY_LSB 0 +// Description : in multiples of 256*xtal_period. The reset value of 0xc4 +// corresponds to approx 50 000 cycles. +#define XOSC_STARTUP_DELAY_RESET _u(0x00c4) +#define XOSC_STARTUP_DELAY_BITS _u(0x00003fff) +#define XOSC_STARTUP_DELAY_MSB _u(13) +#define XOSC_STARTUP_DELAY_LSB _u(0) #define XOSC_STARTUP_DELAY_ACCESS "RW" // ============================================================================= // Register : XOSC_COUNT @@ -149,11 +150,11 @@ // To start the counter write a non-zero value. // Can be used for short software pauses when setting up time // sensitive hardware. -#define XOSC_COUNT_OFFSET 0x0000001c -#define XOSC_COUNT_BITS 0x000000ff -#define XOSC_COUNT_RESET 0x00000000 -#define XOSC_COUNT_MSB 7 -#define XOSC_COUNT_LSB 0 +#define XOSC_COUNT_OFFSET _u(0x0000001c) +#define XOSC_COUNT_BITS _u(0x000000ff) +#define XOSC_COUNT_RESET _u(0x00000000) +#define XOSC_COUNT_MSB _u(7) +#define XOSC_COUNT_LSB _u(0) #define XOSC_COUNT_ACCESS "RW" // ============================================================================= #endif // HARDWARE_REGS_XOSC_DEFINED diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/adc.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/adc.h index 559b5f177..c47e9d453 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/adc.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/adc.h @@ -1,27 +1,90 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ + #ifndef _HARDWARE_STRUCTS_ADC_H #define _HARDWARE_STRUCTS_ADC_H #include "hardware/address_mapped.h" #include "hardware/regs/adc.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_adc +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/adc.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(ADC_CS_OFFSET) // ADC_CS + // ADC Control and Status + // 0x001f0000 [20:16] : RROBIN (0): Round-robin sampling + // 0x00007000 [14:12] : AINSEL (0): Select analog mux input + // 0x00000400 [10] : ERR_STICKY (0): Some past ADC conversion encountered an error + // 0x00000200 [9] : ERR (0): The most recent ADC conversion encountered an error; result is undefined or noisy + // 0x00000100 [8] : READY (0): 1 if the ADC is ready to start a new conversion + // 0x00000008 [3] : START_MANY (0): Continuously perform conversions whilst this bit is 1 + // 0x00000004 [2] : START_ONCE (0): Start a single conversion + // 0x00000002 [1] : TS_EN (0): Power on temperature sensor + // 0x00000001 [0] : EN (0): Power on ADC and enable its clock io_rw_32 cs; - io_rw_32 result; + + _REG_(ADC_RESULT_OFFSET) // ADC_RESULT + // Result of most recent ADC conversion + // 0x00000fff [11:0] : RESULT (0) + io_ro_32 result; + + _REG_(ADC_FCS_OFFSET) // ADC_FCS + // FIFO control and status + // 0x0f000000 [27:24] : THRESH (0): DREQ/IRQ asserted when level >= threshold + // 0x000f0000 [19:16] : LEVEL (0): The number of conversion results currently waiting in the FIFO + // 0x00000800 [11] : OVER (0): 1 if the FIFO has been overflowed + // 0x00000400 [10] : UNDER (0): 1 if the FIFO has been underflowed + // 0x00000200 [9] : FULL (0) + // 0x00000100 [8] : EMPTY (0) + // 0x00000008 [3] : DREQ_EN (0): If 1: assert DMA requests when FIFO contains data + // 0x00000004 [2] : ERR (0): If 1: conversion error bit appears in the FIFO alongside the result + // 0x00000002 [1] : SHIFT (0): If 1: FIFO results are right-shifted to be one byte in size + // 0x00000001 [0] : EN (0): If 1: write result to the FIFO after each conversion io_rw_32 fcs; - io_rw_32 fifo; + + _REG_(ADC_FIFO_OFFSET) // ADC_FIFO + // Conversion result FIFO + // 0x00008000 [15] : ERR (0): 1 if this particular sample experienced a conversion error + // 0x00000fff [11:0] : VAL (0) + io_ro_32 fifo; + + _REG_(ADC_DIV_OFFSET) // ADC_DIV + // Clock divider + // 0x00ffff00 [23:8] : INT (0): Integer part of clock divisor + // 0x000000ff [7:0] : FRAC (0): Fractional part of clock divisor io_rw_32 div; - io_rw_32 intr; + + _REG_(ADC_INTR_OFFSET) // ADC_INTR + // Raw Interrupts + // 0x00000001 [0] : FIFO (0): Triggered when the sample FIFO reaches a certain level + io_ro_32 intr; + + _REG_(ADC_INTE_OFFSET) // ADC_INTE + // Interrupt Enable + // 0x00000001 [0] : FIFO (0): Triggered when the sample FIFO reaches a certain level io_rw_32 inte; + + _REG_(ADC_INTF_OFFSET) // ADC_INTF + // Interrupt Force + // 0x00000001 [0] : FIFO (0): Triggered when the sample FIFO reaches a certain level io_rw_32 intf; - io_rw_32 ints; -} adc_hw_t; -check_hw_layout(adc_hw_t, ints, ADC_INTS_OFFSET); + _REG_(ADC_INTS_OFFSET) // ADC_INTS + // Interrupt status after masking & forcing + // 0x00000001 [0] : FIFO (0): Triggered when the sample FIFO reaches a certain level + io_ro_32 ints; +} adc_hw_t; #define adc_hw ((adc_hw_t *const)ADC_BASE) diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h index ce95a7c19..81118a8f3 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h @@ -1,14 +1,25 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ + #ifndef _HARDWARE_STRUCTS_BUS_CTRL_H #define _HARDWARE_STRUCTS_BUS_CTRL_H #include "hardware/address_mapped.h" #include "hardware/regs/busctrl.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_busctrl +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + enum bus_ctrl_perf_counter { arbiter_rom_perf_event_access = 19, arbiter_rom_perf_event_access_contested = 18, @@ -33,15 +44,33 @@ enum bus_ctrl_perf_counter { }; typedef struct { + _REG_(BUSCTRL_PERFCTR0_OFFSET) // BUSCTRL_PERFCTR0 + // Bus fabric performance counter 0 + // 0x00ffffff [23:0] : PERFCTR0 (0): Busfabric saturating performance counter 0 + io_rw_32 value; + + _REG_(BUSCTRL_PERFSEL0_OFFSET) // BUSCTRL_PERFSEL0 + // Bus fabric performance event select for PERFCTR0 + // 0x0000001f [4:0] : PERFSEL0 (0x1f): Select an event for PERFCTR0 + io_rw_32 sel; +} bus_ctrl_perf_hw_t; + +typedef struct { + _REG_(BUSCTRL_BUS_PRIORITY_OFFSET) // BUSCTRL_BUS_PRIORITY + // Set the priority of each master for bus arbitration + // 0x00001000 [12] : DMA_W (0): 0 - low priority, 1 - high priority + // 0x00000100 [8] : DMA_R (0): 0 - low priority, 1 - high priority + // 0x00000010 [4] : PROC1 (0): 0 - low priority, 1 - high priority + // 0x00000001 [0] : PROC0 (0): 0 - low priority, 1 - high priority io_rw_32 priority; + + _REG_(BUSCTRL_BUS_PRIORITY_ACK_OFFSET) // BUSCTRL_BUS_PRIORITY_ACK + // Bus priority acknowledge + // 0x00000001 [0] : BUS_PRIORITY_ACK (0): Goes to 1 once all arbiters have registered the new global priority levels io_ro_32 priority_ack; - struct { - io_rw_32 value; - io_rw_32 sel; - } counter[4]; -} bus_ctrl_hw_t; -check_hw_layout(bus_ctrl_hw_t, counter[0].value, BUSCTRL_PERFCTR0_OFFSET); + bus_ctrl_perf_hw_t counter[4]; +} bus_ctrl_hw_t; #define bus_ctrl_hw ((bus_ctrl_hw_t *const)BUSCTRL_BASE) diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/clocks.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/clocks.h index 489876d16..a245dbd48 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/clocks.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/clocks.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,9 +10,16 @@ #define _HARDWARE_STRUCTS_CLOCKS_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/clocks.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_clocks +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/clocks.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + /*! \brief Enumeration identifying a hardware clock * \ingroup hardware_clocks */ @@ -32,41 +41,286 @@ enum clock_index { /// \tag::clock_hw[] typedef struct { + _REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL + // Clock control, can be changed on-the-fly (except for auxsrc) + // 0x00100000 [20] : NUDGE (0): An edge on this signal shifts the phase of the output by 1 cycle of the input clock + // 0x00030000 [17:16] : PHASE (0): This delays the enable signal by up to 3 cycles of the input clock + // 0x00001000 [12] : DC50 (0): Enables duty cycle correction for odd divisors + // 0x00000800 [11] : ENABLE (0): Starts and stops the clock generator cleanly + // 0x00000400 [10] : KILL (0): Asynchronously kills the clock generator + // 0x000001e0 [8:5] : AUXSRC (0): Selects the auxiliary clock source, will glitch when switching io_rw_32 ctrl; + + _REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV + // Clock divisor, can be changed on-the-fly + // 0xffffff00 [31:8] : INT (1): Integer component of the divisor, 0 -> divide by 2^16 + // 0x000000ff [7:0] : FRAC (0): Fractional component of the divisor io_rw_32 div; - io_rw_32 selected; + + _REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED + // Indicates which SRC is currently selected by the glitchless mux (one-hot) + io_ro_32 selected; } clock_hw_t; /// \end::clock_hw[] typedef struct { + _REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL + // 0x00010000 [16] : CLEAR (0): For clearing the resus after the fault that triggered it has been corrected + // 0x00001000 [12] : FRCE (0): Force a resus, for test purposes only + // 0x00000100 [8] : ENABLE (0): Enable resus + // 0x000000ff [7:0] : TIMEOUT (0xff): This is expressed as a number of clk_ref cycles + io_rw_32 ctrl; + + _REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS + // 0x00000001 [0] : RESUSSED (0): Clock has been resuscitated, correct the error then send ctrl_clear=1 + io_ro_32 status; +} clock_resus_hw_t; + +typedef struct { + _REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ + // Reference clock frequency in kHz + // 0x000fffff [19:0] : FC0_REF_KHZ (0) io_rw_32 ref_khz; + + _REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ + // Minimum pass frequency in kHz + // 0x01ffffff [24:0] : FC0_MIN_KHZ (0) io_rw_32 min_khz; + + _REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ + // Maximum pass frequency in kHz + // 0x01ffffff [24:0] : FC0_MAX_KHZ (0x1ffffff) io_rw_32 max_khz; + + _REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY + // Delays the start of frequency counting to allow the mux to settle + // 0x00000007 [2:0] : FC0_DELAY (1) io_rw_32 delay; + + _REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL + // The test interval is 0 + // 0x0000000f [3:0] : FC0_INTERVAL (0x8) io_rw_32 interval; + + _REG_(CLOCKS_FC0_SRC_OFFSET) // CLOCKS_FC0_SRC + // Clock sent to frequency counter, set to 0 when not required + // 0x000000ff [7:0] : FC0_SRC (0) io_rw_32 src; + + _REG_(CLOCKS_FC0_STATUS_OFFSET) // CLOCKS_FC0_STATUS + // Frequency counter status + // 0x10000000 [28] : DIED (0): Test clock stopped during test + // 0x01000000 [24] : FAST (0): Test clock faster than expected, only valid when status_done=1 + // 0x00100000 [20] : SLOW (0): Test clock slower than expected, only valid when status_done=1 + // 0x00010000 [16] : FAIL (0): Test failed + // 0x00001000 [12] : WAITING (0): Waiting for test clock to start + // 0x00000100 [8] : RUNNING (0): Test running + // 0x00000010 [4] : DONE (0): Test complete + // 0x00000001 [0] : PASS (0): Test passed io_ro_32 status; + + _REG_(CLOCKS_FC0_RESULT_OFFSET) // CLOCKS_FC0_RESULT + // Result of frequency measurement, only valid when status_done=1 + // 0x3fffffe0 [29:5] : KHZ (0) + // 0x0000001f [4:0] : FRAC (0) io_ro_32 result; } fc_hw_t; typedef struct { - clock_hw_t clk[CLK_COUNT]; - struct { - io_rw_32 ctrl; - io_rw_32 status; - } resus; + clock_hw_t clk[CLK_COUNT]; // 10 + + clock_resus_hw_t resus; + fc_hw_t fc0; + + _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0 + // enable clock in wake mode + // 0x80000000 [31] : clk_sys_sram3 (1) + // 0x40000000 [30] : clk_sys_sram2 (1) + // 0x20000000 [29] : clk_sys_sram1 (1) + // 0x10000000 [28] : clk_sys_sram0 (1) + // 0x08000000 [27] : clk_sys_spi1 (1) + // 0x04000000 [26] : clk_peri_spi1 (1) + // 0x02000000 [25] : clk_sys_spi0 (1) + // 0x01000000 [24] : clk_peri_spi0 (1) + // 0x00800000 [23] : clk_sys_sio (1) + // 0x00400000 [22] : clk_sys_rtc (1) + // 0x00200000 [21] : clk_rtc_rtc (1) + // 0x00100000 [20] : clk_sys_rosc (1) + // 0x00080000 [19] : clk_sys_rom (1) + // 0x00040000 [18] : clk_sys_resets (1) + // 0x00020000 [17] : clk_sys_pwm (1) + // 0x00010000 [16] : clk_sys_psm (1) + // 0x00008000 [15] : clk_sys_pll_usb (1) + // 0x00004000 [14] : clk_sys_pll_sys (1) + // 0x00002000 [13] : clk_sys_pio1 (1) + // 0x00001000 [12] : clk_sys_pio0 (1) + // 0x00000800 [11] : clk_sys_pads (1) + // 0x00000400 [10] : clk_sys_vreg_and_chip_reset (1) + // 0x00000200 [9] : clk_sys_jtag (1) + // 0x00000100 [8] : clk_sys_io (1) + // 0x00000080 [7] : clk_sys_i2c1 (1) + // 0x00000040 [6] : clk_sys_i2c0 (1) + // 0x00000020 [5] : clk_sys_dma (1) + // 0x00000010 [4] : clk_sys_busfabric (1) + // 0x00000008 [3] : clk_sys_busctrl (1) + // 0x00000004 [2] : clk_sys_adc (1) + // 0x00000002 [1] : clk_adc_adc (1) + // 0x00000001 [0] : clk_sys_clocks (1) io_rw_32 wake_en0; + + _REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1 + // enable clock in wake mode + // 0x00004000 [14] : clk_sys_xosc (1) + // 0x00002000 [13] : clk_sys_xip (1) + // 0x00001000 [12] : clk_sys_watchdog (1) + // 0x00000800 [11] : clk_usb_usbctrl (1) + // 0x00000400 [10] : clk_sys_usbctrl (1) + // 0x00000200 [9] : clk_sys_uart1 (1) + // 0x00000100 [8] : clk_peri_uart1 (1) + // 0x00000080 [7] : clk_sys_uart0 (1) + // 0x00000040 [6] : clk_peri_uart0 (1) + // 0x00000020 [5] : clk_sys_timer (1) + // 0x00000010 [4] : clk_sys_tbman (1) + // 0x00000008 [3] : clk_sys_sysinfo (1) + // 0x00000004 [2] : clk_sys_syscfg (1) + // 0x00000002 [1] : clk_sys_sram5 (1) + // 0x00000001 [0] : clk_sys_sram4 (1) io_rw_32 wake_en1; + + _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0 + // enable clock in sleep mode + // 0x80000000 [31] : clk_sys_sram3 (1) + // 0x40000000 [30] : clk_sys_sram2 (1) + // 0x20000000 [29] : clk_sys_sram1 (1) + // 0x10000000 [28] : clk_sys_sram0 (1) + // 0x08000000 [27] : clk_sys_spi1 (1) + // 0x04000000 [26] : clk_peri_spi1 (1) + // 0x02000000 [25] : clk_sys_spi0 (1) + // 0x01000000 [24] : clk_peri_spi0 (1) + // 0x00800000 [23] : clk_sys_sio (1) + // 0x00400000 [22] : clk_sys_rtc (1) + // 0x00200000 [21] : clk_rtc_rtc (1) + // 0x00100000 [20] : clk_sys_rosc (1) + // 0x00080000 [19] : clk_sys_rom (1) + // 0x00040000 [18] : clk_sys_resets (1) + // 0x00020000 [17] : clk_sys_pwm (1) + // 0x00010000 [16] : clk_sys_psm (1) + // 0x00008000 [15] : clk_sys_pll_usb (1) + // 0x00004000 [14] : clk_sys_pll_sys (1) + // 0x00002000 [13] : clk_sys_pio1 (1) + // 0x00001000 [12] : clk_sys_pio0 (1) + // 0x00000800 [11] : clk_sys_pads (1) + // 0x00000400 [10] : clk_sys_vreg_and_chip_reset (1) + // 0x00000200 [9] : clk_sys_jtag (1) + // 0x00000100 [8] : clk_sys_io (1) + // 0x00000080 [7] : clk_sys_i2c1 (1) + // 0x00000040 [6] : clk_sys_i2c0 (1) + // 0x00000020 [5] : clk_sys_dma (1) + // 0x00000010 [4] : clk_sys_busfabric (1) + // 0x00000008 [3] : clk_sys_busctrl (1) + // 0x00000004 [2] : clk_sys_adc (1) + // 0x00000002 [1] : clk_adc_adc (1) + // 0x00000001 [0] : clk_sys_clocks (1) io_rw_32 sleep_en0; + + _REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1 + // enable clock in sleep mode + // 0x00004000 [14] : clk_sys_xosc (1) + // 0x00002000 [13] : clk_sys_xip (1) + // 0x00001000 [12] : clk_sys_watchdog (1) + // 0x00000800 [11] : clk_usb_usbctrl (1) + // 0x00000400 [10] : clk_sys_usbctrl (1) + // 0x00000200 [9] : clk_sys_uart1 (1) + // 0x00000100 [8] : clk_peri_uart1 (1) + // 0x00000080 [7] : clk_sys_uart0 (1) + // 0x00000040 [6] : clk_peri_uart0 (1) + // 0x00000020 [5] : clk_sys_timer (1) + // 0x00000010 [4] : clk_sys_tbman (1) + // 0x00000008 [3] : clk_sys_sysinfo (1) + // 0x00000004 [2] : clk_sys_syscfg (1) + // 0x00000002 [1] : clk_sys_sram5 (1) + // 0x00000001 [0] : clk_sys_sram4 (1) io_rw_32 sleep_en1; - io_rw_32 enabled0; - io_rw_32 enabled1; - io_rw_32 intr; + + _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0 + // indicates the state of the clock enable + // 0x80000000 [31] : clk_sys_sram3 (0) + // 0x40000000 [30] : clk_sys_sram2 (0) + // 0x20000000 [29] : clk_sys_sram1 (0) + // 0x10000000 [28] : clk_sys_sram0 (0) + // 0x08000000 [27] : clk_sys_spi1 (0) + // 0x04000000 [26] : clk_peri_spi1 (0) + // 0x02000000 [25] : clk_sys_spi0 (0) + // 0x01000000 [24] : clk_peri_spi0 (0) + // 0x00800000 [23] : clk_sys_sio (0) + // 0x00400000 [22] : clk_sys_rtc (0) + // 0x00200000 [21] : clk_rtc_rtc (0) + // 0x00100000 [20] : clk_sys_rosc (0) + // 0x00080000 [19] : clk_sys_rom (0) + // 0x00040000 [18] : clk_sys_resets (0) + // 0x00020000 [17] : clk_sys_pwm (0) + // 0x00010000 [16] : clk_sys_psm (0) + // 0x00008000 [15] : clk_sys_pll_usb (0) + // 0x00004000 [14] : clk_sys_pll_sys (0) + // 0x00002000 [13] : clk_sys_pio1 (0) + // 0x00001000 [12] : clk_sys_pio0 (0) + // 0x00000800 [11] : clk_sys_pads (0) + // 0x00000400 [10] : clk_sys_vreg_and_chip_reset (0) + // 0x00000200 [9] : clk_sys_jtag (0) + // 0x00000100 [8] : clk_sys_io (0) + // 0x00000080 [7] : clk_sys_i2c1 (0) + // 0x00000040 [6] : clk_sys_i2c0 (0) + // 0x00000020 [5] : clk_sys_dma (0) + // 0x00000010 [4] : clk_sys_busfabric (0) + // 0x00000008 [3] : clk_sys_busctrl (0) + // 0x00000004 [2] : clk_sys_adc (0) + // 0x00000002 [1] : clk_adc_adc (0) + // 0x00000001 [0] : clk_sys_clocks (0) + io_ro_32 enabled0; + + _REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1 + // indicates the state of the clock enable + // 0x00004000 [14] : clk_sys_xosc (0) + // 0x00002000 [13] : clk_sys_xip (0) + // 0x00001000 [12] : clk_sys_watchdog (0) + // 0x00000800 [11] : clk_usb_usbctrl (0) + // 0x00000400 [10] : clk_sys_usbctrl (0) + // 0x00000200 [9] : clk_sys_uart1 (0) + // 0x00000100 [8] : clk_peri_uart1 (0) + // 0x00000080 [7] : clk_sys_uart0 (0) + // 0x00000040 [6] : clk_peri_uart0 (0) + // 0x00000020 [5] : clk_sys_timer (0) + // 0x00000010 [4] : clk_sys_tbman (0) + // 0x00000008 [3] : clk_sys_sysinfo (0) + // 0x00000004 [2] : clk_sys_syscfg (0) + // 0x00000002 [1] : clk_sys_sram5 (0) + // 0x00000001 [0] : clk_sys_sram4 (0) + io_ro_32 enabled1; + + _REG_(CLOCKS_INTR_OFFSET) // CLOCKS_INTR + // Raw Interrupts + // 0x00000001 [0] : CLK_SYS_RESUS (0) + io_ro_32 intr; + + _REG_(CLOCKS_INTE_OFFSET) // CLOCKS_INTE + // Interrupt Enable + // 0x00000001 [0] : CLK_SYS_RESUS (0) io_rw_32 inte; + + _REG_(CLOCKS_INTF_OFFSET) // CLOCKS_INTF + // Interrupt Force + // 0x00000001 [0] : CLK_SYS_RESUS (0) io_rw_32 intf; - io_rw_32 ints; + + _REG_(CLOCKS_INTS_OFFSET) // CLOCKS_INTS + // Interrupt status after masking & forcing + // 0x00000001 [0] : CLK_SYS_RESUS (0) + io_ro_32 ints; } clocks_hw_t; #define clocks_hw ((clocks_hw_t *const)CLOCKS_BASE) + +static_assert( CLK_COUNT == 10, ""); + #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/dma.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/dma.h index 06cdf7927..0d206416a 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/dma.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/dma.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,51 +10,185 @@ #define _HARDWARE_STRUCTS_DMA_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/dma.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/dma.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR + // DMA Channel 0 Read Address pointer io_rw_32 read_addr; + + _REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR + // DMA Channel 0 Write Address pointer io_rw_32 write_addr; + + _REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT + // DMA Channel 0 Transfer Count io_rw_32 transfer_count; + + _REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG + // DMA Channel 0 Control and Status + // 0x80000000 [31] : AHB_ERROR (0): Logical OR of the READ_ERROR and WRITE_ERROR flags + // 0x40000000 [30] : READ_ERROR (0): If 1, the channel received a read bus error + // 0x20000000 [29] : WRITE_ERROR (0): If 1, the channel received a write bus error + // 0x01000000 [24] : BUSY (0): This flag goes high when the channel starts a new transfer sequence, and low when the... + // 0x00800000 [23] : SNIFF_EN (0): If 1, this channel's data transfers are visible to the sniff hardware, and each... + // 0x00400000 [22] : BSWAP (0): Apply byte-swap transformation to DMA data + // 0x00200000 [21] : IRQ_QUIET (0): In QUIET mode, the channel does not generate IRQs at the end of every transfer block + // 0x001f8000 [20:15] : TREQ_SEL (0): Select a Transfer Request signal + // 0x00007800 [14:11] : CHAIN_TO (0): When this channel completes, it will trigger the channel indicated by CHAIN_TO + // 0x00000400 [10] : RING_SEL (0): Select whether RING_SIZE applies to read or write addresses + // 0x000003c0 [9:6] : RING_SIZE (0): Size of address wrap region + // 0x00000020 [5] : INCR_WRITE (0): If 1, the write address increments with each transfer + // 0x00000010 [4] : INCR_READ (0): If 1, the read address increments with each transfer + // 0x0000000c [3:2] : DATA_SIZE (0): Set the size of each bus transfer (byte/halfword/word) + // 0x00000002 [1] : HIGH_PRIORITY (0): HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in... + // 0x00000001 [0] : EN (0): DMA Channel Enable io_rw_32 ctrl_trig; + + _REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL + // Alias for channel 0 CTRL register io_rw_32 al1_ctrl; + + _REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR + // Alias for channel 0 READ_ADDR register io_rw_32 al1_read_addr; + + _REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR + // Alias for channel 0 WRITE_ADDR register io_rw_32 al1_write_addr; + + _REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG + // Alias for channel 0 TRANS_COUNT register io_rw_32 al1_transfer_count_trig; + + _REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL + // Alias for channel 0 CTRL register io_rw_32 al2_ctrl; + + _REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT + // Alias for channel 0 TRANS_COUNT register io_rw_32 al2_transfer_count; + + _REG_(DMA_CH0_AL2_READ_ADDR_OFFSET) // DMA_CH0_AL2_READ_ADDR + // Alias for channel 0 READ_ADDR register io_rw_32 al2_read_addr; + + _REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET) // DMA_CH0_AL2_WRITE_ADDR_TRIG + // Alias for channel 0 WRITE_ADDR register io_rw_32 al2_write_addr_trig; + + _REG_(DMA_CH0_AL3_CTRL_OFFSET) // DMA_CH0_AL3_CTRL + // Alias for channel 0 CTRL register io_rw_32 al3_ctrl; + + _REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET) // DMA_CH0_AL3_WRITE_ADDR + // Alias for channel 0 WRITE_ADDR register io_rw_32 al3_write_addr; + + _REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET) // DMA_CH0_AL3_TRANS_COUNT + // Alias for channel 0 TRANS_COUNT register io_rw_32 al3_transfer_count; + + _REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET) // DMA_CH0_AL3_READ_ADDR_TRIG + // Alias for channel 0 READ_ADDR register io_rw_32 al3_read_addr_trig; -} dma_channel_hw_t; +} dma_channel_hw_t; typedef struct { - dma_channel_hw_t ch[NUM_DMA_CHANNELS]; - uint32_t _pad0[16 * (16 - NUM_DMA_CHANNELS)]; + dma_channel_hw_t ch[NUM_DMA_CHANNELS]; // 12 + + uint32_t _pad0[64]; + + _REG_(DMA_INTR_OFFSET) // DMA_INTR + // Interrupt Status (raw) + // 0x0000ffff [15:0] : INTR (0): Raw interrupt status for DMA Channels 0 io_ro_32 intr; + + _REG_(DMA_INTE0_OFFSET) // DMA_INTE0 + // Interrupt Enables for IRQ 0 + // 0x0000ffff [15:0] : INTE0 (0): Set bit n to pass interrupts from channel n to DMA IRQ 0 io_rw_32 inte0; + + _REG_(DMA_INTF0_OFFSET) // DMA_INTF0 + // Force Interrupts + // 0x0000ffff [15:0] : INTF0 (0): Write 1s to force the corresponding bits in INTE0 io_rw_32 intf0; + + _REG_(DMA_INTS0_OFFSET) // DMA_INTS0 + // Interrupt Status for IRQ 0 + // 0x0000ffff [15:0] : INTS0 (0): Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted io_rw_32 ints0; - uint32_t _pad1[1]; + + uint32_t _pad1; + + _REG_(DMA_INTE1_OFFSET) // DMA_INTE1 + // Interrupt Enables for IRQ 1 + // 0x0000ffff [15:0] : INTE1 (0): Set bit n to pass interrupts from channel n to DMA IRQ 1 io_rw_32 inte1; + + _REG_(DMA_INTF1_OFFSET) // DMA_INTF1 + // Force Interrupts for IRQ 1 + // 0x0000ffff [15:0] : INTF1 (0): Write 1s to force the corresponding bits in INTE0 io_rw_32 intf1; + + _REG_(DMA_INTS1_OFFSET) // DMA_INTS1 + // Interrupt Status (masked) for IRQ 1 + // 0x0000ffff [15:0] : INTS1 (0): Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted io_rw_32 ints1; - io_rw_32 timer[4]; - io_wo_32 multi_channel_trigger; + + _REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0 + // (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes) + // + // Pacing (X/Y) Fractional Timer + // 0xffff0000 [31:16] : X (0): Pacing Timer Dividend + // 0x0000ffff [15:0] : Y (0): Pacing Timer Divisor + io_rw_32 timer[NUM_DMA_TIMERS]; // 4 + + _REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER + // Trigger one or more channels simultaneously + // 0x0000ffff [15:0] : MULTI_CHAN_TRIGGER (0): Each bit in this register corresponds to a DMA channel + io_rw_32 multi_channel_trigger; + + _REG_(DMA_SNIFF_CTRL_OFFSET) // DMA_SNIFF_CTRL + // Sniffer Control + // 0x00000800 [11] : OUT_INV (0): If set, the result appears inverted (bitwise complement) when read + // 0x00000400 [10] : OUT_REV (0): If set, the result appears bit-reversed when read + // 0x00000200 [9] : BSWAP (0): Locally perform a byte reverse on the sniffed data, before feeding into checksum + // 0x000001e0 [8:5] : CALC (0) + // 0x0000001e [4:1] : DMACH (0): DMA channel for Sniffer to observe + // 0x00000001 [0] : EN (0): Enable sniffer io_rw_32 sniff_ctrl; + + _REG_(DMA_SNIFF_DATA_OFFSET) // DMA_SNIFF_DATA + // Data accumulator for sniff hardware io_rw_32 sniff_data; - uint32_t _pad2[1]; + + uint32_t _pad2; + + _REG_(DMA_FIFO_LEVELS_OFFSET) // DMA_FIFO_LEVELS + // Debug RAF, WAF, TDF levels + // 0x00ff0000 [23:16] : RAF_LVL (0): Current Read-Address-FIFO fill level + // 0x0000ff00 [15:8] : WAF_LVL (0): Current Write-Address-FIFO fill level + // 0x000000ff [7:0] : TDF_LVL (0): Current Transfer-Data-FIFO fill level io_ro_32 fifo_levels; - io_wo_32 abort; + + _REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT + // Abort an in-progress transfer sequence on one or more channels + // 0x0000ffff [15:0] : CHAN_ABORT (0): Each bit corresponds to a channel + io_rw_32 abort; } dma_hw_t; typedef struct { struct dma_debug_hw_channel { - io_ro_32 ctrdeq; + io_rw_32 ctrdeq; io_ro_32 tcr; uint32_t pad[14]; } ch[NUM_DMA_CHANNELS]; @@ -61,4 +197,7 @@ typedef struct { #define dma_hw ((dma_hw_t *const)DMA_BASE) #define dma_debug_hw ((dma_debug_hw_t *const)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET)) +static_assert( NUM_DMA_TIMERS == 4, ""); +static_assert( NUM_DMA_CHANNELS == 12, ""); + #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/i2c.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/i2c.h index 4bc501f28..43d608636 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/i2c.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/i2c.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,132 +12,322 @@ #include "hardware/address_mapped.h" #include "hardware/regs/i2c.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_i2c +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/i2c.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(I2C_IC_CON_OFFSET) // I2C_IC_CON + // I2C Control Register + // 0x00000400 [10] : STOP_DET_IF_MASTER_ACTIVE (0): Master issues the STOP_DET interrupt irrespective of whether... + // 0x00000200 [9] : RX_FIFO_FULL_HLD_CTRL (0): This bit controls whether DW_apb_i2c should hold the bus when the Rx... + // 0x00000100 [8] : TX_EMPTY_CTRL (0): This bit controls the generation of the TX_EMPTY interrupt, as described in... + // 0x00000080 [7] : STOP_DET_IFADDRESSED (0): In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is... + // 0x00000040 [6] : IC_SLAVE_DISABLE (1): This bit controls whether I2C has its slave disabled, which means once... + // 0x00000020 [5] : IC_RESTART_EN (1): Determines whether RESTART conditions may be sent when acting as a master + // 0x00000010 [4] : IC_10BITADDR_MASTER (0): Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit... + // 0x00000008 [3] : IC_10BITADDR_SLAVE (0): When acting as a slave, this bit controls whether the DW_apb_i2c... + // 0x00000006 [2:1] : SPEED (0x2): These bits control at which speed the DW_apb_i2c operates; its setting is relevant... + // 0x00000001 [0] : MASTER_MODE (1): This bit controls whether the DW_apb_i2c master is enabled io_rw_32 con; + + _REG_(I2C_IC_TAR_OFFSET) // I2C_IC_TAR + // I2C Target Address Register + // 0x00000800 [11] : SPECIAL (0): This bit indicates whether software performs a Device-ID or General Call or START... + // 0x00000400 [10] : GC_OR_START (0): If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this... + // 0x000003ff [9:0] : IC_TAR (0x55): This is the target address for any master transaction io_rw_32 tar; + + _REG_(I2C_IC_SAR_OFFSET) // I2C_IC_SAR + // I2C Slave Address Register + // 0x000003ff [9:0] : IC_SAR (0x55): The IC_SAR holds the slave address when the I2C is operating as a slave io_rw_32 sar; + uint32_t _pad0; + + _REG_(I2C_IC_DATA_CMD_OFFSET) // I2C_IC_DATA_CMD + // I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the... + // 0x00000800 [11] : FIRST_DATA_BYTE (0): Indicates the first data byte received after the address phase for receive... + // 0x00000400 [10] : RESTART (0): This bit controls whether a RESTART is issued before the byte is sent or received + // 0x00000200 [9] : STOP (0): This bit controls whether a STOP is issued after the byte is sent or received + // 0x00000100 [8] : CMD (0): This bit controls whether a read or a write is performed + // 0x000000ff [7:0] : DAT (0): This register contains the data to be transmitted or received on the I2C bus io_rw_32 data_cmd; + + _REG_(I2C_IC_SS_SCL_HCNT_OFFSET) // I2C_IC_SS_SCL_HCNT + // Standard Speed I2C Clock SCL High Count Register + // 0x0000ffff [15:0] : IC_SS_SCL_HCNT (0x28): This register must be set before any I2C bus transaction can take place... io_rw_32 ss_scl_hcnt; + + _REG_(I2C_IC_SS_SCL_LCNT_OFFSET) // I2C_IC_SS_SCL_LCNT + // Standard Speed I2C Clock SCL Low Count Register + // 0x0000ffff [15:0] : IC_SS_SCL_LCNT (0x2f): This register must be set before any I2C bus transaction can take place... io_rw_32 ss_scl_lcnt; + + _REG_(I2C_IC_FS_SCL_HCNT_OFFSET) // I2C_IC_FS_SCL_HCNT + // Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register + // 0x0000ffff [15:0] : IC_FS_SCL_HCNT (0x6): This register must be set before any I2C bus transaction can take place... io_rw_32 fs_scl_hcnt; + + _REG_(I2C_IC_FS_SCL_LCNT_OFFSET) // I2C_IC_FS_SCL_LCNT + // Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register + // 0x0000ffff [15:0] : IC_FS_SCL_LCNT (0xd): This register must be set before any I2C bus transaction can take place... io_rw_32 fs_scl_lcnt; + uint32_t _pad1[2]; - io_rw_32 intr_stat; + + _REG_(I2C_IC_INTR_STAT_OFFSET) // I2C_IC_INTR_STAT + // I2C Interrupt Status Register + // 0x00001000 [12] : R_RESTART_DET (0): See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit + // 0x00000800 [11] : R_GEN_CALL (0): See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit + // 0x00000400 [10] : R_START_DET (0): See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit + // 0x00000200 [9] : R_STOP_DET (0): See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit + // 0x00000100 [8] : R_ACTIVITY (0): See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit + // 0x00000080 [7] : R_RX_DONE (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit + // 0x00000040 [6] : R_TX_ABRT (0): See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit + // 0x00000020 [5] : R_RD_REQ (0): See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit + // 0x00000010 [4] : R_TX_EMPTY (0): See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit + // 0x00000008 [3] : R_TX_OVER (0): See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit + // 0x00000004 [2] : R_RX_FULL (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit + // 0x00000002 [1] : R_RX_OVER (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit + // 0x00000001 [0] : R_RX_UNDER (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit + io_ro_32 intr_stat; + + _REG_(I2C_IC_INTR_MASK_OFFSET) // I2C_IC_INTR_MASK + // I2C Interrupt Mask Register + // 0x00001000 [12] : M_RESTART_DET (0): This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register + // 0x00000800 [11] : M_GEN_CALL (1): This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register + // 0x00000400 [10] : M_START_DET (0): This bit masks the R_START_DET interrupt in IC_INTR_STAT register + // 0x00000200 [9] : M_STOP_DET (0): This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register + // 0x00000100 [8] : M_ACTIVITY (0): This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register + // 0x00000080 [7] : M_RX_DONE (1): This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register + // 0x00000040 [6] : M_TX_ABRT (1): This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register + // 0x00000020 [5] : M_RD_REQ (1): This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register + // 0x00000010 [4] : M_TX_EMPTY (1): This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register + // 0x00000008 [3] : M_TX_OVER (1): This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register + // 0x00000004 [2] : M_RX_FULL (1): This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register + // 0x00000002 [1] : M_RX_OVER (1): This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register + // 0x00000001 [0] : M_RX_UNDER (1): This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register io_rw_32 intr_mask; - io_rw_32 raw_intr_stat; + + _REG_(I2C_IC_RAW_INTR_STAT_OFFSET) // I2C_IC_RAW_INTR_STAT + // I2C Raw Interrupt Status Register + // 0x00001000 [12] : RESTART_DET (0): Indicates whether a RESTART condition has occurred on the I2C interface when... + // 0x00000800 [11] : GEN_CALL (0): Set only when a General Call address is received and it is acknowledged + // 0x00000400 [10] : START_DET (0): Indicates whether a START or RESTART condition has occurred on the I2C interface... + // 0x00000200 [9] : STOP_DET (0): Indicates whether a STOP condition has occurred on the I2C interface regardless... + // 0x00000100 [8] : ACTIVITY (0): This bit captures DW_apb_i2c activity and stays set until it is cleared + // 0x00000080 [7] : RX_DONE (0): When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the... + // 0x00000040 [6] : TX_ABRT (0): This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the... + // 0x00000020 [5] : RD_REQ (0): This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is... + // 0x00000010 [4] : TX_EMPTY (0): The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL... + // 0x00000008 [3] : TX_OVER (0): Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the... + // 0x00000004 [2] : RX_FULL (0): Set when the receive buffer reaches or goes above the RX_TL threshold in the... + // 0x00000002 [1] : RX_OVER (0): Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an... + // 0x00000001 [0] : RX_UNDER (0): Set if the processor attempts to read the receive buffer when it is empty by... + io_ro_32 raw_intr_stat; + + _REG_(I2C_IC_RX_TL_OFFSET) // I2C_IC_RX_TL + // I2C Receive FIFO Threshold Register + // 0x000000ff [7:0] : RX_TL (0): Receive FIFO Threshold Level io_rw_32 rx_tl; + + _REG_(I2C_IC_TX_TL_OFFSET) // I2C_IC_TX_TL + // I2C Transmit FIFO Threshold Register + // 0x000000ff [7:0] : TX_TL (0): Transmit FIFO Threshold Level io_rw_32 tx_tl; - io_rw_32 clr_intr; - io_rw_32 clr_rx_under; - io_rw_32 clr_rx_over; - io_rw_32 clr_tx_over; - io_rw_32 clr_rd_req; - io_rw_32 clr_tx_abrt; - io_rw_32 clr_rx_done; - io_rw_32 clr_activity; - io_rw_32 clr_stop_det; - io_rw_32 clr_start_det; - io_rw_32 clr_gen_call; + + _REG_(I2C_IC_CLR_INTR_OFFSET) // I2C_IC_CLR_INTR + // Clear Combined and Individual Interrupt Register + // 0x00000001 [0] : CLR_INTR (0): Read this register to clear the combined interrupt, all individual interrupts,... + io_ro_32 clr_intr; + + _REG_(I2C_IC_CLR_RX_UNDER_OFFSET) // I2C_IC_CLR_RX_UNDER + // Clear RX_UNDER Interrupt Register + // 0x00000001 [0] : CLR_RX_UNDER (0): Read this register to clear the RX_UNDER interrupt (bit 0) of the... + io_ro_32 clr_rx_under; + + _REG_(I2C_IC_CLR_RX_OVER_OFFSET) // I2C_IC_CLR_RX_OVER + // Clear RX_OVER Interrupt Register + // 0x00000001 [0] : CLR_RX_OVER (0): Read this register to clear the RX_OVER interrupt (bit 1) of the... + io_ro_32 clr_rx_over; + + _REG_(I2C_IC_CLR_TX_OVER_OFFSET) // I2C_IC_CLR_TX_OVER + // Clear TX_OVER Interrupt Register + // 0x00000001 [0] : CLR_TX_OVER (0): Read this register to clear the TX_OVER interrupt (bit 3) of the... + io_ro_32 clr_tx_over; + + _REG_(I2C_IC_CLR_RD_REQ_OFFSET) // I2C_IC_CLR_RD_REQ + // Clear RD_REQ Interrupt Register + // 0x00000001 [0] : CLR_RD_REQ (0): Read this register to clear the RD_REQ interrupt (bit 5) of the... + io_ro_32 clr_rd_req; + + _REG_(I2C_IC_CLR_TX_ABRT_OFFSET) // I2C_IC_CLR_TX_ABRT + // Clear TX_ABRT Interrupt Register + // 0x00000001 [0] : CLR_TX_ABRT (0): Read this register to clear the TX_ABRT interrupt (bit 6) of the... + io_ro_32 clr_tx_abrt; + + _REG_(I2C_IC_CLR_RX_DONE_OFFSET) // I2C_IC_CLR_RX_DONE + // Clear RX_DONE Interrupt Register + // 0x00000001 [0] : CLR_RX_DONE (0): Read this register to clear the RX_DONE interrupt (bit 7) of the... + io_ro_32 clr_rx_done; + + _REG_(I2C_IC_CLR_ACTIVITY_OFFSET) // I2C_IC_CLR_ACTIVITY + // Clear ACTIVITY Interrupt Register + // 0x00000001 [0] : CLR_ACTIVITY (0): Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore + io_ro_32 clr_activity; + + _REG_(I2C_IC_CLR_STOP_DET_OFFSET) // I2C_IC_CLR_STOP_DET + // Clear STOP_DET Interrupt Register + // 0x00000001 [0] : CLR_STOP_DET (0): Read this register to clear the STOP_DET interrupt (bit 9) of the... + io_ro_32 clr_stop_det; + + _REG_(I2C_IC_CLR_START_DET_OFFSET) // I2C_IC_CLR_START_DET + // Clear START_DET Interrupt Register + // 0x00000001 [0] : CLR_START_DET (0): Read this register to clear the START_DET interrupt (bit 10) of the... + io_ro_32 clr_start_det; + + _REG_(I2C_IC_CLR_GEN_CALL_OFFSET) // I2C_IC_CLR_GEN_CALL + // Clear GEN_CALL Interrupt Register + // 0x00000001 [0] : CLR_GEN_CALL (0): Read this register to clear the GEN_CALL interrupt (bit 11) of... + io_ro_32 clr_gen_call; + + _REG_(I2C_IC_ENABLE_OFFSET) // I2C_IC_ENABLE + // I2C Enable Register + // 0x00000004 [2] : TX_CMD_BLOCK (0): In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx... + // 0x00000002 [1] : ABORT (0): When set, the controller initiates the transfer abort + // 0x00000001 [0] : ENABLE (0): Controls whether the DW_apb_i2c is enabled io_rw_32 enable; - io_rw_32 status; - io_rw_32 txflr; - io_rw_32 rxflr; + + _REG_(I2C_IC_STATUS_OFFSET) // I2C_IC_STATUS + // I2C Status Register + // 0x00000040 [6] : SLV_ACTIVITY (0): Slave FSM Activity Status + // 0x00000020 [5] : MST_ACTIVITY (0): Master FSM Activity Status + // 0x00000010 [4] : RFF (0): Receive FIFO Completely Full + // 0x00000008 [3] : RFNE (0): Receive FIFO Not Empty + // 0x00000004 [2] : TFE (1): Transmit FIFO Completely Empty + // 0x00000002 [1] : TFNF (1): Transmit FIFO Not Full + // 0x00000001 [0] : ACTIVITY (0): I2C Activity Status + io_ro_32 status; + + _REG_(I2C_IC_TXFLR_OFFSET) // I2C_IC_TXFLR + // I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer + // 0x0000001f [4:0] : TXFLR (0): Transmit FIFO Level + io_ro_32 txflr; + + _REG_(I2C_IC_RXFLR_OFFSET) // I2C_IC_RXFLR + // I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer + // 0x0000001f [4:0] : RXFLR (0): Receive FIFO Level + io_ro_32 rxflr; + + _REG_(I2C_IC_SDA_HOLD_OFFSET) // I2C_IC_SDA_HOLD + // I2C SDA Hold Time Length Register + // 0x00ff0000 [23:16] : IC_SDA_RX_HOLD (0): Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c... + // 0x0000ffff [15:0] : IC_SDA_TX_HOLD (1): Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c... io_rw_32 sda_hold; - io_rw_32 tx_abrt_source; + + _REG_(I2C_IC_TX_ABRT_SOURCE_OFFSET) // I2C_IC_TX_ABRT_SOURCE + // I2C Transmit Abort Source Register + // 0xff800000 [31:23] : TX_FLUSH_CNT (0): This field indicates the number of Tx FIFO Data Commands which are flushed... + // 0x00010000 [16] : ABRT_USER_ABRT (0): This is a master-mode-only bit + // 0x00008000 [15] : ABRT_SLVRD_INTX (0): 1: When the processor side responds to a slave mode request for data to be... + // 0x00004000 [14] : ABRT_SLV_ARBLOST (0): This field indicates that a Slave has lost the bus while transmitting... + // 0x00002000 [13] : ABRT_SLVFLUSH_TXFIFO (0): This field specifies that the Slave has received a read command and... + // 0x00001000 [12] : ARB_LOST (0): This field specifies that the Master has lost arbitration, or if... + // 0x00000800 [11] : ABRT_MASTER_DIS (0): This field indicates that the User tries to initiate a Master operation... + // 0x00000400 [10] : ABRT_10B_RD_NORSTRT (0): This field indicates that the restart is disabled (IC_RESTART_EN bit... + // 0x00000200 [9] : ABRT_SBYTE_NORSTRT (0): To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed... + // 0x00000100 [8] : ABRT_HS_NORSTRT (0): This field indicates that the restart is disabled (IC_RESTART_EN bit... + // 0x00000080 [7] : ABRT_SBYTE_ACKDET (0): This field indicates that the Master has sent a START Byte and the START... + // 0x00000040 [6] : ABRT_HS_ACKDET (0): This field indicates that the Master is in High Speed mode and the High... + // 0x00000020 [5] : ABRT_GCALL_READ (0): This field indicates that DW_apb_i2c in the master mode has sent a General... + // 0x00000010 [4] : ABRT_GCALL_NOACK (0): This field indicates that DW_apb_i2c in master mode has sent a General... + // 0x00000008 [3] : ABRT_TXDATA_NOACK (0): This field indicates the master-mode only bit + // 0x00000004 [2] : ABRT_10ADDR2_NOACK (0): This field indicates that the Master is in 10-bit address mode and that... + // 0x00000002 [1] : ABRT_10ADDR1_NOACK (0): This field indicates that the Master is in 10-bit address mode and the... + // 0x00000001 [0] : ABRT_7B_ADDR_NOACK (0): This field indicates that the Master is in 7-bit addressing mode and... + io_ro_32 tx_abrt_source; + + _REG_(I2C_IC_SLV_DATA_NACK_ONLY_OFFSET) // I2C_IC_SLV_DATA_NACK_ONLY + // Generate Slave Data NACK Register + // 0x00000001 [0] : NACK (0): Generate NACK io_rw_32 slv_data_nack_only; + + _REG_(I2C_IC_DMA_CR_OFFSET) // I2C_IC_DMA_CR + // DMA Control Register + // 0x00000002 [1] : TDMAE (0): Transmit DMA Enable + // 0x00000001 [0] : RDMAE (0): Receive DMA Enable io_rw_32 dma_cr; + + _REG_(I2C_IC_DMA_TDLR_OFFSET) // I2C_IC_DMA_TDLR + // DMA Transmit Data Level Register + // 0x0000000f [3:0] : DMATDL (0): Transmit Data Level io_rw_32 dma_tdlr; + + _REG_(I2C_IC_DMA_RDLR_OFFSET) // I2C_IC_DMA_RDLR + // I2C Receive Data Level Register + // 0x0000000f [3:0] : DMARDL (0): Receive Data Level io_rw_32 dma_rdlr; + + _REG_(I2C_IC_SDA_SETUP_OFFSET) // I2C_IC_SDA_SETUP + // I2C SDA Setup Register + // 0x000000ff [7:0] : SDA_SETUP (0x64): SDA Setup io_rw_32 sda_setup; + + _REG_(I2C_IC_ACK_GENERAL_CALL_OFFSET) // I2C_IC_ACK_GENERAL_CALL + // I2C ACK General Call Register + // 0x00000001 [0] : ACK_GEN_CALL (1): ACK General Call io_rw_32 ack_general_call; - io_rw_32 enable_status; + + _REG_(I2C_IC_ENABLE_STATUS_OFFSET) // I2C_IC_ENABLE_STATUS + // I2C Enable Status Register + // 0x00000004 [2] : SLV_RX_DATA_LOST (0): Slave Received Data Lost + // 0x00000002 [1] : SLV_DISABLED_WHILE_BUSY (0): Slave Disabled While Busy (Transmit, Receive) + // 0x00000001 [0] : IC_EN (0): ic_en Status + io_ro_32 enable_status; + + _REG_(I2C_IC_FS_SPKLEN_OFFSET) // I2C_IC_FS_SPKLEN + // I2C SS, FS or FM+ spike suppression limit + // 0x000000ff [7:0] : IC_FS_SPKLEN (0x7): This register must be set before any I2C bus transaction can take place to... io_rw_32 fs_spklen; + uint32_t _pad2; - io_rw_32 clr_restart_det; + + _REG_(I2C_IC_CLR_RESTART_DET_OFFSET) // I2C_IC_CLR_RESTART_DET + // Clear RESTART_DET Interrupt Register + // 0x00000001 [0] : CLR_RESTART_DET (0): Read this register to clear the RESTART_DET interrupt (bit 12) of... + io_ro_32 clr_restart_det; + + uint32_t _pad3[18]; + + _REG_(I2C_IC_COMP_PARAM_1_OFFSET) // I2C_IC_COMP_PARAM_1 + // Component Parameter Register 1 + // 0x00ff0000 [23:16] : TX_BUFFER_DEPTH (0): TX Buffer Depth = 16 + // 0x0000ff00 [15:8] : RX_BUFFER_DEPTH (0): RX Buffer Depth = 16 + // 0x00000080 [7] : ADD_ENCODED_PARAMS (0): Encoded parameters not visible + // 0x00000040 [6] : HAS_DMA (0): DMA handshaking signals are enabled + // 0x00000020 [5] : INTR_IO (0): COMBINED Interrupt outputs + // 0x00000010 [4] : HC_COUNT_VALUES (0): Programmable count values for each mode + // 0x0000000c [3:2] : MAX_SPEED_MODE (0): MAX SPEED MODE = FAST MODE + // 0x00000003 [1:0] : APB_DATA_WIDTH (0): APB data bus width is 32 bits + io_ro_32 comp_param_1; + + _REG_(I2C_IC_COMP_VERSION_OFFSET) // I2C_IC_COMP_VERSION + // I2C Component Version Register + // 0xffffffff [31:0] : IC_COMP_VERSION (0x3230312a) + io_ro_32 comp_version; + + _REG_(I2C_IC_COMP_TYPE_OFFSET) // I2C_IC_COMP_TYPE + // I2C Component Type Register + // 0xffffffff [31:0] : IC_COMP_TYPE (0x44570140): Designware Component Type number = 0x44_57_01_40 + io_ro_32 comp_type; } i2c_hw_t; #define i2c0_hw ((i2c_hw_t *const)I2C0_BASE) #define i2c1_hw ((i2c_hw_t *const)I2C1_BASE) -// List of configuration constants for the Synopsys I2C hardware (you may see -// references to these in I2C register header; these are *fixed* values, -// set at hardware design time): - -// SLAVE_INTERFACE_TYPE .............. 0 -// REG_TIMEOUT_WIDTH ................. 4 -// REG_TIMEOUT_VALUE ................. 8 -// IC_ULTRA_FAST_MODE ................ 0x0 -// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 -// IC_UFM_SCL_HIGH_COUNT ............. 0x0006 -// IC_TX_TL .......................... 0x0 -// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 -// IC_SS_SCL_LOW_COUNT ............... 0x01d6 -// IC_HAS_DMA ........................ 0x1 -// IC_RX_FULL_GEN_NACK ............... 0x0 -// IC_CLOCK_PERIOD ................... 100 -// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 -// IC_SMBUS_ARP ...................... 0x0 -// IC_FIRST_DATA_BYTE_STATUS ......... 0x1 -// IC_INTR_IO ........................ 0x1 -// IC_MASTER_MODE .................... 0x1 -// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x0 -// IC_INTR_POL ....................... 0x1 -// IC_OPTIONAL_SAR ................... 0x0 -// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 -// IC_DEFAULT_SLAVE_ADDR ............. 0x055 -// IC_DEFAULT_HS_SPKLEN .............. 0x1 -// IC_FS_SCL_HIGH_COUNT .............. 0x003c -// IC_HS_SCL_LOW_COUNT ............... 0x0010 -// IC_DEVICE_ID_VALUE ................ 0x0 -// IC_10BITADDR_MASTER ............... 0x0 -// IC_CLK_FREQ_OPTIMIZATION .......... 0x0 -// IC_DEFAULT_FS_SPKLEN .............. 0xf -// IC_ADD_ENCODED_PARAMS ............. 0x1 -// IC_DEFAULT_SDA_HOLD ............... 0x000001 -// IC_DEFAULT_SDA_SETUP .............. 0x64 -// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 -// SLVERR_RESP_EN .................... 0 -// IC_RESTART_EN ..................... 0x1 -// IC_TX_CMD_BLOCK ................... 0x1 -// HC_REG_TIMEOUT_VALUE .............. 0 -// IC_BUS_CLEAR_FEATURE .............. 0x1 -// IC_CAP_LOADING .................... 100 -// IC_HAS_ASYNC_FIFO ................. 0x0 -// IC_FS_SCL_LOW_COUNT ............... 0x0082 -// APB_DATA_WIDTH .................... 32 -// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff -// IC_SLV_DATA_NACK_ONLY ............. 0x1 -// IC_10BITADDR_SLAVE ................ 0x0 -// IC_TX_BUFFER_DEPTH ................ 32 -// IC_DEFAULT_UFM_SPKLEN ............. 0x1 -// IC_CLK_TYPE ....................... 0x0 -// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 -// IC_SMBUS_UDID_MSB ................. 0x0 -// IC_SMBUS_SUSPEND_ALERT ............ 0x0 -// IC_HS_SCL_HIGH_COUNT .............. 0x0006 -// IC_SLV_RESTART_DET_EN ............. 0x1 -// IC_SMBUS .......................... 0x1 -// IC_STAT_FOR_CLK_STRETCH ........... 0x1 -// IC_MAX_SPEED_MODE ................. 0x2 -// IC_OPTIONAL_SAR_DEFAULT ........... 0x0 -// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 -// IC_USE_COUNTS ..................... 0x1 -// IC_RX_BUFFER_DEPTH ................ 32 -// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff -// IC_RX_FULL_HLD_BUS_EN ............. 0x1 -// IC_SLAVE_DISABLE .................. 0x1 -// IC_RX_TL .......................... 0x0 -// IC_DEVICE_ID ...................... 0x0 -// IC_HC_COUNT_VALUES ................ 0x0 -// I2C_DYNAMIC_TAR_UPDATE ............ 1 -// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff -// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff -// IC_HS_MASTER_CODE ................. 0x1 -// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff -// IC_UFM_SCL_LOW_COUNT .............. 0x0008 -// IC_SMBUS_UDID_HC .................. 0x1 -// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff -// IC_SS_SCL_HIGH_COUNT .............. 0x0190 - #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/interp.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/interp.h index 683750733..e96caab2f 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/interp.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/interp.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,16 +10,68 @@ #define _HARDWARE_STRUCTS_INTERP_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/sio.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0 + // (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes) + // + // Read/write access to accumulator 0 io_rw_32 accum[2]; + + _REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0 + // (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes) + // + // Read/write access to BASE0 register io_rw_32 base[3]; + + _REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0 + // (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes) + // + // Read LANE0 result, and simultaneously write lane results to both accumulators (POP) io_ro_32 pop[3]; + + _REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0 + // (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes) + // + // Read LANE0 result, without altering any internal state (PEEK) io_ro_32 peek[3]; + + _REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0 + // (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes) + // + // Control register for lane 0 + // 0x02000000 [25] : OVERF (0): Set if either OVERF0 or OVERF1 is set + // 0x01000000 [24] : OVERF1 (0): Indicates if any masked-off MSBs in ACCUM1 are set + // 0x00800000 [23] : OVERF0 (0): Indicates if any masked-off MSBs in ACCUM0 are set + // 0x00200000 [21] : BLEND (0): Only present on INTERP0 on each core + // 0x00180000 [20:19] : FORCE_MSB (0): ORed into bits 29:28 of the lane result presented to the processor on the bus + // 0x00040000 [18] : ADD_RAW (0): If 1, mask + shift is bypassed for LANE0 result + // 0x00020000 [17] : CROSS_RESULT (0): If 1, feed the opposite lane's result into this lane's accumulator on POP + // 0x00010000 [16] : CROSS_INPUT (0): If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware + // 0x00008000 [15] : SIGNED (0): If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + // 0x00007c00 [14:10] : MASK_MSB (0): The most-significant bit allowed to pass by the mask (inclusive) + // 0x000003e0 [9:5] : MASK_LSB (0): The least-significant bit allowed to pass by the mask (inclusive) + // 0x0000001f [4:0] : SHIFT (0): Logical right-shift applied to accumulator before masking io_rw_32 ctrl[2]; + + _REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD + // (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes) + // + // Values written here are atomically added to ACCUM0 + // 0x00ffffff [23:0] : INTERP0_ACCUM0_ADD (0) io_rw_32 add_raw[2]; + + _REG_(SIO_INTERP0_BASE_1AND0_OFFSET) // SIO_INTERP0_BASE_1AND0 + // On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously io_wo_32 base01; } interp_hw_t; diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/iobank0.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/iobank0.h index b19800fa7..aae74b2a6 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/iobank0.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/iobank0.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,28 +10,207 @@ #define _HARDWARE_STRUCTS_IOBANK0_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/io_bank0.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_bank0 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(IO_BANK0_GPIO0_STATUS_OFFSET) // IO_BANK0_GPIO0_STATUS + // GPIO status + // 0x04000000 [26] : IRQTOPROC (0): interrupt to processors, after override is applied + // 0x01000000 [24] : IRQFROMPAD (0): interrupt from pad before override is applied + // 0x00080000 [19] : INTOPERI (0): input signal to peripheral, after override is applied + // 0x00020000 [17] : INFROMPAD (0): input signal from pad, before override is applied + // 0x00002000 [13] : OETOPAD (0): output enable to pad after register override is applied + // 0x00001000 [12] : OEFROMPERI (0): output enable from selected peripheral, before register override is applied + // 0x00000200 [9] : OUTTOPAD (0): output signal to pad after register override is applied + // 0x00000100 [8] : OUTFROMPERI (0): output signal from selected peripheral, before register override is applied + io_ro_32 status; + + _REG_(IO_BANK0_GPIO0_CTRL_OFFSET) // IO_BANK0_GPIO0_CTRL + // GPIO control including function select and overrides + // 0x30000000 [29:28] : IRQOVER (0) + // 0x00030000 [17:16] : INOVER (0) + // 0x00003000 [13:12] : OEOVER (0) + // 0x00000300 [9:8] : OUTOVER (0) + // 0x0000001f [4:0] : FUNCSEL (0x1f): 0-31 -> selects pin function according to the gpio table + io_rw_32 ctrl; +} iobank0_status_ctrl_hw_t; + +typedef struct { + _REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0 + // (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes) + // + // Interrupt Enable for proc0 + // 0x80000000 [31] : GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] : GPIO7_EDGE_LOW (0) + // 0x20000000 [29] : GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] : GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] : GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] : GPIO6_EDGE_LOW (0) + // 0x02000000 [25] : GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] : GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] : GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] : GPIO5_EDGE_LOW (0) + // 0x00200000 [21] : GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] : GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] : GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] : GPIO4_EDGE_LOW (0) + // 0x00020000 [17] : GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] : GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] : GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] : GPIO3_EDGE_LOW (0) + // 0x00002000 [13] : GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] : GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] : GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] : GPIO2_EDGE_LOW (0) + // 0x00000200 [9] : GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] : GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] : GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] : GPIO1_EDGE_LOW (0) + // 0x00000020 [5] : GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] : GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] : GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] : GPIO0_EDGE_LOW (0) + // 0x00000002 [1] : GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] : GPIO0_LEVEL_LOW (0) io_rw_32 inte[4]; + + _REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0 + // (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes) + // + // Interrupt Force for proc0 + // 0x80000000 [31] : GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] : GPIO7_EDGE_LOW (0) + // 0x20000000 [29] : GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] : GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] : GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] : GPIO6_EDGE_LOW (0) + // 0x02000000 [25] : GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] : GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] : GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] : GPIO5_EDGE_LOW (0) + // 0x00200000 [21] : GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] : GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] : GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] : GPIO4_EDGE_LOW (0) + // 0x00020000 [17] : GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] : GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] : GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] : GPIO3_EDGE_LOW (0) + // 0x00002000 [13] : GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] : GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] : GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] : GPIO2_EDGE_LOW (0) + // 0x00000200 [9] : GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] : GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] : GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] : GPIO1_EDGE_LOW (0) + // 0x00000020 [5] : GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] : GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] : GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] : GPIO0_EDGE_LOW (0) + // 0x00000002 [1] : GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] : GPIO0_LEVEL_LOW (0) io_rw_32 intf[4]; - io_rw_32 ints[4]; + + _REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0 + // (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes) + // + // Interrupt status after masking & forcing for proc0 + // 0x80000000 [31] : GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] : GPIO7_EDGE_LOW (0) + // 0x20000000 [29] : GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] : GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] : GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] : GPIO6_EDGE_LOW (0) + // 0x02000000 [25] : GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] : GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] : GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] : GPIO5_EDGE_LOW (0) + // 0x00200000 [21] : GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] : GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] : GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] : GPIO4_EDGE_LOW (0) + // 0x00020000 [17] : GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] : GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] : GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] : GPIO3_EDGE_LOW (0) + // 0x00002000 [13] : GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] : GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] : GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] : GPIO2_EDGE_LOW (0) + // 0x00000200 [9] : GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] : GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] : GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] : GPIO1_EDGE_LOW (0) + // 0x00000020 [5] : GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] : GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] : GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] : GPIO0_EDGE_LOW (0) + // 0x00000002 [1] : GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] : GPIO0_LEVEL_LOW (0) + io_ro_32 ints[4]; } io_irq_ctrl_hw_t; /// \tag::iobank0_hw[] typedef struct { - struct { - io_rw_32 status; - io_rw_32 ctrl; - } io[30]; + iobank0_status_ctrl_hw_t io[NUM_BANK0_GPIOS]; // 30 + + _REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0 + // (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes) + // + // Raw Interrupts + // 0x80000000 [31] : GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] : GPIO7_EDGE_LOW (0) + // 0x20000000 [29] : GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] : GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] : GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] : GPIO6_EDGE_LOW (0) + // 0x02000000 [25] : GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] : GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] : GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] : GPIO5_EDGE_LOW (0) + // 0x00200000 [21] : GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] : GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] : GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] : GPIO4_EDGE_LOW (0) + // 0x00020000 [17] : GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] : GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] : GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] : GPIO3_EDGE_LOW (0) + // 0x00002000 [13] : GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] : GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] : GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] : GPIO2_EDGE_LOW (0) + // 0x00000200 [9] : GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] : GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] : GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] : GPIO1_EDGE_LOW (0) + // 0x00000020 [5] : GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] : GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] : GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] : GPIO0_EDGE_LOW (0) + // 0x00000002 [1] : GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] : GPIO0_LEVEL_LOW (0) io_rw_32 intr[4]; + io_irq_ctrl_hw_t proc0_irq_ctrl; + io_irq_ctrl_hw_t proc1_irq_ctrl; + io_irq_ctrl_hw_t dormant_wake_irq_ctrl; } iobank0_hw_t; -/// \end::iobank0_hw[] #define iobank0_hw ((iobank0_hw_t *const)IO_BANK0_BASE) +/// \end::iobank0_hw[] + +static_assert( NUM_BANK0_GPIOS == 30, ""); #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ioqspi.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ioqspi.h index 48d08a7c9..2992bfe52 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ioqspi.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ioqspi.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,16 +10,165 @@ #define _HARDWARE_STRUCTS_IOQSPI_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/io_qspi.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_qspi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + +typedef struct { + _REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS + // GPIO status + // 0x04000000 [26] : IRQTOPROC (0): interrupt to processors, after override is applied + // 0x01000000 [24] : IRQFROMPAD (0): interrupt from pad before override is applied + // 0x00080000 [19] : INTOPERI (0): input signal to peripheral, after override is applied + // 0x00020000 [17] : INFROMPAD (0): input signal from pad, before override is applied + // 0x00002000 [13] : OETOPAD (0): output enable to pad after register override is applied + // 0x00001000 [12] : OEFROMPERI (0): output enable from selected peripheral, before register override is applied + // 0x00000200 [9] : OUTTOPAD (0): output signal to pad after register override is applied + // 0x00000100 [8] : OUTFROMPERI (0): output signal from selected peripheral, before register override is applied + io_ro_32 status; + + _REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL + // GPIO control including function select and overrides + // 0x30000000 [29:28] : IRQOVER (0) + // 0x00030000 [17:16] : INOVER (0) + // 0x00003000 [13:12] : OEOVER (0) + // 0x00000300 [9:8] : OUTOVER (0) + // 0x0000001f [4:0] : FUNCSEL (0x1f): 0-31 -> selects pin function according to the gpio table + io_rw_32 ctrl; +} ioqspi_status_ctrl_hw_t; + +typedef struct { + _REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE + // Interrupt Enable for proc0 + // 0x00800000 [23] : GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x00400000 [22] : GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x00200000 [21] : GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x00100000 [20] : GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x00080000 [19] : GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x00040000 [18] : GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x00020000 [17] : GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x00010000 [16] : GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00008000 [15] : GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00004000 [14] : GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00002000 [13] : GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00001000 [12] : GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00000800 [11] : GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00000400 [10] : GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00000200 [9] : GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00000100 [8] : GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00000080 [7] : GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00000040 [6] : GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00000020 [5] : GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00000010 [4] : GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000008 [3] : GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000004 [2] : GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000002 [1] : GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000001 [0] : GPIO_QSPI_SCLK_LEVEL_LOW (0) + io_rw_32 inte; + + _REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF + // Interrupt Force for proc0 + // 0x00800000 [23] : GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x00400000 [22] : GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x00200000 [21] : GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x00100000 [20] : GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x00080000 [19] : GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x00040000 [18] : GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x00020000 [17] : GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x00010000 [16] : GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00008000 [15] : GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00004000 [14] : GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00002000 [13] : GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00001000 [12] : GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00000800 [11] : GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00000400 [10] : GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00000200 [9] : GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00000100 [8] : GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00000080 [7] : GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00000040 [6] : GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00000020 [5] : GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00000010 [4] : GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000008 [3] : GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000004 [2] : GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000002 [1] : GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000001 [0] : GPIO_QSPI_SCLK_LEVEL_LOW (0) + io_rw_32 intf; + + _REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS + // Interrupt status after masking & forcing for proc0 + // 0x00800000 [23] : GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x00400000 [22] : GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x00200000 [21] : GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x00100000 [20] : GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x00080000 [19] : GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x00040000 [18] : GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x00020000 [17] : GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x00010000 [16] : GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00008000 [15] : GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00004000 [14] : GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00002000 [13] : GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00001000 [12] : GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00000800 [11] : GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00000400 [10] : GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00000200 [9] : GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00000100 [8] : GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00000080 [7] : GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00000040 [6] : GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00000020 [5] : GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00000010 [4] : GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000008 [3] : GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000004 [2] : GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000002 [1] : GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000001 [0] : GPIO_QSPI_SCLK_LEVEL_LOW (0) + io_ro_32 ints; +} io_qspi_ctrl_hw_t; + typedef struct { - struct { - io_rw_32 status; - io_rw_32 ctrl; - } io[6]; + ioqspi_status_ctrl_hw_t io[NUM_QSPI_GPIOS]; // 6 + + _REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR + // Raw Interrupts + // 0x00800000 [23] : GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x00400000 [22] : GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x00200000 [21] : GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x00100000 [20] : GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x00080000 [19] : GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x00040000 [18] : GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x00020000 [17] : GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x00010000 [16] : GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00008000 [15] : GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00004000 [14] : GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00002000 [13] : GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00001000 [12] : GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00000800 [11] : GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00000400 [10] : GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00000200 [9] : GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00000100 [8] : GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00000080 [7] : GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00000040 [6] : GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00000020 [5] : GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00000010 [4] : GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000008 [3] : GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000004 [2] : GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000002 [1] : GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000001 [0] : GPIO_QSPI_SCLK_LEVEL_LOW (0) + io_rw_32 intr; + + io_qspi_ctrl_hw_t proc0_qspi_ctrl; + + io_qspi_ctrl_hw_t proc1_qspi_ctrl; + + io_qspi_ctrl_hw_t dormant_wake_qspi_ctrl; } ioqspi_hw_t; #define ioqspi_hw ((ioqspi_hw_t *const)IO_QSPI_BASE) +static_assert( NUM_QSPI_GPIOS == 6, ""); + #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/mpu.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/mpu.h index 34e5c39e8..e6472209b 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/mpu.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/mpu.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,11 +12,47 @@ #include "hardware/address_mapped.h" #include "hardware/regs/m0plus.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE + // Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports + // 0x00ff0000 [23:16] : IREGION (0): Instruction region + // 0x0000ff00 [15:8] : DREGION (0x8): Number of regions supported by the MPU + // 0x00000001 [0] : SEPARATE (0): Indicates support for separate instruction and data address maps io_ro_32 type; + + _REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL + // Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled... + // 0x00000004 [2] : PRIVDEFENA (0): Controls whether the default memory map is enabled as a background region for... + // 0x00000002 [1] : HFNMIENA (0): Controls the use of the MPU for HardFaults and NMIs + // 0x00000001 [0] : ENABLE (0): Enables the MPU io_rw_32 ctrl; + + _REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR + // Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR + // 0x0000000f [3:0] : REGION (0): Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers io_rw_32 rnr; + + _REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR + // Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR + // 0xffffff00 [31:8] : ADDR (0): Base address of the region + // 0x00000010 [4] : VALID (0): On writes, indicates whether the write must update the base address of the region... + // 0x0000000f [3:0] : REGION (0): On writes, specifies the number of the region whose base address to update provided... io_rw_32 rbar; + + _REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR + // Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region... + // 0xffff0000 [31:16] : ATTRS (0): The MPU Region Attribute field + // 0x0000ff00 [15:8] : SRD (0): Subregion Disable + // 0x0000003e [5:1] : SIZE (0): Indicates the region size + // 0x00000001 [0] : ENABLE (0): Enables the region io_rw_32 rasr; } mpu_hw_t; diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h index 451d7ebc3..8036cd940 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,14 +10,38 @@ #define _HARDWARE_STRUCTS_PADS_QSPI_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/pads_qspi.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_qspi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pads_qspi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(PADS_QSPI_VOLTAGE_SELECT_OFFSET) // PADS_QSPI_VOLTAGE_SELECT + // Voltage select + // 0x00000001 [0] : VOLTAGE_SELECT (0) io_rw_32 voltage_select; - io_rw_32 io[6]; + + _REG_(PADS_QSPI_GPIO_QSPI_SCLK_OFFSET) // PADS_QSPI_GPIO_QSPI_SCLK + // (Description copied from array index 0 register PADS_QSPI_GPIO_QSPI_SCLK applies similarly to other array indexes) + // + // Pad control register + // 0x00000080 [7] : OD (0): Output disable + // 0x00000040 [6] : IE (1): Input enable + // 0x00000030 [5:4] : DRIVE (1): Drive strength + // 0x00000008 [3] : PUE (0): Pull up enable + // 0x00000004 [2] : PDE (1): Pull down enable + // 0x00000002 [1] : SCHMITT (1): Enable schmitt trigger + // 0x00000001 [0] : SLEWFAST (0): Slew rate control + io_rw_32 io[NUM_QSPI_GPIOS]; // 6 } pads_qspi_hw_t; #define pads_qspi_hw ((pads_qspi_hw_t *const)PADS_QSPI_BASE) +static_assert( NUM_QSPI_GPIOS == 6, ""); + #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/padsbank0.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/padsbank0.h index f56dc4011..2c067fa95 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/padsbank0.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/padsbank0.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,14 +10,38 @@ #define _HARDWARE_STRUCTS_PADSBANK0_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/pads_bank0.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_bank0 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pads_bank0.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(PADS_BANK0_VOLTAGE_SELECT_OFFSET) // PADS_BANK0_VOLTAGE_SELECT + // Voltage select + // 0x00000001 [0] : VOLTAGE_SELECT (0) io_rw_32 voltage_select; - io_rw_32 io[30]; + + _REG_(PADS_BANK0_GPIO0_OFFSET) // PADS_BANK0_GPIO0 + // (Description copied from array index 0 register PADS_BANK0_GPIO0 applies similarly to other array indexes) + // + // Pad control register + // 0x00000080 [7] : OD (0): Output disable + // 0x00000040 [6] : IE (1): Input enable + // 0x00000030 [5:4] : DRIVE (1): Drive strength + // 0x00000008 [3] : PUE (0): Pull up enable + // 0x00000004 [2] : PDE (1): Pull down enable + // 0x00000002 [1] : SCHMITT (1): Enable schmitt trigger + // 0x00000001 [0] : SLEWFAST (0): Slew rate control + io_rw_32 io[NUM_BANK0_GPIOS]; // 30 } padsbank0_hw_t; -#define padsbank0_hw ((padsbank0_hw_t *)PADS_BANK0_BASE) +#define padsbank0_hw ((padsbank0_hw_t *const)PADS_BANK0_BASE) + +static_assert( NUM_BANK0_GPIOS == 30, ""); #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pio.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pio.h index 176863bb4..515e4d1a0 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pio.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pio.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,41 +10,275 @@ #define _HARDWARE_STRUCTS_PIO_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/pio.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + +typedef struct pio_sm_hw { + _REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV + // Clock divisor register for state machine 0 + // 0xffff0000 [31:16] : INT (1): Effective frequency is sysclk/(int + frac/256) + // 0x0000ff00 [15:8] : FRAC (0): Fractional part of clock divisor + io_rw_32 clkdiv; + + _REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL + // Execution/behavioural settings for state machine 0 + // 0x80000000 [31] : EXEC_STALLED (0): If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine + // 0x40000000 [30] : SIDE_EN (0): If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable,... + // 0x20000000 [29] : SIDE_PINDIR (0): If 1, side-set data is asserted to pin directions, instead of pin values + // 0x1f000000 [28:24] : JMP_PIN (0): The GPIO number to use as condition for JMP PIN + // 0x00f80000 [23:19] : OUT_EN_SEL (0): Which data bit to use for inline OUT enable + // 0x00040000 [18] : INLINE_OUT_EN (0): If 1, use a bit of OUT data as an auxiliary write enable + // 0x00020000 [17] : OUT_STICKY (0): Continuously assert the most recent OUT/SET to the pins + // 0x0001f000 [16:12] : WRAP_TOP (0x1f): After reaching this address, execution is wrapped to wrap_bottom + // 0x00000f80 [11:7] : WRAP_BOTTOM (0): After reaching wrap_top, execution is wrapped to this address + // 0x00000010 [4] : STATUS_SEL (0): Comparison used for the MOV x, STATUS instruction + // 0x0000000f [3:0] : STATUS_N (0): Comparison level for the MOV x, STATUS instruction + io_rw_32 execctrl; + + _REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL + // Control behaviour of the input/output shift registers for state machine 0 + // 0x80000000 [31] : FJOIN_RX (0): When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep + // 0x40000000 [30] : FJOIN_TX (0): When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep + // 0x3e000000 [29:25] : PULL_THRESH (0): Number of bits shifted out of OSR before autopull, or conditional pull (PULL... + // 0x01f00000 [24:20] : PUSH_THRESH (0): Number of bits shifted into ISR before autopush, or conditional push (PUSH... + // 0x00080000 [19] : OUT_SHIFTDIR (1): 1 = shift out of output shift register to right + // 0x00040000 [18] : IN_SHIFTDIR (1): 1 = shift input shift register to right (data enters from left) + // 0x00020000 [17] : AUTOPULL (0): Pull automatically when the output shift register is emptied, i + // 0x00010000 [16] : AUTOPUSH (0): Push automatically when the input shift register is filled, i + io_rw_32 shiftctrl; + + _REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR + // Current instruction address of state machine 0 + // 0x0000001f [4:0] : SM0_ADDR (0) + io_ro_32 addr; + + _REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR + // Read to see the instruction currently addressed by state machine 0's program counter + // 0x0000ffff [15:0] : SM0_INSTR (0) + io_rw_32 instr; + + _REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL + // State machine pin control + // 0xe0000000 [31:29] : SIDESET_COUNT (0): The number of MSBs of the Delay/Side-set instruction field which are used... + // 0x1c000000 [28:26] : SET_COUNT (0x5): The number of pins asserted by a SET + // 0x03f00000 [25:20] : OUT_COUNT (0): The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction + // 0x000f8000 [19:15] : IN_BASE (0): The pin which is mapped to the least-significant bit of a state machine's IN data bus + // 0x00007c00 [14:10] : SIDESET_BASE (0): The lowest-numbered pin that will be affected by a side-set operation + // 0x000003e0 [9:5] : SET_BASE (0): The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction + // 0x0000001f [4:0] : OUT_BASE (0): The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV... + io_rw_32 pinctrl; +} pio_sm_hw_t; + typedef struct { + _REG_(PIO_CTRL_OFFSET) // PIO_CTRL + // PIO control register + // 0x00000f00 [11:8] : CLKDIV_RESTART (0): Restart a state machine's clock divider from an initial phase of 0 + // 0x000000f0 [7:4] : SM_RESTART (0): Write 1 to instantly clear internal SM state which may be otherwise difficult... + // 0x0000000f [3:0] : SM_ENABLE (0): Enable/disable each of the four state machines by writing 1/0 to each of these four bits io_rw_32 ctrl; + + _REG_(PIO_FSTAT_OFFSET) // PIO_FSTAT + // FIFO status register + // 0x0f000000 [27:24] : TXEMPTY (0xf): State machine TX FIFO is empty + // 0x000f0000 [19:16] : TXFULL (0): State machine TX FIFO is full + // 0x00000f00 [11:8] : RXEMPTY (0xf): State machine RX FIFO is empty + // 0x0000000f [3:0] : RXFULL (0): State machine RX FIFO is full io_ro_32 fstat; + + _REG_(PIO_FDEBUG_OFFSET) // PIO_FDEBUG + // FIFO debug register + // 0x0f000000 [27:24] : TXSTALL (0): State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with... + // 0x000f0000 [19:16] : TXOVER (0): TX FIFO overflow (i + // 0x00000f00 [11:8] : RXUNDER (0): RX FIFO underflow (i + // 0x0000000f [3:0] : RXSTALL (0): State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with... io_rw_32 fdebug; + + _REG_(PIO_FLEVEL_OFFSET) // PIO_FLEVEL + // FIFO levels + // 0xf0000000 [31:28] : RX3 (0) + // 0x0f000000 [27:24] : TX3 (0) + // 0x00f00000 [23:20] : RX2 (0) + // 0x000f0000 [19:16] : TX2 (0) + // 0x0000f000 [15:12] : RX1 (0) + // 0x00000f00 [11:8] : TX1 (0) + // 0x000000f0 [7:4] : RX0 (0) + // 0x0000000f [3:0] : TX0 (0) io_ro_32 flevel; - io_wo_32 txf[NUM_PIO_STATE_MACHINES]; - io_ro_32 rxf[NUM_PIO_STATE_MACHINES]; + + _REG_(PIO_TXF0_OFFSET) // PIO_TXF0 + // (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes) + // + // Direct write access to the TX FIFO for this state machine + io_wo_32 txf[NUM_PIO_STATE_MACHINES]; // 4 + + _REG_(PIO_RXF0_OFFSET) // PIO_RXF0 + // (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes) + // + // Direct read access to the RX FIFO for this state machine + io_ro_32 rxf[NUM_PIO_STATE_MACHINES]; // 4 + + _REG_(PIO_IRQ_OFFSET) // PIO_IRQ + // State machine IRQ flags register + // 0x000000ff [7:0] : IRQ (0) io_rw_32 irq; + + _REG_(PIO_IRQ_FORCE_OFFSET) // PIO_IRQ_FORCE + // Writing a 1 to each of these bits will forcibly assert the corresponding IRQ + // 0x000000ff [7:0] : IRQ_FORCE (0) io_wo_32 irq_force; + + _REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) // PIO_INPUT_SYNC_BYPASS + // There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities io_rw_32 input_sync_bypass; - io_rw_32 dbg_padout; - io_rw_32 dbg_padoe; - io_rw_32 dbg_cfginfo; - io_wo_32 instr_mem[32]; - struct pio_sm_hw { - io_rw_32 clkdiv; - io_rw_32 execctrl; - io_rw_32 shiftctrl; - io_ro_32 addr; - io_rw_32 instr; - io_rw_32 pinctrl; - } sm[NUM_PIO_STATE_MACHINES]; - io_rw_32 intr; + + _REG_(PIO_DBG_PADOUT_OFFSET) // PIO_DBG_PADOUT + // Read to sample the pad output values PIO is currently driving to the GPIOs + io_ro_32 dbg_padout; + + _REG_(PIO_DBG_PADOE_OFFSET) // PIO_DBG_PADOE + // Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs + io_ro_32 dbg_padoe; + + _REG_(PIO_DBG_CFGINFO_OFFSET) // PIO_DBG_CFGINFO + // The PIO hardware has some free parameters that may vary between chip products + // 0x003f0000 [21:16] : IMEM_SIZE (0): The size of the instruction memory, measured in units of one instruction + // 0x00000f00 [11:8] : SM_COUNT (0): The number of state machines this PIO instance is equipped with + // 0x0000003f [5:0] : FIFO_DEPTH (0): The depth of the state machine TX/RX FIFOs, measured in words + io_ro_32 dbg_cfginfo; + + _REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0 + // (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes) + // + // Write-only access to instruction memory location 0 + // 0x0000ffff [15:0] : INSTR_MEM0 (0) + io_wo_32 instr_mem[PIO_INSTRUCTION_COUNT]; // 32 + + pio_sm_hw_t sm[NUM_PIO_STATE_MACHINES]; // 4 + + _REG_(PIO_INTR_OFFSET) // PIO_INTR + // Raw Interrupts + // 0x00000800 [11] : SM3 (0) + // 0x00000400 [10] : SM2 (0) + // 0x00000200 [9] : SM1 (0) + // 0x00000100 [8] : SM0 (0) + // 0x00000080 [7] : SM3_TXNFULL (0) + // 0x00000040 [6] : SM2_TXNFULL (0) + // 0x00000020 [5] : SM1_TXNFULL (0) + // 0x00000010 [4] : SM0_TXNFULL (0) + // 0x00000008 [3] : SM3_RXNEMPTY (0) + // 0x00000004 [2] : SM2_RXNEMPTY (0) + // 0x00000002 [1] : SM1_RXNEMPTY (0) + // 0x00000001 [0] : SM0_RXNEMPTY (0) + io_ro_32 intr; + + _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE + // Interrupt Enable for irq0 + // 0x00000800 [11] : SM3 (0) + // 0x00000400 [10] : SM2 (0) + // 0x00000200 [9] : SM1 (0) + // 0x00000100 [8] : SM0 (0) + // 0x00000080 [7] : SM3_TXNFULL (0) + // 0x00000040 [6] : SM2_TXNFULL (0) + // 0x00000020 [5] : SM1_TXNFULL (0) + // 0x00000010 [4] : SM0_TXNFULL (0) + // 0x00000008 [3] : SM3_RXNEMPTY (0) + // 0x00000004 [2] : SM2_RXNEMPTY (0) + // 0x00000002 [1] : SM1_RXNEMPTY (0) + // 0x00000001 [0] : SM0_RXNEMPTY (0) io_rw_32 inte0; + + _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF + // Interrupt Force for irq0 + // 0x00000800 [11] : SM3 (0) + // 0x00000400 [10] : SM2 (0) + // 0x00000200 [9] : SM1 (0) + // 0x00000100 [8] : SM0 (0) + // 0x00000080 [7] : SM3_TXNFULL (0) + // 0x00000040 [6] : SM2_TXNFULL (0) + // 0x00000020 [5] : SM1_TXNFULL (0) + // 0x00000010 [4] : SM0_TXNFULL (0) + // 0x00000008 [3] : SM3_RXNEMPTY (0) + // 0x00000004 [2] : SM2_RXNEMPTY (0) + // 0x00000002 [1] : SM1_RXNEMPTY (0) + // 0x00000001 [0] : SM0_RXNEMPTY (0) io_rw_32 intf0; + + _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS + // Interrupt status after masking & forcing for irq0 + // 0x00000800 [11] : SM3 (0) + // 0x00000400 [10] : SM2 (0) + // 0x00000200 [9] : SM1 (0) + // 0x00000100 [8] : SM0 (0) + // 0x00000080 [7] : SM3_TXNFULL (0) + // 0x00000040 [6] : SM2_TXNFULL (0) + // 0x00000020 [5] : SM1_TXNFULL (0) + // 0x00000010 [4] : SM0_TXNFULL (0) + // 0x00000008 [3] : SM3_RXNEMPTY (0) + // 0x00000004 [2] : SM2_RXNEMPTY (0) + // 0x00000002 [1] : SM1_RXNEMPTY (0) + // 0x00000001 [0] : SM0_RXNEMPTY (0) io_ro_32 ints0; + + _REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE + // Interrupt Enable for irq1 + // 0x00000800 [11] : SM3 (0) + // 0x00000400 [10] : SM2 (0) + // 0x00000200 [9] : SM1 (0) + // 0x00000100 [8] : SM0 (0) + // 0x00000080 [7] : SM3_TXNFULL (0) + // 0x00000040 [6] : SM2_TXNFULL (0) + // 0x00000020 [5] : SM1_TXNFULL (0) + // 0x00000010 [4] : SM0_TXNFULL (0) + // 0x00000008 [3] : SM3_RXNEMPTY (0) + // 0x00000004 [2] : SM2_RXNEMPTY (0) + // 0x00000002 [1] : SM1_RXNEMPTY (0) + // 0x00000001 [0] : SM0_RXNEMPTY (0) io_rw_32 inte1; + + _REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF + // Interrupt Force for irq1 + // 0x00000800 [11] : SM3 (0) + // 0x00000400 [10] : SM2 (0) + // 0x00000200 [9] : SM1 (0) + // 0x00000100 [8] : SM0 (0) + // 0x00000080 [7] : SM3_TXNFULL (0) + // 0x00000040 [6] : SM2_TXNFULL (0) + // 0x00000020 [5] : SM1_TXNFULL (0) + // 0x00000010 [4] : SM0_TXNFULL (0) + // 0x00000008 [3] : SM3_RXNEMPTY (0) + // 0x00000004 [2] : SM2_RXNEMPTY (0) + // 0x00000002 [1] : SM1_RXNEMPTY (0) + // 0x00000001 [0] : SM0_RXNEMPTY (0) io_rw_32 intf1; + + _REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS + // Interrupt status after masking & forcing for irq1 + // 0x00000800 [11] : SM3 (0) + // 0x00000400 [10] : SM2 (0) + // 0x00000200 [9] : SM1 (0) + // 0x00000100 [8] : SM0 (0) + // 0x00000080 [7] : SM3_TXNFULL (0) + // 0x00000040 [6] : SM2_TXNFULL (0) + // 0x00000020 [5] : SM1_TXNFULL (0) + // 0x00000010 [4] : SM0_TXNFULL (0) + // 0x00000008 [3] : SM3_RXNEMPTY (0) + // 0x00000004 [2] : SM2_RXNEMPTY (0) + // 0x00000002 [1] : SM1_RXNEMPTY (0) + // 0x00000001 [0] : SM0_RXNEMPTY (0) io_ro_32 ints1; } pio_hw_t; #define pio0_hw ((pio_hw_t *const)PIO0_BASE) #define pio1_hw ((pio_hw_t *const)PIO1_BASE) +static_assert( NUM_PIO_STATE_MACHINES == 4, ""); +static_assert( PIO_INSTRUCTION_COUNT == 32, ""); + #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pll.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pll.h index 4d5b5b78c..5a506e3e9 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pll.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pll.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,11 +12,40 @@ #include "hardware/address_mapped.h" #include "hardware/regs/pll.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pll +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pll.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + /// \tag::pll_hw[] typedef struct { + _REG_(PLL_CS_OFFSET) // PLL_CS + // Control and Status + // 0x80000000 [31] : LOCK (0): PLL is locked + // 0x00000100 [8] : BYPASS (0): Passes the reference clock to the output instead of the divided VCO + // 0x0000003f [5:0] : REFDIV (1): Divides the PLL input reference clock io_rw_32 cs; + + _REG_(PLL_PWR_OFFSET) // PLL_PWR + // Controls the PLL power modes + // 0x00000020 [5] : VCOPD (1): PLL VCO powerdown + // 0x00000008 [3] : POSTDIVPD (1): PLL post divider powerdown + // 0x00000004 [2] : DSMPD (1): PLL DSM powerdown + // 0x00000001 [0] : PD (1): PLL powerdown io_rw_32 pwr; + + _REG_(PLL_FBDIV_INT_OFFSET) // PLL_FBDIV_INT + // Feedback divisor + // 0x00000fff [11:0] : FBDIV_INT (0): see ctrl reg description for constraints io_rw_32 fbdiv_int; + + _REG_(PLL_PRIM_OFFSET) // PLL_PRIM + // Controls the PLL post dividers for the primary output + // 0x00070000 [18:16] : POSTDIV1 (0x7): divide by 1-7 + // 0x00007000 [14:12] : POSTDIV2 (0x7): divide by 1-7 io_rw_32 prim; } pll_hw_t; diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/psm.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/psm.h index cc9fb97e0..cdfb2e385 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/psm.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/psm.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,14 +10,100 @@ #define _HARDWARE_STRUCTS_PSM_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/psm.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_psm +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/psm.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(PSM_FRCE_ON_OFFSET) // PSM_FRCE_ON + // Force block out of reset (i + // 0x00010000 [16] : proc1 (0) + // 0x00008000 [15] : proc0 (0) + // 0x00004000 [14] : sio (0) + // 0x00002000 [13] : vreg_and_chip_reset (0) + // 0x00001000 [12] : xip (0) + // 0x00000800 [11] : sram5 (0) + // 0x00000400 [10] : sram4 (0) + // 0x00000200 [9] : sram3 (0) + // 0x00000100 [8] : sram2 (0) + // 0x00000080 [7] : sram1 (0) + // 0x00000040 [6] : sram0 (0) + // 0x00000020 [5] : rom (0) + // 0x00000010 [4] : busfabric (0) + // 0x00000008 [3] : resets (0) + // 0x00000004 [2] : clocks (0) + // 0x00000002 [1] : xosc (0) + // 0x00000001 [0] : rosc (0) io_rw_32 frce_on; + + _REG_(PSM_FRCE_OFF_OFFSET) // PSM_FRCE_OFF + // Force into reset (i + // 0x00010000 [16] : proc1 (0) + // 0x00008000 [15] : proc0 (0) + // 0x00004000 [14] : sio (0) + // 0x00002000 [13] : vreg_and_chip_reset (0) + // 0x00001000 [12] : xip (0) + // 0x00000800 [11] : sram5 (0) + // 0x00000400 [10] : sram4 (0) + // 0x00000200 [9] : sram3 (0) + // 0x00000100 [8] : sram2 (0) + // 0x00000080 [7] : sram1 (0) + // 0x00000040 [6] : sram0 (0) + // 0x00000020 [5] : rom (0) + // 0x00000010 [4] : busfabric (0) + // 0x00000008 [3] : resets (0) + // 0x00000004 [2] : clocks (0) + // 0x00000002 [1] : xosc (0) + // 0x00000001 [0] : rosc (0) io_rw_32 frce_off; + + _REG_(PSM_WDSEL_OFFSET) // PSM_WDSEL + // Set to 1 if this peripheral should be reset when the watchdog fires + // 0x00010000 [16] : proc1 (0) + // 0x00008000 [15] : proc0 (0) + // 0x00004000 [14] : sio (0) + // 0x00002000 [13] : vreg_and_chip_reset (0) + // 0x00001000 [12] : xip (0) + // 0x00000800 [11] : sram5 (0) + // 0x00000400 [10] : sram4 (0) + // 0x00000200 [9] : sram3 (0) + // 0x00000100 [8] : sram2 (0) + // 0x00000080 [7] : sram1 (0) + // 0x00000040 [6] : sram0 (0) + // 0x00000020 [5] : rom (0) + // 0x00000010 [4] : busfabric (0) + // 0x00000008 [3] : resets (0) + // 0x00000004 [2] : clocks (0) + // 0x00000002 [1] : xosc (0) + // 0x00000001 [0] : rosc (0) io_rw_32 wdsel; - io_rw_32 done; + + _REG_(PSM_DONE_OFFSET) // PSM_DONE + // Indicates the peripheral's registers are ready to access + // 0x00010000 [16] : proc1 (0) + // 0x00008000 [15] : proc0 (0) + // 0x00004000 [14] : sio (0) + // 0x00002000 [13] : vreg_and_chip_reset (0) + // 0x00001000 [12] : xip (0) + // 0x00000800 [11] : sram5 (0) + // 0x00000400 [10] : sram4 (0) + // 0x00000200 [9] : sram3 (0) + // 0x00000100 [8] : sram2 (0) + // 0x00000080 [7] : sram1 (0) + // 0x00000040 [6] : sram0 (0) + // 0x00000020 [5] : rom (0) + // 0x00000010 [4] : busfabric (0) + // 0x00000008 [3] : resets (0) + // 0x00000004 [2] : clocks (0) + // 0x00000002 [1] : xosc (0) + // 0x00000001 [0] : rosc (0) + io_ro_32 done; } psm_hw_t; #define psm_hw ((psm_hw_t *const)PSM_BASE) diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pwm.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pwm.h index 549956109..fd9a75ca2 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pwm.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/pwm.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,26 +10,117 @@ #define _HARDWARE_STRUCTS_PWM_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/pwm.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pwm +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pwm.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct pwm_slice_hw { + _REG_(PWM_CH0_CSR_OFFSET) // PWM_CH0_CSR + // Control and status register + // 0x00000080 [7] : PH_ADV (0): Advance the phase of the counter by 1 count, while it is running + // 0x00000040 [6] : PH_RET (0): Retard the phase of the counter by 1 count, while it is running + // 0x00000030 [5:4] : DIVMODE (0) + // 0x00000008 [3] : B_INV (0): Invert output B + // 0x00000004 [2] : A_INV (0): Invert output A + // 0x00000002 [1] : PH_CORRECT (0): 1: Enable phase-correct modulation + // 0x00000001 [0] : EN (0): Enable the PWM channel io_rw_32 csr; + + _REG_(PWM_CH0_DIV_OFFSET) // PWM_CH0_DIV + // INT and FRAC form a fixed-point fractional number + // 0x00000ff0 [11:4] : INT (1) + // 0x0000000f [3:0] : FRAC (0) io_rw_32 div; + + _REG_(PWM_CH0_CTR_OFFSET) // PWM_CH0_CTR + // Direct access to the PWM counter + // 0x0000ffff [15:0] : CH0_CTR (0) io_rw_32 ctr; + + _REG_(PWM_CH0_CC_OFFSET) // PWM_CH0_CC + // Counter compare values + // 0xffff0000 [31:16] : B (0) + // 0x0000ffff [15:0] : A (0) io_rw_32 cc; + + _REG_(PWM_CH0_TOP_OFFSET) // PWM_CH0_TOP + // Counter wrap value + // 0x0000ffff [15:0] : CH0_TOP (0xffff) io_rw_32 top; } pwm_slice_hw_t; typedef struct { - pwm_slice_hw_t slice[NUM_PWM_SLICES]; + pwm_slice_hw_t slice[NUM_PWM_SLICES]; // 8 + + _REG_(PWM_EN_OFFSET) // PWM_EN + // This register aliases the CSR_EN bits for all channels + // 0x00000080 [7] : CH7 (0) + // 0x00000040 [6] : CH6 (0) + // 0x00000020 [5] : CH5 (0) + // 0x00000010 [4] : CH4 (0) + // 0x00000008 [3] : CH3 (0) + // 0x00000004 [2] : CH2 (0) + // 0x00000002 [1] : CH1 (0) + // 0x00000001 [0] : CH0 (0) io_rw_32 en; + + _REG_(PWM_INTR_OFFSET) // PWM_INTR + // Raw Interrupts + // 0x00000080 [7] : CH7 (0) + // 0x00000040 [6] : CH6 (0) + // 0x00000020 [5] : CH5 (0) + // 0x00000010 [4] : CH4 (0) + // 0x00000008 [3] : CH3 (0) + // 0x00000004 [2] : CH2 (0) + // 0x00000002 [1] : CH1 (0) + // 0x00000001 [0] : CH0 (0) io_rw_32 intr; + + _REG_(PWM_INTE_OFFSET) // PWM_INTE + // Interrupt Enable + // 0x00000080 [7] : CH7 (0) + // 0x00000040 [6] : CH6 (0) + // 0x00000020 [5] : CH5 (0) + // 0x00000010 [4] : CH4 (0) + // 0x00000008 [3] : CH3 (0) + // 0x00000004 [2] : CH2 (0) + // 0x00000002 [1] : CH1 (0) + // 0x00000001 [0] : CH0 (0) io_rw_32 inte; + + _REG_(PWM_INTF_OFFSET) // PWM_INTF + // Interrupt Force + // 0x00000080 [7] : CH7 (0) + // 0x00000040 [6] : CH6 (0) + // 0x00000020 [5] : CH5 (0) + // 0x00000010 [4] : CH4 (0) + // 0x00000008 [3] : CH3 (0) + // 0x00000004 [2] : CH2 (0) + // 0x00000002 [1] : CH1 (0) + // 0x00000001 [0] : CH0 (0) io_rw_32 intf; - io_rw_32 ints; + + _REG_(PWM_INTS_OFFSET) // PWM_INTS + // Interrupt status after masking & forcing + // 0x00000080 [7] : CH7 (0) + // 0x00000040 [6] : CH6 (0) + // 0x00000020 [5] : CH5 (0) + // 0x00000010 [4] : CH4 (0) + // 0x00000008 [3] : CH3 (0) + // 0x00000004 [2] : CH2 (0) + // 0x00000002 [1] : CH1 (0) + // 0x00000001 [0] : CH0 (0) + io_ro_32 ints; } pwm_hw_t; #define pwm_hw ((pwm_hw_t *const)PWM_BASE) +static_assert( NUM_PWM_SLICES == 8, ""); + #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/resets.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/resets.h index a96ddebd7..bc1c10c5e 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/resets.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/resets.h @@ -1,19 +1,113 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ + #ifndef _HARDWARE_STRUCTS_RESETS_H #define _HARDWARE_STRUCTS_RESETS_H #include "hardware/address_mapped.h" #include "hardware/regs/resets.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_resets +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/resets.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + /// \tag::resets_hw[] typedef struct { + _REG_(RESETS_RESET_OFFSET) // RESETS_RESET + // Reset control + // 0x01000000 [24] : usbctrl (1) + // 0x00800000 [23] : uart1 (1) + // 0x00400000 [22] : uart0 (1) + // 0x00200000 [21] : timer (1) + // 0x00100000 [20] : tbman (1) + // 0x00080000 [19] : sysinfo (1) + // 0x00040000 [18] : syscfg (1) + // 0x00020000 [17] : spi1 (1) + // 0x00010000 [16] : spi0 (1) + // 0x00008000 [15] : rtc (1) + // 0x00004000 [14] : pwm (1) + // 0x00002000 [13] : pll_usb (1) + // 0x00001000 [12] : pll_sys (1) + // 0x00000800 [11] : pio1 (1) + // 0x00000400 [10] : pio0 (1) + // 0x00000200 [9] : pads_qspi (1) + // 0x00000100 [8] : pads_bank0 (1) + // 0x00000080 [7] : jtag (1) + // 0x00000040 [6] : io_qspi (1) + // 0x00000020 [5] : io_bank0 (1) + // 0x00000010 [4] : i2c1 (1) + // 0x00000008 [3] : i2c0 (1) + // 0x00000004 [2] : dma (1) + // 0x00000002 [1] : busctrl (1) + // 0x00000001 [0] : adc (1) io_rw_32 reset; + + _REG_(RESETS_WDSEL_OFFSET) // RESETS_WDSEL + // Watchdog select + // 0x01000000 [24] : usbctrl (0) + // 0x00800000 [23] : uart1 (0) + // 0x00400000 [22] : uart0 (0) + // 0x00200000 [21] : timer (0) + // 0x00100000 [20] : tbman (0) + // 0x00080000 [19] : sysinfo (0) + // 0x00040000 [18] : syscfg (0) + // 0x00020000 [17] : spi1 (0) + // 0x00010000 [16] : spi0 (0) + // 0x00008000 [15] : rtc (0) + // 0x00004000 [14] : pwm (0) + // 0x00002000 [13] : pll_usb (0) + // 0x00001000 [12] : pll_sys (0) + // 0x00000800 [11] : pio1 (0) + // 0x00000400 [10] : pio0 (0) + // 0x00000200 [9] : pads_qspi (0) + // 0x00000100 [8] : pads_bank0 (0) + // 0x00000080 [7] : jtag (0) + // 0x00000040 [6] : io_qspi (0) + // 0x00000020 [5] : io_bank0 (0) + // 0x00000010 [4] : i2c1 (0) + // 0x00000008 [3] : i2c0 (0) + // 0x00000004 [2] : dma (0) + // 0x00000002 [1] : busctrl (0) + // 0x00000001 [0] : adc (0) io_rw_32 wdsel; - io_rw_32 reset_done; + + _REG_(RESETS_RESET_DONE_OFFSET) // RESETS_RESET_DONE + // Reset done + // 0x01000000 [24] : usbctrl (0) + // 0x00800000 [23] : uart1 (0) + // 0x00400000 [22] : uart0 (0) + // 0x00200000 [21] : timer (0) + // 0x00100000 [20] : tbman (0) + // 0x00080000 [19] : sysinfo (0) + // 0x00040000 [18] : syscfg (0) + // 0x00020000 [17] : spi1 (0) + // 0x00010000 [16] : spi0 (0) + // 0x00008000 [15] : rtc (0) + // 0x00004000 [14] : pwm (0) + // 0x00002000 [13] : pll_usb (0) + // 0x00001000 [12] : pll_sys (0) + // 0x00000800 [11] : pio1 (0) + // 0x00000400 [10] : pio0 (0) + // 0x00000200 [9] : pads_qspi (0) + // 0x00000100 [8] : pads_bank0 (0) + // 0x00000080 [7] : jtag (0) + // 0x00000040 [6] : io_qspi (0) + // 0x00000020 [5] : io_bank0 (0) + // 0x00000010 [4] : i2c1 (0) + // 0x00000008 [3] : i2c0 (0) + // 0x00000004 [2] : dma (0) + // 0x00000002 [1] : busctrl (0) + // 0x00000001 [0] : adc (0) + io_ro_32 reset_done; } resets_hw_t; #define resets_hw ((resets_hw_t *const)RESETS_BASE) diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rosc.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rosc.h index 10543937c..114c6029f 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rosc.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rosc.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,20 +10,75 @@ #define _HARDWARE_STRUCTS_ROSC_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/rosc.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rosc +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/rosc.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(ROSC_CTRL_OFFSET) // ROSC_CTRL + // Ring Oscillator control + // 0x00fff000 [23:12] : ENABLE (0): On power-up this field is initialised to ENABLE + // 0x00000fff [11:0] : FREQ_RANGE (0xaa0): Controls the number of delay stages in the ROSC ring io_rw_32 ctrl; + + _REG_(ROSC_FREQA_OFFSET) // ROSC_FREQA + // The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage + // 0xffff0000 [31:16] : PASSWD (0): Set to 0x9696 to apply the settings + // 0x00007000 [14:12] : DS3 (0): Stage 3 drive strength + // 0x00000700 [10:8] : DS2 (0): Stage 2 drive strength + // 0x00000070 [6:4] : DS1 (0): Stage 1 drive strength + // 0x00000007 [2:0] : DS0 (0): Stage 0 drive strength io_rw_32 freqa; + + _REG_(ROSC_FREQB_OFFSET) // ROSC_FREQB + // For a detailed description see freqa register + // 0xffff0000 [31:16] : PASSWD (0): Set to 0x9696 to apply the settings + // 0x00007000 [14:12] : DS7 (0): Stage 7 drive strength + // 0x00000700 [10:8] : DS6 (0): Stage 6 drive strength + // 0x00000070 [6:4] : DS5 (0): Stage 5 drive strength + // 0x00000007 [2:0] : DS4 (0): Stage 4 drive strength io_rw_32 freqb; + + _REG_(ROSC_DORMANT_OFFSET) // ROSC_DORMANT + // Ring Oscillator pause control io_rw_32 dormant; + + _REG_(ROSC_DIV_OFFSET) // ROSC_DIV + // Controls the output divider + // 0x00000fff [11:0] : DIV (0): set to 0xaa0 + div where io_rw_32 div; + + _REG_(ROSC_PHASE_OFFSET) // ROSC_PHASE + // Controls the phase shifted output + // 0x00000ff0 [11:4] : PASSWD (0): set to 0xaa + // 0x00000008 [3] : ENABLE (1): enable the phase-shifted output + // 0x00000004 [2] : FLIP (0): invert the phase-shifted output + // 0x00000003 [1:0] : SHIFT (0): phase shift the phase-shifted output by SHIFT input clocks io_rw_32 phase; + + _REG_(ROSC_STATUS_OFFSET) // ROSC_STATUS + // Ring Oscillator Status + // 0x80000000 [31] : STABLE (0): Oscillator is running and stable + // 0x01000000 [24] : BADWRITE (0): An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or... + // 0x00010000 [16] : DIV_RUNNING (0): post-divider is running + // 0x00001000 [12] : ENABLED (0): Oscillator is enabled but not necessarily running and stable io_rw_32 status; - io_rw_32 randombit; + + _REG_(ROSC_RANDOMBIT_OFFSET) // ROSC_RANDOMBIT + // This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or... + // 0x00000001 [0] : RANDOMBIT (1) + io_ro_32 randombit; + + _REG_(ROSC_COUNT_OFFSET) // ROSC_COUNT + // A down counter running at the ROSC frequency which counts to zero and stops + // 0x000000ff [7:0] : COUNT (0) io_rw_32 count; - io_rw_32 dftx; } rosc_hw_t; #define rosc_hw ((rosc_hw_t *const)ROSC_BASE) diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rtc.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rtc.h index 276bd7a24..794a0e07a 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rtc.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/rtc.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,22 +10,103 @@ #define _HARDWARE_STRUCTS_RTC_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/rtc.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rtc +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/rtc.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(RTC_CLKDIV_M1_OFFSET) // RTC_CLKDIV_M1 + // Divider minus 1 for the 1 second counter + // 0x0000ffff [15:0] : CLKDIV_M1 (0) io_rw_32 clkdiv_m1; + + _REG_(RTC_SETUP_0_OFFSET) // RTC_SETUP_0 + // RTC setup register 0 + // 0x00fff000 [23:12] : YEAR (0): Year + // 0x00000f00 [11:8] : MONTH (0): Month (1 + // 0x0000001f [4:0] : DAY (0): Day of the month (1 io_rw_32 setup_0; + + _REG_(RTC_SETUP_1_OFFSET) // RTC_SETUP_1 + // RTC setup register 1 + // 0x07000000 [26:24] : DOTW (0): Day of the week: 1-Monday + // 0x001f0000 [20:16] : HOUR (0): Hours + // 0x00003f00 [13:8] : MIN (0): Minutes + // 0x0000003f [5:0] : SEC (0): Seconds io_rw_32 setup_1; + + _REG_(RTC_CTRL_OFFSET) // RTC_CTRL + // RTC Control and status + // 0x00000100 [8] : FORCE_NOTLEAPYEAR (0): If set, leapyear is forced off + // 0x00000010 [4] : LOAD (0): Load RTC + // 0x00000002 [1] : RTC_ACTIVE (0): RTC enabled (running) + // 0x00000001 [0] : RTC_ENABLE (0): Enable RTC io_rw_32 ctrl; + + _REG_(RTC_IRQ_SETUP_0_OFFSET) // RTC_IRQ_SETUP_0 + // Interrupt setup register 0 + // 0x20000000 [29] : MATCH_ACTIVE (0) + // 0x10000000 [28] : MATCH_ENA (0): Global match enable + // 0x04000000 [26] : YEAR_ENA (0): Enable year matching + // 0x02000000 [25] : MONTH_ENA (0): Enable month matching + // 0x01000000 [24] : DAY_ENA (0): Enable day matching + // 0x00fff000 [23:12] : YEAR (0): Year + // 0x00000f00 [11:8] : MONTH (0): Month (1 + // 0x0000001f [4:0] : DAY (0): Day of the month (1 io_rw_32 irq_setup_0; + + _REG_(RTC_IRQ_SETUP_1_OFFSET) // RTC_IRQ_SETUP_1 + // Interrupt setup register 1 + // 0x80000000 [31] : DOTW_ENA (0): Enable day of the week matching + // 0x40000000 [30] : HOUR_ENA (0): Enable hour matching + // 0x20000000 [29] : MIN_ENA (0): Enable minute matching + // 0x10000000 [28] : SEC_ENA (0): Enable second matching + // 0x07000000 [26:24] : DOTW (0): Day of the week + // 0x001f0000 [20:16] : HOUR (0): Hours + // 0x00003f00 [13:8] : MIN (0): Minutes + // 0x0000003f [5:0] : SEC (0): Seconds io_rw_32 irq_setup_1; - io_rw_32 rtc_1; - io_rw_32 rtc_0; - io_rw_32 intr; + + _REG_(RTC_RTC_1_OFFSET) // RTC_RTC_1 + // RTC register 1 + // 0x00fff000 [23:12] : YEAR (0): Year + // 0x00000f00 [11:8] : MONTH (0): Month (1 + // 0x0000001f [4:0] : DAY (0): Day of the month (1 + io_ro_32 rtc_1; + + _REG_(RTC_RTC_0_OFFSET) // RTC_RTC_0 + // RTC register 0 + // 0x07000000 [26:24] : DOTW (0): Day of the week + // 0x001f0000 [20:16] : HOUR (0): Hours + // 0x00003f00 [13:8] : MIN (0): Minutes + // 0x0000003f [5:0] : SEC (0): Seconds + io_ro_32 rtc_0; + + _REG_(RTC_INTR_OFFSET) // RTC_INTR + // Raw Interrupts + // 0x00000001 [0] : RTC (0) + io_ro_32 intr; + + _REG_(RTC_INTE_OFFSET) // RTC_INTE + // Interrupt Enable + // 0x00000001 [0] : RTC (0) io_rw_32 inte; + + _REG_(RTC_INTF_OFFSET) // RTC_INTF + // Interrupt Force + // 0x00000001 [0] : RTC (0) io_rw_32 intf; - io_rw_32 ints; + + _REG_(RTC_INTS_OFFSET) // RTC_INTS + // Interrupt status after masking & forcing + // 0x00000001 [0] : RTC (0) + io_ro_32 ints; } rtc_hw_t; #define rtc_hw ((rtc_hw_t *const)RTC_BASE) diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/scb.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/scb.h index b48a87254..42569c7e9 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/scb.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/scb.h @@ -1,22 +1,67 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ + #ifndef _HARDWARE_STRUCTS_SCB_H #define _HARDWARE_STRUCTS_SCB_H #include "hardware/address_mapped.h" #include "hardware/regs/m0plus.h" -// SCB == System Control Block +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID + // Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor... + // 0xff000000 [31:24] : IMPLEMENTER (0x41): Implementor code: 0x41 = ARM + // 0x00f00000 [23:20] : VARIANT (0): Major revision number n in the rnpm revision status: + // 0x000f0000 [19:16] : ARCHITECTURE (0xc): Constant that defines the architecture of the processor: + // 0x0000fff0 [15:4] : PARTNO (0xc60): Number of processor within family: 0xC60 = Cortex-M0+ + // 0x0000000f [3:0] : REVISION (1): Minor revision number m in the rnpm revision status: io_ro_32 cpuid; + + _REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR + // Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending... + // 0x80000000 [31] : NMIPENDSET (0): Setting this bit will activate an NMI + // 0x10000000 [28] : PENDSVSET (0): PendSV set-pending bit + // 0x08000000 [27] : PENDSVCLR (0): PendSV clear-pending bit + // 0x04000000 [26] : PENDSTSET (0): SysTick exception set-pending bit + // 0x02000000 [25] : PENDSTCLR (0): SysTick exception clear-pending bit + // 0x00800000 [23] : ISRPREEMPT (0): The system can only access this bit when the core is halted + // 0x00400000 [22] : ISRPENDING (0): External interrupt pending flag + // 0x001ff000 [20:12] : VECTPENDING (0): Indicates the exception number for the highest priority pending exception: 0 =... + // 0x000001ff [8:0] : VECTACTIVE (0): Active exception number field io_rw_32 icsr; + + _REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR + // The VTOR holds the vector table offset address + // 0xffffff00 [31:8] : TBLOFF (0): Bits [31:8] of the indicate the vector table offset address io_rw_32 vtor; + + _REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR + // Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state... + // 0xffff0000 [31:16] : VECTKEY (0): Register key: + // 0x00008000 [15] : ENDIANESS (0): Data endianness implemented: + // 0x00000004 [2] : SYSRESETREQ (0): Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be... + // 0x00000002 [1] : VECTCLRACTIVE (0): Clears all active state information for fixed and configurable exceptions io_rw_32 aircr; + + _REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR + // System Control Register + // 0x00000010 [4] : SEVONPEND (0): Send Event on Pending bit: + // 0x00000004 [2] : SLEEPDEEP (0): Controls whether the processor uses sleep or deep sleep as its low power mode: + // 0x00000002 [1] : SLEEPONEXIT (0): Indicates sleep-on-exit when returning from Handler mode to Thread mode: io_rw_32 scr; - // ... } armv6m_scb_t; #define scb_hw ((armv6m_scb_t *const)(PPB_BASE + M0PLUS_CPUID_OFFSET)) diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/sio.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/sio.h index 400083f81..00b7e7e89 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/sio.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/sio.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,51 +13,164 @@ #include "hardware/regs/sio.h" #include "hardware/structs/interp.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(SIO_CPUID_OFFSET) // SIO_CPUID + // Processor core identifier io_ro_32 cpuid; + + _REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN + // Input value for GPIO pins + // 0x3fffffff [29:0] : GPIO_IN (0): Input value for GPIO0 io_ro_32 gpio_in; + + _REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN + // Input value for QSPI pins + // 0x0000003f [5:0] : GPIO_HI_IN (0): Input value on QSPI IO in order 0 io_ro_32 gpio_hi_in; - uint32_t _pad; - io_wo_32 gpio_out; + uint32_t _pad0; + + _REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT + // GPIO output value + // 0x3fffffff [29:0] : GPIO_OUT (0): Set output level (1/0 -> high/low) for GPIO0 + io_rw_32 gpio_out; + + _REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET + // GPIO output value set + // 0x3fffffff [29:0] : GPIO_OUT_SET (0): Perform an atomic bit-set on GPIO_OUT, i io_wo_32 gpio_set; + + _REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR + // GPIO output value clear + // 0x3fffffff [29:0] : GPIO_OUT_CLR (0): Perform an atomic bit-clear on GPIO_OUT, i io_wo_32 gpio_clr; + + _REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR + // GPIO output value XOR + // 0x3fffffff [29:0] : GPIO_OUT_XOR (0): Perform an atomic bitwise XOR on GPIO_OUT, i io_wo_32 gpio_togl; - io_wo_32 gpio_oe; + _REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE + // GPIO output enable + // 0x3fffffff [29:0] : GPIO_OE (0): Set output enable (1/0 -> output/input) for GPIO0 + io_rw_32 gpio_oe; + + _REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET + // GPIO output enable set + // 0x3fffffff [29:0] : GPIO_OE_SET (0): Perform an atomic bit-set on GPIO_OE, i io_wo_32 gpio_oe_set; + + _REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR + // GPIO output enable clear + // 0x3fffffff [29:0] : GPIO_OE_CLR (0): Perform an atomic bit-clear on GPIO_OE, i io_wo_32 gpio_oe_clr; + + _REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR + // GPIO output enable XOR + // 0x3fffffff [29:0] : GPIO_OE_XOR (0): Perform an atomic bitwise XOR on GPIO_OE, i io_wo_32 gpio_oe_togl; - io_wo_32 gpio_hi_out; + _REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT + // QSPI output value + // 0x0000003f [5:0] : GPIO_HI_OUT (0): Set output level (1/0 -> high/low) for QSPI IO0 + io_rw_32 gpio_hi_out; + + _REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET + // QSPI output value set + // 0x0000003f [5:0] : GPIO_HI_OUT_SET (0): Perform an atomic bit-set on GPIO_HI_OUT, i io_wo_32 gpio_hi_set; + + _REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR + // QSPI output value clear + // 0x0000003f [5:0] : GPIO_HI_OUT_CLR (0): Perform an atomic bit-clear on GPIO_HI_OUT, i io_wo_32 gpio_hi_clr; + + _REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR + // QSPI output value XOR + // 0x0000003f [5:0] : GPIO_HI_OUT_XOR (0): Perform an atomic bitwise XOR on GPIO_HI_OUT, i io_wo_32 gpio_hi_togl; - io_wo_32 gpio_hi_oe; + _REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE + // QSPI output enable + // 0x0000003f [5:0] : GPIO_HI_OE (0): Set output enable (1/0 -> output/input) for QSPI IO0 + io_rw_32 gpio_hi_oe; + + _REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET + // QSPI output enable set + // 0x0000003f [5:0] : GPIO_HI_OE_SET (0): Perform an atomic bit-set on GPIO_HI_OE, i io_wo_32 gpio_hi_oe_set; + + _REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR + // QSPI output enable clear + // 0x0000003f [5:0] : GPIO_HI_OE_CLR (0): Perform an atomic bit-clear on GPIO_HI_OE, i io_wo_32 gpio_hi_oe_clr; + + _REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR + // QSPI output enable XOR + // 0x0000003f [5:0] : GPIO_HI_OE_XOR (0): Perform an atomic bitwise XOR on GPIO_HI_OE, i io_wo_32 gpio_hi_oe_togl; + _REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST + // Status register for inter-core FIFOs (mailboxes) + // 0x00000008 [3] : ROE (0): Sticky flag indicating the RX FIFO was read when empty + // 0x00000004 [2] : WOF (0): Sticky flag indicating the TX FIFO was written when full + // 0x00000002 [1] : RDY (1): Value is 1 if this core's TX FIFO is not full (i + // 0x00000001 [0] : VLD (0): Value is 1 if this core's RX FIFO is not empty (i io_rw_32 fifo_st; + + _REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR + // Write access to this core's TX FIFO io_wo_32 fifo_wr; + + _REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD + // Read access to this core's RX FIFO io_ro_32 fifo_rd; + + _REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST + // Spinlock state io_ro_32 spinlock_st; + _REG_(SIO_DIV_UDIVIDEND_OFFSET) // SIO_DIV_UDIVIDEND + // Divider unsigned dividend io_rw_32 div_udividend; + + _REG_(SIO_DIV_UDIVISOR_OFFSET) // SIO_DIV_UDIVISOR + // Divider unsigned divisor io_rw_32 div_udivisor; + + _REG_(SIO_DIV_SDIVIDEND_OFFSET) // SIO_DIV_SDIVIDEND + // Divider signed dividend io_rw_32 div_sdividend; + + _REG_(SIO_DIV_SDIVISOR_OFFSET) // SIO_DIV_SDIVISOR + // Divider signed divisor io_rw_32 div_sdivisor; + _REG_(SIO_DIV_QUOTIENT_OFFSET) // SIO_DIV_QUOTIENT + // Divider result quotient io_rw_32 div_quotient; - io_rw_32 div_remainder; - io_rw_32 div_csr; - uint32_t _pad2; + _REG_(SIO_DIV_REMAINDER_OFFSET) // SIO_DIV_REMAINDER + // Divider result remainder + io_rw_32 div_remainder; + _REG_(SIO_DIV_CSR_OFFSET) // SIO_DIV_CSR + // Control and status register for divider + // 0x00000002 [1] : DIRTY (0): Changes to 1 when any register is written, and back to 0 when QUOTIENT is read + // 0x00000001 [0] : READY (1): Reads as 0 when a calculation is in progress, 1 otherwise + io_ro_32 div_csr; + uint32_t _pad1; interp_hw_t interp[2]; } sio_hw_t; -#define sio_hw ((sio_hw_t *)SIO_BASE) +#define sio_hw ((sio_hw_t *const)SIO_BASE) #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/spi.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/spi.h index 5b3b2bab5..f7fffb83c 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/spi.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/spi.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,16 +12,85 @@ #include "hardware/address_mapped.h" #include "hardware/regs/spi.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_spi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/spi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(SPI_SSPCR0_OFFSET) // SPI_SSPCR0 + // Control register 0, SSPCR0 on page 3-4 + // 0x0000ff00 [15:8] : SCR (0): Serial clock rate + // 0x00000080 [7] : SPH (0): SSPCLKOUT phase, applicable to Motorola SPI frame format only + // 0x00000040 [6] : SPO (0): SSPCLKOUT polarity, applicable to Motorola SPI frame format only + // 0x00000030 [5:4] : FRF (0): Frame format: 00 Motorola SPI frame format + // 0x0000000f [3:0] : DSS (0): Data Size Select: 0000 Reserved, undefined operation io_rw_32 cr0; + + _REG_(SPI_SSPCR1_OFFSET) // SPI_SSPCR1 + // Control register 1, SSPCR1 on page 3-5 + // 0x00000008 [3] : SOD (0): Slave-mode output disable + // 0x00000004 [2] : MS (0): Master or slave mode select + // 0x00000002 [1] : SSE (0): Synchronous serial port enable: 0 SSP operation disabled + // 0x00000001 [0] : LBM (0): Loop back mode: 0 Normal serial port operation enabled io_rw_32 cr1; + + _REG_(SPI_SSPDR_OFFSET) // SPI_SSPDR + // Data register, SSPDR on page 3-6 + // 0x0000ffff [15:0] : DATA (0): Transmit/Receive FIFO: Read Receive FIFO io_rw_32 dr; - io_rw_32 sr; + + _REG_(SPI_SSPSR_OFFSET) // SPI_SSPSR + // Status register, SSPSR on page 3-7 + // 0x00000010 [4] : BSY (0): PrimeCell SSP busy flag, RO: 0 SSP is idle + // 0x00000008 [3] : RFF (0): Receive FIFO full, RO: 0 Receive FIFO is not full + // 0x00000004 [2] : RNE (0): Receive FIFO not empty, RO: 0 Receive FIFO is empty + // 0x00000002 [1] : TNF (1): Transmit FIFO not full, RO: 0 Transmit FIFO is full + // 0x00000001 [0] : TFE (1): Transmit FIFO empty, RO: 0 Transmit FIFO is not empty + io_ro_32 sr; + + _REG_(SPI_SSPCPSR_OFFSET) // SPI_SSPCPSR + // Clock prescale register, SSPCPSR on page 3-8 + // 0x000000ff [7:0] : CPSDVSR (0): Clock prescale divisor io_rw_32 cpsr; + + _REG_(SPI_SSPIMSC_OFFSET) // SPI_SSPIMSC + // Interrupt mask set or clear register, SSPIMSC on page 3-9 + // 0x00000008 [3] : TXIM (0): Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked + // 0x00000004 [2] : RXIM (0): Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked + // 0x00000002 [1] : RTIM (0): Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout... + // 0x00000001 [0] : RORIM (0): Receive overrun interrupt mask: 0 Receive FIFO written to while full condition... io_rw_32 imsc; - io_rw_32 ris; - io_rw_32 mis; + + _REG_(SPI_SSPRIS_OFFSET) // SPI_SSPRIS + // Raw interrupt status register, SSPRIS on page 3-10 + // 0x00000008 [3] : TXRIS (1): Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + // 0x00000004 [2] : RXRIS (0): Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + // 0x00000002 [1] : RTRIS (0): Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + // 0x00000001 [0] : RORRIS (0): Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + io_ro_32 ris; + + _REG_(SPI_SSPMIS_OFFSET) // SPI_SSPMIS + // Masked interrupt status register, SSPMIS on page 3-11 + // 0x00000008 [3] : TXMIS (0): Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + // 0x00000004 [2] : RXMIS (0): Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + // 0x00000002 [1] : RTMIS (0): Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + // 0x00000001 [0] : RORMIS (0): Gives the receive over run masked interrupt status, after masking, of the... + io_ro_32 mis; + + _REG_(SPI_SSPICR_OFFSET) // SPI_SSPICR + // Interrupt clear register, SSPICR on page 3-11 + // 0x00000002 [1] : RTIC (0): Clears the SSPRTINTR interrupt + // 0x00000001 [0] : RORIC (0): Clears the SSPRORINTR interrupt io_rw_32 icr; + + _REG_(SPI_SSPDMACR_OFFSET) // SPI_SSPDMACR + // DMA control register, SSPDMACR on page 3-12 + // 0x00000002 [1] : TXDMAE (0): Transmit DMA Enable + // 0x00000001 [0] : RXDMAE (0): Receive DMA Enable io_rw_32 dmacr; } spi_hw_t; diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ssi.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ssi.h index 80779fe6b..0ab18beb5 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ssi.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/ssi.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,40 +10,201 @@ #define _HARDWARE_STRUCTS_SSI_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/ssi.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_ssi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/ssi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(SSI_CTRLR0_OFFSET) // SSI_CTRLR0 + // Control register 0 + // 0x01000000 [24] : SSTE (0): Slave select toggle enable + // 0x00600000 [22:21] : SPI_FRF (0): SPI frame format + // 0x001f0000 [20:16] : DFS_32 (0): Data frame size in 32b transfer mode + // 0x0000f000 [15:12] : CFS (0): Control frame size + // 0x00000800 [11] : SRL (0): Shift register loop (test mode) + // 0x00000400 [10] : SLV_OE (0): Slave output enable + // 0x00000300 [9:8] : TMOD (0): Transfer mode + // 0x00000080 [7] : SCPOL (0): Serial clock polarity + // 0x00000040 [6] : SCPH (0): Serial clock phase + // 0x00000030 [5:4] : FRF (0): Frame format + // 0x0000000f [3:0] : DFS (0): Data frame size io_rw_32 ctrlr0; + + _REG_(SSI_CTRLR1_OFFSET) // SSI_CTRLR1 + // Master Control register 1 + // 0x0000ffff [15:0] : NDF (0): Number of data frames io_rw_32 ctrlr1; + + _REG_(SSI_SSIENR_OFFSET) // SSI_SSIENR + // SSI Enable + // 0x00000001 [0] : SSI_EN (0): SSI enable io_rw_32 ssienr; + + _REG_(SSI_MWCR_OFFSET) // SSI_MWCR + // Microwire Control + // 0x00000004 [2] : MHS (0): Microwire handshaking + // 0x00000002 [1] : MDD (0): Microwire control + // 0x00000001 [0] : MWMOD (0): Microwire transfer mode io_rw_32 mwcr; + + _REG_(SSI_SER_OFFSET) // SSI_SER + // Slave enable + // 0x00000001 [0] : SER (0): For each bit: io_rw_32 ser; + + _REG_(SSI_BAUDR_OFFSET) // SSI_BAUDR + // Baud rate + // 0x0000ffff [15:0] : SCKDV (0): SSI clock divider io_rw_32 baudr; + + _REG_(SSI_TXFTLR_OFFSET) // SSI_TXFTLR + // TX FIFO threshold level + // 0x000000ff [7:0] : TFT (0): Transmit FIFO threshold io_rw_32 txftlr; + + _REG_(SSI_RXFTLR_OFFSET) // SSI_RXFTLR + // RX FIFO threshold level + // 0x000000ff [7:0] : RFT (0): Receive FIFO threshold io_rw_32 rxftlr; - io_rw_32 txflr; - io_rw_32 rxflr; - io_rw_32 sr; + + _REG_(SSI_TXFLR_OFFSET) // SSI_TXFLR + // TX FIFO level + // 0x000000ff [7:0] : TFTFL (0): Transmit FIFO level + io_ro_32 txflr; + + _REG_(SSI_RXFLR_OFFSET) // SSI_RXFLR + // RX FIFO level + // 0x000000ff [7:0] : RXTFL (0): Receive FIFO level + io_ro_32 rxflr; + + _REG_(SSI_SR_OFFSET) // SSI_SR + // Status register + // 0x00000040 [6] : DCOL (0): Data collision error + // 0x00000020 [5] : TXE (0): Transmission error + // 0x00000010 [4] : RFF (0): Receive FIFO full + // 0x00000008 [3] : RFNE (0): Receive FIFO not empty + // 0x00000004 [2] : TFE (0): Transmit FIFO empty + // 0x00000002 [1] : TFNF (0): Transmit FIFO not full + // 0x00000001 [0] : BUSY (0): SSI busy flag + io_ro_32 sr; + + _REG_(SSI_IMR_OFFSET) // SSI_IMR + // Interrupt mask + // 0x00000020 [5] : MSTIM (0): Multi-master contention interrupt mask + // 0x00000010 [4] : RXFIM (0): Receive FIFO full interrupt mask + // 0x00000008 [3] : RXOIM (0): Receive FIFO overflow interrupt mask + // 0x00000004 [2] : RXUIM (0): Receive FIFO underflow interrupt mask + // 0x00000002 [1] : TXOIM (0): Transmit FIFO overflow interrupt mask + // 0x00000001 [0] : TXEIM (0): Transmit FIFO empty interrupt mask io_rw_32 imr; - io_rw_32 isr; - io_rw_32 risr; - io_rw_32 txoicr; - io_rw_32 rxoicr; - io_rw_32 rxuicr; - io_rw_32 msticr; - io_rw_32 icr; + + _REG_(SSI_ISR_OFFSET) // SSI_ISR + // Interrupt status + // 0x00000020 [5] : MSTIS (0): Multi-master contention interrupt status + // 0x00000010 [4] : RXFIS (0): Receive FIFO full interrupt status + // 0x00000008 [3] : RXOIS (0): Receive FIFO overflow interrupt status + // 0x00000004 [2] : RXUIS (0): Receive FIFO underflow interrupt status + // 0x00000002 [1] : TXOIS (0): Transmit FIFO overflow interrupt status + // 0x00000001 [0] : TXEIS (0): Transmit FIFO empty interrupt status + io_ro_32 isr; + + _REG_(SSI_RISR_OFFSET) // SSI_RISR + // Raw interrupt status + // 0x00000020 [5] : MSTIR (0): Multi-master contention raw interrupt status + // 0x00000010 [4] : RXFIR (0): Receive FIFO full raw interrupt status + // 0x00000008 [3] : RXOIR (0): Receive FIFO overflow raw interrupt status + // 0x00000004 [2] : RXUIR (0): Receive FIFO underflow raw interrupt status + // 0x00000002 [1] : TXOIR (0): Transmit FIFO overflow raw interrupt status + // 0x00000001 [0] : TXEIR (0): Transmit FIFO empty raw interrupt status + io_ro_32 risr; + + _REG_(SSI_TXOICR_OFFSET) // SSI_TXOICR + // TX FIFO overflow interrupt clear + // 0x00000001 [0] : TXOICR (0): Clear-on-read transmit FIFO overflow interrupt + io_ro_32 txoicr; + + _REG_(SSI_RXOICR_OFFSET) // SSI_RXOICR + // RX FIFO overflow interrupt clear + // 0x00000001 [0] : RXOICR (0): Clear-on-read receive FIFO overflow interrupt + io_ro_32 rxoicr; + + _REG_(SSI_RXUICR_OFFSET) // SSI_RXUICR + // RX FIFO underflow interrupt clear + // 0x00000001 [0] : RXUICR (0): Clear-on-read receive FIFO underflow interrupt + io_ro_32 rxuicr; + + _REG_(SSI_MSTICR_OFFSET) // SSI_MSTICR + // Multi-master interrupt clear + // 0x00000001 [0] : MSTICR (0): Clear-on-read multi-master contention interrupt + io_ro_32 msticr; + + _REG_(SSI_ICR_OFFSET) // SSI_ICR + // Interrupt clear + // 0x00000001 [0] : ICR (0): Clear-on-read all active interrupts + io_ro_32 icr; + + _REG_(SSI_DMACR_OFFSET) // SSI_DMACR + // DMA control + // 0x00000002 [1] : TDMAE (0): Transmit DMA enable + // 0x00000001 [0] : RDMAE (0): Receive DMA enable io_rw_32 dmacr; + + _REG_(SSI_DMATDLR_OFFSET) // SSI_DMATDLR + // DMA TX data level + // 0x000000ff [7:0] : DMATDL (0): Transmit data watermark level io_rw_32 dmatdlr; + + _REG_(SSI_DMARDLR_OFFSET) // SSI_DMARDLR + // DMA RX data level + // 0x000000ff [7:0] : DMARDL (0): Receive data watermark level (DMARDLR+1) io_rw_32 dmardlr; - io_rw_32 idr; - io_rw_32 ssi_version_id; + + _REG_(SSI_IDR_OFFSET) // SSI_IDR + // Identification register + // 0xffffffff [31:0] : IDCODE (0x51535049): Peripheral dentification code + io_ro_32 idr; + + _REG_(SSI_SSI_VERSION_ID_OFFSET) // SSI_SSI_VERSION_ID + // Version ID + // 0xffffffff [31:0] : SSI_COMP_VERSION (0x3430312a): SNPS component version (format X + io_ro_32 ssi_version_id; + + _REG_(SSI_DR0_OFFSET) // SSI_DR0 + // Data Register 0 (of 36) + // 0xffffffff [31:0] : DR (0): First data register of 36 io_rw_32 dr0; - uint32_t _pad[(0xf0 - 0x60) / 4 - 1]; + + uint32_t _pad0[35]; + + _REG_(SSI_RX_SAMPLE_DLY_OFFSET) // SSI_RX_SAMPLE_DLY + // RX sample delay + // 0x000000ff [7:0] : RSD (0): RXD sample delay (in SCLK cycles) io_rw_32 rx_sample_dly; + + _REG_(SSI_SPI_CTRLR0_OFFSET) // SSI_SPI_CTRLR0 + // SPI control + // 0xff000000 [31:24] : XIP_CMD (0x3): SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit) + // 0x00040000 [18] : SPI_RXDS_EN (0): Read data strobe enable + // 0x00020000 [17] : INST_DDR_EN (0): Instruction DDR transfer enable + // 0x00010000 [16] : SPI_DDR_EN (0): SPI DDR transfer enable + // 0x0000f800 [15:11] : WAIT_CYCLES (0): Wait cycles between control frame transmit and data reception (in SCLK cycles) + // 0x00000300 [9:8] : INST_L (0): Instruction length (0/4/8/16b) + // 0x0000003c [5:2] : ADDR_L (0): Address length (0b-60b in 4b increments) + // 0x00000003 [1:0] : TRANS_TYPE (0): Address and instruction transfer format io_rw_32 spi_ctrlr0; + + _REG_(SSI_TXD_DRIVE_EDGE_OFFSET) // SSI_TXD_DRIVE_EDGE + // TX drive edge + // 0x000000ff [7:0] : TDE (0): TXD drive edge io_rw_32 txd_drive_edge; } ssi_hw_t; #define ssi_hw ((ssi_hw_t *const)XIP_SSI_BASE) + #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/syscfg.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/syscfg.h index 0bfc7293c..52218fb1a 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/syscfg.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/syscfg.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,16 +10,65 @@ #define _HARDWARE_STRUCTS_SYSCFG_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/syscfg.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_syscfg +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/syscfg.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(SYSCFG_PROC0_NMI_MASK_OFFSET) // SYSCFG_PROC0_NMI_MASK + // Processor core 0 NMI source mask io_rw_32 proc0_nmi_mask; + + _REG_(SYSCFG_PROC1_NMI_MASK_OFFSET) // SYSCFG_PROC1_NMI_MASK + // Processor core 1 NMI source mask io_rw_32 proc1_nmi_mask; + + _REG_(SYSCFG_PROC_CONFIG_OFFSET) // SYSCFG_PROC_CONFIG + // Configuration for processors + // 0xf0000000 [31:28] : PROC1_DAP_INSTID (1): Configure proc1 DAP instance ID + // 0x0f000000 [27:24] : PROC0_DAP_INSTID (0): Configure proc0 DAP instance ID + // 0x00000002 [1] : PROC1_HALTED (0): Indication that proc1 has halted + // 0x00000001 [0] : PROC0_HALTED (0): Indication that proc0 has halted io_rw_32 proc_config; + + _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS + // For each bit, if 1, bypass the input synchronizer between that GPIO + // 0x3fffffff [29:0] : PROC_IN_SYNC_BYPASS (0) io_rw_32 proc_in_sync_bypass; + + _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS_HI + // For each bit, if 1, bypass the input synchronizer between that GPIO + // 0x0000003f [5:0] : PROC_IN_SYNC_BYPASS_HI (0) io_rw_32 proc_in_sync_bypass_hi; + + _REG_(SYSCFG_DBGFORCE_OFFSET) // SYSCFG_DBGFORCE + // Directly control the SWD debug port of either processor + // 0x00000080 [7] : PROC1_ATTACH (0): Attach processor 1 debug port to syscfg controls, and disconnect it from... + // 0x00000040 [6] : PROC1_SWCLK (1): Directly drive processor 1 SWCLK, if PROC1_ATTACH is set + // 0x00000020 [5] : PROC1_SWDI (1): Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set + // 0x00000010 [4] : PROC1_SWDO (0): Observe the value of processor 1 SWDIO output + // 0x00000008 [3] : PROC0_ATTACH (0): Attach processor 0 debug port to syscfg controls, and disconnect it from... + // 0x00000004 [2] : PROC0_SWCLK (1): Directly drive processor 0 SWCLK, if PROC0_ATTACH is set + // 0x00000002 [1] : PROC0_SWDI (1): Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set + // 0x00000001 [0] : PROC0_SWDO (0): Observe the value of processor 0 SWDIO output io_rw_32 dbgforce; + + _REG_(SYSCFG_MEMPOWERDOWN_OFFSET) // SYSCFG_MEMPOWERDOWN + // Control power downs to memories + // 0x00000080 [7] : ROM (0) + // 0x00000040 [6] : USB (0) + // 0x00000020 [5] : SRAM5 (0) + // 0x00000010 [4] : SRAM4 (0) + // 0x00000008 [3] : SRAM3 (0) + // 0x00000004 [2] : SRAM2 (0) + // 0x00000002 [1] : SRAM1 (0) + // 0x00000001 [0] : SRAM0 (0) io_rw_32 mempowerdown; } syscfg_hw_t; diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/systick.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/systick.h index 3c9997152..a859feae9 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/systick.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/systick.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,10 +12,38 @@ #include "hardware/address_mapped.h" #include "hardware/regs/m0plus.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(M0PLUS_SYST_CSR_OFFSET) // M0PLUS_SYST_CSR + // Use the SysTick Control and Status Register to enable the SysTick features + // 0x00010000 [16] : COUNTFLAG (0): Returns 1 if timer counted to 0 since last time this was read + // 0x00000004 [2] : CLKSOURCE (0): SysTick clock source + // 0x00000002 [1] : TICKINT (0): Enables SysTick exception request: + // 0x00000001 [0] : ENABLE (0): Enable SysTick counter: io_rw_32 csr; + + _REG_(M0PLUS_SYST_RVR_OFFSET) // M0PLUS_SYST_RVR + // Use the SysTick Reload Value Register to specify the start value to load into the current value register when the... + // 0x00ffffff [23:0] : RELOAD (0): Value to load into the SysTick Current Value Register when the counter reaches 0 io_rw_32 rvr; - io_ro_32 cvr; + + _REG_(M0PLUS_SYST_CVR_OFFSET) // M0PLUS_SYST_CVR + // Use the SysTick Current Value Register to find the current value in the register + // 0x00ffffff [23:0] : CURRENT (0): Reads return the current value of the SysTick counter + io_rw_32 cvr; + + _REG_(M0PLUS_SYST_CALIB_OFFSET) // M0PLUS_SYST_CALIB + // Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply + // 0x80000000 [31] : NOREF (0): If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the... + // 0x40000000 [30] : SKEW (0): If reads as 1, the calibration value for 10ms is inexact (due to clock frequency) + // 0x00ffffff [23:0] : TENMS (0): An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock... io_ro_32 calib; } systick_hw_t; diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/timer.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/timer.h index e051a0697..c7c706692 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/timer.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/timer.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,28 +10,98 @@ #define _HARDWARE_STRUCTS_TIMER_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/timer.h" -#define NUM_TIMERS 4 +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_timer +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/timer.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION typedef struct { + _REG_(TIMER_TIMEHW_OFFSET) // TIMER_TIMEHW + // Write to bits 63:32 of time io_wo_32 timehw; + + _REG_(TIMER_TIMELW_OFFSET) // TIMER_TIMELW + // Write to bits 31:0 of time io_wo_32 timelw; + + _REG_(TIMER_TIMEHR_OFFSET) // TIMER_TIMEHR + // Read from bits 63:32 of time io_ro_32 timehr; + + _REG_(TIMER_TIMELR_OFFSET) // TIMER_TIMELR + // Read from bits 31:0 of time io_ro_32 timelr; - io_rw_32 alarm[NUM_TIMERS]; + + _REG_(TIMER_ALARM0_OFFSET) // TIMER_ALARM0 + // (Description copied from array index 0 register TIMER_ALARM0 applies similarly to other array indexes) + // + // Arm alarm 0, and configure the time it will fire + io_rw_32 alarm[NUM_TIMERS]; // 4 + + _REG_(TIMER_ARMED_OFFSET) // TIMER_ARMED + // Indicates the armed/disarmed status of each alarm + // 0x0000000f [3:0] : ARMED (0) io_rw_32 armed; + + _REG_(TIMER_TIMERAWH_OFFSET) // TIMER_TIMERAWH + // Raw read from bits 63:32 of time (no side effects) io_ro_32 timerawh; + + _REG_(TIMER_TIMERAWL_OFFSET) // TIMER_TIMERAWL + // Raw read from bits 31:0 of time (no side effects) io_ro_32 timerawl; + + _REG_(TIMER_DBGPAUSE_OFFSET) // TIMER_DBGPAUSE + // Set bits high to enable pause when the corresponding debug ports are active + // 0x00000004 [2] : DBG1 (1): Pause when processor 1 is in debug mode + // 0x00000002 [1] : DBG0 (1): Pause when processor 0 is in debug mode io_rw_32 dbgpause; + + _REG_(TIMER_PAUSE_OFFSET) // TIMER_PAUSE + // Set high to pause the timer + // 0x00000001 [0] : PAUSE (0) io_rw_32 pause; + + _REG_(TIMER_INTR_OFFSET) // TIMER_INTR + // Raw Interrupts + // 0x00000008 [3] : ALARM_3 (0) + // 0x00000004 [2] : ALARM_2 (0) + // 0x00000002 [1] : ALARM_1 (0) + // 0x00000001 [0] : ALARM_0 (0) io_rw_32 intr; + + _REG_(TIMER_INTE_OFFSET) // TIMER_INTE + // Interrupt Enable + // 0x00000008 [3] : ALARM_3 (0) + // 0x00000004 [2] : ALARM_2 (0) + // 0x00000002 [1] : ALARM_1 (0) + // 0x00000001 [0] : ALARM_0 (0) io_rw_32 inte; + + _REG_(TIMER_INTF_OFFSET) // TIMER_INTF + // Interrupt Force + // 0x00000008 [3] : ALARM_3 (0) + // 0x00000004 [2] : ALARM_2 (0) + // 0x00000002 [1] : ALARM_1 (0) + // 0x00000001 [0] : ALARM_0 (0) io_rw_32 intf; + + _REG_(TIMER_INTS_OFFSET) // TIMER_INTS + // Interrupt status after masking & forcing + // 0x00000008 [3] : ALARM_3 (0) + // 0x00000004 [2] : ALARM_2 (0) + // 0x00000002 [1] : ALARM_1 (0) + // 0x00000001 [0] : ALARM_0 (0) io_ro_32 ints; } timer_hw_t; #define timer_hw ((timer_hw_t *const)TIMER_BASE) +static_assert( NUM_TIMERS == 4, ""); + #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/uart.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/uart.h index 42fe8e88b..09af33e43 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/uart.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/uart.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,22 +12,162 @@ #include "hardware/address_mapped.h" #include "hardware/regs/uart.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_uart +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/uart.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(UART_UARTDR_OFFSET) // UART_UARTDR + // Data Register, UARTDR + // 0x00000800 [11] : OE (0): Overrun error + // 0x00000400 [10] : BE (0): Break error + // 0x00000200 [9] : PE (0): Parity error + // 0x00000100 [8] : FE (0): Framing error + // 0x000000ff [7:0] : DATA (0): Receive (read) data character io_rw_32 dr; + + _REG_(UART_UARTRSR_OFFSET) // UART_UARTRSR + // Receive Status Register/Error Clear Register, UARTRSR/UARTECR + // 0x00000008 [3] : OE (0): Overrun error + // 0x00000004 [2] : BE (0): Break error + // 0x00000002 [1] : PE (0): Parity error + // 0x00000001 [0] : FE (0): Framing error io_rw_32 rsr; + uint32_t _pad0[4]; - io_rw_32 fr; + + _REG_(UART_UARTFR_OFFSET) // UART_UARTFR + // Flag Register, UARTFR + // 0x00000100 [8] : RI (0): Ring indicator + // 0x00000080 [7] : TXFE (1): Transmit FIFO empty + // 0x00000040 [6] : RXFF (0): Receive FIFO full + // 0x00000020 [5] : TXFF (0): Transmit FIFO full + // 0x00000010 [4] : RXFE (1): Receive FIFO empty + // 0x00000008 [3] : BUSY (0): UART busy + // 0x00000004 [2] : DCD (0): Data carrier detect + // 0x00000002 [1] : DSR (0): Data set ready + // 0x00000001 [0] : CTS (0): Clear to send + io_ro_32 fr; + uint32_t _pad1; + + _REG_(UART_UARTILPR_OFFSET) // UART_UARTILPR + // IrDA Low-Power Counter Register, UARTILPR + // 0x000000ff [7:0] : ILPDVSR (0): 8-bit low-power divisor value io_rw_32 ilpr; + + _REG_(UART_UARTIBRD_OFFSET) // UART_UARTIBRD + // Integer Baud Rate Register, UARTIBRD + // 0x0000ffff [15:0] : BAUD_DIVINT (0): The integer baud rate divisor io_rw_32 ibrd; + + _REG_(UART_UARTFBRD_OFFSET) // UART_UARTFBRD + // Fractional Baud Rate Register, UARTFBRD + // 0x0000003f [5:0] : BAUD_DIVFRAC (0): The fractional baud rate divisor io_rw_32 fbrd; + + _REG_(UART_UARTLCR_H_OFFSET) // UART_UARTLCR_H + // Line Control Register, UARTLCR_H + // 0x00000080 [7] : SPS (0): Stick parity select + // 0x00000060 [6:5] : WLEN (0): Word length + // 0x00000010 [4] : FEN (0): Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become... + // 0x00000008 [3] : STP2 (0): Two stop bits select + // 0x00000004 [2] : EPS (0): Even parity select + // 0x00000002 [1] : PEN (0): Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 =... + // 0x00000001 [0] : BRK (0): Send break io_rw_32 lcr_h; + + _REG_(UART_UARTCR_OFFSET) // UART_UARTCR + // Control Register, UARTCR + // 0x00008000 [15] : CTSEN (0): CTS hardware flow control enable + // 0x00004000 [14] : RTSEN (0): RTS hardware flow control enable + // 0x00002000 [13] : OUT2 (0): This bit is the complement of the UART Out2 (nUARTOut2) modem status output + // 0x00001000 [12] : OUT1 (0): This bit is the complement of the UART Out1 (nUARTOut1) modem status output + // 0x00000800 [11] : RTS (0): Request to send + // 0x00000400 [10] : DTR (0): Data transmit ready + // 0x00000200 [9] : RXE (1): Receive enable + // 0x00000100 [8] : TXE (1): Transmit enable + // 0x00000080 [7] : LBE (0): Loopback enable + // 0x00000004 [2] : SIRLP (0): SIR low-power IrDA mode + // 0x00000002 [1] : SIREN (0): SIR enable: 0 = IrDA SIR ENDEC is disabled + // 0x00000001 [0] : UARTEN (0): UART enable: 0 = UART is disabled io_rw_32 cr; + + _REG_(UART_UARTIFLS_OFFSET) // UART_UARTIFLS + // Interrupt FIFO Level Select Register, UARTIFLS + // 0x00000038 [5:3] : RXIFLSEL (0x2): Receive interrupt FIFO level select + // 0x00000007 [2:0] : TXIFLSEL (0x2): Transmit interrupt FIFO level select io_rw_32 ifls; + + _REG_(UART_UARTIMSC_OFFSET) // UART_UARTIMSC + // Interrupt Mask Set/Clear Register, UARTIMSC + // 0x00000400 [10] : OEIM (0): Overrun error interrupt mask + // 0x00000200 [9] : BEIM (0): Break error interrupt mask + // 0x00000100 [8] : PEIM (0): Parity error interrupt mask + // 0x00000080 [7] : FEIM (0): Framing error interrupt mask + // 0x00000040 [6] : RTIM (0): Receive timeout interrupt mask + // 0x00000020 [5] : TXIM (0): Transmit interrupt mask + // 0x00000010 [4] : RXIM (0): Receive interrupt mask + // 0x00000008 [3] : DSRMIM (0): nUARTDSR modem interrupt mask + // 0x00000004 [2] : DCDMIM (0): nUARTDCD modem interrupt mask + // 0x00000002 [1] : CTSMIM (0): nUARTCTS modem interrupt mask + // 0x00000001 [0] : RIMIM (0): nUARTRI modem interrupt mask io_rw_32 imsc; - io_rw_32 ris; - io_rw_32 mis; + + _REG_(UART_UARTRIS_OFFSET) // UART_UARTRIS + // Raw Interrupt Status Register, UARTRIS + // 0x00000400 [10] : OERIS (0): Overrun error interrupt status + // 0x00000200 [9] : BERIS (0): Break error interrupt status + // 0x00000100 [8] : PERIS (0): Parity error interrupt status + // 0x00000080 [7] : FERIS (0): Framing error interrupt status + // 0x00000040 [6] : RTRIS (0): Receive timeout interrupt status + // 0x00000020 [5] : TXRIS (0): Transmit interrupt status + // 0x00000010 [4] : RXRIS (0): Receive interrupt status + // 0x00000008 [3] : DSRRMIS (0): nUARTDSR modem interrupt status + // 0x00000004 [2] : DCDRMIS (0): nUARTDCD modem interrupt status + // 0x00000002 [1] : CTSRMIS (0): nUARTCTS modem interrupt status + // 0x00000001 [0] : RIRMIS (0): nUARTRI modem interrupt status + io_ro_32 ris; + + _REG_(UART_UARTMIS_OFFSET) // UART_UARTMIS + // Masked Interrupt Status Register, UARTMIS + // 0x00000400 [10] : OEMIS (0): Overrun error masked interrupt status + // 0x00000200 [9] : BEMIS (0): Break error masked interrupt status + // 0x00000100 [8] : PEMIS (0): Parity error masked interrupt status + // 0x00000080 [7] : FEMIS (0): Framing error masked interrupt status + // 0x00000040 [6] : RTMIS (0): Receive timeout masked interrupt status + // 0x00000020 [5] : TXMIS (0): Transmit masked interrupt status + // 0x00000010 [4] : RXMIS (0): Receive masked interrupt status + // 0x00000008 [3] : DSRMMIS (0): nUARTDSR modem masked interrupt status + // 0x00000004 [2] : DCDMMIS (0): nUARTDCD modem masked interrupt status + // 0x00000002 [1] : CTSMMIS (0): nUARTCTS modem masked interrupt status + // 0x00000001 [0] : RIMMIS (0): nUARTRI modem masked interrupt status + io_ro_32 mis; + + _REG_(UART_UARTICR_OFFSET) // UART_UARTICR + // Interrupt Clear Register, UARTICR + // 0x00000400 [10] : OEIC (0): Overrun error interrupt clear + // 0x00000200 [9] : BEIC (0): Break error interrupt clear + // 0x00000100 [8] : PEIC (0): Parity error interrupt clear + // 0x00000080 [7] : FEIC (0): Framing error interrupt clear + // 0x00000040 [6] : RTIC (0): Receive timeout interrupt clear + // 0x00000020 [5] : TXIC (0): Transmit interrupt clear + // 0x00000010 [4] : RXIC (0): Receive interrupt clear + // 0x00000008 [3] : DSRMIC (0): nUARTDSR modem interrupt clear + // 0x00000004 [2] : DCDMIC (0): nUARTDCD modem interrupt clear + // 0x00000002 [1] : CTSMIC (0): nUARTCTS modem interrupt clear + // 0x00000001 [0] : RIMIC (0): nUARTRI modem interrupt clear io_rw_32 icr; + + _REG_(UART_UARTDMACR_OFFSET) // UART_UARTDMACR + // DMA Control Register, UARTDMACR + // 0x00000004 [2] : DMAONERR (0): DMA on error + // 0x00000002 [1] : TXDMAE (0): Transmit DMA enable + // 0x00000001 [0] : RXDMAE (0): Receive DMA enable io_rw_32 dmacr; } uart_hw_t; diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/usb.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/usb.h index 5c3c45339..c9455d065 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/usb.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/usb.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +12,14 @@ #include "hardware/address_mapped.h" #include "hardware/regs/usb.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_usb +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/usb.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + // 0-15 #define USB_NUM_ENDPOINTS 16 @@ -39,10 +49,10 @@ #define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28) #define EP_CTRL_INTERRUPT_ON_NAK (1u << 16) #define EP_CTRL_INTERRUPT_ON_STALL (1u << 17) -#define EP_CTRL_BUFFER_TYPE_LSB 26 -#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16 +#define EP_CTRL_BUFFER_TYPE_LSB 26u +#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16u -#define USB_DPRAM_SIZE 4096 +#define USB_DPRAM_SIZE 4096u // PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb // Allow user to claim some of the USB RAM for themselves @@ -79,6 +89,7 @@ typedef struct { } usb_device_dpram_t; static_assert(sizeof(usb_device_dpram_t) == USB_DPRAM_MAX, ""); +static_assert(offsetof(usb_device_dpram_t, epx_data) == 0x180, ""); typedef struct { // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses @@ -108,40 +119,460 @@ typedef struct { } usb_host_dpram_t; static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, ""); +static_assert(offsetof(usb_host_dpram_t, epx_data) == 0x180, ""); typedef struct { + _REG_(USB_ADDR_ENDP_OFFSET) // USB_ADDR_ENDP + // Device address and endpoint control + // 0x000f0000 [19:16] : ENDPOINT (0): Device endpoint to send data to + // 0x0000007f [6:0] : ADDRESS (0): In device mode, the address that the device should respond to io_rw_32 dev_addr_ctrl; - io_rw_32 int_ep_addr_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; + + _REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP1 + // (Description copied from array index 0 register USB_ADDR_ENDP1 applies similarly to other array indexes) + // + // Interrupt endpoint 1 + // 0x04000000 [26] : INTEP_PREAMBLE (0): Interrupt EP requires preamble (is a low speed device on a full speed hub) + // 0x02000000 [25] : INTEP_DIR (0): Direction of the interrupt endpoint + // 0x000f0000 [19:16] : ENDPOINT (0): Endpoint number of the interrupt endpoint + // 0x0000007f [6:0] : ADDRESS (0): Device address + io_rw_32 int_ep_addr_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; // 15 + + _REG_(USB_MAIN_CTRL_OFFSET) // USB_MAIN_CTRL + // Main control register + // 0x80000000 [31] : SIM_TIMING (0): Reduced timings for simulation + // 0x00000002 [1] : HOST_NDEVICE (0): Device mode = 0, Host mode = 1 + // 0x00000001 [0] : CONTROLLER_EN (0): Enable controller io_rw_32 main_ctrl; - io_rw_32 sof_rw; + + _REG_(USB_SOF_WR_OFFSET) // USB_SOF_WR + // Set the SOF (Start of Frame) frame number in the host controller + // 0x000007ff [10:0] : COUNT (0) + io_wo_32 sof_rw; + + _REG_(USB_SOF_RD_OFFSET) // USB_SOF_RD + // Read the last SOF (Start of Frame) frame number seen + // 0x000007ff [10:0] : COUNT (0) io_ro_32 sof_rd; + + _REG_(USB_SIE_CTRL_OFFSET) // USB_SIE_CTRL + // SIE control register + // 0x80000000 [31] : EP0_INT_STALL (0): Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL + // 0x40000000 [30] : EP0_DOUBLE_BUF (0): Device: EP0 single buffered = 0, double buffered = 1 + // 0x20000000 [29] : EP0_INT_1BUF (0): Device: Set bit in BUFF_STATUS for every buffer completed on EP0 + // 0x10000000 [28] : EP0_INT_2BUF (0): Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 + // 0x08000000 [27] : EP0_INT_NAK (0): Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK + // 0x04000000 [26] : DIRECT_EN (0): Direct bus drive enable + // 0x02000000 [25] : DIRECT_DP (0): Direct control of DP + // 0x01000000 [24] : DIRECT_DM (0): Direct control of DM + // 0x00040000 [18] : TRANSCEIVER_PD (0): Power down bus transceiver + // 0x00020000 [17] : RPU_OPT (0): Device: Pull-up strength (0=1K2, 1=2k3) + // 0x00010000 [16] : PULLUP_EN (0): Device: Enable pull up resistor + // 0x00008000 [15] : PULLDOWN_EN (0): Host: Enable pull down resistors + // 0x00002000 [13] : RESET_BUS (0): Host: Reset bus + // 0x00001000 [12] : RESUME (0): Device: Remote wakeup + // 0x00000800 [11] : VBUS_EN (0): Host: Enable VBUS + // 0x00000400 [10] : KEEP_ALIVE_EN (0): Host: Enable keep alive packet (for low speed bus) + // 0x00000200 [9] : SOF_EN (0): Host: Enable SOF generation (for full speed bus) + // 0x00000100 [8] : SOF_SYNC (0): Host: Delay packet(s) until after SOF + // 0x00000040 [6] : PREAMBLE_EN (0): Host: Preable enable for LS device on FS hub + // 0x00000010 [4] : STOP_TRANS (0): Host: Stop transaction + // 0x00000008 [3] : RECEIVE_DATA (0): Host: Receive transaction (IN to host) + // 0x00000004 [2] : SEND_DATA (0): Host: Send transaction (OUT from host) + // 0x00000002 [1] : SEND_SETUP (0): Host: Send Setup packet + // 0x00000001 [0] : START_TRANS (0): Host: Start transaction io_rw_32 sie_ctrl; + + _REG_(USB_SIE_STATUS_OFFSET) // USB_SIE_STATUS + // SIE status register + // 0x80000000 [31] : DATA_SEQ_ERROR (0): Data Sequence Error + // 0x40000000 [30] : ACK_REC (0): ACK received + // 0x20000000 [29] : STALL_REC (0): Host: STALL received + // 0x10000000 [28] : NAK_REC (0): Host: NAK received + // 0x08000000 [27] : RX_TIMEOUT (0): RX timeout is raised by both the host and device if an ACK is not received in... + // 0x04000000 [26] : RX_OVERFLOW (0): RX overflow is raised by the Serial RX engine if the incoming data is too fast + // 0x02000000 [25] : BIT_STUFF_ERROR (0): Bit Stuff Error + // 0x01000000 [24] : CRC_ERROR (0): CRC Error + // 0x00080000 [19] : BUS_RESET (0): Device: bus reset received + // 0x00040000 [18] : TRANS_COMPLETE (0): Transaction complete + // 0x00020000 [17] : SETUP_REC (0): Device: Setup packet received + // 0x00010000 [16] : CONNECTED (0): Device: connected + // 0x00000800 [11] : RESUME (0): Host: Device has initiated a remote resume + // 0x00000400 [10] : VBUS_OVER_CURR (0): VBUS over current detected + // 0x00000300 [9:8] : SPEED (0): Host: device speed + // 0x00000010 [4] : SUSPENDED (0): Bus in suspended state + // 0x0000000c [3:2] : LINE_STATE (0): USB bus line state + // 0x00000001 [0] : VBUS_DETECTED (0): Device: VBUS Detected io_rw_32 sie_status; + + _REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL + // interrupt endpoint control register + // 0x0000fffe [15:1] : INT_EP_ACTIVE (0): Host: Enable interrupt endpoint 1 -> 15 io_rw_32 int_ep_ctrl; + + _REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS + // Buffer status register + // 0x80000000 [31] : EP15_OUT (0) + // 0x40000000 [30] : EP15_IN (0) + // 0x20000000 [29] : EP14_OUT (0) + // 0x10000000 [28] : EP14_IN (0) + // 0x08000000 [27] : EP13_OUT (0) + // 0x04000000 [26] : EP13_IN (0) + // 0x02000000 [25] : EP12_OUT (0) + // 0x01000000 [24] : EP12_IN (0) + // 0x00800000 [23] : EP11_OUT (0) + // 0x00400000 [22] : EP11_IN (0) + // 0x00200000 [21] : EP10_OUT (0) + // 0x00100000 [20] : EP10_IN (0) + // 0x00080000 [19] : EP9_OUT (0) + // 0x00040000 [18] : EP9_IN (0) + // 0x00020000 [17] : EP8_OUT (0) + // 0x00010000 [16] : EP8_IN (0) + // 0x00008000 [15] : EP7_OUT (0) + // 0x00004000 [14] : EP7_IN (0) + // 0x00002000 [13] : EP6_OUT (0) + // 0x00001000 [12] : EP6_IN (0) + // 0x00000800 [11] : EP5_OUT (0) + // 0x00000400 [10] : EP5_IN (0) + // 0x00000200 [9] : EP4_OUT (0) + // 0x00000100 [8] : EP4_IN (0) + // 0x00000080 [7] : EP3_OUT (0) + // 0x00000040 [6] : EP3_IN (0) + // 0x00000020 [5] : EP2_OUT (0) + // 0x00000010 [4] : EP2_IN (0) + // 0x00000008 [3] : EP1_OUT (0) + // 0x00000004 [2] : EP1_IN (0) + // 0x00000002 [1] : EP0_OUT (0) + // 0x00000001 [0] : EP0_IN (0) io_rw_32 buf_status; - io_rw_32 buf_cpu_should_handle; // for double buff + + _REG_(USB_BUFF_CPU_SHOULD_HANDLE_OFFSET) // USB_BUFF_CPU_SHOULD_HANDLE + // Which of the double buffers should be handled + // 0x80000000 [31] : EP15_OUT (0) + // 0x40000000 [30] : EP15_IN (0) + // 0x20000000 [29] : EP14_OUT (0) + // 0x10000000 [28] : EP14_IN (0) + // 0x08000000 [27] : EP13_OUT (0) + // 0x04000000 [26] : EP13_IN (0) + // 0x02000000 [25] : EP12_OUT (0) + // 0x01000000 [24] : EP12_IN (0) + // 0x00800000 [23] : EP11_OUT (0) + // 0x00400000 [22] : EP11_IN (0) + // 0x00200000 [21] : EP10_OUT (0) + // 0x00100000 [20] : EP10_IN (0) + // 0x00080000 [19] : EP9_OUT (0) + // 0x00040000 [18] : EP9_IN (0) + // 0x00020000 [17] : EP8_OUT (0) + // 0x00010000 [16] : EP8_IN (0) + // 0x00008000 [15] : EP7_OUT (0) + // 0x00004000 [14] : EP7_IN (0) + // 0x00002000 [13] : EP6_OUT (0) + // 0x00001000 [12] : EP6_IN (0) + // 0x00000800 [11] : EP5_OUT (0) + // 0x00000400 [10] : EP5_IN (0) + // 0x00000200 [9] : EP4_OUT (0) + // 0x00000100 [8] : EP4_IN (0) + // 0x00000080 [7] : EP3_OUT (0) + // 0x00000040 [6] : EP3_IN (0) + // 0x00000020 [5] : EP2_OUT (0) + // 0x00000010 [4] : EP2_IN (0) + // 0x00000008 [3] : EP1_OUT (0) + // 0x00000004 [2] : EP1_IN (0) + // 0x00000002 [1] : EP0_OUT (0) + // 0x00000001 [0] : EP0_IN (0) + io_ro_32 buf_cpu_should_handle; + + _REG_(USB_EP_ABORT_OFFSET) // USB_EP_ABORT + // Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer + // 0x80000000 [31] : EP15_OUT (0) + // 0x40000000 [30] : EP15_IN (0) + // 0x20000000 [29] : EP14_OUT (0) + // 0x10000000 [28] : EP14_IN (0) + // 0x08000000 [27] : EP13_OUT (0) + // 0x04000000 [26] : EP13_IN (0) + // 0x02000000 [25] : EP12_OUT (0) + // 0x01000000 [24] : EP12_IN (0) + // 0x00800000 [23] : EP11_OUT (0) + // 0x00400000 [22] : EP11_IN (0) + // 0x00200000 [21] : EP10_OUT (0) + // 0x00100000 [20] : EP10_IN (0) + // 0x00080000 [19] : EP9_OUT (0) + // 0x00040000 [18] : EP9_IN (0) + // 0x00020000 [17] : EP8_OUT (0) + // 0x00010000 [16] : EP8_IN (0) + // 0x00008000 [15] : EP7_OUT (0) + // 0x00004000 [14] : EP7_IN (0) + // 0x00002000 [13] : EP6_OUT (0) + // 0x00001000 [12] : EP6_IN (0) + // 0x00000800 [11] : EP5_OUT (0) + // 0x00000400 [10] : EP5_IN (0) + // 0x00000200 [9] : EP4_OUT (0) + // 0x00000100 [8] : EP4_IN (0) + // 0x00000080 [7] : EP3_OUT (0) + // 0x00000040 [6] : EP3_IN (0) + // 0x00000020 [5] : EP2_OUT (0) + // 0x00000010 [4] : EP2_IN (0) + // 0x00000008 [3] : EP1_OUT (0) + // 0x00000004 [2] : EP1_IN (0) + // 0x00000002 [1] : EP0_OUT (0) + // 0x00000001 [0] : EP0_IN (0) io_rw_32 abort; + + _REG_(USB_EP_ABORT_DONE_OFFSET) // USB_EP_ABORT_DONE + // Device only: Used in conjunction with `EP_ABORT` + // 0x80000000 [31] : EP15_OUT (0) + // 0x40000000 [30] : EP15_IN (0) + // 0x20000000 [29] : EP14_OUT (0) + // 0x10000000 [28] : EP14_IN (0) + // 0x08000000 [27] : EP13_OUT (0) + // 0x04000000 [26] : EP13_IN (0) + // 0x02000000 [25] : EP12_OUT (0) + // 0x01000000 [24] : EP12_IN (0) + // 0x00800000 [23] : EP11_OUT (0) + // 0x00400000 [22] : EP11_IN (0) + // 0x00200000 [21] : EP10_OUT (0) + // 0x00100000 [20] : EP10_IN (0) + // 0x00080000 [19] : EP9_OUT (0) + // 0x00040000 [18] : EP9_IN (0) + // 0x00020000 [17] : EP8_OUT (0) + // 0x00010000 [16] : EP8_IN (0) + // 0x00008000 [15] : EP7_OUT (0) + // 0x00004000 [14] : EP7_IN (0) + // 0x00002000 [13] : EP6_OUT (0) + // 0x00001000 [12] : EP6_IN (0) + // 0x00000800 [11] : EP5_OUT (0) + // 0x00000400 [10] : EP5_IN (0) + // 0x00000200 [9] : EP4_OUT (0) + // 0x00000100 [8] : EP4_IN (0) + // 0x00000080 [7] : EP3_OUT (0) + // 0x00000040 [6] : EP3_IN (0) + // 0x00000020 [5] : EP2_OUT (0) + // 0x00000010 [4] : EP2_IN (0) + // 0x00000008 [3] : EP1_OUT (0) + // 0x00000004 [2] : EP1_IN (0) + // 0x00000002 [1] : EP0_OUT (0) + // 0x00000001 [0] : EP0_IN (0) io_rw_32 abort_done; + + _REG_(USB_EP_STALL_ARM_OFFSET) // USB_EP_STALL_ARM + // Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0 + // 0x00000002 [1] : EP0_OUT (0) + // 0x00000001 [0] : EP0_IN (0) io_rw_32 ep_stall_arm; + + _REG_(USB_NAK_POLL_OFFSET) // USB_NAK_POLL + // Used by the host controller + // 0x03ff0000 [25:16] : DELAY_FS (0x10): NAK polling interval for a full speed device + // 0x000003ff [9:0] : DELAY_LS (0x10): NAK polling interval for a low speed device io_rw_32 nak_poll; + + _REG_(USB_EP_STATUS_STALL_NAK_OFFSET) // USB_EP_STATUS_STALL_NAK + // Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set + // 0x80000000 [31] : EP15_OUT (0) + // 0x40000000 [30] : EP15_IN (0) + // 0x20000000 [29] : EP14_OUT (0) + // 0x10000000 [28] : EP14_IN (0) + // 0x08000000 [27] : EP13_OUT (0) + // 0x04000000 [26] : EP13_IN (0) + // 0x02000000 [25] : EP12_OUT (0) + // 0x01000000 [24] : EP12_IN (0) + // 0x00800000 [23] : EP11_OUT (0) + // 0x00400000 [22] : EP11_IN (0) + // 0x00200000 [21] : EP10_OUT (0) + // 0x00100000 [20] : EP10_IN (0) + // 0x00080000 [19] : EP9_OUT (0) + // 0x00040000 [18] : EP9_IN (0) + // 0x00020000 [17] : EP8_OUT (0) + // 0x00010000 [16] : EP8_IN (0) + // 0x00008000 [15] : EP7_OUT (0) + // 0x00004000 [14] : EP7_IN (0) + // 0x00002000 [13] : EP6_OUT (0) + // 0x00001000 [12] : EP6_IN (0) + // 0x00000800 [11] : EP5_OUT (0) + // 0x00000400 [10] : EP5_IN (0) + // 0x00000200 [9] : EP4_OUT (0) + // 0x00000100 [8] : EP4_IN (0) + // 0x00000080 [7] : EP3_OUT (0) + // 0x00000040 [6] : EP3_IN (0) + // 0x00000020 [5] : EP2_OUT (0) + // 0x00000010 [4] : EP2_IN (0) + // 0x00000008 [3] : EP1_OUT (0) + // 0x00000004 [2] : EP1_IN (0) + // 0x00000002 [1] : EP0_OUT (0) + // 0x00000001 [0] : EP0_IN (0) io_rw_32 ep_nak_stall_status; + + _REG_(USB_USB_MUXING_OFFSET) // USB_USB_MUXING + // Where to connect the USB controller + // 0x00000008 [3] : SOFTCON (0) + // 0x00000004 [2] : TO_DIGITAL_PAD (0) + // 0x00000002 [1] : TO_EXTPHY (0) + // 0x00000001 [0] : TO_PHY (0) io_rw_32 muxing; + + _REG_(USB_USB_PWR_OFFSET) // USB_USB_PWR + // Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO + // 0x00000020 [5] : OVERCURR_DETECT_EN (0) + // 0x00000010 [4] : OVERCURR_DETECT (0) + // 0x00000008 [3] : VBUS_DETECT_OVERRIDE_EN (0) + // 0x00000004 [2] : VBUS_DETECT (0) + // 0x00000002 [1] : VBUS_EN_OVERRIDE_EN (0) + // 0x00000001 [0] : VBUS_EN (0) io_rw_32 pwr; + + _REG_(USB_USBPHY_DIRECT_OFFSET) // USB_USBPHY_DIRECT + // This register allows for direct control of the USB phy + // 0x00400000 [22] : DM_OVV (0): DM over voltage + // 0x00200000 [21] : DP_OVV (0): DP over voltage + // 0x00100000 [20] : DM_OVCN (0): DM overcurrent + // 0x00080000 [19] : DP_OVCN (0): DP overcurrent + // 0x00040000 [18] : RX_DM (0): DPM pin state + // 0x00020000 [17] : RX_DP (0): DPP pin state + // 0x00010000 [16] : RX_DD (0): Differential RX + // 0x00008000 [15] : TX_DIFFMODE (0): TX_DIFFMODE=0: Single ended mode + // 0x00004000 [14] : TX_FSSLEW (0): TX_FSSLEW=0: Low speed slew rate + // 0x00002000 [13] : TX_PD (0): TX power down override (if override enable is set) + // 0x00001000 [12] : RX_PD (0): RX power down override (if override enable is set) + // 0x00000800 [11] : TX_DM (0): Output data + // 0x00000400 [10] : TX_DP (0): Output data + // 0x00000200 [9] : TX_DM_OE (0): Output enable + // 0x00000100 [8] : TX_DP_OE (0): Output enable + // 0x00000040 [6] : DM_PULLDN_EN (0): DM pull down enable + // 0x00000020 [5] : DM_PULLUP_EN (0): DM pull up enable + // 0x00000010 [4] : DM_PULLUP_HISEL (0): Enable the second DM pull up resistor + // 0x00000004 [2] : DP_PULLDN_EN (0): DP pull down enable + // 0x00000002 [1] : DP_PULLUP_EN (0): DP pull up enable + // 0x00000001 [0] : DP_PULLUP_HISEL (0): Enable the second DP pull up resistor io_rw_32 phy_direct; + + _REG_(USB_USBPHY_DIRECT_OVERRIDE_OFFSET) // USB_USBPHY_DIRECT_OVERRIDE + // Override enable for each control in usbphy_direct + // 0x00008000 [15] : TX_DIFFMODE_OVERRIDE_EN (0) + // 0x00001000 [12] : DM_PULLUP_OVERRIDE_EN (0) + // 0x00000800 [11] : TX_FSSLEW_OVERRIDE_EN (0) + // 0x00000400 [10] : TX_PD_OVERRIDE_EN (0) + // 0x00000200 [9] : RX_PD_OVERRIDE_EN (0) + // 0x00000100 [8] : TX_DM_OVERRIDE_EN (0) + // 0x00000080 [7] : TX_DP_OVERRIDE_EN (0) + // 0x00000040 [6] : TX_DM_OE_OVERRIDE_EN (0) + // 0x00000020 [5] : TX_DP_OE_OVERRIDE_EN (0) + // 0x00000010 [4] : DM_PULLDN_EN_OVERRIDE_EN (0) + // 0x00000008 [3] : DP_PULLDN_EN_OVERRIDE_EN (0) + // 0x00000004 [2] : DP_PULLUP_EN_OVERRIDE_EN (0) + // 0x00000002 [1] : DM_PULLUP_HISEL_OVERRIDE_EN (0) + // 0x00000001 [0] : DP_PULLUP_HISEL_OVERRIDE_EN (0) io_rw_32 phy_direct_override; + + _REG_(USB_USBPHY_TRIM_OFFSET) // USB_USBPHY_TRIM + // Used to adjust trim values of USB phy pull down resistors + // 0x00001f00 [12:8] : DM_PULLDN_TRIM (0x1f): Value to drive to USB PHY + // 0x0000001f [4:0] : DP_PULLDN_TRIM (0x1f): Value to drive to USB PHY io_rw_32 phy_trim; - io_rw_32 linestate_tuning; - io_rw_32 intr; + + uint32_t _pad0; + + _REG_(USB_INTR_OFFSET) // USB_INTR + // Raw Interrupts + // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] : SETUP_REQ (0): Device + // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host + // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes + // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes + // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS + // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS + // 0x00000400 [10] : STALL (0): Source: SIE_STATUS + // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS + // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS + // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS + // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS + // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS + // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS + // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host + // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i + io_ro_32 intr; + + _REG_(USB_INTE_OFFSET) // USB_INTE + // Interrupt Enable + // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] : SETUP_REQ (0): Device + // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host + // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes + // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes + // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS + // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS + // 0x00000400 [10] : STALL (0): Source: SIE_STATUS + // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS + // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS + // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS + // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS + // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS + // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS + // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host + // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i io_rw_32 inte; + + _REG_(USB_INTF_OFFSET) // USB_INTF + // Interrupt Force + // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] : SETUP_REQ (0): Device + // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host + // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes + // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes + // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS + // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS + // 0x00000400 [10] : STALL (0): Source: SIE_STATUS + // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS + // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS + // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS + // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS + // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS + // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS + // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host + // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i io_rw_32 intf; - io_rw_32 ints; -} usb_hw_t; -check_hw_layout(usb_hw_t, ints, USB_INTS_OFFSET); + _REG_(USB_INTS_OFFSET) // USB_INTS + // Interrupt status after masking & forcing + // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] : SETUP_REQ (0): Device + // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host + // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes + // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes + // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS + // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS + // 0x00000400 [10] : STALL (0): Source: SIE_STATUS + // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS + // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS + // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS + // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS + // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS + // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS + // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host + // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i + io_ro_32 ints; +} usb_hw_t; -#define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE) +#define usb_hw ((usb_hw_t *const)USBCTRL_REGS_BASE) #define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE) #define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE) +static_assert( USB_HOST_INTERRUPT_ENDPOINTS == 15, ""); + #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h index 9956d6831..554d9e447 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,12 +10,37 @@ #define _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/vreg_and_chip_reset.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_vreg_and_chip_reset +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/vreg_and_chip_reset.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(VREG_AND_CHIP_RESET_VREG_OFFSET) // VREG_AND_CHIP_RESET_VREG + // Voltage regulator control and status + // 0x00001000 [12] : ROK (0): regulation status + // 0x000000f0 [7:4] : VSEL (0xb): output voltage select + // 0x00000002 [1] : HIZ (0): high impedance mode select + // 0x00000001 [0] : EN (1): enable io_rw_32 vreg; + + _REG_(VREG_AND_CHIP_RESET_BOD_OFFSET) // VREG_AND_CHIP_RESET_BOD + // brown-out detection control + // 0x000000f0 [7:4] : VSEL (0x9): threshold select + // 0x00000001 [0] : EN (1): enable io_rw_32 bod; + + _REG_(VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET) // VREG_AND_CHIP_RESET_CHIP_RESET + // Chip reset control and status + // 0x01000000 [24] : PSM_RESTART_FLAG (0): This is set by psm_restart from the debugger + // 0x00100000 [20] : HAD_PSM_RESTART (0): Last reset was from the debug port + // 0x00010000 [16] : HAD_RUN (0): Last reset was from the RUN pin + // 0x00000100 [8] : HAD_POR (0): Last reset was from the power-on reset or brown-out detection blocks io_rw_32 chip_reset; } vreg_and_chip_reset_hw_t; diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/watchdog.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/watchdog.h index 2cf05f19d..9579700b6 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/watchdog.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/watchdog.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,14 +10,50 @@ #define _HARDWARE_STRUCTS_WATCHDOG_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/watchdog.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_watchdog +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/watchdog.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(WATCHDOG_CTRL_OFFSET) // WATCHDOG_CTRL + // Watchdog control + // 0x80000000 [31] : TRIGGER (0): Trigger a watchdog reset + // 0x40000000 [30] : ENABLE (0): When not enabled the watchdog timer is paused + // 0x04000000 [26] : PAUSE_DBG1 (1): Pause the watchdog timer when processor 1 is in debug mode + // 0x02000000 [25] : PAUSE_DBG0 (1): Pause the watchdog timer when processor 0 is in debug mode + // 0x01000000 [24] : PAUSE_JTAG (1): Pause the watchdog timer when JTAG is accessing the bus fabric + // 0x00ffffff [23:0] : TIME (0): Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will... io_rw_32 ctrl; + + _REG_(WATCHDOG_LOAD_OFFSET) // WATCHDOG_LOAD + // Load the watchdog timer + // 0x00ffffff [23:0] : LOAD (0) io_wo_32 load; + + _REG_(WATCHDOG_REASON_OFFSET) // WATCHDOG_REASON + // Logs the reason for the last reset + // 0x00000002 [1] : FORCE (0) + // 0x00000001 [0] : TIMER (0) io_ro_32 reason; + + _REG_(WATCHDOG_SCRATCH0_OFFSET) // WATCHDOG_SCRATCH0 + // (Description copied from array index 0 register WATCHDOG_SCRATCH0 applies similarly to other array indexes) + // + // Scratch register io_rw_32 scratch[8]; + + _REG_(WATCHDOG_TICK_OFFSET) // WATCHDOG_TICK + // Controls the tick generator + // 0x000ff800 [19:11] : COUNT (0): Count down timer: the remaining number clk_tick cycles before the next tick is generated + // 0x00000400 [10] : RUNNING (0): Is the tick generator running? + // 0x00000200 [9] : ENABLE (1): start / stop tick generation + // 0x000001ff [8:0] : CYCLES (0): Total number of clk_tick cycles before the next tick io_rw_32 tick; } watchdog_hw_t; diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h index bfa5b1c0c..21885e867 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h @@ -1,29 +1,72 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ + #ifndef _HARDWARE_STRUCTS_XIP_CTRL_H #define _HARDWARE_STRUCTS_XIP_CTRL_H #include "hardware/address_mapped.h" #include "hardware/regs/xip.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xip +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/xip.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + typedef struct { + _REG_(XIP_CTRL_OFFSET) // XIP_CTRL + // Cache control + // 0x00000008 [3] : POWER_DOWN (0): When 1, the cache memories are powered down + // 0x00000002 [1] : ERR_BADWRITE (1): When 1, writes to any alias other than 0x0 (caching, allocating) + // 0x00000001 [0] : EN (1): When 1, enable the cache io_rw_32 ctrl; + + _REG_(XIP_FLUSH_OFFSET) // XIP_FLUSH + // Cache Flush control + // 0x00000001 [0] : FLUSH (0): Write 1 to flush the cache io_rw_32 flush; - io_rw_32 stat; + + _REG_(XIP_STAT_OFFSET) // XIP_STAT + // Cache Status + // 0x00000004 [2] : FIFO_FULL (0): When 1, indicates the XIP streaming FIFO is completely full + // 0x00000002 [1] : FIFO_EMPTY (1): When 1, indicates the XIP streaming FIFO is completely empty + // 0x00000001 [0] : FLUSH_READY (0): Reads as 0 while a cache flush is in progress, and 1 otherwise + io_ro_32 stat; + + _REG_(XIP_CTR_HIT_OFFSET) // XIP_CTR_HIT + // Cache Hit counter io_rw_32 ctr_hit; + + _REG_(XIP_CTR_ACC_OFFSET) // XIP_CTR_ACC + // Cache Access counter io_rw_32 ctr_acc; + + _REG_(XIP_STREAM_ADDR_OFFSET) // XIP_STREAM_ADDR + // FIFO stream address + // 0xfffffffc [31:2] : STREAM_ADDR (0): The address of the next word to be streamed from flash to the streaming FIFO io_rw_32 stream_addr; + + _REG_(XIP_STREAM_CTR_OFFSET) // XIP_STREAM_CTR + // FIFO stream control + // 0x003fffff [21:0] : STREAM_CTR (0): Write a nonzero value to start a streaming read io_rw_32 stream_ctr; - io_rw_32 stream_fifo; -} xip_ctrl_hw_t; -#define XIP_STAT_FIFO_FULL 0x4u -#define XIP_STAT_FIFO_EMPTY 0x2u -#define XIP_STAT_FLUSH_RDY 0x1u + _REG_(XIP_STREAM_FIFO_OFFSET) // XIP_STREAM_FIFO + // FIFO stream data + io_ro_32 stream_fifo; +} xip_ctrl_hw_t; #define xip_ctrl_hw ((xip_ctrl_hw_t *const)XIP_CTRL_BASE) +#define XIP_STAT_FIFO_FULL XIP_STAT_FIFO_FULL_BITS +#define XIP_STAT_FIFO_EMPTY XIP_STAT_FIFO_EMPTY_BITS +#define XIP_STAT_FLUSH_RDY XIP_STAT_FLUSH_READY_BITS + #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xosc.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xosc.h index 698e6a2ff..0ff4db487 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xosc.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2040/hardware_structs/include/hardware/structs/xosc.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,16 +10,47 @@ #define _HARDWARE_STRUCTS_XOSC_H #include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" #include "hardware/regs/xosc.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xosc +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/xosc.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION + /// \tag::xosc_hw[] typedef struct { + _REG_(XOSC_CTRL_OFFSET) // XOSC_CTRL + // Crystal Oscillator Control + // 0x00fff000 [23:12] : ENABLE (0): On power-up this field is initialised to DISABLE and the chip runs from the ROSC + // 0x00000fff [11:0] : FREQ_RANGE (0): Frequency range io_rw_32 ctrl; + + _REG_(XOSC_STATUS_OFFSET) // XOSC_STATUS + // Crystal Oscillator Status + // 0x80000000 [31] : STABLE (0): Oscillator is running and stable + // 0x01000000 [24] : BADWRITE (0): An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT + // 0x00001000 [12] : ENABLED (0): Oscillator is enabled but not necessarily running and stable, resets to 0 + // 0x00000003 [1:0] : FREQ_RANGE (0): The current frequency range setting, always reads 0 io_rw_32 status; + + _REG_(XOSC_DORMANT_OFFSET) // XOSC_DORMANT + // Crystal Oscillator pause control io_rw_32 dormant; + + _REG_(XOSC_STARTUP_OFFSET) // XOSC_STARTUP + // Controls the startup delay + // 0x00100000 [20] : X4 (0): Multiplies the startup_delay by 4 + // 0x00003fff [13:0] : DELAY (0xc4): in multiples of 256*xtal_period io_rw_32 startup; - io_rw_32 _reserved[3]; + + uint32_t _pad0[3]; + + _REG_(XOSC_COUNT_OFFSET) // XOSC_COUNT + // A down counter running at the xosc frequency which counts to zero and stops + // 0x000000ff [7:0] : COUNT (0) io_rw_32 count; } xosc_hw_t; diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_adc/include/hardware/adc.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_adc/include/hardware/adc.h index 13d7c418f..be82025a5 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_adc/include/hardware/adc.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_adc/include/hardware/adc.h @@ -19,7 +19,7 @@ * The RP2040 has an internal analogue-digital converter (ADC) with the following features: * - SAR ADC * - 500 kS/s (Using an independent 48MHz clock) - * - 12 bit (9.5 ENOB) + * - 12 bit (8.7 ENOB) * - 5 input mux: * - 4 inputs that are available on package pins shared with GPIO[29:26] * - 1 input is dedicated to the internal temperature sensor @@ -28,7 +28,7 @@ * - DMA interface * * Although there is only one ADC you can specify the input to it using the adc_select_input() function. - * In round robin mode (adc_rrobin()) will use that input and move to the next one after a read. + * In round robin mode (adc_set_round_robin()), the ADC will use that input and move to the next one after a read. * * User ADC inputs are on 0-3 (GPIO 26-29), the temperature sensor is on input 4. * @@ -62,7 +62,7 @@ void adc_init(void); /*! \brief Initialise the gpio for use as an ADC pin * \ingroup hardware_adc * - * Prepare a GPIO for use with ADC, by disabling all digital functions. + * Prepare a GPIO for use with ADC by disabling all digital functions. * * \param gpio The GPIO number to use. Allowable GPIO numbers are 26 to 29 inclusive. */ @@ -84,10 +84,19 @@ static inline void adc_gpio_init(uint gpio) { * \param input Input to select. */ static inline void adc_select_input(uint input) { - invalid_params_if(ADC, input > 4); + valid_params_if(ADC, input < NUM_ADC_CHANNELS); hw_write_masked(&adc_hw->cs, input << ADC_CS_AINSEL_LSB, ADC_CS_AINSEL_BITS); } +/*! \brief Get the currently selected ADC input channel + * \ingroup hardware_adc + * + * \return The currently selected input channel. 0...3 are GPIOs 26...29 respectively. Input 4 is the onboard temperature sensor. + */ +static inline uint adc_get_selected_input(void) { + return (adc_hw->cs & ADC_CS_AINSEL_BITS) >> ADC_CS_AINSEL_LSB; +} + /*! \brief Round Robin sampling selector * \ingroup hardware_adc * @@ -127,7 +136,7 @@ static inline uint16_t adc_read(void) { while (!(adc_hw->cs & ADC_CS_READY_BITS)) tight_loop_contents(); - return adc_hw->result; + return (uint16_t) adc_hw->result; } /*! \brief Enable or disable free-running sampling mode @@ -158,7 +167,7 @@ static inline void adc_set_clkdiv(float clkdiv) { /*! \brief Setup the ADC FIFO * \ingroup hardware_adc * - * FIFO is 4 samples long, if a conversion is completed and the FIFO is full the result is dropped. + * FIFO is 4 samples long, if a conversion is completed and the FIFO is full, the result is dropped. * * \param en Enables write each conversion result to the FIFO * \param dreq_en Enable DMA requests when FIFO contains data @@ -166,13 +175,13 @@ static inline void adc_set_clkdiv(float clkdiv) { * \param err_in_fifo If enabled, bit 15 of the FIFO contains error flag for each sample * \param byte_shift Shift FIFO contents to be one byte in size (for byte DMA) - enables DMA to byte buffers. */ -static inline void adc_fifo_setup(bool en, bool dreq_en, uint16_t dreq_thresh, bool err_in_fifo, bool byte_shift) { + static inline void adc_fifo_setup(bool en, bool dreq_en, uint16_t dreq_thresh, bool err_in_fifo, bool byte_shift) { hw_write_masked(&adc_hw->fcs, - (!!en << ADC_FCS_EN_LSB) | - (!!dreq_en << ADC_FCS_DREQ_EN_LSB) | - (dreq_thresh << ADC_FCS_THRESH_LSB) | - (!!err_in_fifo << ADC_FCS_ERR_LSB) | - (!!byte_shift << ADC_FCS_SHIFT_LSB), + (bool_to_bit(en) << ADC_FCS_EN_LSB) | + (bool_to_bit(dreq_en) << ADC_FCS_DREQ_EN_LSB) | + (((uint)dreq_thresh) << ADC_FCS_THRESH_LSB) | + (bool_to_bit(err_in_fifo) << ADC_FCS_ERR_LSB) | + (bool_to_bit(byte_shift) << ADC_FCS_SHIFT_LSB), ADC_FCS_EN_BITS | ADC_FCS_DREQ_EN_BITS | ADC_FCS_THRESH_BITS | @@ -184,7 +193,7 @@ static inline void adc_fifo_setup(bool en, bool dreq_en, uint16_t dreq_thresh, b /*! \brief Check FIFO empty state * \ingroup hardware_adc * - * \return Returns true if the fifo is empty + * \return Returns true if the FIFO is empty */ static inline bool adc_fifo_is_empty(void) { return !!(adc_hw->fcs & ADC_FCS_EMPTY_BITS); @@ -205,7 +214,7 @@ static inline uint8_t adc_fifo_get_level(void) { * Pops the latest result from the ADC FIFO. */ static inline uint16_t adc_fifo_get(void) { - return adc_hw->fifo; + return (uint16_t)adc_hw->fifo; } /*! \brief Wait for the ADC FIFO to have data. @@ -216,13 +225,13 @@ static inline uint16_t adc_fifo_get(void) { static inline uint16_t adc_fifo_get_blocking(void) { while (adc_fifo_is_empty()) tight_loop_contents(); - return adc_hw->fifo; + return (uint16_t)adc_hw->fifo; } /*! \brief Drain the ADC FIFO * \ingroup hardware_adc * - * Will wait for any conversion to complete then drain the FIFO discarding any results. + * Will wait for any conversion to complete then drain the FIFO, discarding any results. */ static inline void adc_fifo_drain(void) { // Potentially there is still a conversion in progress -- wait for this to complete before draining diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_base/include/hardware/address_mapped.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_base/include/hardware/address_mapped.h index 6645fbdd0..a3b958413 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_base/include/hardware/address_mapped.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_base/include/hardware/address_mapped.h @@ -48,9 +48,18 @@ * leaving the other bits unchanged. */ +#ifdef __cplusplus +extern "C" { +#endif + #define check_hw_layout(type, member, offset) static_assert(offsetof(type, member) == (offset), "hw offset mismatch") #define check_hw_size(type, size) static_assert(sizeof(type) == (size), "hw size mismatch") +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS, Enable/disable assertions in memory address aliasing macros, type=bool, default=0, group=hardware_base +#ifndef PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS +#define PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS 0 +#endif + typedef volatile uint32_t io_rw_32; typedef const volatile uint32_t io_ro_32; typedef volatile uint32_t io_wo_32; @@ -64,15 +73,44 @@ typedef volatile uint8_t io_wo_8; typedef volatile uint8_t *const ioptr; typedef ioptr const const_ioptr; +// A non-functional (empty) helper macro to help IDEs follow links from the autogenerated +// hardware struct headers in hardware/structs/xxx.h to the raw register definitions +// in hardware/regs/xxx.h. A preprocessor define such as TIMER_TIMEHW_OFFSET (a timer register offset) +// is not generally clickable (in an IDE) if placed in a C comment, so _REG_(TIMER_TIMEHW_OFFSET) is +// included outside of a comment instead +#define _REG_(x) + +// Helper method used by hw_alias macros to optionally check input validity +#define hw_alias_check_addr(addr) ((uintptr_t)(addr)) +// can't use the following impl as it breaks existing static declarations using hw_alias, so would be a backwards incompatibility +//static __force_inline uint32_t hw_alias_check_addr(volatile void *addr) { +// uint32_t rc = (uintptr_t)addr; +// invalid_params_if(ADDRESS_ALIAS, rc < 0x40000000); // catch likely non HW pointer types +// return rc; +//} + +// Helper method used by xip_alias macros to optionally check input validity +static __force_inline uint32_t xip_alias_check_addr(const void *addr) { + uint32_t rc = (uintptr_t)addr; + valid_params_if(ADDRESS_ALIAS, rc >= XIP_MAIN_BASE && rc < XIP_NOALLOC_BASE); + return rc; +} + // Untyped conversion alias pointer generation macros -#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS | (uintptr_t)(addr))) -#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS | (uintptr_t)(addr))) -#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS | (uintptr_t)(addr))) +#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS | hw_alias_check_addr(addr))) +#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS | hw_alias_check_addr(addr))) +#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS | hw_alias_check_addr(addr))) +#define xip_noalloc_alias_untyped(addr) ((void *)(XIP_NOALLOC_BASE | xip_alias_check_addr(addr))) +#define xip_nocache_alias_untyped(addr) ((void *)(XIP_NOCACHE_BASE | xip_alias_check_addr(addr))) +#define xip_nocache_noalloc_alias_untyped(addr) ((void *)(XIP_NOCACHE_NOALLOC_BASE | xip_alias_check_addr(addr))) // Typed conversion alias pointer generation macros #define hw_set_alias(p) ((typeof(p))hw_set_alias_untyped(p)) #define hw_clear_alias(p) ((typeof(p))hw_clear_alias_untyped(p)) #define hw_xor_alias(p) ((typeof(p))hw_xor_alias_untyped(p)) +#define xip_noalloc_alias(p) ((typeof(p))xip_noalloc_alias_untyped(p)) +#define xip_nocache_alias(p) ((typeof(p))xip_nocache_alias_untyped(p)) +#define xip_nocache_noalloc_alias(p) ((typeof(p))xip_nocache_noalloc_alias_untyped(p)) /*! \brief Atomically set the specified bits to 1 in a HW register * \ingroup hardware_base @@ -80,7 +118,7 @@ typedef ioptr const const_ioptr; * \param addr Address of writable register * \param mask Bit-mask specifying bits to set */ -inline static void hw_set_bits(io_rw_32 *addr, uint32_t mask) { +__force_inline static void hw_set_bits(io_rw_32 *addr, uint32_t mask) { *(io_rw_32 *) hw_set_alias_untyped((volatile void *) addr) = mask; } @@ -90,7 +128,7 @@ inline static void hw_set_bits(io_rw_32 *addr, uint32_t mask) { * \param addr Address of writable register * \param mask Bit-mask specifying bits to clear */ -inline static void hw_clear_bits(io_rw_32 *addr, uint32_t mask) { +__force_inline static void hw_clear_bits(io_rw_32 *addr, uint32_t mask) { *(io_rw_32 *) hw_clear_alias_untyped((volatile void *) addr) = mask; } @@ -100,7 +138,7 @@ inline static void hw_clear_bits(io_rw_32 *addr, uint32_t mask) { * \param addr Address of writable register * \param mask Bit-mask specifying bits to invert */ -inline static void hw_xor_bits(io_rw_32 *addr, uint32_t mask) { +__force_inline static void hw_xor_bits(io_rw_32 *addr, uint32_t mask) { *(io_rw_32 *) hw_xor_alias_untyped((volatile void *) addr) = mask; } @@ -116,8 +154,12 @@ inline static void hw_xor_bits(io_rw_32 *addr, uint32_t mask) { * \param values Bits values * \param write_mask Mask of bits to change */ -inline static void hw_write_masked(io_rw_32 *addr, uint32_t values, uint32_t write_mask) { +__force_inline static void hw_write_masked(io_rw_32 *addr, uint32_t values, uint32_t write_mask) { hw_xor_bits(addr, (*addr ^ values) & write_mask); } +#ifdef __cplusplus +} +#endif + #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/include/hardware/claim.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/include/hardware/claim.h index 0c0551355..5c9345394 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/include/hardware/claim.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_claim/include/hardware/claim.h @@ -32,6 +32,10 @@ * 3. Finding unused resources */ +#ifdef __cplusplus +extern "C" { +#endif + /*! \brief Atomically claim a resource, panicking if it is already in use * \ingroup hardware_claim * @@ -61,10 +65,10 @@ int hw_claim_unused_from_range(uint8_t *bits, bool required, uint bit_lsb, uint * The resource ownership is indicated by the bit_index bit in an array of bits. * * \param bits pointer to an array of bits (8 bits per byte) - * \param bit_index resource to unclaim (bit index into array of bits) + * \param bit_index resource to check (bit index into array of bits) * \return true if the resource is claimed */ -bool hw_is_claimed(uint8_t *bits, uint bit_index); +bool hw_is_claimed(const uint8_t *bits, uint bit_index); /*! \brief Atomically unclaim a resource * \ingroup hardware_claim @@ -87,7 +91,7 @@ void hw_claim_clear(uint8_t *bits, uint bit_index); * * \return a token to pass to hw_claim_unlock() */ -uint32_t hw_claim_lock(); +uint32_t hw_claim_lock(void); /*! \brief Release the runtime mutual exclusion lock provided by the `hardware_claim` library * \ingroup hardware_claim @@ -98,4 +102,8 @@ uint32_t hw_claim_lock(); */ void hw_claim_unlock(uint32_t token); -#endif \ No newline at end of file +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/include/hardware/clocks.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/include/hardware/clocks.h index 35940eaae..04d373dcb 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/include/hardware/clocks.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_clocks/include/hardware/clocks.h @@ -99,7 +99,7 @@ extern "C" { * * Must be called before any other clock function. */ -void clocks_init(); +void clocks_init(void); /*! \brief Configure the specified clock * \ingroup hardware_clocks @@ -140,7 +140,7 @@ uint32_t frequency_count_khz(uint src); /*! \brief Set the "current frequency" of the clock as reported by clock_get_hz without actually changing the clock * \ingroup hardware_clocks * - * \see clock_get_hz + * \see clock_get_hz() */ void clock_set_reported_hz(enum clock_index clk_index, uint hz); @@ -170,7 +170,7 @@ void clocks_enable_resus(resus_callback_t resus_callback); /*! \brief Output an optionally divided clock to the specified gpio pin. * \ingroup hardware_clocks * - * \param gpio The GPIO pin to output the clock to. Valid GPIOs are: 21, 23, 24, 26. These GPIOs are connected to the GPOUT0-3 clock generators. + * \param gpio The GPIO pin to output the clock to. Valid GPIOs are: 21, 23, 24, 25. These GPIOs are connected to the GPOUT0-3 clock generators. * \param src The source clock. See the register field CLOCKS_CLK_GPOUT0_CTRL_AUXSRC for a full list. The list is the same for each GPOUT clock generator. * \param div The amount to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock. */ diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/include/hardware/dma.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/include/hardware/dma.h index bd30eaf4b..7c9406f31 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/include/hardware/dma.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/include/hardware/dma.h @@ -34,15 +34,19 @@ extern "C" { * * Memory to memory */ -// this is not defined in generated dreq.h -#define DREQ_FORCE 63 +// these are not defined in generated dreq.h +#define DREQ_DMA_TIMER0 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 +#define DREQ_DMA_TIMER1 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 +#define DREQ_DMA_TIMER2 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 +#define DREQ_DMA_TIMER3 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 +#define DREQ_FORCE DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT // PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_DMA, Enable/disable DMA assertions, type=bool, default=0, group=hardware_dma #ifndef PARAM_ASSERTIONS_ENABLED_DMA #define PARAM_ASSERTIONS_ENABLED_DMA 0 #endif -static inline void check_dma_channel_param(uint channel) { +static inline void check_dma_channel_param(__unused uint channel) { #if PARAM_ASSERTIONS_ENABLED(DMA) // this method is used a lot by inline functions so avoid code bloat by deferring to function extern void check_dma_channel_param_impl(uint channel); @@ -50,6 +54,10 @@ static inline void check_dma_channel_param(uint channel) { #endif } +static inline void check_dma_timer_param(__unused uint timer_num) { + valid_params_if(DMA, timer_num < NUM_DMA_TIMERS); +} + inline static dma_channel_hw_t *dma_channel_hw_addr(uint channel) { check_dma_channel_param(channel); return &dma_hw->ch[channel]; @@ -94,6 +102,16 @@ void dma_channel_unclaim(uint channel); */ int dma_claim_unused_channel(bool required); +/*! \brief Determine if a dma channel is claimed + * \ingroup hardware_dma + * + * \param channel the dma channel + * \return true if the channel is claimed, false otherwise + * \see dma_channel_claim + * \see dma_channel_claim_mask + */ +bool dma_channel_is_claimed(uint channel); + /** \brief DMA channel configuration * \defgroup channel_config channel_config * \ingroup hardware_dma @@ -186,7 +204,7 @@ static inline void channel_config_set_chain_to(dma_channel_config *c, uint chain */ static inline void channel_config_set_transfer_data_size(dma_channel_config *c, enum dma_channel_transfer_size size) { assert(size == DMA_SIZE_8 || size == DMA_SIZE_16 || size == DMA_SIZE_32); - c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) | (size << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB); + c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) | (((uint)size) << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB); } /*! \brief Set address wrapping parameters @@ -353,7 +371,7 @@ static inline void dma_channel_set_read_addr(uint channel, const volatile void * } } -/*! \brief Set the DMA initial read address +/*! \brief Set the DMA initial write address * \ingroup hardware_dma * * \param channel DMA channel @@ -409,7 +427,8 @@ static inline void dma_channel_configure(uint channel, const dma_channel_config * \param read_addr Sets the initial read address * \param transfer_count Number of transfers to make. Not bytes, but the number of transfers of channel_config_set_transfer_data_size() to be sent. */ -inline static void __attribute__((always_inline)) dma_channel_transfer_from_buffer_now(uint channel, void *read_addr, +inline static void __attribute__((always_inline)) dma_channel_transfer_from_buffer_now(uint channel, + const volatile void *read_addr, uint32_t transfer_count) { // check_dma_channel_param(channel); dma_channel_hw_t *hw = dma_channel_hw_addr(channel); @@ -424,7 +443,7 @@ inline static void __attribute__((always_inline)) dma_channel_transfer_from_buff * \param write_addr Sets the initial write address * \param transfer_count Number of transfers to make. Not bytes, but the number of transfers of channel_config_set_transfer_data_size() to be sent. */ -inline static void dma_channel_transfer_to_buffer_now(uint channel, void *write_addr, uint32_t transfer_count) { +inline static void dma_channel_transfer_to_buffer_now(uint channel, volatile void *write_addr, uint32_t transfer_count) { dma_channel_hw_t *hw = dma_channel_hw_addr(channel); hw->write_addr = (uintptr_t) write_addr; hw->al1_transfer_count_trig = transfer_count; @@ -464,7 +483,7 @@ static inline void dma_channel_abort(uint channel) { while (dma_hw->abort & (1ul << channel)) tight_loop_contents(); } -/*! \brief Enable single DMA channel interrupt 0 +/*! \brief Enable single DMA channel's interrupt via DMA_IRQ_0 * \ingroup hardware_dma * * \param channel DMA channel @@ -479,7 +498,7 @@ static inline void dma_channel_set_irq0_enabled(uint channel, bool enabled) { hw_clear_bits(&dma_hw->inte0, 1u << channel); } -/*! \brief Enable multiple DMA channels interrupt 0 +/*! \brief Enable multiple DMA channels' interrupts via DMA_IRQ_0 * \ingroup hardware_dma * * \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. @@ -493,7 +512,7 @@ static inline void dma_set_irq0_channel_mask_enabled(uint32_t channel_mask, bool } } -/*! \brief Enable single DMA channel interrupt 1 +/*! \brief Enable single DMA channel's interrupt via DMA_IRQ_1 * \ingroup hardware_dma * * \param channel DMA channel @@ -508,7 +527,7 @@ static inline void dma_channel_set_irq1_enabled(uint channel, bool enabled) { hw_clear_bits(&dma_hw->inte1, 1u << channel); } -/*! \brief Enable multiple DMA channels interrupt 0 +/*! \brief Enable multiple DMA channels' interrupts via DMA_IRQ_1 * \ingroup hardware_dma * * \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. @@ -522,6 +541,105 @@ static inline void dma_set_irq1_channel_mask_enabled(uint32_t channel_mask, bool } } +/*! \brief Enable single DMA channel interrupt on either DMA_IRQ_0 or DMA_IRQ_1 + * \ingroup hardware_dma + * + * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1 + * \param channel DMA channel + * \param enabled true to enable interrupt via irq_index for specified channel, false to disable. + */ +static inline void dma_irqn_set_channel_enabled(uint irq_index, uint channel, bool enabled) { + invalid_params_if(DMA, irq_index > 1); + if (irq_index) { + dma_channel_set_irq1_enabled(channel, enabled); + } else { + dma_channel_set_irq0_enabled(channel, enabled); + } +} + +/*! \brief Enable multiple DMA channels' interrupt via either DMA_IRQ_0 or DMA_IRQ_1 + * \ingroup hardware_dma + * + * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1 + * \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. + * \param enabled true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask. + */ +static inline void dma_irqn_set_channel_mask_enabled(uint irq_index, uint32_t channel_mask, bool enabled) { + invalid_params_if(DMA, irq_index > 1); + if (irq_index) { + dma_set_irq1_channel_mask_enabled(channel_mask, enabled); + } else { + dma_set_irq0_channel_mask_enabled(channel_mask, enabled); + } +} + +/*! \brief Determine if a particular channel is a cause of DMA_IRQ_0 + * \ingroup hardware_dma + * + * \param channel DMA channel + * \return true if the channel is a cause of DMA_IRQ_0, false otherwise + */ +static inline bool dma_channel_get_irq0_status(uint channel) { + check_dma_channel_param(channel); + return dma_hw->ints0 & (1u << channel); +} + +/*! \brief Determine if a particular channel is a cause of DMA_IRQ_1 + * \ingroup hardware_dma + * + * \param channel DMA channel + * \return true if the channel is a cause of DMA_IRQ_1, false otherwise + */ +static inline bool dma_channel_get_irq1_status(uint channel) { + check_dma_channel_param(channel); + return dma_hw->ints1 & (1u << channel); +} + +/*! \brief Determine if a particular channel is a cause of DMA_IRQ_N + * \ingroup hardware_dma + * + * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1 + * \param channel DMA channel + * \return true if the channel is a cause of the DMA_IRQ_N, false otherwise + */ +static inline bool dma_irqn_get_channel_status(uint irq_index, uint channel) { + invalid_params_if(DMA, irq_index > 1); + check_dma_channel_param(channel); + return (irq_index ? dma_hw->ints1 : dma_hw->ints0) & (1u << channel); +} + +/*! \brief Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_0 + * \ingroup hardware_dma + * + * \param channel DMA channel + */ +static inline void dma_channel_acknowledge_irq0(uint channel) { + check_dma_channel_param(channel); + hw_set_bits(&dma_hw->ints0, (1u << channel)); +} + +/*! \brief Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_1 + * \ingroup hardware_dma + * + * \param channel DMA channel + */ +static inline void dma_channel_acknowledge_irq1(uint channel) { + check_dma_channel_param(channel); + hw_set_bits(&dma_hw->ints1, (1u << channel)); +} + +/*! \brief Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_N + * \ingroup hardware_dma + * + * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1 + * \param channel DMA channel + */ +static inline void dma_irqn_acknowledge_channel(uint irq_index, uint channel) { + invalid_params_if(DMA, irq_index > 1); + check_dma_channel_param(channel); + hw_set_bits(irq_index ? &dma_hw->ints1 : &dma_hw->ints0, (1u << channel)); +} + /*! \brief Check if DMA channel is busy * \ingroup hardware_dma * @@ -540,6 +658,8 @@ inline static bool dma_channel_is_busy(uint channel) { */ inline static void dma_channel_wait_for_finish_blocking(uint channel) { while (dma_channel_is_busy(channel)) tight_loop_contents(); + // stop the compiler hoisting a non volatile buffer access above the DMA completion. + __compiler_memory_barrier(); } /*! \brief Enable the DMA sniffing targeting the specified channel @@ -595,10 +715,75 @@ inline static void dma_sniffer_set_byte_swap_enabled(bool swap) { * \ingroup hardware_dma * */ -inline static void dma_sniffer_disable() { +inline static void dma_sniffer_disable(void) { dma_hw->sniff_ctrl = 0; } +/*! \brief Mark a dma timer as used + * \ingroup hardware_dma + * + * Method for cooperative claiming of hardware. Will cause a panic if the timer + * is already claimed. Use of this method by libraries detects accidental + * configurations that would fail in unpredictable ways. + * + * \param timer the dma timer + */ +void dma_timer_claim(uint timer); + +/*! \brief Mark a dma timer as no longer used + * \ingroup hardware_dma + * + * Method for cooperative claiming of hardware. + * + * \param timer the dma timer to release + */ +void dma_timer_unclaim(uint timer); + +/*! \brief Claim a free dma timer + * \ingroup hardware_dma + * + * \param required if true the function will panic if none are available + * \return the dma timer number or -1 if required was false, and none were free + */ +int dma_claim_unused_timer(bool required); + +/*! \brief Determine if a dma timer is claimed + * \ingroup hardware_dma + * + * \param timer the dma timer + * \return true if the timer is claimed, false otherwise + * \see dma_timer_claim + */ +bool dma_timer_is_claimed(uint timer); + +/*! \brief Set the divider for the given DMA timer + * \ingroup hardware_dma + * + * The timer will run at the system_clock_freq * numerator / denominator, so this is the speed + * that data elements will be transferred at via a DMA channel using this timer as a DREQ + * + * \param timer the dma timer + * \param numerator the fraction's numerator + * \param denominator the fraction's denominator + */ +static inline void dma_timer_set_fraction(uint timer, uint16_t numerator, uint16_t denominator) { + check_dma_timer_param(timer); + dma_hw->timer[timer] = (((uint32_t)numerator) << DMA_TIMER0_X_LSB) | (((uint32_t)denominator) << DMA_TIMER0_Y_LSB); +} + +/*! \brief Return the DREQ number for a given DMA timer + * \ingroup hardware_dma + * + * \param timer_num DMA timer number 0-3 + */ +static inline uint dma_get_timer_dreq(uint timer_num) { + static_assert(DREQ_DMA_TIMER1 == DREQ_DMA_TIMER0 + 1, ""); + static_assert(DREQ_DMA_TIMER2 == DREQ_DMA_TIMER0 + 2, ""); + static_assert(DREQ_DMA_TIMER3 == DREQ_DMA_TIMER0 + 3, ""); + check_dma_timer_param(timer_num); + return DREQ_DMA_TIMER0 + timer_num; +} + #ifndef NDEBUG void print_dma_ctrl(dma_channel_hw_t *channel); #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_exception/include/hardware/exception.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_exception/include/hardware/exception.h new file mode 100644 index 000000000..005168bcd --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_exception/include/hardware/exception.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_EXCEPTION_H_ +#define _HARDWARE_EXCEPTION_H_ + +#include "pico.h" +#include "hardware/address_mapped.h" +#include "hardware/regs/m0plus.h" + +/** \file exception.h + * \defgroup hardware_exception hardware_exception + * + * Methods for setting processor exception handlers + * + * Exceptions are identified by a \ref exception_number which is a number from -15 to -1; these are the numbers relative to + * the index of the first IRQ vector in the vector table. (i.e. vector table index is exception_num plus 16) + * + * There is one set of exception handlers per core, so the exception handlers for each core as set by these methods are independent. + * + * \note That all exception APIs affect the executing core only (i.e. the core calling the function). + */ + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_EXCEPTION, Enable/disable assertions in the exception module, type=bool, default=0, group=hardware_exception +#ifndef PARAM_ASSERTIONS_ENABLED_EXCEPTION +#define PARAM_ASSERTIONS_ENABLED_EXCEPTION 0 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*! \brief Exception number definitions + * + * Note for consistency with irq numbers, these numbers are defined to be negative. The VTABLE index is + * the number here plus 16. + * + * Name | Value | Exception + * ---------------------|-------|---------- + * NMI_EXCEPTION | -14 | Non Maskable Interrupt + * HARDFAULT_EXCEPTION | -13 | HardFault + * SVCALL_EXCEPTION | -5 | SV Call + * PENDSV_EXCEPTION | -2 | Pend SV + * SYSTICK_EXCEPTION | -1 | System Tick + * + * \ingroup hardware_exception + */ +enum exception_number { + NMI_EXCEPTION = -14, /* Non Maskable Interrupt */ + HARDFAULT_EXCEPTION = -13, /* HardFault Interrupt */ + SVCALL_EXCEPTION = -5, /* SV Call Interrupt */ + PENDSV_EXCEPTION = -2, /* Pend SV Interrupt */ + SYSTICK_EXCEPTION = -1, /* System Tick Interrupt */ +}; + +/*! \brief Exception handler function type + * \ingroup hardware_exception + * + * All exception handlers should be of this type, and follow normal ARM EABI register saving conventions + */ +typedef void (*exception_handler_t)(void); + +/*! \brief Set the exception handler for an exception on the executing core. + * \ingroup hardware_exception + * + * This method will assert if an exception handler has been set for this exception number on this core via + * this method, without an intervening restore via exception_restore_handler. + * + * \note this method may not be used to override an exception handler that was specified at link time by + * providing a strong replacement for the weakly defined stub exception handlers. It will assert in this case too. + * + * \param num Exception number + * \param handler The handler to set + * \see exception_number + */ +exception_handler_t exception_set_exclusive_handler(enum exception_number num, exception_handler_t handler); + +/*! \brief Restore the original exception handler for an exception on this core + * \ingroup hardware_exception + * + * This method may be used to restore the exception handler for an exception on this core to the state + * prior to the call to exception_set_exclusive_handler(), so that exception_set_exclusive_handler() + * may be called again in the future. + * + * \param num Exception number \ref exception_number + * \param original_handler The original handler returned from \ref exception_set_exclusive_handler + * \see exception_set_exclusive_handler() + */ +void exception_restore_handler(enum exception_number num, exception_handler_t original_handler); + +/*! \brief Get the current exception handler for the specified exception from the currently installed vector table + * of the execution core + * \ingroup hardware_exception + * + * \param num Exception number + * \return the address stored in the VTABLE for the given exception number + */ +exception_handler_t exception_get_vtable_handler(enum exception_number num); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/include/hardware/flash.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/include/hardware/flash.h index 40e2949d6..e6cd229bb 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/include/hardware/flash.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/include/hardware/flash.h @@ -9,17 +9,6 @@ #include "pico.h" -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_FLASH, Enable/disable assertions in the flash module, type=bool, default=0, group=hardware_flash -#ifndef PARAM_ASSERTIONS_ENABLED_FLASH -#define PARAM_ASSERTIONS_ENABLED_FLASH 0 -#endif - -#define FLASH_PAGE_SIZE (1u << 8) -#define FLASH_SECTOR_SIZE (1u << 12) -#define FLASH_BLOCK_SIZE (1u << 16) - -#define FLASH_UNIQUE_ID_SIZE_BYTES 8 - /** \file flash.h * \defgroup hardware_flash hardware_flash * @@ -44,6 +33,22 @@ * \include flash_program.c */ +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_FLASH, Enable/disable assertions in the flash module, type=bool, default=0, group=hardware_flash +#ifndef PARAM_ASSERTIONS_ENABLED_FLASH +#define PARAM_ASSERTIONS_ENABLED_FLASH 0 +#endif + +#define FLASH_PAGE_SIZE (1u << 8) +#define FLASH_SECTOR_SIZE (1u << 12) +#define FLASH_BLOCK_SIZE (1u << 16) + +#define FLASH_UNIQUE_ID_SIZE_BYTES 8 + +// PICO_CONFIG: PICO_FLASH_SIZE_BYTES, size of primary flash in bytes, type=int, group=hardware_flash + +#ifdef __cplusplus +extern "C" { +#endif /*! \brief Erase areas of flash * \ingroup hardware_flash @@ -75,4 +80,34 @@ void flash_range_program(uint32_t flash_offs, const uint8_t *data, size_t count) */ void flash_get_unique_id(uint8_t *id_out); +/*! \brief Execute bidirectional flash command + * \ingroup hardware_flash + * + * Low-level function to execute a serial command on a flash device attached + * to the QSPI interface. Bytes are simultaneously transmitted and received + * from txbuf and to rxbuf. Therefore, both buffers must be the same length, + * count, which is the length of the overall transaction. This is useful for + * reading metadata from the flash chip, such as device ID or SFDP + * parameters. + * + * The XIP cache is flushed following each command, in case flash state + * has been modified. Like other hardware_flash functions, the flash is not + * accessible for execute-in-place transfers whilst the command is in + * progress, so entering a flash-resident interrupt handler or executing flash + * code on the second core concurrently will be fatal. To avoid these pitfalls + * it is recommended that this function only be used to extract flash metadata + * during startup, before the main application begins to run: see the + * implementation of pico_get_unique_id() for an example of this. + * + * \param txbuf Pointer to a byte buffer which will be transmitted to the flash + * \param rxbuf Pointer to a byte buffer where data received from the flash will be written. txbuf and rxbuf may be the same buffer. + * \param count Length in bytes of txbuf and of rxbuf + */ +void flash_do_cmd(const uint8_t *txbuf, uint8_t *rxbuf, size_t count); + + +#ifdef __cplusplus +} +#endif + #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/include/hardware/gpio.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/include/hardware/gpio.h index 563c6a013..87e75e7a5 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/include/hardware/gpio.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_gpio/include/hardware/gpio.h @@ -96,7 +96,7 @@ enum gpio_function { GPIO_FUNC_PIO1 = 7, GPIO_FUNC_GPCK = 8, GPIO_FUNC_USB = 9, - GPIO_FUNC_NULL = 0xf, + GPIO_FUNC_NULL = 0x1f, }; #define GPIO_OUT 1 @@ -124,6 +124,13 @@ enum gpio_irq_level { GPIO_IRQ_EDGE_RISE = 0x8u, }; +/*! Callback function type for GPIO events + * \ingroup hardware_gpio + * + * \param gpio Which GPIO caused this interrupt + * \param events Which events caused this interrupt. See \ref gpio_set_irq_enabled for details. + * \sa gpio_set_irq_enabled_with_callback() + */ typedef void (*gpio_irq_callback_t)(uint gpio, uint32_t events); enum gpio_override { @@ -133,6 +140,31 @@ enum gpio_override { GPIO_OVERRIDE_HIGH = 3, ///< drive high/enable output }; +/*! \brief Slew rate limiting levels for GPIO outputs + * \ingroup hardware_gpio + * + * Slew rate limiting increases the minimum rise/fall time when a GPIO output + * is lightly loaded, which can help to reduce electromagnetic emissions. + * \sa gpio_set_slew_rate + */ +enum gpio_slew_rate { + GPIO_SLEW_RATE_SLOW = 0, ///< Slew rate limiting enabled + GPIO_SLEW_RATE_FAST = 1 ///< Slew rate limiting disabled +}; + +/*! \brief Drive strength levels for GPIO outputs + * \ingroup hardware_gpio + * + * Drive strength levels for GPIO outputs. + * \sa gpio_set_drive_strength + */ +enum gpio_drive_strength { + GPIO_DRIVE_STRENGTH_2MA = 0, ///< 2 mA nominal drive strength + GPIO_DRIVE_STRENGTH_4MA = 1, ///< 4 mA nominal drive strength + GPIO_DRIVE_STRENGTH_8MA = 2, ///< 8 mA nominal drive strength + GPIO_DRIVE_STRENGTH_12MA = 3 ///< 12 mA nominal drive strength +}; + // ---------------------------------------------------------------------------- // Pad Controls + IO Muxing // ---------------------------------------------------------------------------- @@ -146,6 +178,12 @@ enum gpio_override { */ void gpio_set_function(uint gpio, enum gpio_function fn); +/*! \brief Determine current GPIO function + * \ingroup hardware_gpio + * + * \param gpio GPIO number + * \return Which GPIO function is currently selected from list \ref gpio_function + */ enum gpio_function gpio_get_function(uint gpio); /*! \brief Select up and down pulls on specific GPIO @@ -207,6 +245,16 @@ static inline void gpio_disable_pulls(uint gpio) { gpio_set_pulls(gpio, false, false); } +/*! \brief Set GPIO IRQ override + * \ingroup hardware_gpio + * + * Optionally invert a GPIO IRQ signal, or drive it high or low + * + * \param gpio GPIO number + * \param value See \ref gpio_override + */ +void gpio_set_irqover(uint gpio, uint value); + /*! \brief Set GPIO output override * \ingroup hardware_gpio * @@ -239,6 +287,65 @@ void gpio_set_oeover(uint gpio, uint value); */ void gpio_set_input_enabled(uint gpio, bool enabled); +/*! \brief Enable/disable GPIO input hysteresis (Schmitt trigger) + * \ingroup hardware_gpio + * + * Enable or disable the Schmitt trigger hysteresis on a given GPIO. This is + * enabled on all GPIOs by default. Disabling input hysteresis can lead to + * inconsistent readings when the input signal has very long rise or fall + * times, but slightly reduces the GPIO's input delay. + * + * \sa gpio_is_input_hysteresis_enabled + * \param gpio GPIO number + * \param enabled true to enable input hysteresis on specified GPIO + */ +void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled); + +/*! \brief Determine whether input hysteresis is enabled on a specified GPIO + * \ingroup hardware_gpio + * + * \sa gpio_set_input_hysteresis_enabled + * \param gpio GPIO number + */ +bool gpio_is_input_hysteresis_enabled(uint gpio); + + +/*! \brief Set slew rate for a specified GPIO + * \ingroup hardware_gpio + * + * \sa gpio_get_slew_rate + * \param gpio GPIO number + * \param slew GPIO output slew rate + */ +void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew); + +/*! \brief Determine current slew rate for a specified GPIO + * \ingroup hardware_gpio + * + * \sa gpio_set_slew_rate + * \param gpio GPIO number + * \return Current slew rate of that GPIO + */ +enum gpio_slew_rate gpio_get_slew_rate(uint gpio); + +/*! \brief Set drive strength for a specified GPIO + * \ingroup hardware_gpio + * + * \sa gpio_get_drive_strength + * \param gpio GPIO number + * \param drive GPIO output drive strength + */ +void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive); + +/*! \brief Determine current slew rate for a specified GPIO + * \ingroup hardware_gpio + * + * \sa gpio_set_drive_strength + * \param gpio GPIO number + * \return Current drive strength of that GPIO + */ +enum gpio_drive_strength gpio_get_drive_strength(uint gpio); + /*! \brief Enable or disable interrupts for specified GPIO * \ingroup hardware_gpio * @@ -267,7 +374,7 @@ void gpio_set_irq_enabled(uint gpio, uint32_t events, bool enabled); * the processor that calls the function. * * \param gpio GPIO number - * \param events Which events will cause an interrupt See \ref gpio_set_irq_enabled for details. + * \param events Which events will cause an interrupt. See \ref gpio_set_irq_enabled for details. * \param enabled Enable or disable flag * \param callback user function to call on GPIO irq. Note only one of these can be set per processor. * @@ -300,7 +407,7 @@ void gpio_acknowledge_irq(uint gpio, uint32_t events); /*! \brief Initialise a GPIO for (enabled I/O and set func to GPIO_FUNC_SIO) * \ingroup hardware_gpio * - * Clear the output enable (i.e. set to input) + * Clear the output enable (i.e. set to input). * Clear any output value. * * \param gpio GPIO number @@ -310,7 +417,7 @@ void _gpio_init(uint gpio); /*! \brief Initialise multiple GPIOs (enabled I/O and set func to GPIO_FUNC_SIO) * \ingroup hardware_gpio * - * Clear the output enable (i.e. set to input) + * Clear the output enable (i.e. set to input). * Clear any output value. * * \param gpio_mask Mask with 1 bit per GPIO number to initialize @@ -335,7 +442,7 @@ static inline bool gpio_get(uint gpio) { * * \return Bitmask of raw GPIO values, as bits 0-29 */ -static inline uint32_t gpio_get_all() { +static inline uint32_t gpio_get_all(void) { return sio_hw->gpio_in; } @@ -408,6 +515,26 @@ static inline void gpio_put(uint gpio, bool value) { gpio_clr_mask(mask); } +/*! \brief Determine whether a GPIO is currently driven high or low + * \ingroup hardware_gpio + * + * This function returns the high/low output level most recently assigned to a + * GPIO via gpio_put() or similar. This is the value that is presented outward + * to the IO muxing, *not* the input level back from the pad (which can be + * read using gpio_get()). + * + * To avoid races, this function must not be used for read-modify-write + * sequences when driving GPIOs -- instead functions like gpio_put() should be + * used to atomically update GPIOs. This accessor is intended for debug use + * only. + * + * \param gpio GPIO number + * \return true if the GPIO output level is high, false if low. + */ +static inline bool gpio_get_out_level(uint gpio) { + return !!(sio_hw->gpio_out & (1u << gpio)); +} + // ---------------------------------------------------------------------------- // Direction // ---------------------------------------------------------------------------- @@ -490,7 +617,7 @@ static inline uint gpio_get_dir(uint gpio) { return gpio_is_dir_out(gpio); // note GPIO_OUT is 1/true and GPIO_IN is 0/false anyway } -extern void gpio_debug_pins_init(); +extern void gpio_debug_pins_init(void); #ifdef __cplusplus } diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h index 2b5dca779..258bad6a5 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_i2c/include/hardware/i2c.h @@ -10,6 +10,7 @@ #include "pico.h" #include "pico/time.h" #include "hardware/structs/i2c.h" +#include "hardware/regs/dreq.h" #include "stdio.h" // PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_I2C, Enable/disable assertions in the I2C module, type=bool, default=0, group=hardware_i2c @@ -27,10 +28,12 @@ extern "C" { * I2C Controller API * * The I2C bus is a two-wire serial interface, consisting of a serial data line SDA and a serial clock SCL. These wires carry - * information between the devices connected to the bus. Each device is recognized by a unique address and can operate as + * information between the devices connected to the bus. Each device is recognized by a unique 7-bit address and can operate as * either a “transmitter” or “receiver”, depending on the function of the device. Devices can also be considered as masters or * slaves when performing data transfers. A master is a device that initiates a data transfer on the bus and generates the - * clock signals to permit that transfer. At that time, any device addressed is considered a slave. + * clock signals to permit that transfer. The first byte in the data transfer always contains the 7-bit address and + * a read/write bit in the LSB position. This API takes care of toggling the read/write bit. After this, any device addressed + * is considered a slave. * * This API allows the controller to be set up as a master or a slave using the \ref i2c_set_slave_mode function. * @@ -49,6 +52,10 @@ extern "C" { typedef struct i2c_inst i2c_inst_t; +// PICO_CONFIG: PICO_DEFAULT_I2C, Define the default I2C for a board, min=0, max=1, group=hardware_i2c +// PICO_CONFIG: PICO_DEFAULT_I2C_SDA_PIN, Define the default I2C SDA pin, min=0, max=29, group=hardware_i2c +// PICO_CONFIG: PICO_DEFAULT_I2C_SCL_PIN, Define the default I2C SCL pin, min=0, max=29, group=hardware_i2c + /** The I2C identifiers for use in I2C functions. * * e.g. i2c_init(i2c0, 48000) @@ -62,6 +69,14 @@ extern i2c_inst_t i2c1_inst; #define i2c0 (&i2c0_inst) ///< Identifier for I2C HW Block 0 #define i2c1 (&i2c1_inst) ///< Identifier for I2C HW Block 1 +#if !defined(PICO_DEFAULT_I2C_INSTANCE) && defined(PICO_DEFAULT_I2C) +#define PICO_DEFAULT_I2C_INSTANCE (__CONCAT(i2c,PICO_DEFAULT_I2C)) +#endif + +#ifdef PICO_DEFAULT_I2C_INSTANCE +#define i2c_default PICO_DEFAULT_I2C_INSTANCE +#endif + /** @} */ // ---------------------------------------------------------------------------- @@ -123,11 +138,11 @@ struct i2c_inst { bool restart_on_next; }; -/*! \brief Convert I2c instance to hardware instance number +/*! \brief Convert I2C instance to hardware instance number * \ingroup hardware_i2c * * \param i2c I2C instance - * \return Number of UART, 0 or 1. + * \return Number of I2C, 0 or 1. */ static inline uint i2c_hw_index(i2c_inst_t *i2c) { invalid_params_if(I2C, i2c != i2c0 && i2c != i2c1); @@ -143,7 +158,7 @@ static inline i2c_hw_t *i2c_get_hw(i2c_inst_t *i2c) { * \ingroup hardware_i2c * * \param i2c Either \ref i2c0 or \ref i2c1 - * \param addr Address of device to write to + * \param addr 7-bit address of device to write to * \param src Pointer to data to send * \param len Length of data in bytes to send * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), @@ -160,7 +175,7 @@ int i2c_write_blocking_until(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, * \ingroup hardware_i2c * * \param i2c Either \ref i2c0 or \ref i2c1 - * \param addr Address of device to read from + * \param addr 7-bit address of device to read from * \param dst Pointer to buffer to receive data * \param len Length of data in bytes to receive * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), @@ -174,7 +189,7 @@ int i2c_read_blocking_until(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t * \ingroup hardware_i2c * * \param i2c Either \ref i2c0 or \ref i2c1 - * \param addr Address of device to write to + * \param addr 7-bit address of device to write to * \param src Pointer to data to send * \param len Length of data in bytes to send * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), @@ -196,7 +211,7 @@ int i2c_write_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, const uint8_t * * \ingroup hardware_i2c * * \param i2c Either \ref i2c0 or \ref i2c1 - * \param addr Address of device to read from + * \param addr 7-bit address of device to read from * \param dst Pointer to buffer to receive data * \param len Length of data in bytes to receive * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), @@ -215,7 +230,7 @@ int i2c_read_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, si * \ingroup hardware_i2c * * \param i2c Either \ref i2c0 or \ref i2c1 - * \param addr Address of device to write to + * \param addr 7-bit address of device to write to * \param src Pointer to data to send * \param len Length of data in bytes to send * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), @@ -228,12 +243,12 @@ int i2c_write_blocking(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t * \ingroup hardware_i2c * * \param i2c Either \ref i2c0 or \ref i2c1 - * \param addr Address of device to read from + * \param addr 7-bit address of device to read from * \param dst Pointer to buffer to receive data * \param len Length of data in bytes to receive * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued), * and the next transfer will begin with a Restart rather than a Start. - * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged, no device present. + * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged or no device present. */ int i2c_read_blocking(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop); @@ -246,7 +261,7 @@ int i2c_read_blocking(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, b * least that many bytes can be written without blocking. */ static inline size_t i2c_get_write_available(i2c_inst_t *i2c) { - const size_t IC_TX_BUFFER_DEPTH = 32; + const size_t IC_TX_BUFFER_DEPTH = 16; return IC_TX_BUFFER_DEPTH - i2c_get_hw(i2c)->txflr; } @@ -268,7 +283,7 @@ static inline size_t i2c_get_read_available(i2c_inst_t *i2c) { * \param src Data to send * \param len Number of bytes to send * - * Writes directly to the to I2C TX FIFO which us mainly useful for + * Writes directly to the I2C TX FIFO which is mainly useful for * slave-mode operation. */ static inline void i2c_write_raw_blocking(i2c_inst_t *i2c, const uint8_t *src, size_t len) { @@ -280,18 +295,17 @@ static inline void i2c_write_raw_blocking(i2c_inst_t *i2c, const uint8_t *src, s } } -/*! \brief Write direct to TX FIFO +/*! \brief Read direct from RX FIFO * \ingroup hardware_i2c * * \param i2c Either \ref i2c0 or \ref i2c1 * \param dst Buffer to accept data - * \param len Number of bytes to send + * \param len Number of bytes to read * - * Reads directly from the I2C RX FIFO which us mainly useful for + * Reads directly from the I2C RX FIFO which is mainly useful for * slave-mode operation. */ static inline size_t i2c_read_raw_blocking(i2c_inst_t *i2c, uint8_t *dst, size_t len) { - size_t bytes_read = 0; for (size_t i = 0; i < len; ++i) { @@ -318,7 +332,20 @@ static inline size_t i2c_read_raw_blocking(i2c_inst_t *i2c, uint8_t *dst, size_t } - return bytes_read; + return bytes_read; +} + +/*! \brief Return the DREQ to use for pacing transfers to/from a particular I2C instance + * \ingroup hardware_i2c + * + * \param i2c Either \ref i2c0 or \ref i2c1 + * \param is_tx true for sending data to the I2C instance, false for receiving data from the I2C instance + */ +static inline uint i2c_get_dreq(i2c_inst_t *i2c, bool is_tx) { + static_assert(DREQ_I2C0_RX == DREQ_I2C0_TX + 1, ""); + static_assert(DREQ_I2C1_RX == DREQ_I2C1_TX + 1, ""); + static_assert(DREQ_I2C1_TX == DREQ_I2C0_TX + 2, ""); + return DREQ_I2C0_TX + i2c_hw_index(i2c) * 2 + !is_tx; } #ifdef __cplusplus diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_interp/include/hardware/interp.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_interp/include/hardware/interp.h index 18cefc53e..35372e975 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_interp/include/hardware/interp.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_interp/include/hardware/interp.h @@ -55,7 +55,7 @@ typedef struct { } interp_config; static inline uint interp_index(interp_hw_t *interp) { - assert(interp == interp0 || interp == interp1); + valid_params_if(INTERP, interp == interp0 || interp == interp1); return interp == interp1 ? 1 : 0; } @@ -70,6 +70,8 @@ static inline uint interp_index(interp_hw_t *interp) { * \param lane The lane number, 0 or 1. */ void interp_claim_lane(interp_hw_t *interp, uint lane); +// The above really should be called this for consistency +#define interp_lane_claim interp_claim_lane /*! \brief Claim the interpolator lanes specified in the mask * \ingroup hardware_interp @@ -86,6 +88,27 @@ void interp_claim_lane_mask(interp_hw_t *interp, uint lane_mask); * \param lane The lane number, 0 or 1 */ void interp_unclaim_lane(interp_hw_t *interp, uint lane); +// The above really should be called this for consistency +#define interp_lane_unclaim interp_unclaim_lane + +/*! \brief Determine if an interpolator lane is claimed + * \ingroup hardware_interp + * + * \param interp Interpolator whose lane to check + * \param lane The lane number, 0 or 1 + * \return true if claimed, false otherwise + * \see interp_claim_lane + * \see interp_claim_lane_mask + */ +bool interp_lane_is_claimed(interp_hw_t *interp, uint lane); + +/*! \brief Release previously claimed interpolator lanes \see interp_claim_lane_mask + * \ingroup hardware_interp + * + * \param interp Interpolator on which to release lanes. interp0 or interp1 + * \param lane_mask Bit pattern of lanes to unclaim (only bits 0 and 1 are valid) + */ +void interp_unclaim_lane_mask(interp_hw_t *interp, uint lane_mask); /*! \brief Set the interpolator shift value * \ingroup interp_config @@ -231,7 +254,7 @@ static inline void interp_config_set_force_bits(interp_config *c, uint bits) { * * \return A default interpolation configuration */ -static inline interp_config interp_default_config() { +static inline interp_config interp_default_config(void) { interp_config c = {0}; // Just pass through everything interp_config_set_mask(&c, 0, 31); @@ -277,9 +300,9 @@ static inline void interp_set_force_bits(interp_hw_t *interp, uint lane, uint bi } typedef struct { - io_rw_32 accum[2]; - io_rw_32 base[3]; - io_rw_32 ctrl[2]; + uint32_t accum[2]; + uint32_t base[3]; + uint32_t ctrl[2]; } interp_hw_save_t; /*! \brief Save the specified interpolator state diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/include/hardware/irq.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/include/hardware/irq.h index 6075118f2..424a49712 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/include/hardware/irq.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_irq/include/hardware/irq.h @@ -8,12 +8,12 @@ #define _HARDWARE_IRQ_H_ // These two config items are also used by assembler, so keeping separate -// PICO_CONFIG: PICO_MAX_SHARED_IRQ_HANDLERS, Maximum Number of shared IRQ handers, default=4, advanced=true, group=hardware_irq +// PICO_CONFIG: PICO_MAX_SHARED_IRQ_HANDLERS, Maximum number of shared IRQ handlers, default=4, advanced=true, group=hardware_irq #ifndef PICO_MAX_SHARED_IRQ_HANDLERS #define PICO_MAX_SHARED_IRQ_HANDLERS 4u #endif -// PICO_CONFIG: PICO_DISABLE_SHARED_IRQ_HANDLERS, Disable shared IRQ handers, type=bool, default=0, group=hardware_irq +// PICO_CONFIG: PICO_DISABLE_SHARED_IRQ_HANDLERS, Disable shared IRQ handlers, type=bool, default=0, group=hardware_irq #ifndef PICO_DISABLE_SHARED_IRQ_HANDLERS #define PICO_DISABLE_SHARED_IRQ_HANDLERS 0 #endif @@ -21,6 +21,7 @@ #ifndef __ASSEMBLER__ #include "pico.h" +#include "hardware/address_mapped.h" #include "hardware/regs/intctrl.h" #include "hardware/regs/m0plus.h" @@ -36,13 +37,13 @@ * On the RP2040, only the lower 26 IRQ signals are connected on the NVIC; IRQs 26 to 31 are tied to zero (never firing). * * There is one NVIC per core, and each core's NVIC has the same hardware interrupt lines routed to it, with the exception of the IO interrupts - * where there is one IO interrupt per bank, per core. These are completely independent, so for example, processor 0 can be + * where there is one IO interrupt per bank, per core. These are completely independent, so, for example, processor 0 can be * interrupted by GPIO 0 in bank 0, and processor 1 by GPIO 1 in the same bank. * * \note That all IRQ APIs affect the executing core only (i.e. the core calling the function). * * \note You should not enable the same (shared) IRQ number on both cores, as this will lead to race conditions - * or starvation of one of the cores. Additionally don't forget that disabling interrupts on one core does not disable interrupts + * or starvation of one of the cores. Additionally, don't forget that disabling interrupts on one core does not disable interrupts * on the other core. * * There are three different ways to set handlers for an IRQ: @@ -52,7 +53,7 @@ * you will not be able to change it using the above APIs at runtime). Using this method can cause link conflicts at runtime, and offers no runtime performance benefit (i.e, it should not generally be used). * * \note If an IRQ is enabled and fires with no handler installed, a breakpoint will be hit and the IRQ number will - * be in r0. + * be in register r0. * * \section interrupt_nums Interrupt Numbers * @@ -94,8 +95,8 @@ #define PICO_DEFAULT_IRQ_PRIORITY 0x80 #endif -#define PICO_LOWEST_IRQ_PRIORITY 0x01 -#define PICO_HIGHEST_IRQ_PRIORITY 0xff +#define PICO_LOWEST_IRQ_PRIORITY 0xff +#define PICO_HIGHEST_IRQ_PRIORITY 0x00 // PICO_CONFIG: PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, Set default shared IRQ order priority, default=0x80, group=hardware_irq #ifndef PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY @@ -116,19 +117,41 @@ extern "C" { * * All interrupts handlers should be of this type, and follow normal ARM EABI register saving conventions */ -typedef void (*irq_handler_t)(); +typedef void (*irq_handler_t)(void); -/*! \brief Set specified interrupts priority +static inline void check_irq_param(__unused uint num) { + invalid_params_if(IRQ, num >= NUM_IRQS); +} + +/*! \brief Set specified interrupt's priority * \ingroup hardware_irq * * \param num Interrupt number - * \param hardware_priority Priority to set. Hardware priorities range from 0 (lowest) to 255 (highest) though only - * the top 2 bits are significant on ARM Cortex M0+. To make it easier to specify higher or lower priorities - * than the default, all IRQ priorities are initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup. + * \param hardware_priority Priority to set. + * Numerically-lower values indicate a higher priority. Hardware priorities + * range from 0 (highest priority) to 255 (lowest priority) though only the + * top 2 bits are significant on ARM Cortex-M0+. To make it easier to specify + * higher or lower priorities than the default, all IRQ priorities are + * initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup. * PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80 */ void irq_set_priority(uint num, uint8_t hardware_priority); +/*! \brief Get specified interrupt's priority + * \ingroup hardware_irq + * + * Numerically-lower values indicate a higher priority. Hardware priorities + * range from 0 (highest priority) to 255 (lowest priority) though only the + * top 2 bits are significant on ARM Cortex-M0+. To make it easier to specify + * higher or lower priorities than the default, all IRQ priorities are + * initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup. + * PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80 + * + * \param num Interrupt number + * \return the IRQ priority + */ +uint irq_get_priority(uint num); + /*! \brief Enable or disable a specific interrupt on the executing core * \ingroup hardware_irq * @@ -165,7 +188,7 @@ void irq_set_mask_enabled(uint32_t mask, bool enabled); * * \param num Interrupt number \ref interrupt_nums * \param handler The handler to set. See \ref irq_handler_t - * \see irq_add_shared_handler + * \see irq_add_shared_handler() */ void irq_set_exclusive_handler(uint num, irq_handler_t handler); @@ -176,7 +199,7 @@ void irq_set_exclusive_handler(uint num, irq_handler_t handler); * by irq_set_exclusive_handler if there is one. * * \param num Interrupt number \ref interrupt_nums - * \see irq_set_exclusive_handler + * \see irq_set_exclusive_handler() * \return handler The handler if an exclusive handler is set for the IRQ, * NULL if no handler is set or shared/shareable handlers are installed */ @@ -201,7 +224,7 @@ irq_handler_t irq_get_exclusive_handler(uint num); * rule of thumb is to use PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY if you don't much care, as it is in the middle of * the priority range by default. * - * \see irq_set_exclusive_handler + * \see irq_set_exclusive_handler() */ void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority); @@ -218,8 +241,8 @@ void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_prior * * \param num Interrupt number \ref interrupt_nums * \param handler The handler to removed. - * \see irq_set_exclusive_handler - * \see irq_add_shared_handler + * \see irq_set_exclusive_handler() + * \see irq_add_shared_handler() */ void irq_remove_handler(uint num, irq_handler_t handler); @@ -241,7 +264,7 @@ static inline void irq_clear(uint int_num) { *((volatile uint32_t *) (PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = (1u << ((uint32_t) (int_num & 0x1F))); } -/*! \brief Force an interrupt to pending on the executing core +/*! \brief Force an interrupt to be pending on the executing core * \ingroup hardware_irq * * This should generally not be used for IRQs connected to hardware. @@ -251,11 +274,11 @@ static inline void irq_clear(uint int_num) { void irq_set_pending(uint num); -/*! \brief Perform IRQ priority intiialization for the current core +/*! \brief Perform IRQ priority initialization for the current core * * \note This is an internal method and user should generally not call it. */ -void irq_init_priorities(); +void irq_init_priorities(void); #ifdef __cplusplus } #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio.h index 68975a977..d2377ac84 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio.h @@ -25,7 +25,7 @@ * Programmable I/O (PIO) API * * A programmable input/output block (PIO) is a versatile hardware interface which - * can support a number of different IO standards. There are two PIO blocks in the RP2040 + * can support a number of different IO standards. There are two PIO blocks in the RP2040. * * Each PIO is programmable in the same sense as a processor: the four state machines independently * execute short, sequential programs, to manipulate GPIOs and transfer data. Unlike a general @@ -58,6 +58,9 @@ enum pio_fifo_join { PIO_FIFO_JOIN_RX = 2, }; +/** \brief MOV status types + * \ingroup hardware_pio + */ enum pio_mov_status_type { STATUS_TX_LESSTHAN = 0, STATUS_RX_LESSTHAN = 1 @@ -104,10 +107,19 @@ typedef struct { uint32_t pinctrl; } pio_sm_config; -static inline void check_sm_param(uint sm) { +static inline void check_sm_param(__unused uint sm) { valid_params_if(PIO, sm < NUM_PIO_STATE_MACHINES); } +static inline void check_sm_mask(__unused uint mask) { + valid_params_if(PIO, mask < (1u << NUM_PIO_STATE_MACHINES)); +} + + +static inline void check_pio_param(__unused PIO pio) { + valid_params_if(PIO, pio == pio0 || pio == pio1); +} + /*! \brief Set the 'out' pins in a state machine configuration * \ingroup sm_config * @@ -118,8 +130,8 @@ static inline void check_sm_param(uint sm) { * \param out_count 0-32 Number of pins to set. */ static inline void sm_config_set_out_pins(pio_sm_config *c, uint out_base, uint out_count) { - assert(out_base < 32); - assert(out_count <= 32); + valid_params_if(PIO, out_base < 32); + valid_params_if(PIO, out_count <= 32); c->pinctrl = (c->pinctrl & ~(PIO_SM0_PINCTRL_OUT_BASE_BITS | PIO_SM0_PINCTRL_OUT_COUNT_BITS)) | (out_base << PIO_SM0_PINCTRL_OUT_BASE_LSB) | (out_count << PIO_SM0_PINCTRL_OUT_COUNT_LSB); @@ -135,8 +147,8 @@ static inline void sm_config_set_out_pins(pio_sm_config *c, uint out_base, uint * \param set_count 0-5 Number of pins to set. */ static inline void sm_config_set_set_pins(pio_sm_config *c, uint set_base, uint set_count) { - assert(set_base < 32); - assert(set_count <= 5); + valid_params_if(PIO, set_base < 32); + valid_params_if(PIO, set_count <= 5); c->pinctrl = (c->pinctrl & ~(PIO_SM0_PINCTRL_SET_BASE_BITS | PIO_SM0_PINCTRL_SET_COUNT_BITS)) | (set_base << PIO_SM0_PINCTRL_SET_BASE_LSB) | (set_count << PIO_SM0_PINCTRL_SET_COUNT_LSB); @@ -148,10 +160,10 @@ static inline void sm_config_set_set_pins(pio_sm_config *c, uint set_base, uint * Can overlap with the 'out', ''set' and 'sideset' pins * * \param c Pointer to the configuration structure to modify - * \param in_base 0-31 First pin to set as input + * \param in_base 0-31 First pin to use as input */ static inline void sm_config_set_in_pins(pio_sm_config *c, uint in_base) { - assert(in_base < 32); + valid_params_if(PIO, in_base < 32); c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_IN_BASE_BITS) | (in_base << PIO_SM0_PINCTRL_IN_BASE_LSB); } @@ -162,10 +174,10 @@ static inline void sm_config_set_in_pins(pio_sm_config *c, uint in_base) { * Can overlap with the 'in', 'out' and 'set' pins * * \param c Pointer to the configuration structure to modify - * \param sideset_base base pin for 'side set' + * \param sideset_base 0-31 base pin for 'side set' */ static inline void sm_config_set_sideset_pins(pio_sm_config *c, uint sideset_base) { - assert(sideset_base < 32); + valid_params_if(PIO, sideset_base < 32); c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SIDESET_BASE_BITS) | (sideset_base << PIO_SM0_PINCTRL_SIDESET_BASE_LSB); } @@ -174,55 +186,70 @@ static inline void sm_config_set_sideset_pins(pio_sm_config *c, uint sideset_bas * \ingroup sm_config * * \param c Pointer to the configuration structure to modify - * \param bit_count Number of bits to steal from delay field in the instruction for use of side set + * \param bit_count Number of bits to steal from delay field in the instruction for use of side set (max 5) * \param optional True if the topmost side set bit is used as a flag for whether to apply side set on that instruction * \param pindirs True if the side set affects pin directions rather than values */ static inline void sm_config_set_sideset(pio_sm_config *c, uint bit_count, bool optional, bool pindirs) { - assert(bit_count <= 32); + valid_params_if(PIO, bit_count <= 5); + valid_params_if(PIO, !optional || bit_count >= 1); c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SIDESET_COUNT_BITS) | (bit_count << PIO_SM0_PINCTRL_SIDESET_COUNT_LSB); c->execctrl = (c->execctrl & ~(PIO_SM0_EXECCTRL_SIDE_EN_BITS | PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS)) | - (!!optional << PIO_SM0_EXECCTRL_SIDE_EN_LSB) | - (!!pindirs << PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB); + (bool_to_bit(optional) << PIO_SM0_EXECCTRL_SIDE_EN_LSB) | + (bool_to_bit(pindirs) << PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB); } -/*! \brief Set the state machine clock divider (from a floating point value) in a state machine configuration +/*! \brief Set the state machine clock divider (from integer and fractional parts - 16:8) in a state machine configuration * \ingroup sm_config * - * The clock divider acts on the system clock to provide a clock for the state machine. - * See the datasheet for more details. + * The clock divider can slow the state machine's execution to some rate below + * the system clock frequency, by enabling the state machine on some cycles + * but not on others, in a regular pattern. This can be used to generate e.g. + * a given UART baud rate. See the datasheet for further detail. * * \param c Pointer to the configuration structure to modify - * \param div The fractional divisor to be set. 1 for full speed. An integer clock divisor of n - * will cause the state machine to run 1 cycle in every n. - * Note that for small n, the jitter introduced by a fractional divider (e.g. 2.5) may be unacceptable - * although it will depend on the use case. + * \param div_int Integer part of the divisor + * \param div_frac Fractional part in 1/256ths + * \sa sm_config_set_clkdiv() */ -static inline void sm_config_set_clkdiv(pio_sm_config *c, float div) { - uint16_t div_int = (uint16_t) div; - uint8_t div_frac = (uint8_t) ((div - div_int) * (1u << 8u)); +static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_int, uint8_t div_frac) { c->clkdiv = - (div_frac << PIO_SM0_CLKDIV_FRAC_LSB) | - (div_int << PIO_SM0_CLKDIV_INT_LSB); + (((uint)div_frac) << PIO_SM0_CLKDIV_FRAC_LSB) | + (((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB); } -/*! \brief Set the state machine clock divider (from integer and fractional parts - 16:8) in a state machine configuration +static inline void pio_calculate_clkdiv_from_float(float div, uint16_t *div_int, uint8_t *div_frac) { + valid_params_if(PIO, div >= 1 && div <= 65536); + *div_int = (uint16_t)div; + if (*div_int == 0) { + *div_frac = 0; + } else { + *div_frac = (uint8_t)((div - (float)*div_int) * (1u << 8u)); + } +} + +/*! \brief Set the state machine clock divider (from a floating point value) in a state machine configuration * \ingroup sm_config * - * The clock divider acts on the system clock to provide a clock for the state machine. - * See the datasheet for more details. + * The clock divider slows the state machine's execution by masking the + * system clock on some cycles, in a repeating pattern, so that the state + * machine does not advance. Effectively this produces a slower clock for the + * state machine to run from, which can be used to generate e.g. a particular + * UART baud rate. See the datasheet for further detail. * * \param c Pointer to the configuration structure to modify - * \param div_int Integer part of the divisor - * \param div_frac Fractional part in 1/256ths - * \sa sm_config_set_clkdiv + * \param div The fractional divisor to be set. 1 for full speed. An integer clock divisor of n + * will cause the state machine to run 1 cycle in every n. + * Note that for small n, the jitter introduced by a fractional divider (e.g. 2.5) may be unacceptable + * although it will depend on the use case. */ -static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_int, uint8_t div_frac) { - c->clkdiv = - (div_frac << PIO_SM0_CLKDIV_FRAC_LSB) | - (div_int << PIO_SM0_CLKDIV_INT_LSB); +static inline void sm_config_set_clkdiv(pio_sm_config *c, float div) { + uint16_t div_int; + uint8_t div_frac; + pio_calculate_clkdiv_from_float(div, &div_int, &div_frac); + sm_config_set_clkdiv_int_frac(c, div_int, div_frac); } /*! \brief Set the wrap addresses in a state machine configuration @@ -234,8 +261,8 @@ static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_ * if the instruction does not itself update the program_counter */ static inline void sm_config_set_wrap(pio_sm_config *c, uint wrap_target, uint wrap) { - assert(wrap < PIO_INSTRUCTION_COUNT); - assert(wrap_target < PIO_INSTRUCTION_COUNT); + valid_params_if(PIO, wrap < PIO_INSTRUCTION_COUNT); + valid_params_if(PIO, wrap_target < PIO_INSTRUCTION_COUNT); c->execctrl = (c->execctrl & ~(PIO_SM0_EXECCTRL_WRAP_TOP_BITS | PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) | (wrap_target << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB) | (wrap << PIO_SM0_EXECCTRL_WRAP_TOP_LSB); @@ -245,10 +272,10 @@ static inline void sm_config_set_wrap(pio_sm_config *c, uint wrap_target, uint w * \ingroup sm_config * * \param c Pointer to the configuration structure to modify - * \param pin The raw GPIO pin number to use as the source for a `jmp pin` instruction + * \param pin The raw GPIO pin number to use as the source for a `jmp pin` instruction */ static inline void sm_config_set_jmp_pin(pio_sm_config *c, uint pin) { - assert(pin < 32); + valid_params_if(PIO, pin < 32); c->execctrl = (c->execctrl & ~PIO_SM0_EXECCTRL_JMP_PIN_BITS) | (pin << PIO_SM0_EXECCTRL_JMP_PIN_LSB); } @@ -259,7 +286,7 @@ static inline void sm_config_set_jmp_pin(pio_sm_config *c, uint pin) { * \param c Pointer to the configuration structure to modify * \param shift_right true to shift ISR to right, false to shift ISR to left * \param autopush whether autopush is enabled - * \param push_threshold threshold in bits to shift in before auto/conditional re-pushing of the ISR + * \param push_threshold threshold in bits to shift in before auto/conditional re-pushing of the ISR */ static inline void sm_config_set_in_shift(pio_sm_config *c, bool shift_right, bool autopush, uint push_threshold) { valid_params_if(PIO, push_threshold <= 32); @@ -267,8 +294,8 @@ static inline void sm_config_set_in_shift(pio_sm_config *c, bool shift_right, bo ~(PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS | PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS | PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS)) | - (!!shift_right << PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB) | - (!!autopush << PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB) | + (bool_to_bit(shift_right) << PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB) | + (bool_to_bit(autopush) << PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB) | ((push_threshold & 0x1fu) << PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB); } @@ -278,7 +305,7 @@ static inline void sm_config_set_in_shift(pio_sm_config *c, bool shift_right, bo * \param c Pointer to the configuration structure to modify * \param shift_right true to shift OSR to right, false to shift OSR to left * \param autopull whether autopull is enabled - * \param pull_threshold threshold in bits to shift out before auto/conditional re-pulling of the OSR + * \param pull_threshold threshold in bits to shift out before auto/conditional re-pulling of the OSR */ static inline void sm_config_set_out_shift(pio_sm_config *c, bool shift_right, bool autopull, uint pull_threshold) { valid_params_if(PIO, pull_threshold <= 32); @@ -286,8 +313,8 @@ static inline void sm_config_set_out_shift(pio_sm_config *c, bool shift_right, b ~(PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS | PIO_SM0_SHIFTCTRL_AUTOPULL_BITS | PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS)) | - (!!shift_right << PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB) | - (!!autopull << PIO_SM0_SHIFTCTRL_AUTOPULL_LSB) | + (bool_to_bit(shift_right) << PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB) | + (bool_to_bit(autopull) << PIO_SM0_SHIFTCTRL_AUTOPULL_LSB) | ((pull_threshold & 0x1fu) << PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB); } @@ -298,9 +325,9 @@ static inline void sm_config_set_out_shift(pio_sm_config *c, bool shift_right, b * \param join Specifies the join type. \see enum pio_fifo_join */ static inline void sm_config_set_fifo_join(pio_sm_config *c, enum pio_fifo_join join) { - assert(join >= 0 && join <= 2); - c->shiftctrl = (c->shiftctrl & ~(PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS)) | - (join << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB); + valid_params_if(PIO, join == PIO_FIFO_JOIN_NONE || join == PIO_FIFO_JOIN_TX || join == PIO_FIFO_JOIN_RX); + c->shiftctrl = (c->shiftctrl & (uint)~(PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS)) | + (((uint)join) << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB); } /*! \brief Set special 'out' operations in a state machine configuration @@ -308,15 +335,15 @@ static inline void sm_config_set_fifo_join(pio_sm_config *c, enum pio_fifo_join * * \param c Pointer to the configuration structure to modify * \param sticky to enable 'sticky' output (i.e. re-asserting most recent OUT/SET pin values on subsequent cycles) - * \param has_enable_pin true to enable auxiliary OUT enable pin + * \param has_enable_pin true to enable auxiliary OUT enable pin * \param enable_pin_index pin index for auxiliary OUT enable */ -static inline void sm_config_set_out_special(pio_sm_config *c, bool sticky, bool has_enable_pin, int enable_pin_index) { +static inline void sm_config_set_out_special(pio_sm_config *c, bool sticky, bool has_enable_pin, uint enable_pin_index) { c->execctrl = (c->execctrl & - ~(PIO_SM0_EXECCTRL_OUT_STICKY_BITS | PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS | + (uint)~(PIO_SM0_EXECCTRL_OUT_STICKY_BITS | PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS | PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS)) | - (!!sticky << PIO_SM0_EXECCTRL_OUT_STICKY_LSB) | - (!!has_enable_pin << PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB) | + (bool_to_bit(sticky) << PIO_SM0_EXECCTRL_OUT_STICKY_LSB) | + (bool_to_bit(has_enable_pin) << PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB) | ((enable_pin_index << PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB) & PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS); } @@ -324,13 +351,14 @@ static inline void sm_config_set_out_special(pio_sm_config *c, bool sticky, bool * \ingroup sm_config * * \param c Pointer to the configuration structure to modify - * \param status_sel the status operation selector + * \param status_sel the status operation selector. \see enum pio_mov_status_type * \param status_n parameter for the mov status operation (currently a bit count) */ static inline void sm_config_set_mov_status(pio_sm_config *c, enum pio_mov_status_type status_sel, uint status_n) { + valid_params_if(PIO, status_sel == STATUS_TX_LESSTHAN || status_sel == STATUS_RX_LESSTHAN); c->execctrl = (c->execctrl - & ~(PIO_SM0_EXECCTRL_STATUS_SEL_BITS | PIO_SM0_EXECCTRL_STATUS_N_BITS)) - | ((status_sel << PIO_SM0_EXECCTRL_STATUS_SEL_LSB) & PIO_SM0_EXECCTRL_STATUS_SEL_BITS) + & ~(PIO_SM0_EXECCTRL_STATUS_SEL_BITS | PIO_SM0_EXECCTRL_STATUS_N_BITS)) + | ((((uint)status_sel) << PIO_SM0_EXECCTRL_STATUS_SEL_LSB) & PIO_SM0_EXECCTRL_STATUS_SEL_BITS) | ((status_n << PIO_SM0_EXECCTRL_STATUS_N_LSB) & PIO_SM0_EXECCTRL_STATUS_N_BITS); } @@ -349,13 +377,13 @@ static inline void sm_config_set_mov_status(pio_sm_config *c, enum pio_mov_statu * In Shift | shift_direction=right, autopush=false, push_thrshold=32 * Out Shift | shift_direction=right, autopull=false, pull_thrshold=32 * Jmp Pin | 0 - * Out Special | sticky=false, has_enable_pin=false, enable_pin_index=0 + * Out Special | sticky=false, has_enable_pin=false, enable_pin_index=0 * Mov Status | status_sel=STATUS_TX_LESSTHAN, n=0 * * \return the default state machine configuration which can then be modified. */ -static inline pio_sm_config pio_get_default_sm_config() { - pio_sm_config c = {0, 0, 0}; +static inline pio_sm_config pio_get_default_sm_config(void) { + pio_sm_config c = {0, 0, 0, 0}; sm_config_set_clkdiv_int_frac(&c, 1, 0); sm_config_set_wrap(&c, 0, 31); sm_config_set_in_shift(&c, true, false, 32); @@ -371,6 +399,7 @@ static inline pio_sm_config pio_get_default_sm_config() { * \param config the configuration to apply */ static inline void pio_sm_set_config(PIO pio, uint sm, const pio_sm_config *config) { + check_pio_param(pio); check_sm_param(sm); pio->sm[sm].clkdiv = config->clkdiv; pio->sm[sm].execctrl = config->execctrl; @@ -385,30 +414,42 @@ static inline void pio_sm_set_config(PIO pio, uint sm, const pio_sm_config *conf * \return the PIO instance number (either 0 or 1) */ static inline uint pio_get_index(PIO pio) { - assert(pio == pio0 || pio == pio1); + check_pio_param(pio); return pio == pio1 ? 1 : 0; } -/*! \brief Setup the function select for a GPIO to use output from the given PIO instance +/*! \brief Setup the function select for a GPIO to use output from the given PIO instance * \ingroup hardware_pio * + * PIO appears as an alternate function in the GPIO muxing, just like an SPI + * or UART. This function configures that multiplexing to connect a given PIO + * instance to a GPIO. Note that this is not necessary for a state machine to + * be able to read the *input* value from a GPIO, but only for it to set the + * output value or output enable. + * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param pin the GPIO pin whose function select to set */ static inline void pio_gpio_init(PIO pio, uint pin) { - assert(pio == pio0 || pio == pio1); + check_pio_param(pio); + valid_params_if(PIO, pin < 32); gpio_set_function(pin, pio == pio0 ? GPIO_FUNC_PIO0 : GPIO_FUNC_PIO1); } -/*! \brief Return the DREQ to use for pacing transfers to a particular state machine +/*! \brief Return the DREQ to use for pacing transfers to/from a particular state machine FIFO * \ingroup hardware_pio * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param sm State machine index (0..3) - * \param is_tx true for sending data to the state machine, false for received data from the state machine + * \param is_tx true for sending data to the state machine, false for receiving data from the state machine */ static inline uint pio_get_dreq(PIO pio, uint sm, bool is_tx) { - assert(pio == pio0 || pio == pio1); + static_assert(DREQ_PIO0_TX1 == DREQ_PIO0_TX0 + 1, ""); + static_assert(DREQ_PIO0_TX2 == DREQ_PIO0_TX0 + 2, ""); + static_assert(DREQ_PIO0_TX3 == DREQ_PIO0_TX0 + 3, ""); + static_assert(DREQ_PIO0_RX0 == DREQ_PIO0_TX0 + NUM_PIO_STATE_MACHINES, ""); + static_assert(DREQ_PIO1_RX0 == DREQ_PIO1_TX0 + NUM_PIO_STATE_MACHINES, ""); + check_pio_param(pio); check_sm_param(sm); return sm + (is_tx ? 0 : NUM_PIO_STATE_MACHINES) + (pio == pio0 ? DREQ_PIO0_TX0 : DREQ_PIO1_TX0); } @@ -441,7 +482,7 @@ bool pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint o /*! \brief Attempt to load the program, panicking if not possible * \ingroup hardware_pio * - * \see pico_can_add_program if you need to check whether the program can be loaded + * \see pio_can_add_program() if you need to check whether the program can be loaded * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param program the program definition @@ -452,7 +493,7 @@ uint pio_add_program(PIO pio, const pio_program_t *program); /*! \brief Attempt to load the program at the specified instruction memory offset, panicking if not possible * \ingroup hardware_pio * - * \see pico_can_add_program_at_offset if you need to check whether the program can be loaded + * \see pio_can_add_program_at_offset() if you need to check whether the program can be loaded * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param program the program definition @@ -480,13 +521,13 @@ void pio_clear_instruction_memory(PIO pio); * \ingroup hardware_pio * * This method: - * - disables the state machine (if running) - * - clears the FIFOs - * - applies the configuration - * - resets any internal state - * - jumps to the initial program location + * - Disables the state machine (if running) + * - Clears the FIFOs + * - Applies the configuration specified by 'config' + * - Resets any internal state e.g. shift counters + * - Jumps to the initial program location given by 'initial_pc' * - * The state machine is disabled on return from this call + * The state machine is left disabled on return from this call. * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param sm State machine index (0..3) @@ -503,7 +544,9 @@ void pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config) * \param enabled true to enable the state machine; false to disable */ static inline void pio_sm_set_enabled(PIO pio, uint sm, bool enabled) { - pio->ctrl = (pio->ctrl & ~(1u << sm)) | (!!enabled << sm); + check_pio_param(pio); + check_sm_param(sm); + pio->ctrl = (pio->ctrl & ~(1u << sm)) | (bool_to_bit(enabled) << sm); } /*! \brief Enable or disable multiple PIO state machines @@ -512,7 +555,7 @@ static inline void pio_sm_set_enabled(PIO pio, uint sm, bool enabled) { * Note that this method just sets the enabled state of the state machine; * if now enabled they continue exactly from where they left off. * - * \see pio_enable_sm_mask_in_sync if you wish to enable multiple state machines + * \see pio_enable_sm_mask_in_sync() if you wish to enable multiple state machines * and ensure their clock dividers are in sync. * * \param pio The PIO instance; either \ref pio0 or \ref pio1 @@ -520,6 +563,8 @@ static inline void pio_sm_set_enabled(PIO pio, uint sm, bool enabled) { * \param enabled true to enable the state machines; false to disable */ static inline void pio_set_sm_mask_enabled(PIO pio, uint32_t mask, bool enabled) { + check_pio_param(pio); + check_sm_mask(mask); pio->ctrl = (pio->ctrl & ~mask) | (enabled ? mask : 0u); } @@ -533,6 +578,8 @@ static inline void pio_set_sm_mask_enabled(PIO pio, uint32_t mask, bool enabled) * \param sm State machine index (0..3) */ static inline void pio_sm_restart(PIO pio, uint sm) { + check_pio_param(pio); + check_sm_param(sm); pio->ctrl |= 1u << (PIO_CTRL_SM_RESTART_LSB + sm); } @@ -546,43 +593,234 @@ static inline void pio_sm_restart(PIO pio, uint sm) { * \param mask bit mask of state machine indexes to modify the enabled state of */ static inline void pio_restart_sm_mask(PIO pio, uint32_t mask) { + check_pio_param(pio); + check_sm_mask(mask); pio->ctrl |= (mask << PIO_CTRL_SM_RESTART_LSB) & PIO_CTRL_SM_RESTART_BITS; } -/*! \brief Restart a state machine's clock divider (resetting the fractional count) +/*! \brief Restart a state machine's clock divider from a phase of 0 * \ingroup hardware_pio * + * Each state machine's clock divider is a free-running piece of hardware, + * that generates a pattern of clock enable pulses for the state machine, + * based *only* on the configured integer/fractional divisor. The pattern of + * running/halted cycles slows the state machine's execution to some + * controlled rate. + * + * This function clears the divider's integer and fractional phase + * accumulators so that it restarts this pattern from the beginning. It is + * called automatically by pio_sm_init() but can also be called at a later + * time, when you enable the state machine, to ensure precisely consistent + * timing each time you load and run a given PIO program. + * + * More commonly this hardware mechanism is used to synchronise the execution + * clocks of multiple state machines -- see pio_clkdiv_restart_sm_mask(). + * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param sm State machine index (0..3) */ static inline void pio_sm_clkdiv_restart(PIO pio, uint sm) { + check_pio_param(pio); + check_sm_param(sm); pio->ctrl |= 1u << (PIO_CTRL_CLKDIV_RESTART_LSB + sm); } -/*! \brief Restart multiple state machines' clock dividers (resetting the fractional count) +/*! \brief Restart multiple state machines' clock dividers from a phase of 0. * \ingroup hardware_pio * - * This method can be used to guarantee that multiple state machines with fractional clock dividers - * are exactly in sync + * Each state machine's clock divider is a free-running piece of hardware, + * that generates a pattern of clock enable pulses for the state machine, + * based *only* on the configured integer/fractional divisor. The pattern of + * running/halted cycles slows the state machine's execution to some + * controlled rate. + * + * This function simultaneously clears the integer and fractional phase + * accumulators of multiple state machines' clock dividers. If these state + * machines all have the same integer and fractional divisors configured, + * their clock dividers will run in precise deterministic lockstep from this + * point. + * + * With their execution clocks synchronised in this way, it is then safe to + * e.g. have multiple state machines performing a 'wait irq' on the same flag, + * and all clear it on the same cycle. + * + * Also note that this function can be called whilst state machines are + * running (e.g. if you have just changed the clock divisors of some state + * machines and wish to resynchronise them), and that disabling a state + * machine does not halt its clock divider: that is, if multiple state + * machines have their clocks synchronised, you can safely disable and + * reenable one of the state machines without losing synchronisation. * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param mask bit mask of state machine indexes to modify the enabled state of */ static inline void pio_clkdiv_restart_sm_mask(PIO pio, uint32_t mask) { + check_pio_param(pio); + check_sm_mask(mask); pio->ctrl |= (mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS; } /*! \brief Enable multiple PIO state machines synchronizing their clock dividers * \ingroup hardware_pio * + * This is equivalent to calling both pio_set_sm_mask_enabled() and + * pio_clkdiv_restart_sm_mask() on the *same* clock cycle. All state machines + * specified by 'mask' are started simultaneously and, assuming they have the + * same clock divisors, their divided clocks will stay precisely synchronised. + * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param mask bit mask of state machine indexes to modify the enabled state of */ static inline void pio_enable_sm_mask_in_sync(PIO pio, uint32_t mask) { + check_pio_param(pio); + check_sm_mask(mask); pio->ctrl |= ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) | ((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS); } +/*! \brief PIO interrupt source numbers for pio related IRQs + * \ingroup hardware_pio + */ +enum pio_interrupt_source { + pis_interrupt0 = PIO_INTR_SM0_LSB, + pis_interrupt1 = PIO_INTR_SM1_LSB, + pis_interrupt2 = PIO_INTR_SM2_LSB, + pis_interrupt3 = PIO_INTR_SM3_LSB, + pis_sm0_tx_fifo_not_full = PIO_INTR_SM0_TXNFULL_LSB, + pis_sm1_tx_fifo_not_full = PIO_INTR_SM1_TXNFULL_LSB, + pis_sm2_tx_fifo_not_full = PIO_INTR_SM2_TXNFULL_LSB, + pis_sm3_tx_fifo_not_full = PIO_INTR_SM3_TXNFULL_LSB, + pis_sm0_rx_fifo_not_empty = PIO_INTR_SM0_RXNEMPTY_LSB, + pis_sm1_rx_fifo_not_empty = PIO_INTR_SM1_RXNEMPTY_LSB, + pis_sm2_rx_fifo_not_empty = PIO_INTR_SM2_RXNEMPTY_LSB, + pis_sm3_rx_fifo_not_empty = PIO_INTR_SM3_RXNEMPTY_LSB, +}; + +/*! \brief Enable/Disable a single source on a PIO's IRQ 0 + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param source the source number (see \ref pio_interrupt_source) + * \param enabled true to enable IRQ 0 for the source, false to disable. + */ +static inline void pio_set_irq0_source_enabled(PIO pio, enum pio_interrupt_source source, bool enabled) { + check_pio_param(pio); + invalid_params_if(PIO, source >= 12); + if (enabled) + hw_set_bits(&pio->inte0, 1u << source); + else + hw_clear_bits(&pio->inte0, 1u << source); +} + +/*! \brief Enable/Disable a single source on a PIO's IRQ 1 + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param source the source number (see \ref pio_interrupt_source) + * \param enabled true to enable IRQ 0 for the source, false to disable. + */ +static inline void pio_set_irq1_source_enabled(PIO pio, enum pio_interrupt_source source, bool enabled) { + check_pio_param(pio); + invalid_params_if(PIO, source >= 12); + if (enabled) + hw_set_bits(&pio->inte1, 1u << source); + else + hw_clear_bits(&pio->inte1, 1u << source); +} + +/*! \brief Enable/Disable multiple sources on a PIO's IRQ 0 + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param source_mask Mask of bits, one for each source number (see \ref pio_interrupt_source) to affect + * \param enabled true to enable all the sources specified in the mask on IRQ 0, false to disable all the sources specified in the mask on IRQ 0 + */ +static inline void pio_set_irq0_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled) { + check_pio_param(pio); + invalid_params_if(PIO, source_mask > PIO_INTR_BITS); + if (enabled) { + hw_set_bits(&pio->inte0, source_mask); + } else { + hw_clear_bits(&pio->inte0, source_mask); + } +} + +/*! \brief Enable/Disable multiple sources on a PIO's IRQ 1 + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param source_mask Mask of bits, one for each source number (see \ref pio_interrupt_source) to affect + * \param enabled true to enable all the sources specified in the mask on IRQ 1, false to disable all the source specified in the mask on IRQ 1 + */ +static inline void pio_set_irq1_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled) { + check_pio_param(pio); + invalid_params_if(PIO, source_mask > PIO_INTR_BITS); + if (enabled) { + hw_set_bits(&pio->inte1, source_mask); + } else { + hw_clear_bits(&pio->inte1, source_mask); + } +} + +/*! \brief Enable/Disable a single source on a PIO's specified (0/1) IRQ index + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param irq_index the IRQ index; either 0 or 1 + * \param source the source number (see \ref pio_interrupt_source) + * \param enabled true to enable the source on the specified IRQ, false to disable. + */ +static inline void pio_set_irqn_source_enabled(PIO pio, uint irq_index, enum pio_interrupt_source source, bool enabled) { + invalid_params_if(PIO, irq_index > 1); + if (irq_index) { + pio_set_irq1_source_enabled(pio, source, enabled); + } else { + pio_set_irq0_source_enabled(pio, source, enabled); + } +} + +/*! \brief Enable/Disable multiple sources on a PIO's specified (0/1) IRQ index + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param irq_index the IRQ index; either 0 or 1 + * \param source_mask Mask of bits, one for each source number (see \ref pio_interrupt_source) to affect + * \param enabled true to enable all the sources specified in the mask on the specified IRQ, false to disable all the sources specified in the mask on the specified IRQ + */ +static inline void pio_set_irqn_source_mask_enabled(PIO pio, uint irq_index, uint32_t source_mask, bool enabled) { + invalid_params_if(PIO, irq_index > 1); + if (irq_index) { + pio_set_irq0_source_mask_enabled(pio, source_mask, enabled); + } else { + pio_set_irq1_source_mask_enabled(pio, source_mask, enabled); + } +} + +/*! \brief Determine if a particular PIO interrupt is set + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio_interrupt_num the PIO interrupt number 0-7 + * \return true if corresponding PIO interrupt is currently set + */ +static inline bool pio_interrupt_get(PIO pio, uint pio_interrupt_num) { + check_pio_param(pio); + invalid_params_if(PIO, pio_interrupt_num >= 8); + return pio->irq & (1u << pio_interrupt_num); +} + +/*! \brief Clear a particular PIO interrupt + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio_interrupt_num the PIO interrupt number 0-7 + */ +static inline void pio_interrupt_clear(PIO pio, uint pio_interrupt_num) { + check_pio_param(pio); + invalid_params_if(PIO, pio_interrupt_num >= 8); + hw_set_bits(&pio->irq, (1u << pio_interrupt_num)); +} + /*! \brief Return the current program counter for a state machine * \ingroup hardware_pio * @@ -591,6 +829,7 @@ static inline void pio_enable_sm_mask_in_sync(PIO pio, uint32_t mask) { * \return the program counter */ static inline uint8_t pio_sm_get_pc(PIO pio, uint sm) { + check_pio_param(pio); check_sm_param(sm); return (uint8_t) pio->sm[sm].addr; } @@ -600,7 +839,7 @@ static inline uint8_t pio_sm_get_pc(PIO pio, uint sm) { * * This instruction is executed instead of the next instruction in the normal control flow on the state machine. * Subsequent calls to this method replace the previous executed - * instruction if it is still running. \see pio_sm_is_exec_stalled to see if an executed instruction + * instruction if it is still running. \see pio_sm_is_exec_stalled() to see if an executed instruction * is still running (i.e. it is stalled on some condition) * * \param pio The PIO instance; either \ref pio0 or \ref pio1 @@ -608,6 +847,7 @@ static inline uint8_t pio_sm_get_pc(PIO pio, uint sm) { * \param instr the encoded PIO instruction */ inline static void pio_sm_exec(PIO pio, uint sm, uint instr) { + check_pio_param(pio); check_sm_param(sm); pio->sm[sm].instr = instr; } @@ -620,6 +860,7 @@ inline static void pio_sm_exec(PIO pio, uint sm, uint instr) { * \return true if the executed instruction is still running (stalled) */ static inline bool pio_sm_is_exec_stalled(PIO pio, uint sm) { + check_pio_param(pio); check_sm_param(sm); return !!(pio->sm[sm].execctrl & PIO_SM0_EXECCTRL_EXEC_STALLED_BITS); } @@ -629,7 +870,7 @@ static inline bool pio_sm_is_exec_stalled(PIO pio, uint sm) { * * This instruction is executed instead of the next instruction in the normal control flow on the state machine. * Subsequent calls to this method replace the previous executed - * instruction if it is still running. \see pio_sm_is_exec_stalled to see if an executed instruction + * instruction if it is still running. \see pio_sm_is_exec_stalled() to see if an executed instruction * is still running (i.e. it is stalled on some condition) * * \param pio The PIO instance; either \ref pio0 or \ref pio1 @@ -637,6 +878,8 @@ static inline bool pio_sm_is_exec_stalled(PIO pio, uint sm) { * \param instr the encoded PIO instruction */ static inline void pio_sm_exec_wait_blocking(PIO pio, uint sm, uint instr) { + check_pio_param(pio); + check_sm_param(sm); pio_sm_exec(pio, sm, instr); while (pio_sm_is_exec_stalled(pio, sm)) tight_loop_contents(); } @@ -651,7 +894,10 @@ static inline void pio_sm_exec_wait_blocking(PIO pio, uint sm, uint instr) { * if the instruction does not itself update the program_counter */ static inline void pio_sm_set_wrap(PIO pio, uint sm, uint wrap_target, uint wrap) { + check_pio_param(pio); check_sm_param(sm); + valid_params_if(PIO, wrap < PIO_INSTRUCTION_COUNT); + valid_params_if(PIO, wrap_target < PIO_INSTRUCTION_COUNT); pio->sm[sm].execctrl = (pio->sm[sm].execctrl & ~(PIO_SM0_EXECCTRL_WRAP_TOP_BITS | PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) | (wrap_target << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB) | @@ -669,9 +915,10 @@ static inline void pio_sm_set_wrap(PIO pio, uint sm, uint wrap_target, uint wrap * \param out_count 0-32 Number of pins to set. */ static inline void pio_sm_set_out_pins(PIO pio, uint sm, uint out_base, uint out_count) { + check_pio_param(pio); check_sm_param(sm); - assert(out_base < 32); - assert(out_count <= 32); + valid_params_if(PIO, out_base < 32); + valid_params_if(PIO, out_count <= 32); pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~(PIO_SM0_PINCTRL_OUT_BASE_BITS | PIO_SM0_PINCTRL_OUT_COUNT_BITS)) | (out_base << PIO_SM0_PINCTRL_OUT_BASE_LSB) | (out_count << PIO_SM0_PINCTRL_OUT_COUNT_LSB); @@ -689,9 +936,10 @@ static inline void pio_sm_set_out_pins(PIO pio, uint sm, uint out_base, uint out * \param set_count 0-5 Number of pins to set. */ static inline void pio_sm_set_set_pins(PIO pio, uint sm, uint set_base, uint set_count) { + check_pio_param(pio); check_sm_param(sm); - assert(set_base < 32); - assert(set_count <= 5); + valid_params_if(PIO, set_base < 32); + valid_params_if(PIO, set_count <= 5); pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~(PIO_SM0_PINCTRL_SET_BASE_BITS | PIO_SM0_PINCTRL_SET_COUNT_BITS)) | (set_base << PIO_SM0_PINCTRL_SET_BASE_LSB) | (set_count << PIO_SM0_PINCTRL_SET_COUNT_LSB); @@ -704,11 +952,12 @@ static inline void pio_sm_set_set_pins(PIO pio, uint sm, uint set_base, uint set * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param sm State machine index (0..3) - * \param in_base 0-31 First pin to set as input + * \param in_base 0-31 First pin to use as input */ static inline void pio_sm_set_in_pins(PIO pio, uint sm, uint in_base) { + check_pio_param(pio); check_sm_param(sm); - assert(in_base < 32); + valid_params_if(PIO, in_base < 32); pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~PIO_SM0_PINCTRL_IN_BASE_BITS) | (in_base << PIO_SM0_PINCTRL_IN_BASE_LSB); } @@ -720,11 +969,12 @@ static inline void pio_sm_set_in_pins(PIO pio, uint sm, uint in_base) { * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param sm State machine index (0..3) - * \param sideset_base base pin for 'side set' + * \param sideset_base 0-31 base pin for 'side set' */ static inline void pio_sm_set_sideset_pins(PIO pio, uint sm, uint sideset_base) { + check_pio_param(pio); check_sm_param(sm); - assert(sideset_base < 32); + valid_params_if(PIO, sideset_base < 32); pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~PIO_SM0_PINCTRL_SIDESET_BASE_BITS) | (sideset_base << PIO_SM0_PINCTRL_SIDESET_BASE_LSB); } @@ -732,13 +982,19 @@ static inline void pio_sm_set_sideset_pins(PIO pio, uint sm, uint sideset_base) /*! \brief Write a word of data to a state machine's TX FIFO * \ingroup hardware_pio * - * If the FIFO is full, the most recent value will be overwritten + * This is a raw FIFO access that does not check for fullness. If the FIFO is + * full, the FIFO contents and state are not affected by the write attempt. + * Hardware sets the TXOVER sticky flag for this FIFO in FDEBUG, to indicate + * that the system attempted to write to a full FIFO. * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \param data the 32 bit data value + * + * \sa pio_sm_put_blocking() */ static inline void pio_sm_put(PIO pio, uint sm, uint32_t data) { + check_pio_param(pio); check_sm_param(sm); pio->txf[sm] = data; } @@ -746,12 +1002,20 @@ static inline void pio_sm_put(PIO pio, uint sm, uint32_t data) { /*! \brief Read a word of data from a state machine's RX FIFO * \ingroup hardware_pio * - * If the FIFO is empty, the return value is zero. + * This is a raw FIFO access that does not check for emptiness. If the FIFO is + * empty, the hardware ignores the attempt to read from the FIFO (the FIFO + * remains in an empty state following the read) and the sticky RXUNDER flag + * for this FIFO is set in FDEBUG to indicate that the system tried to read + * from this FIFO when empty. The data returned by this function is undefined + * when the FIFO is empty. * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param sm State machine index (0..3) + * + * \sa pio_sm_get_blocking() */ static inline uint32_t pio_sm_get(PIO pio, uint sm) { + check_pio_param(pio); check_sm_param(sm); return pio->rxf[sm]; } @@ -764,6 +1028,7 @@ static inline uint32_t pio_sm_get(PIO pio, uint sm) { * \return true if the RX FIFO is full */ static inline bool pio_sm_is_rx_fifo_full(PIO pio, uint sm) { + check_pio_param(pio); check_sm_param(sm); return (pio->fstat & (1u << (PIO_FSTAT_RXFULL_LSB + sm))) != 0; } @@ -776,6 +1041,7 @@ static inline bool pio_sm_is_rx_fifo_full(PIO pio, uint sm) { * \return true if the RX FIFO is empty */ static inline bool pio_sm_is_rx_fifo_empty(PIO pio, uint sm) { + check_pio_param(pio); check_sm_param(sm); return (pio->fstat & (1u << (PIO_FSTAT_RXEMPTY_LSB + sm))) != 0; } @@ -788,8 +1054,9 @@ static inline bool pio_sm_is_rx_fifo_empty(PIO pio, uint sm) { * \return the number of elements in the RX FIFO */ static inline uint pio_sm_get_rx_fifo_level(PIO pio, uint sm) { + check_pio_param(pio); check_sm_param(sm); - int bitoffs = PIO_FLEVEL_RX0_LSB + sm * (PIO_FLEVEL_RX1_LSB - PIO_FLEVEL_RX0_LSB); + uint bitoffs = PIO_FLEVEL_RX0_LSB + sm * (PIO_FLEVEL_RX1_LSB - PIO_FLEVEL_RX0_LSB); const uint32_t mask = PIO_FLEVEL_RX0_BITS >> PIO_FLEVEL_RX0_LSB; return (pio->flevel >> bitoffs) & mask; } @@ -802,6 +1069,7 @@ static inline uint pio_sm_get_rx_fifo_level(PIO pio, uint sm) { * \return true if the TX FIFO is full */ static inline bool pio_sm_is_tx_fifo_full(PIO pio, uint sm) { + check_pio_param(pio); check_sm_param(sm); return (pio->fstat & (1u << (PIO_FSTAT_TXFULL_LSB + sm))) != 0; } @@ -814,6 +1082,7 @@ static inline bool pio_sm_is_tx_fifo_full(PIO pio, uint sm) { * \return true if the TX FIFO is empty */ static inline bool pio_sm_is_tx_fifo_empty(PIO pio, uint sm) { + check_pio_param(pio); check_sm_param(sm); return (pio->fstat & (1u << (PIO_FSTAT_TXEMPTY_LSB + sm))) != 0; } @@ -826,6 +1095,7 @@ static inline bool pio_sm_is_tx_fifo_empty(PIO pio, uint sm) { * \return the number of elements in the TX FIFO */ static inline uint pio_sm_get_tx_fifo_level(PIO pio, uint sm) { + check_pio_param(pio); check_sm_param(sm); unsigned int bitoffs = PIO_FLEVEL_TX0_LSB + sm * (PIO_FLEVEL_TX1_LSB - PIO_FLEVEL_TX0_LSB); const uint32_t mask = PIO_FLEVEL_TX0_BITS >> PIO_FLEVEL_TX0_LSB; @@ -840,6 +1110,7 @@ static inline uint pio_sm_get_tx_fifo_level(PIO pio, uint sm) { * \param data the 32 bit data value */ static inline void pio_sm_put_blocking(PIO pio, uint sm, uint32_t data) { + check_pio_param(pio); check_sm_param(sm); while (pio_sm_is_tx_fifo_full(pio, sm)) tight_loop_contents(); pio_sm_put(pio, sm, data); @@ -852,6 +1123,7 @@ static inline void pio_sm_put_blocking(PIO pio, uint sm, uint32_t data) { * \param sm State machine index (0..3) */ static inline uint32_t pio_sm_get_blocking(PIO pio, uint sm) { + check_pio_param(pio); check_sm_param(sm); while (pio_sm_is_rx_fifo_empty(pio, sm)) tight_loop_contents(); return pio_sm_get(pio, sm); @@ -860,45 +1132,51 @@ static inline uint32_t pio_sm_get_blocking(PIO pio, uint sm) { /*! \brief Empty out a state machine's TX FIFO * \ingroup hardware_pio * - * This method executes `pull` instructions on the state machine until the TX FIFO is empty + * This method executes `pull` instructions on the state machine until the TX + * FIFO is empty. This disturbs the contents of the OSR, so see also + * pio_sm_clear_fifos() which clears both FIFOs but leaves the state machine's + * internal state undisturbed. * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param sm State machine index (0..3) + * + * \sa pio_sm_clear_fifos() */ void pio_sm_drain_tx_fifo(PIO pio, uint sm); -/*! \brief set the current clock divider for a state machine +/*! \brief set the current clock divider for a state machine using a 16:8 fraction * \ingroup hardware_pio * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param sm State machine index (0..3) - * \param div the floating point clock divider + * \param div_int the integer part of the clock divider + * \param div_frac the fractional part of the clock divider in 1/256s */ -static inline void pio_sm_set_clkdiv(PIO pio, uint sm, float div) { +static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac) { + check_pio_param(pio); check_sm_param(sm); - uint16_t div_int = (uint16_t) div; - uint8_t div_frac = (uint8_t) ((div - div_int) * (1u << 8u)); pio->sm[sm].clkdiv = - (div_frac << PIO_SM0_CLKDIV_FRAC_LSB) | - (div_int << PIO_SM0_CLKDIV_INT_LSB); + (((uint)div_frac) << PIO_SM0_CLKDIV_FRAC_LSB) | + (((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB); } -/*! \brief set the current clock divider for a state machine using a 16:8 fraction +/*! \brief set the current clock divider for a state machine * \ingroup hardware_pio * * \param pio The PIO instance; either \ref pio0 or \ref pio1 * \param sm State machine index (0..3) - * \param div_int the integer part of the clock divider - * \param div_frac the fractional part of the clock divider in 1/256s + * \param div the floating point clock divider */ -static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac) { +static inline void pio_sm_set_clkdiv(PIO pio, uint sm, float div) { + check_pio_param(pio); check_sm_param(sm); - pio->sm[sm].clkdiv = - (div_frac << PIO_SM0_CLKDIV_FRAC_LSB) | - (div_int << PIO_SM0_CLKDIV_INT_LSB); + uint16_t div_int; + uint8_t div_frac; + pio_calculate_clkdiv_from_float(div, &div_int, &div_frac); + pio_sm_set_clkdiv_int_frac(pio, sm, div_int, div_frac); } -/*! \brief Clear a state machine's TX and RX FIFOFs +/*! \brief Clear a state machine's TX and RX FIFOs * \ingroup hardware_pio * * \param pio The PIO instance; either \ref pio0 or \ref pio1 @@ -906,6 +1184,7 @@ static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int */ static inline void pio_sm_clear_fifos(PIO pio, uint sm) { // changing the FIFO join state clears the fifo + check_pio_param(pio); check_sm_param(sm); hw_xor_bits(&pio->sm[sm].shiftctrl, PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS); hw_xor_bits(&pio->sm[sm].shiftctrl, PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS); @@ -1014,6 +1293,17 @@ void pio_sm_unclaim(PIO pio, uint sm); */ int pio_claim_unused_sm(PIO pio, bool required); +/*! \brief Determine if a PIO state machine is claimed + * \ingroup hardware_pio + * + * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \return true if claimed, false otherwise + * \see pio_sm_claim + * \see pio_claim_sm_mask + */ +bool pio_sm_is_claimed(PIO pio, uint sm); + #ifdef __cplusplus } #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio_instructions.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio_instructions.h index 757411d5e..366213580 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio_instructions.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pio/include/hardware/pio_instructions.h @@ -9,7 +9,18 @@ #include "pico.h" -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS, Enable/disable assertions in the PIO instructions, type=bool, default=0, group=hardware_pio +/** \brief PIO instruction encoding + * \defgroup pio_instructions pio_instructions + * \ingroup hardware_pio + * + * Functions for generating PIO instruction encodings programmatically. In debug builds + *`PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS` can be set to 1 to enable validation of encoding function + * parameters. + * + * For fuller descriptions of the instructions in question see the "RP2040 Datasheet" + */ + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS, Enable/disable assertions in the PIO instructions, type=bool, default=0, group=pio_instructions #ifndef PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS #define PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS 0 #endif @@ -44,6 +55,12 @@ enum pio_instr_bits { #define _PIO_INVALID_MOV_DEST 0u #endif +/*! \brief Enumeration of values to pass for source/destination args for instruction encoding functions + * \ingroup pio_instructions + * + * \note Not all values are suitable for all functions. Validity is only checked in debug mode when + * `PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS` is 1 + */ enum pio_src_dest { pio_pins = 0u, pio_x = 1u, @@ -58,11 +75,11 @@ enum pio_src_dest { pio_exec_out = 7u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST, }; -inline static uint _pio_major_instr_bits(uint instr) { +static inline uint _pio_major_instr_bits(uint instr) { return instr & 0xe000u; } -inline static uint _pio_encode_instr_and_args(enum pio_instr_bits instr_bits, uint arg1, uint arg2) { +static inline uint _pio_encode_instr_and_args(enum pio_instr_bits instr_bits, uint arg1, uint arg2) { valid_params_if(PIO_INSTRUCTIONS, arg1 <= 0x7); #if PARAM_ASSERTIONS_ENABLED(PIO_INSTRUCTIONS) uint32_t major = _pio_major_instr_bits(instr_bits); @@ -75,99 +92,388 @@ inline static uint _pio_encode_instr_and_args(enum pio_instr_bits instr_bits, ui return instr_bits | (arg1 << 5u) | (arg2 & 0x1fu); } -inline static uint _pio_encode_instr_and_src_dest(enum pio_instr_bits instr_bits, enum pio_src_dest dest, uint value) { +static inline uint _pio_encode_instr_and_src_dest(enum pio_instr_bits instr_bits, enum pio_src_dest dest, uint value) { return _pio_encode_instr_and_args(instr_bits, dest & 7u, value); } -inline static uint pio_encode_delay(uint cycles) { +/*! \brief Encode just the delay slot bits of an instruction + * \ingroup pio_instructions + * + * \note This function does not return a valid instruction encoding; instead it returns an encoding of the delay + * slot suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when + * combining the results of this function with the results of \ref pio_encode_sideset and \ref pio_encode_sideset_opt + * as they share the same bits within the instruction encoding. + * + * \param cycles the number of cycles 0-31 (or less if side set is being used) + * \return the delay slot bits to be ORed with an instruction encoding + */ +static inline uint pio_encode_delay(uint cycles) { + // note that the maximum cycles will be smaller if sideset_bit_count > 0 valid_params_if(PIO_INSTRUCTIONS, cycles <= 0x1f); return cycles << 8u; } -inline static uint pio_encode_sideset(uint sideset_bit_count, uint value) { +/*! \brief Encode just the side set bits of an instruction (in non optional side set mode) + * \ingroup pio_instructions + * + * \note This function does not return a valid instruction encoding; instead it returns an encoding of the side set bits + * suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when + * combining the results of this function with the results of \ref pio_encode_delay as they share the same bits + * within the instruction encoding. + * + * \param sideset_bit_count number of side set bits as would be specified via `.sideset` in pioasm + * \param value the value to sideset on the pins + * \return the side set bits to be ORed with an instruction encoding + */ +static inline uint pio_encode_sideset(uint sideset_bit_count, uint value) { valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 1 && sideset_bit_count <= 5); - valid_params_if(PIO_INSTRUCTIONS, value <= (0x1fu >> sideset_bit_count)); + valid_params_if(PIO_INSTRUCTIONS, value <= ((1u << sideset_bit_count) - 1)); return value << (13u - sideset_bit_count); } -inline static uint pio_encode_sideset_opt(uint sideset_bit_count, uint value) { - valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 2 && sideset_bit_count <= 5); - valid_params_if(PIO_INSTRUCTIONS, value <= (0x1fu >> sideset_bit_count)); +/*! \brief Encode just the side set bits of an instruction (in optional -`opt` side set mode) + * \ingroup pio_instructions + * + * \note This function does not return a valid instruction encoding; instead it returns an encoding of the side set bits + * suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when + * combining the results of this function with the results of \ref pio_encode_delay as they share the same bits + * within the instruction encoding. + * + * \param sideset_bit_count number of side set bits as would be specified via `.sideset opt` in pioasm + * \param value the value to sideset on the pins + * \return the side set bits to be ORed with an instruction encoding + */ +static inline uint pio_encode_sideset_opt(uint sideset_bit_count, uint value) { + valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 1 && sideset_bit_count <= 4); + valid_params_if(PIO_INSTRUCTIONS, value <= ((1u << sideset_bit_count) - 1)); return 0x1000u | value << (12u - sideset_bit_count); } -inline static uint pio_encode_jmp(uint addr) { +/*! \brief Encode an unconditional JMP instruction + * \ingroup pio_instructions + * + * This is the equivalent of `JMP ` + * + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_jmp(uint addr) { return _pio_encode_instr_and_args(pio_instr_bits_jmp, 0, addr); } -inline static uint _pio_encode_irq(bool relative, uint irq) { +/*! \brief Encode a conditional JMP if scratch X zero instruction + * \ingroup pio_instructions + * + * This is the equivalent of `JMP !X ` + * + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_jmp_not_x(uint addr) { + return _pio_encode_instr_and_args(pio_instr_bits_jmp, 1, addr); +} + +/*! \brief Encode a conditional JMP if scratch X non-zero (and post-decrement X) instruction + * \ingroup pio_instructions + * + * This is the equivalent of `JMP X-- ` + * + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_jmp_x_dec(uint addr) { + return _pio_encode_instr_and_args(pio_instr_bits_jmp, 2, addr); +} + +/*! \brief Encode a conditional JMP if scratch Y zero instruction + * \ingroup pio_instructions + * + * This is the equivalent of `JMP !Y ` + * + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_jmp_not_y(uint addr) { + return _pio_encode_instr_and_args(pio_instr_bits_jmp, 3, addr); +} + +/*! \brief Encode a conditional JMP if scratch Y non-zero (and post-decrement Y) instruction + * \ingroup pio_instructions + * + * This is the equivalent of `JMP Y-- ` + * + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_jmp_y_dec(uint addr) { + return _pio_encode_instr_and_args(pio_instr_bits_jmp, 4, addr); +} + +/*! \brief Encode a conditional JMP if scratch X not equal scratch Y instruction + * \ingroup pio_instructions + * + * This is the equivalent of `JMP X!=Y ` + * + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_jmp_x_ne_y(uint addr) { + return _pio_encode_instr_and_args(pio_instr_bits_jmp, 5, addr); +} + +/*! \brief Encode a conditional JMP if input pin high instruction + * \ingroup pio_instructions + * + * This is the equivalent of `JMP PIN ` + * + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_jmp_pin(uint addr) { + return _pio_encode_instr_and_args(pio_instr_bits_jmp, 6, addr); +} + +/*! \brief Encode a conditional JMP if output shift register not empty instruction + * \ingroup pio_instructions + * + * This is the equivalent of `JMP !OSRE ` + * + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_jmp_not_osre(uint addr) { + return _pio_encode_instr_and_args(pio_instr_bits_jmp, 7, addr); +} + +static inline uint _pio_encode_irq(bool relative, uint irq) { valid_params_if(PIO_INSTRUCTIONS, irq <= 7); return (relative ? 0x10u : 0x0u) | irq; } -inline static uint pio_encode_wait_gpio(bool polarity, uint pin) { - return _pio_encode_instr_and_args(pio_instr_bits_wait, 0u | (polarity ? 4u : 0u), pin); +/*! \brief Encode a WAIT for GPIO pin instruction + * \ingroup pio_instructions + * + * This is the equivalent of `WAIT GPIO ` + * + * \param polarity true for `WAIT 1`, false for `WAIT 0` + * \param gpio The real GPIO number 0-31 + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_wait_gpio(bool polarity, uint gpio) { + return _pio_encode_instr_and_args(pio_instr_bits_wait, 0u | (polarity ? 4u : 0u), gpio); } -inline static uint pio_encode_wait_pin(bool polarity, uint pin) { +/*! \brief Encode a WAIT for pin instruction + * \ingroup pio_instructions + * + * This is the equivalent of `WAIT PIN ` + * + * \param polarity true for `WAIT 1`, false for `WAIT 0` + * \param pin The pin number 0-31 relative to the executing SM's input pin mapping + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_wait_pin(bool polarity, uint pin) { return _pio_encode_instr_and_args(pio_instr_bits_wait, 1u | (polarity ? 4u : 0u), pin); } -inline static uint pio_encode_wait_irq(bool polarity, bool relative, uint irq) { +/*! \brief Encode a WAIT for IRQ instruction + * \ingroup pio_instructions + * + * This is the equivalent of `WAIT IRQ ` + * + * \param polarity true for `WAIT 1`, false for `WAIT 0` + * \param relative true for a `WAIT IRQ REL`, false for regular `WAIT IRQ ` + * \param irq the irq number 0-7 + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_wait_irq(bool polarity, bool relative, uint irq) { valid_params_if(PIO_INSTRUCTIONS, irq <= 7); return _pio_encode_instr_and_args(pio_instr_bits_wait, 2u | (polarity ? 4u : 0u), _pio_encode_irq(relative, irq)); } -inline static uint pio_encode_in(enum pio_src_dest src, uint value) { +/*! \brief Encode an IN instruction + * \ingroup pio_instructions + * + * This is the equivalent of `IN , ` + * + * \param src The source to take data from + * \param count The number of bits 1-32 + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_in(enum pio_src_dest src, uint count) { valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_IN_SRC)); - return _pio_encode_instr_and_src_dest(pio_instr_bits_in, src, value); + return _pio_encode_instr_and_src_dest(pio_instr_bits_in, src, count); } -inline static uint pio_encode_out(enum pio_src_dest dest, uint value) { +/*! \brief Encode an OUT instruction + * \ingroup pio_instructions + * + * This is the equivalent of `OUT , ` + * + * \param dest The destination to write data to + * \param count The number of bits 1-32 + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_out(enum pio_src_dest dest, uint count) { valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_OUT_DEST)); - return _pio_encode_instr_and_src_dest(pio_instr_bits_out, dest, value); + return _pio_encode_instr_and_src_dest(pio_instr_bits_out, dest, count); } -inline static uint pio_encode_push(bool if_full, bool block) { +/*! \brief Encode a PUSH instruction + * \ingroup pio_instructions + * + * This is the equivalent of `PUSH , ` + * + * \param if_full true for `PUSH IF_FULL ...`, false for `PUSH ...` + * \param block true for `PUSH ... BLOCK`, false for `PUSH ...` + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_push(bool if_full, bool block) { return _pio_encode_instr_and_args(pio_instr_bits_push, (if_full ? 2u : 0u) | (block ? 1u : 0u), 0); } -inline static uint pio_encode_pull(bool if_empty, bool block) { +/*! \brief Encode a PULL instruction + * \ingroup pio_instructions + * + * This is the equivalent of `PULL , ` + * + * \param if_empty true for `PULL IF_EMPTY ...`, false for `PULL ...` + * \param block true for `PULL ... BLOCK`, false for `PULL ...` + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_pull(bool if_empty, bool block) { return _pio_encode_instr_and_args(pio_instr_bits_pull, (if_empty ? 2u : 0u) | (block ? 1u : 0u), 0); } -inline static uint pio_encode_mov(enum pio_src_dest dest, enum pio_src_dest src) { +/*! \brief Encode a MOV instruction + * \ingroup pio_instructions + * + * This is the equivalent of `MOV , ` + * + * \param dest The destination to write data to + * \param src The source to take data from + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_mov(enum pio_src_dest dest, enum pio_src_dest src) { valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST)); valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC)); return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, src & 7u); } -inline static uint pio_encode_mov_not(enum pio_src_dest dest, enum pio_src_dest src) { +/*! \brief Encode a MOV instruction with bit invert + * \ingroup pio_instructions + * + * This is the equivalent of `MOV , ~` + * + * \param dest The destination to write inverted data to + * \param src The source to take data from + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_mov_not(enum pio_src_dest dest, enum pio_src_dest src) { valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST)); valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC)); return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, (1u << 3u) | (src & 7u)); } -inline static uint pio_encode_mov_reverse(enum pio_src_dest dest, enum pio_src_dest src) { +/*! \brief Encode a MOV instruction with bit reverse + * \ingroup pio_instructions + * + * This is the equivalent of `MOV , ::` + * + * \param dest The destination to write bit reversed data to + * \param src The source to take data from + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_mov_reverse(enum pio_src_dest dest, enum pio_src_dest src) { valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST)); valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC)); return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, (2u << 3u) | (src & 7u)); } -inline static uint pio_encode_irq_set(bool relative, uint irq) { +/*! \brief Encode a IRQ SET instruction + * \ingroup pio_instructions + * + * This is the equivalent of `IRQ SET ` + * + * \param relative true for a `IRQ SET REL`, false for regular `IRQ SET ` + * \param irq the irq number 0-7 + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_irq_set(bool relative, uint irq) { return _pio_encode_instr_and_args(pio_instr_bits_irq, 0, _pio_encode_irq(relative, irq)); } -inline static uint pio_encode_irq_clear(bool relative, uint irq) { +/*! \brief Encode a IRQ WAIT instruction + * \ingroup pio_instructions + * + * This is the equivalent of `IRQ WAIT ` + * + * \param relative true for a `IRQ WAIT REL`, false for regular `IRQ WAIT ` + * \param irq the irq number 0-7 + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_irq_wait(bool relative, uint irq) { + return _pio_encode_instr_and_args(pio_instr_bits_irq, 1, _pio_encode_irq(relative, irq)); +} + +/*! \brief Encode a IRQ CLEAR instruction + * \ingroup pio_instructions + * + * This is the equivalent of `IRQ CLEAR ` + * + * \param relative true for a `IRQ CLEAR REL`, false for regular `IRQ CLEAR ` + * \param irq the irq number 0-7 + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_irq_clear(bool relative, uint irq) { return _pio_encode_instr_and_args(pio_instr_bits_irq, 2, _pio_encode_irq(relative, irq)); } -inline static uint pio_encode_set(enum pio_src_dest dest, uint value) { +/*! \brief Encode a SET instruction + * \ingroup pio_instructions + * + * This is the equivalent of `SET , ` + * + * \param dest The destination to apply the value to + * \param value The value 0-31 + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_set(enum pio_src_dest dest, uint value) { valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_SET_DEST)); return _pio_encode_instr_and_src_dest(pio_instr_bits_set, dest, value); } -inline static uint pio_encode_nop() { +/*! \brief Encode a NOP instruction + * \ingroup pio_instructions + * + * This is the equivalent of `NOP` which is itself encoded as `MOV y, y` + * + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + */ +static inline uint pio_encode_nop(void) { return pio_encode_mov(pio_y, pio_y); } @@ -175,4 +481,4 @@ inline static uint pio_encode_nop() { } #endif -#endif \ No newline at end of file +#endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pll/include/hardware/pll.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pll/include/hardware/pll.h index 023e34033..ee0c3aef0 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pll/include/hardware/pll.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pll/include/hardware/pll.h @@ -39,7 +39,7 @@ typedef pll_hw_t *PLL; * \param post_div1 Post Divider 1 - range 1-7. Must be >= post_div2 * \param post_div2 Post Divider 2 - range 1-7 */ -void pll_init(PLL pll, uint32_t ref_div, uint32_t vco_freq, uint32_t post_div1, uint8_t post_div2); +void pll_init(PLL pll, uint ref_div, uint vco_freq, uint post_div1, uint post_div2); /*! \brief Release/uninitialise specified PLL. * \ingroup hardware_pll diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pwm/include/hardware/pwm.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pwm/include/hardware/pwm.h index 4b572f771..634375e76 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pwm/include/hardware/pwm.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_pwm/include/hardware/pwm.h @@ -9,12 +9,13 @@ #include "pico.h" #include "hardware/structs/pwm.h" +#include "hardware/regs/dreq.h" #ifdef __cplusplus extern "C" { #endif -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PWM, Enable/disable assertions in the PWM module, type=bool, default=0, group=hadrware_pwm +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PWM, Enable/disable assertions in the PWM module, type=bool, default=0, group=hardware_pwm #ifndef PARAM_ASSERTIONS_ENABLED_PWM #define PARAM_ASSERTIONS_ENABLED_PWM 0 #endif @@ -26,7 +27,7 @@ extern "C" { * * The RP2040 PWM block has 8 identical slices. Each slice can drive two PWM output signals, or * measure the frequency or duty cycle of an input signal. This gives a total of up to 16 controllable - * PWM outputs. All 30 GPIOs can be driven by the PWM block + * PWM outputs. All 30 GPIOs can be driven by the PWM block. * * The PWM hardware functions by continuously comparing the input value to a free-running counter. This produces a * toggling output where the amount of time spent at the high output level is proportional to the input value. The fraction of @@ -47,10 +48,10 @@ extern "C" { */ enum pwm_clkdiv_mode { - PWM_DIV_FREE_RUNNING, ///< Free-running counting at rate dictated by fractional divider - PWM_DIV_B_HIGH, ///< Fractional divider is gated by the PWM B pin - PWM_DIV_B_RISING, ///< Fractional divider advances with each rising edge of the PWM B pin - PWM_DIV_B_FALLING ///< Fractional divider advances with each falling edge of the PWM B pin + PWM_DIV_FREE_RUNNING = 0, ///< Free-running counting at rate dictated by fractional divider + PWM_DIV_B_HIGH = 1, ///< Fractional divider is gated by the PWM B pin + PWM_DIV_B_RISING = 2, ///< Fractional divider advances with each rising edge of the PWM B pin + PWM_DIV_B_FALLING = 3 ///< Fractional divider advances with each falling edge of the PWM B pin }; enum pwm_chan @@ -65,6 +66,10 @@ typedef struct { uint32_t top; } pwm_config; +static inline void check_slice_num_param(__unused uint slice_num) { + valid_params_if(PWM, slice_num < NUM_PWM_SLICES); +} + /** \brief Determine the PWM slice that is attached to the specified GPIO * \ingroup hardware_pwm * @@ -98,7 +103,7 @@ static inline uint pwm_gpio_to_channel(uint gpio) { */ static inline void pwm_config_set_phase_correct(pwm_config *c, bool phase_correct) { c->csr = (c->csr & ~PWM_CH0_CSR_PH_CORRECT_BITS) - | (!!phase_correct << PWM_CH0_CSR_PH_CORRECT_LSB); + | (bool_to_bit(phase_correct) << PWM_CH0_CSR_PH_CORRECT_LSB); } /** \brief Set clock divider in a PWM configuration @@ -112,21 +117,21 @@ static inline void pwm_config_set_phase_correct(pwm_config *c, bool phase_correc * before passing them on to the PWM counter. */ static inline void pwm_config_set_clkdiv(pwm_config *c, float div) { - c->div = (uint32_t)(div * (float)(1u << PWM_CH1_DIV_INT_LSB)); + c->div = (uint32_t)(div * (float)(1u << PWM_CH0_DIV_INT_LSB)); } /** \brief Set PWM clock divider in a PWM configuration * \ingroup hardware_pwm * * \param c PWM configuration struct to modify - * \param div integer value to reduce counting rate by. Must be greater than or equal to 1. + * \param div Integer value to reduce counting rate by. Must be greater than or equal to 1. * * If the divide mode is free-running, the PWM counter runs at clk_sys / div. * Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge) * before passing them on to the PWM counter. */ static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint div) { - c->div = div << PWM_CH1_DIV_INT_LSB; + c->div = div << PWM_CH0_DIV_INT_LSB; } /** \brief Set PWM counting mode in a PWM configuration @@ -140,9 +145,12 @@ static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint div) { * high level, rising edge or falling edge of the B pin input. */ static inline void pwm_config_set_clkdiv_mode(pwm_config *c, enum pwm_clkdiv_mode mode) { - valid_params_if(PWM, mode >= PWM_DIV_FREE_RUNNING && mode <= PWM_DIV_B_FALLING); + valid_params_if(PWM, mode == PWM_DIV_FREE_RUNNING || + mode == PWM_DIV_B_RISING || + mode == PWM_DIV_B_HIGH || + mode == PWM_DIV_B_FALLING); c->csr = (c->csr & ~PWM_CH0_CSR_DIVMODE_BITS) - | (mode << PWM_CH0_CSR_DIVMODE_LSB); + | (((uint)mode) << PWM_CH0_CSR_DIVMODE_LSB); } /** \brief Set output polarity in a PWM configuration @@ -154,7 +162,7 @@ static inline void pwm_config_set_clkdiv_mode(pwm_config *c, enum pwm_clkdiv_mod */ static inline void pwm_config_set_output_polarity(pwm_config *c, bool a, bool b) { c->csr = (c->csr & ~(PWM_CH0_CSR_A_INV_BITS | PWM_CH0_CSR_B_INV_BITS)) - | ((!!a << PWM_CH0_CSR_A_INV_LSB) | (!!b << PWM_CH0_CSR_B_INV_LSB)); + | ((bool_to_bit(a) << PWM_CH0_CSR_A_INV_LSB) | (bool_to_bit(b) << PWM_CH0_CSR_B_INV_LSB)); } /** \brief Set PWM counter wrap value in a PWM configuration @@ -181,25 +189,25 @@ static inline void pwm_config_set_wrap(pwm_config *c, uint16_t wrap) { * manually using \ref pwm_set_enabled() or \ref pwm_set_mask_enabled() */ static inline void pwm_init(uint slice_num, pwm_config *c, bool start) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + check_slice_num_param(slice_num); pwm_hw->slice[slice_num].csr = 0; pwm_hw->slice[slice_num].ctr = PWM_CH0_CTR_RESET; pwm_hw->slice[slice_num].cc = PWM_CH0_CC_RESET; pwm_hw->slice[slice_num].top = c->top; pwm_hw->slice[slice_num].div = c->div; - pwm_hw->slice[slice_num].csr = c->csr | (!!start << PWM_CH0_CSR_EN_LSB); + pwm_hw->slice[slice_num].csr = c->csr | (bool_to_bit(start) << PWM_CH0_CSR_EN_LSB); } /** \brief Get a set of default values for PWM configuration * \ingroup hardware_pwm * - * PWM config is free running at system clock speed, no phase correction, wrapping at 0xffff, + * PWM config is free-running at system clock speed, no phase correction, wrapping at 0xffff, * with standard polarities for channels A and B. * * \return Set of default values. */ -static inline pwm_config pwm_get_default_config() { +static inline pwm_config pwm_get_default_config(void) { pwm_config c = {0, 0, 0}; pwm_config_set_phase_correct(&c, false); pwm_config_set_clkdiv_int(&c, 1); @@ -212,30 +220,43 @@ static inline pwm_config pwm_get_default_config() { /** \brief Set the current PWM counter wrap value * \ingroup hardware_pwm * - * Set the highest value the counter will reach before returning to 0. Also known as TOP. + * Set the highest value the counter will reach before returning to 0. Also + * known as TOP. + * + * The counter wrap value is double-buffered in hardware. This means that, + * when the PWM is running, a write to the counter wrap value does not take + * effect until after the next time the PWM slice wraps (or, in phase-correct + * mode, the next time the slice reaches 0). If the PWM is not running, the + * write is latched in immediately. * * \param slice_num PWM slice number * \param wrap Value to set wrap to */ static inline void pwm_set_wrap(uint slice_num, uint16_t wrap) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + check_slice_num_param(slice_num); pwm_hw->slice[slice_num].top = wrap; } /** \brief Set the current PWM counter compare value for one channel * \ingroup hardware_pwm * - * Set the value of the PWM counter compare value, for either channel A or channel B + * Set the value of the PWM counter compare value, for either channel A or channel B. + * + * The counter compare register is double-buffered in hardware. This means + * that, when the PWM is running, a write to the counter compare values does + * not take effect until the next time the PWM slice wraps (or, in + * phase-correct mode, the next time the slice reaches 0). If the PWM is not + * running, the write is latched in immediately. * * \param slice_num PWM slice number * \param chan Which channel to update. 0 for A, 1 for B. * \param level new level for the selected output */ static inline void pwm_set_chan_level(uint slice_num, uint chan, uint16_t level) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + check_slice_num_param(slice_num); hw_write_masked( &pwm_hw->slice[slice_num].cc, - level << (chan ? PWM_CH0_CC_B_LSB : PWM_CH0_CC_A_LSB), + ((uint)level) << (chan ? PWM_CH0_CC_B_LSB : PWM_CH0_CC_A_LSB), chan ? PWM_CH0_CC_B_BITS : PWM_CH0_CC_A_BITS ); } @@ -243,26 +264,38 @@ static inline void pwm_set_chan_level(uint slice_num, uint chan, uint16_t level) /** \brief Set PWM counter compare values * \ingroup hardware_pwm * - * Set the value of the PWM counter compare values, A and B + * Set the value of the PWM counter compare values, A and B. + * + * The counter compare register is double-buffered in hardware. This means + * that, when the PWM is running, a write to the counter compare values does + * not take effect until the next time the PWM slice wraps (or, in + * phase-correct mode, the next time the slice reaches 0). If the PWM is not + * running, the write is latched in immediately. * * \param slice_num PWM slice number * \param level_a Value to set compare A to. When the counter reaches this value the A output is deasserted * \param level_b Value to set compare B to. When the counter reaches this value the B output is deasserted */ static inline void pwm_set_both_levels(uint slice_num, uint16_t level_a, uint16_t level_b) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); - pwm_hw->slice[slice_num].cc = (level_b << PWM_CH0_CC_B_LSB) | (level_a << PWM_CH0_CC_A_LSB); + check_slice_num_param(slice_num); + pwm_hw->slice[slice_num].cc = (((uint)level_b) << PWM_CH0_CC_B_LSB) | (((uint)level_a) << PWM_CH0_CC_A_LSB); } /** \brief Helper function to set the PWM level for the slice and channel associated with a GPIO. * \ingroup hardware_pwm * * Look up the correct slice (0 to 7) and channel (A or B) for a given GPIO, and update the corresponding - * counter-compare field. + * counter compare field. * * This PWM slice should already have been configured and set running. Also be careful of multiple GPIOs * mapping to the same slice and channel (if GPIOs have a difference of 16). * + * The counter compare register is double-buffered in hardware. This means + * that, when the PWM is running, a write to the counter compare values does + * not take effect until the next time the PWM slice wraps (or, in + * phase-correct mode, the next time the slice reaches 0). If the PWM is not + * running, the write is latched in immediately. + * * \param gpio GPIO to set level of * \param level PWM level for this GPIO */ @@ -277,11 +310,11 @@ static inline void pwm_set_gpio_level(uint gpio, uint16_t level) { * Get current value of PWM counter * * \param slice_num PWM slice number - * \return Current value of PWM counter + * \return Current value of the PWM counter */ -static inline int16_t pwm_get_counter(uint slice_num) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); - return (pwm_hw->slice[slice_num].ctr); +static inline uint16_t pwm_get_counter(uint slice_num) { + check_slice_num_param(slice_num); + return (uint16_t)(pwm_hw->slice[slice_num].ctr); } /** \brief Set PWM counter @@ -294,7 +327,7 @@ static inline int16_t pwm_get_counter(uint slice_num) { * */ static inline void pwm_set_counter(uint slice_num, uint16_t c) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + check_slice_num_param(slice_num); pwm_hw->slice[slice_num].ctr = c; } @@ -308,7 +341,7 @@ static inline void pwm_set_counter(uint slice_num, uint16_t c) { * \param slice_num PWM slice number */ static inline void pwm_advance_count(uint slice_num) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + check_slice_num_param(slice_num); hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_ADV_BITS); while (pwm_hw->slice[slice_num].csr & PWM_CH0_CSR_PH_ADV_BITS) { tight_loop_contents(); @@ -325,7 +358,7 @@ static inline void pwm_advance_count(uint slice_num) { * \param slice_num PWM slice number */ static inline void pwm_retard_count(uint slice_num) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + check_slice_num_param(slice_num); hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_RET_BITS); while (pwm_hw->slice[slice_num].csr & PWM_CH0_CSR_PH_RET_BITS) { tight_loop_contents(); @@ -335,28 +368,28 @@ static inline void pwm_retard_count(uint slice_num) { /** \brief Set PWM clock divider using an 8:4 fractional value * \ingroup hardware_pwm * - * Set the clock divider. Counter increment will be on sysclock divided by this value, taking in to account the gating. + * Set the clock divider. Counter increment will be on sysclock divided by this value, taking into account the gating. * * \param slice_num PWM slice number * \param integer 8 bit integer part of the clock divider * \param fract 4 bit fractional part of the clock divider */ static inline void pwm_set_clkdiv_int_frac(uint slice_num, uint8_t integer, uint8_t fract) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); - valid_params_if(PWM, fract >= 0 && slice_num <= 16); - pwm_hw->slice[slice_num].div = (integer << PWM_CH0_DIV_INT_LSB) | (fract << PWM_CH0_DIV_FRAC_LSB); + check_slice_num_param(slice_num); + valid_params_if(PWM, fract < 16); + pwm_hw->slice[slice_num].div = (((uint)integer) << PWM_CH0_DIV_INT_LSB) | (((uint)fract) << PWM_CH0_DIV_FRAC_LSB); } /** \brief Set PWM clock divider * \ingroup hardware_pwm * - * Set the clock divider. Counter increment will be on sysclock divided by this value, taking in to account the gating. + * Set the clock divider. Counter increment will be on sysclock divided by this value, taking into account the gating. * * \param slice_num PWM slice number * \param divider Floating point clock divider, 1.f <= value < 256.f */ static inline void pwm_set_clkdiv(uint slice_num, float divider) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + check_slice_num_param(slice_num); valid_params_if(PWM, divider >= 1.f && divider < 256.f); uint8_t i = (uint8_t)divider; uint8_t f = (uint8_t)((divider - i) * (0x01 << 4)); @@ -371,8 +404,8 @@ static inline void pwm_set_clkdiv(uint slice_num, float divider) { * \param b true to invert output B */ static inline void pwm_set_output_polarity(uint slice_num, bool a, bool b) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); - hw_write_masked(&pwm_hw->slice[slice_num].csr, !!a << PWM_CH0_CSR_A_INV_LSB | !!b << PWM_CH0_CSR_B_INV_LSB, + check_slice_num_param(slice_num); + hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(a) << PWM_CH0_CSR_A_INV_LSB | bool_to_bit(b) << PWM_CH0_CSR_B_INV_LSB, PWM_CH0_CSR_A_INV_BITS | PWM_CH0_CSR_B_INV_BITS); } @@ -384,9 +417,12 @@ static inline void pwm_set_output_polarity(uint slice_num, bool a, bool b) { * \param mode Required divider mode */ static inline void pwm_set_clkdiv_mode(uint slice_num, enum pwm_clkdiv_mode mode) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); - valid_params_if(PWM, mode >= PWM_DIV_FREE_RUNNING && mode <= PWM_DIV_B_FALLING); - hw_write_masked(&pwm_hw->slice[slice_num].csr, mode << PWM_CH0_CSR_DIVMODE_LSB, PWM_CH0_CSR_DIVMODE_BITS); + check_slice_num_param(slice_num); + valid_params_if(PWM, mode == PWM_DIV_FREE_RUNNING || + mode == PWM_DIV_B_RISING || + mode == PWM_DIV_B_HIGH || + mode == PWM_DIV_B_FALLING); + hw_write_masked(&pwm_hw->slice[slice_num].csr, ((uint)mode) << PWM_CH0_CSR_DIVMODE_LSB, PWM_CH0_CSR_DIVMODE_BITS); } /** \brief Set PWM phase correct on/off @@ -399,19 +435,39 @@ static inline void pwm_set_clkdiv_mode(uint slice_num, enum pwm_clkdiv_mode mode * the PWM starts counting back down. The output frequency is halved when phase-correct mode is enabled. */ static inline void pwm_set_phase_correct(uint slice_num, bool phase_correct) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); - hw_write_masked(&pwm_hw->slice[slice_num].csr, phase_correct << PWM_CH0_CSR_PH_CORRECT_LSB, PWM_CH0_CSR_PH_CORRECT_BITS); + check_slice_num_param(slice_num); + hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(phase_correct) << PWM_CH0_CSR_PH_CORRECT_LSB, PWM_CH0_CSR_PH_CORRECT_BITS); } /** \brief Enable/Disable PWM * \ingroup hardware_pwm * + * When a PWM is disabled, it halts its counter, and the output pins are left + * high or low depending on exactly when the counter is halted. When + * re-enabled the PWM resumes immediately from where it left off. + * + * If the PWM's output pins need to be low when halted: + * + * - The counter compare can be set to zero whilst the PWM is enabled, and + * then the PWM disabled once both pins are seen to be low + * + * - The GPIO output overrides can be used to force the actual pins low + * + * - The PWM can be run for one cycle (i.e. enabled then immediately disabled) + * with a TOP of 0, count of 0 and counter compare of 0, to force the pins + * low when the PWM has already been halted. The same method can be used + * with a counter compare value of 1 to force a pin high. + * + * Note that, when disabled, the PWM can still be advanced one count at a time + * by pulsing the PH_ADV bit in its CSR. The output pins transition as though + * the PWM were enabled. + * * \param slice_num PWM slice number - * \param enabled true to enable the specified PWM, false to disable + * \param enabled true to enable the specified PWM, false to disable. */ static inline void pwm_set_enabled(uint slice_num, bool enabled) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); - hw_write_masked(&pwm_hw->slice[slice_num].csr, !!enabled << PWM_CH0_CSR_EN_LSB, PWM_CH0_CSR_EN_BITS); + check_slice_num_param(slice_num); + hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(enabled) << PWM_CH0_CSR_EN_LSB, PWM_CH0_CSR_EN_BITS); } /** \brief Enable/Disable multiple PWM slices simultaneously @@ -426,13 +482,13 @@ static inline void pwm_set_mask_enabled(uint32_t mask) { /*! \brief Enable PWM instance interrupt * \ingroup hardware_pwm * - * Used to enable a single PWM instance interrupt + * Used to enable a single PWM instance interrupt. * * \param slice_num PWM block to enable/disable * \param enabled true to enable, false to disable */ static inline void pwm_set_irq_enabled(uint slice_num, bool enabled) { - valid_params_if(PWM, slice_num >= 0 && slice_num < NUM_PWM_SLICES); + check_slice_num_param(slice_num); if (enabled) { hw_set_bits(&pwm_hw->inte, 1u << slice_num); } else { @@ -457,7 +513,7 @@ static inline void pwm_set_irq_mask_enabled(uint32_t slice_mask, bool enabled) { } } -/*! \brief Clear single PWM channel interrupt +/*! \brief Clear a single PWM channel interrupt * \ingroup hardware_pwm * * \param slice_num PWM slice number @@ -471,7 +527,7 @@ static inline void pwm_clear_irq(uint slice_num) { * * \return Bitmask of all PWM interrupts currently set */ -static inline int32_t pwm_get_irq_status_mask() { +static inline uint32_t pwm_get_irq_status_mask(void) { return pwm_hw->ints; } @@ -484,6 +540,18 @@ static inline void pwm_force_irq(uint slice_num) { pwm_hw->intf = 1u << slice_num; } +/*! \brief Return the DREQ to use for pacing transfers to a particular PWM slice + * \ingroup hardware_pwm + * + * \param slice_num PWM slice number + */ +static inline uint pwm_get_dreq(uint slice_num) { + static_assert(DREQ_PWM_WRAP1 == DREQ_PWM_WRAP0 + 1, ""); + static_assert(DREQ_PWM_WRAP7 == DREQ_PWM_WRAP0 + 7, ""); + check_slice_num_param(slice_num); + return DREQ_PWM_WRAP0 + slice_num; +} + #ifdef __cplusplus } #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_resets/include/hardware/resets.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_resets/include/hardware/resets.h index fab604bda..a3f7014b7 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_resets/include/hardware/resets.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_resets/include/hardware/resets.h @@ -56,6 +56,10 @@ * \include hello_reset.c */ +#ifdef __cplusplus +extern "C" { +#endif + /// \tag::reset_funcs[] /*! \brief Reset the specified HW blocks @@ -88,4 +92,8 @@ static inline void unreset_block_wait(uint32_t bits) { } /// \end::reset_funcs[] +#ifdef __cplusplus +} +#endif + #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h index dcdcd2285..f9ec793d4 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_rtc/include/hardware/rtc.h @@ -28,7 +28,15 @@ * \include hello_rtc.c */ +#ifdef __cplusplus +extern "C" { +#endif +/*! Callback function type for RTC alarms + * \ingroup hardware_rtc + * + * \sa rtc_set_alarm() + */ typedef void (*rtc_callback_t)(void); /*! \brief Initialise the RTC system @@ -66,9 +74,18 @@ bool rtc_running(void); */ void rtc_set_alarm(datetime_t *t, rtc_callback_t user_callback); +/*! \brief Enable the RTC alarm (if inactive) + * \ingroup hardware_rtc + */ +void rtc_enable_alarm(void); + /*! \brief Disable the RTC alarm (if active) * \ingroup hardware_rtc */ void rtc_disable_alarm(void); +#ifdef __cplusplus +} +#endif + #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h index 789efc6f0..eea706213 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_spi/include/hardware/spi.h @@ -10,6 +10,7 @@ #include "pico.h" #include "pico/time.h" #include "hardware/structs/spi.h" +#include "hardware/regs/dreq.h" // PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_SPI, Enable/disable assertions in the SPI module, type=bool, default=0, group=hardware_spi #ifndef PARAM_ASSERTIONS_ENABLED_SPI @@ -35,6 +36,12 @@ extern "C" { * Each controller can be connected to a number of GPIO pins, see the datasheet GPIO function selection table for more information. */ +// PICO_CONFIG: PICO_DEFAULT_SPI, Define the default SPI for a board, min=0, max=1, group=hardware_spi +// PICO_CONFIG: PICO_DEFAULT_SPI_SCK_PIN, Define the default SPI SCK pin, min=0, max=29, group=hardware_spi +// PICO_CONFIG: PICO_DEFAULT_SPI_TX_PIN, Define the default SPI TX pin, min=0, max=29, group=hardware_spi +// PICO_CONFIG: PICO_DEFAULT_SPI_RX_PIN, Define the default SPI RX pin, min=0, max=29, group=hardware_spi +// PICO_CONFIG: PICO_DEFAULT_SPI_CSN_PIN, Define the default SPI CSN pin, min=0, max=29, group=hardware_spi + /** * Opaque type representing an SPI instance. */ @@ -56,16 +63,33 @@ typedef struct spi_inst spi_inst_t; */ #define spi1 ((spi_inst_t * const)spi1_hw) +#if !defined(PICO_DEFAULT_SPI_INSTANCE) && defined(PICO_DEFAULT_SPI) +#define PICO_DEFAULT_SPI_INSTANCE (__CONCAT(spi,PICO_DEFAULT_SPI)) +#endif + +#ifdef PICO_DEFAULT_SPI_INSTANCE +#define spi_default PICO_DEFAULT_SPI_INSTANCE +#endif + +/** \brief Enumeration of SPI CPHA (clock phase) values. + * \ingroup hardware_spi + */ typedef enum { SPI_CPHA_0 = 0, SPI_CPHA_1 = 1 } spi_cpha_t; +/** \brief Enumeration of SPI CPOL (clock polarity) values. + * \ingroup hardware_spi + */ typedef enum { SPI_CPOL_0 = 0, SPI_CPOL_1 = 1 } spi_cpol_t; +/** \brief Enumeration of SPI bit-order values. + * \ingroup hardware_spi + */ typedef enum { SPI_LSB_FIRST = 0, SPI_MSB_FIRST = 1 @@ -79,14 +103,14 @@ typedef enum { * Puts the SPI into a known state, and enable it. Must be called before other * functions. * - * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - * \param baudrate Baudrate required in Hz + * \note There is no guarantee that the baudrate requested can be achieved exactly; the nearest will be chosen + * and returned * - * \note There is no guarantee that the baudrate requested will be possible, the nearest will be chosen, - * and this function does not return any indication of this. You can use the \ref spi_set_baudrate function - * which will return the actual baudrate selected if this is important. + * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 + * \param baudrate Baudrate requested in Hz + * \return the actual baud rate set */ -void _spi_init(spi_inst_t *spi, uint baudrate); +uint _spi_init(spi_inst_t *spi, uint baudrate); /*! \brief Deinitialise SPI instances * \ingroup hardware_spi @@ -109,13 +133,23 @@ void spi_deinit(spi_inst_t *spi); */ uint spi_set_baudrate(spi_inst_t *spi, uint baudrate); -/*! \brief Convert I2c instance to hardware instance number +/*! \brief Get SPI baudrate + * \ingroup hardware_spi + * + * Get SPI baudrate which was set by \see spi_set_baudrate + * + * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 + * \return The actual baudrate set + */ +uint spi_get_baudrate(const spi_inst_t *spi); + +/*! \brief Convert SPI instance to hardware instance number * \ingroup hardware_spi * * \param spi SPI instance * \return Number of SPI, 0 or 1. */ -static inline uint spi_get_index(spi_inst_t *spi) { +static inline uint spi_get_index(const spi_inst_t *spi) { invalid_params_if(SPI, spi != spi0 && spi != spi1); return spi == spi1 ? 1 : 0; } @@ -125,6 +159,11 @@ static inline spi_hw_t *spi_get_hw(spi_inst_t *spi) { return (spi_hw_t *)spi; } +static inline const spi_hw_t *spi_get_const_hw(const spi_inst_t *spi) { + spi_get_index(spi); // check it is a hw spi + return (const spi_hw_t *)spi; +} + /*! \brief Configure SPI * \ingroup hardware_spi * @@ -136,16 +175,16 @@ static inline spi_hw_t *spi_get_hw(spi_inst_t *spi) { * \param cpha SSPCLKOUT phase, applicable to Motorola SPI frame format only * \param order Must be SPI_MSB_FIRST, no other values supported on the PL022 */ -static inline void spi_set_format(spi_inst_t *spi, uint data_bits, spi_cpol_t cpol, spi_cpha_t cpha, spi_order_t order) { +static inline void spi_set_format(spi_inst_t *spi, uint data_bits, spi_cpol_t cpol, spi_cpha_t cpha, __unused spi_order_t order) { invalid_params_if(SPI, data_bits < 4 || data_bits > 16); // LSB-first not supported on PL022: invalid_params_if(SPI, order != SPI_MSB_FIRST); invalid_params_if(SPI, cpol != SPI_CPOL_0 && cpol != SPI_CPOL_1); invalid_params_if(SPI, cpha != SPI_CPHA_0 && cpha != SPI_CPHA_1); hw_write_masked(&spi_get_hw(spi)->cr0, - (data_bits - 1) << SPI_SSPCR0_DSS_LSB | - cpol << SPI_SSPCR0_SPO_LSB | - cpha << SPI_SSPCR0_SPH_LSB, + ((uint)(data_bits - 1)) << SPI_SSPCR0_DSS_LSB | + ((uint)cpol) << SPI_SSPCR0_SPO_LSB | + ((uint)cpha) << SPI_SSPCR0_SPH_LSB, SPI_SSPCR0_DSS_BITS | SPI_SSPCR0_SPO_BITS | SPI_SSPCR0_SPH_BITS); @@ -174,27 +213,30 @@ static inline void spi_set_slave(spi_inst_t *spi, bool slave) { * \ingroup hardware_spi * * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - * \return 0 if no space is available to write. Non-zero if a write is possible - * - * \note Although the controllers each have a 8 deep TX FIFO, the current HW implementation can only return 0 or 1 - * rather than the space available. + * \return false if no space is available to write. True if a write is possible */ -static inline size_t spi_is_writable(spi_inst_t *spi) { - // PL022 doesn't expose levels directly, so return values are only 0 or 1 - return (spi_get_hw(spi)->sr & SPI_SSPSR_TNF_BITS) >> SPI_SSPSR_TNF_LSB; +static inline bool spi_is_writable(const spi_inst_t *spi) { + return (spi_get_const_hw(spi)->sr & SPI_SSPSR_TNF_BITS); } /*! \brief Check whether a read can be done on SPI device * \ingroup hardware_spi * * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 - * \return Non-zero if a read is possible i.e. data is present + * \return true if a read is possible i.e. data is present + */ +static inline bool spi_is_readable(const spi_inst_t *spi) { + return (spi_get_const_hw(spi)->sr & SPI_SSPSR_RNE_BITS); +} + +/*! \brief Check whether SPI is busy + * \ingroup hardware_spi * - * \note Although the controllers each have a 8 deep RX FIFO, the current HW implementation can only return 0 or 1 - * rather than the data available. + * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 + * \return true if SPI is busy */ -static inline size_t spi_is_readable(spi_inst_t *spi) { - return (spi_get_hw(spi)->sr & SPI_SSPSR_RNE_BITS) >> SPI_SSPSR_RNE_LSB; +static inline bool spi_is_busy(const spi_inst_t *spi) { + return (spi_get_const_hw(spi)->sr & SPI_SSPSR_BSY_BITS); } /*! \brief Write/Read to/from an SPI device @@ -258,7 +300,7 @@ int spi_read_blocking(spi_inst_t *spi, uint8_t repeated_tx_data, uint8_t *dst, s * \param src Buffer of data to write * \param dst Buffer for read data * \param len Length of BOTH buffers in halfwords - * \return Number of bytes written/read + * \return Number of halfwords written/read */ int spi_write16_read16_blocking(spi_inst_t *spi, const uint16_t *src, uint16_t *dst, size_t len); @@ -273,7 +315,7 @@ int spi_write16_read16_blocking(spi_inst_t *spi, const uint16_t *src, uint16_t * * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 * \param src Buffer of data to write * \param len Length of buffers - * \return Number of bytes written/read + * \return Number of halfwords written/read */ int spi_write16_blocking(spi_inst_t *spi, const uint16_t *src, size_t len); @@ -291,11 +333,24 @@ int spi_write16_blocking(spi_inst_t *spi, const uint16_t *src, size_t len); * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 * \param repeated_tx_data Buffer of data to write * \param dst Buffer for read data - * \param len Length of buffer \p dst in halfwords - * \return Number of bytes written/read + * \param len Length of buffer \p dst in halfwords + * \return Number of halfwords written/read */ int spi_read16_blocking(spi_inst_t *spi, uint16_t repeated_tx_data, uint16_t *dst, size_t len); +/*! \brief Return the DREQ to use for pacing transfers to/from a particular SPI instance + * \ingroup hardware_spi + * + * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 + * \param is_tx true for sending data to the SPI instance, false for receiving data from the SPI instance + */ +static inline uint spi_get_dreq(spi_inst_t *spi, bool is_tx) { + static_assert(DREQ_SPI0_RX == DREQ_SPI0_TX + 1, ""); + static_assert(DREQ_SPI1_RX == DREQ_SPI1_TX + 1, ""); + static_assert(DREQ_SPI1_TX == DREQ_SPI0_TX + 2, ""); + return DREQ_SPI0_TX + spi_get_index(spi) * 2 + !is_tx; +} + #ifdef __cplusplus } #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/include/hardware/sync.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/include/hardware/sync.h index f375ff8bd..8f91d5595 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/include/hardware/sync.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_sync/include/hardware/sync.h @@ -15,21 +15,41 @@ extern "C" { #endif - /** \file hardware/sync.h * \defgroup hardware_sync hardware_sync * - * Low level hardware spin-lock, barrier and processor event API + * Low level hardware spin locks, barrier and processor event APIs * - * Functions for synchronisation between core's, HW, etc + * Spin Locks + * ---------- * * The RP2040 provides 32 hardware spin locks, which can be used to manage mutually-exclusive access to shared software - * resources. + * and hardware resources. + * + * Generally each spin lock itself is a shared resource, + * i.e. the same hardware spin lock can be used by multiple higher level primitives (as long as the spin locks are neither held for long periods, nor + * held concurrently with other spin locks by the same core - which could lead to deadlock). A hardware spin lock that is exclusively owned can be used + * individually without more flexibility and without regard to other software. Note that no hardware spin lock may + * be acquired re-entrantly (i.e. hardware spin locks are not on their own safe for use by both thread code and IRQs) however the default spinlock related + * methods here (e.g. \ref spin_lock_blocking) always disable interrupts while the lock is held as use by IRQ handlers and user code is common/desirable, + * and spin locks are only expected to be held for brief periods. * - * \note spin locks 0-15 are currently reserved for fixed uses by the SDK - i.e. if you use them other - * functionality may break or not function optimally + * The SDK uses the following default spin lock assignments, classifying which spin locks are reserved for exclusive/special purposes + * vs those suitable for more general shared use: + * + * Number (ID) | Description + * :---------: | ----------- + * 0-13 | Currently reserved for exclusive use by the SDK and other libraries. If you use these spin locks, you risk breaking SDK or other library functionality. Each reserved spin lock used individually has its own PICO_SPINLOCK_ID so you can search for those. + * 14,15 | (\ref PICO_SPINLOCK_ID_OS1 and \ref PICO_SPINLOCK_ID_OS2). Currently reserved for exclusive use by an operating system (or other system level software) co-existing with the SDK. + * 16-23 | (\ref PICO_SPINLOCK_ID_STRIPED_FIRST - \ref PICO_SPINLOCK_ID_STRIPED_LAST). Spin locks from this range are assigned in a round-robin fashion via \ref next_striped_spin_lock_num(). These spin locks are shared, but assigning numbers from a range reduces the probability that two higher level locking primitives using _striped_ spin locks will actually be using the same spin lock. + * 24-31 | (\ref PICO_SPINLOCK_ID_CLAIM_FREE_FIRST - \ref PICO_SPINLOCK_ID_CLAIM_FREE_LAST). These are reserved for exclusive use and are allocated on a first come first served basis at runtime via \ref spin_lock_claim_unused() */ +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_SYNC, Enable/disable assertions in the HW sync module, type=bool, default=0, group=hardware_sync +#ifndef PARAM_ASSERTIONS_ENABLED_SYNC +#define PARAM_ASSERTIONS_ENABLED_SYNC 0 +#endif + /** \brief A spin lock identifier * \ingroup hardware_sync */ @@ -50,38 +70,46 @@ typedef volatile uint32_t spin_lock_t; #define PICO_SPINLOCK_ID_HARDWARE_CLAIM 11 #endif -// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_FIRST, Spinlock ID for striped first, min=16, max=31, default=16, group=hardware_sync +// PICO_CONFIG: PICO_SPINLOCK_ID_OS1, First Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=14, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_OS1 +#define PICO_SPINLOCK_ID_OS1 14 +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_OS2, Second Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=15, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_OS2 +#define PICO_SPINLOCK_ID_OS2 15 +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_FIRST, Lowest Spinlock ID in the 'striped' range, min=0, max=31, default=16, group=hardware_sync #ifndef PICO_SPINLOCK_ID_STRIPED_FIRST #define PICO_SPINLOCK_ID_STRIPED_FIRST 16 #endif -// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_LAST, Spinlock ID for striped last, min=16, max=31, default=23, group=hardware_sync +// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_LAST, Highest Spinlock ID in the 'striped' range, min=0, max=31, default=23, group=hardware_sync #ifndef PICO_SPINLOCK_ID_STRIPED_LAST #define PICO_SPINLOCK_ID_STRIPED_LAST 23 #endif -// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, Spinlock ID for claim free first, min=16, max=31, default=24, group=hardware_sync +// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, Lowest Spinlock ID in the 'claim free' range, min=0, max=31, default=24, group=hardware_sync #ifndef PICO_SPINLOCK_ID_CLAIM_FREE_FIRST #define PICO_SPINLOCK_ID_CLAIM_FREE_FIRST 24 #endif -// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_END, Spinlock ID for claim free end, min=16, max=31, default=31, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_END -#define PICO_SPINLOCK_ID_CLAIM_FREE_END 31 +#ifdef PICO_SPINLOCK_ID_CLAIM_FREE_END +#warning PICO_SPINLOCK_ID_CLAIM_FREE_END has been renamed to PICO_SPINLOCK_ID_CLAIM_FREE_LAST #endif -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_SYNC, Enable/disable assertions in the HW sync module, type=bool, default=0, group=hardware_sync -#ifndef PARAM_ASSERTIONS_ENABLED_SYNC -#define PARAM_ASSERTIONS_ENABLED_SYNC 0 +// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_LAST, Highest Spinlock ID in the 'claim free' range, min=0, max=31, default=31, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_LAST +#define PICO_SPINLOCK_ID_CLAIM_FREE_LAST 31 #endif - /*! \brief Insert a SEV instruction in to the code path. * \ingroup hardware_sync * The SEV (send event) instruction sends an event to both cores. */ -inline static void __sev() { +__force_inline static void __sev(void) { __asm volatile ("sev"); } @@ -91,7 +119,7 @@ inline static void __sev() { * The WFE (wait for event) instruction waits until one of a number of * events occurs, including events signalled by the SEV instruction on either core. */ -inline static void __wfe() { +__force_inline static void __wfe(void) { __asm volatile ("wfe"); } @@ -100,7 +128,7 @@ inline static void __wfe() { * * The WFI (wait for interrupt) instruction waits for a interrupt to wake up the core. */ -inline static void __wfi() { +__force_inline static void __wfi(void) { __asm volatile ("wfi"); } @@ -110,8 +138,19 @@ inline static void __wfi() { * The DMB (data memory barrier) acts as a memory barrier, all memory accesses prior to this * instruction will be observed before any explicit access after the instruction. */ -inline static void __dmb() { - __asm volatile ("dmb"); +__force_inline static void __dmb(void) { + __asm volatile ("dmb" : : : "memory"); +} + +/*! \brief Insert a DSB instruction in to the code path. + * \ingroup hardware_sync + * + * The DSB (data synchronization barrier) acts as a special kind of data + * memory barrier (DMB). The DSB operation completes when all explicit memory + * accesses before this instruction complete. + */ +__force_inline static void __dsb(void) { + __asm volatile ("dsb" : : : "memory"); } /*! \brief Insert a ISB instruction in to the code path. @@ -121,14 +160,14 @@ inline static void __dmb() { * so that all instructions following the ISB are fetched from cache or memory again, after * the ISB instruction has been completed. */ -inline static void __isb() { +__force_inline static void __isb(void) { __asm volatile ("isb"); } /*! \brief Acquire a memory fence * \ingroup hardware_sync */ -inline static void __mem_fence_acquire() { +__force_inline static void __mem_fence_acquire(void) { // the original code below makes it hard for us to be included from C++ via a header // which itself is in an extern "C", so just use __dmb instead, which is what // is required on Cortex M0+ @@ -144,7 +183,7 @@ inline static void __mem_fence_acquire() { * \ingroup hardware_sync * */ -inline static void __mem_fence_release() { +__force_inline static void __mem_fence_release(void) { // the original code below makes it hard for us to be included from C++ via a header // which itself is in an extern "C", so just use __dmb instead, which is what // is required on Cortex M0+ @@ -161,7 +200,7 @@ inline static void __mem_fence_release() { * * \return The prior interrupt enable status for restoration later via restore_interrupts() */ -inline static uint32_t save_and_disable_interrupts() { +__force_inline static uint32_t save_and_disable_interrupts(void) { uint32_t status; __asm volatile ("mrs %0, PRIMASK" : "=r" (status)::); __asm volatile ("cpsid i"); @@ -173,7 +212,7 @@ inline static uint32_t save_and_disable_interrupts() { * * \param status Previous interrupt status from save_and_disable_interrupts() */ -inline static void restore_interrupts(uint32_t status) { +__force_inline static void restore_interrupts(uint32_t status) { __asm volatile ("msr PRIMASK,%0"::"r" (status) : ); } @@ -183,7 +222,8 @@ inline static void restore_interrupts(uint32_t status) { * \param lock_num Spinlock ID * \return The spinlock instance */ -inline static spin_lock_t *spin_lock_instance(uint lock_num) { +__force_inline static spin_lock_t *spin_lock_instance(uint lock_num) { + invalid_params_if(SYNC, lock_num >= NUM_SPIN_LOCKS); return (spin_lock_t *) (SIO_BASE + SIO_SPINLOCK0_OFFSET + lock_num * 4); } @@ -193,8 +233,11 @@ inline static spin_lock_t *spin_lock_instance(uint lock_num) { * \param lock The Spinlock instance * \return The Spinlock ID */ -inline static uint spin_lock_get_num(spin_lock_t *lock) { - return lock - (spin_lock_t *) (SIO_BASE + SIO_SPINLOCK0_OFFSET); +__force_inline static uint spin_lock_get_num(spin_lock_t *lock) { + invalid_params_if(SYNC, (uint) lock < SIO_BASE + SIO_SPINLOCK0_OFFSET || + (uint) lock >= NUM_SPIN_LOCKS * sizeof(spin_lock_t) + SIO_BASE + SIO_SPINLOCK0_OFFSET || + ((uint) lock - SIO_BASE + SIO_SPINLOCK0_OFFSET) % sizeof(spin_lock_t) != 0); + return (uint) (lock - (spin_lock_t *) (SIO_BASE + SIO_SPINLOCK0_OFFSET)); } /*! \brief Acquire a spin lock without disabling interrupts (hence unsafe) @@ -202,7 +245,7 @@ inline static uint spin_lock_get_num(spin_lock_t *lock) { * * \param lock Spinlock instance */ -inline static void spin_lock_unsafe_blocking(spin_lock_t *lock) { +__force_inline static void spin_lock_unsafe_blocking(spin_lock_t *lock) { // Note we don't do a wfe or anything, because by convention these spin_locks are VERY SHORT LIVED and NEVER BLOCK and run // with INTERRUPTS disabled (to ensure that)... therefore nothing on our core could be blocking us, so we just need to wait on another core // anyway which should be finished soon @@ -215,7 +258,7 @@ inline static void spin_lock_unsafe_blocking(spin_lock_t *lock) { * * \param lock Spinlock instance */ -inline static void spin_unlock_unsafe(spin_lock_t *lock) { +__force_inline static void spin_unlock_unsafe(spin_lock_t *lock) { __mem_fence_release(); *lock = 0; } @@ -228,7 +271,7 @@ inline static void spin_unlock_unsafe(spin_lock_t *lock) { * \param lock Spinlock instance * \return interrupt status to be used when unlocking, to restore to original state */ -inline static uint32_t spin_lock_blocking(spin_lock_t *lock) { +__force_inline static uint32_t spin_lock_blocking(spin_lock_t *lock) { uint32_t save = save_and_disable_interrupts(); spin_lock_unsafe_blocking(lock); return save; @@ -239,9 +282,9 @@ inline static uint32_t spin_lock_blocking(spin_lock_t *lock) { * * \param lock Spinlock instance */ -inline static bool is_spin_locked(const spin_lock_t *lock) { +inline static bool is_spin_locked(spin_lock_t *lock) { check_hw_size(spin_lock_t, 4); - uint32_t lock_num = lock - spin_lock_instance(0); + uint lock_num = spin_lock_get_num(lock); return 0 != (*(io_ro_32 *) (SIO_BASE + SIO_SPINLOCK_ST_OFFSET) & (1u << lock_num)); } @@ -256,7 +299,7 @@ inline static bool is_spin_locked(const spin_lock_t *lock) { * * \sa spin_lock_blocking() */ -inline static void spin_unlock(spin_lock_t *lock, uint32_t saved_irq) { +__force_inline static void spin_unlock(spin_lock_t *lock, uint32_t saved_irq) { spin_unlock_unsafe(lock); restore_interrupts(saved_irq); } @@ -266,7 +309,7 @@ inline static void spin_unlock(spin_lock_t *lock, uint32_t saved_irq) { * * \return The core number the call was made from */ -static inline uint get_core_num() { +__force_inline static uint get_core_num(void) { return (*(uint32_t *) (SIO_BASE + SIO_CPUID_OFFSET)); } @@ -285,8 +328,22 @@ spin_lock_t *spin_lock_init(uint lock_num); */ void spin_locks_reset(void); -// this number is not claimed -uint next_striped_spin_lock_num(); +/*! \brief Return a spin lock number from the _striped_ range + * \ingroup hardware_sync + * + * Returns a spin lock number in the range PICO_SPINLOCK_ID_STRIPED_FIRST to PICO_SPINLOCK_ID_STRIPED_LAST + * in a round robin fashion. This does not grant the caller exclusive access to the spin lock, so the caller + * must: + * + * -# Abide (with other callers) by the contract of only holding this spin lock briefly (and with IRQs disabled - the default via \ref spin_lock_blocking()), + * and not whilst holding other spin locks. + * -# Be OK with any contention caused by the - brief due to the above requirement - contention with other possible users of the spin lock. + * + * \return lock_num a spin lock number the caller may use (non exclusively) + * \see PICO_SPINLOCK_ID_STRIPED_FIRST + * \see PICO_SPINLOCK_ID_STRIPED_LAST + */ +uint next_striped_spin_lock_num(void); /*! \brief Mark a spin lock as used * \ingroup hardware_sync @@ -327,6 +384,16 @@ void spin_lock_unclaim(uint lock_num); */ int spin_lock_claim_unused(bool required); +/*! \brief Determine if a spin lock is claimed + * \ingroup hardware_sync + * + * \param lock_num the spin lock number + * \return true if claimed, false otherwise + * \see spin_lock_claim + * \see spin_lock_claim_mask + */ +bool spin_lock_is_claimed(uint lock_num); + #define remove_volatile_cast(t, x) ({__mem_fence_acquire(); (t)(x); }) #ifdef __cplusplus diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/include/hardware/timer.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/include/hardware/timer.h index 1815a2780..1799cd00e 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/include/hardware/timer.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_timer/include/hardware/timer.h @@ -50,7 +50,7 @@ extern "C" { #define PARAM_ASSERTIONS_ENABLED_TIMER 0 #endif -static inline void check_hardware_alarm_num_param(uint alarm_num) { +static inline void check_hardware_alarm_num_param(__unused uint alarm_num) { invalid_params_if(TIMER, alarm_num >= NUM_TIMERS); } @@ -62,7 +62,7 @@ static inline void check_hardware_alarm_num_param(uint alarm_num) { * * \return the 32 bit timestamp */ -static inline uint32_t time_us_32() { +static inline uint32_t time_us_32(void) { return timer_hw->timerawl; } @@ -75,22 +75,29 @@ static inline uint32_t time_us_32() { * * \return the 64 bit timestamp */ -uint64_t time_us_64(); +uint64_t time_us_64(void); /*! \brief Busy wait wasting cycles for the given (32 bit) number of microseconds * \ingroup hardware_timer * - * \param delay_us delay amount + * \param delay_us delay amount in microseconds */ void busy_wait_us_32(uint32_t delay_us); /*! \brief Busy wait wasting cycles for the given (64 bit) number of microseconds * \ingroup hardware_timer * - * \param delay_us delay amount + * \param delay_us delay amount in microseconds */ void busy_wait_us(uint64_t delay_us); +/*! \brief Busy wait wasting cycles for the given number of milliseconds + * \ingroup hardware_timer + * + * \param delay_ms delay amount in milliseconds + */ +void busy_wait_ms(uint32_t delay_ms); + /*! \brief Busy wait wasting cycles until after the specified timestamp * \ingroup hardware_timer * @@ -106,7 +113,7 @@ void busy_wait_until(absolute_time_t t); */ static inline bool time_reached(absolute_time_t t) { uint64_t target = to_us_since_boot(t); - uint32_t hi_target = target >> 32u; + uint32_t hi_target = (uint32_t)(target >> 32u); uint32_t hi = timer_hw->timerawh; return (hi >= hi_target && (timer_hw->timerawl >= (uint32_t) target || hi != hi_target)); } @@ -115,7 +122,7 @@ static inline bool time_reached(absolute_time_t t) { * \ingroup hardware_timer * * \param alarm_num the hardware alarm number - * \sa hardware_alarm_set_callback + * \sa hardware_alarm_set_callback() */ typedef void (*hardware_alarm_callback_t)(uint alarm_num); @@ -137,6 +144,15 @@ void hardware_alarm_claim(uint alarm_num); */ void hardware_alarm_unclaim(uint alarm_num); +/*! \brief Determine if a hardware alarm has been claimed + * \ingroup hardware_timer + * + * \param alarm_num the hardware alarm number + * \return true if claimed, false otherwise + * \see hardware_alarm_claim + */ +bool hardware_alarm_is_claimed(uint alarm_num); + /*! \brief Enable/Disable a callback for a hardware timer on this core * \ingroup hardware_timer * @@ -151,12 +167,13 @@ void hardware_alarm_unclaim(uint alarm_num); * \param alarm_num the hardware alarm number * \param callback the callback to install, or NULL to unset * - * \sa hardware_alarm_set_target + * \sa hardware_alarm_set_target() */ void hardware_alarm_set_callback(uint alarm_num, hardware_alarm_callback_t callback); /** * \brief Set the current target for the specified hardware alarm + * \ingroup hardware_timer * * This will replace any existing target * @@ -168,6 +185,7 @@ bool hardware_alarm_set_target(uint alarm_num, absolute_time_t t); /** * \brief Cancel an existing target (if any) for a given hardware_alarm + * \ingroup hardware_timer * * @param alarm_num */ diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h index 58c0e800b..a274207ee 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_uart/include/hardware/uart.h @@ -9,6 +9,7 @@ #include "pico.h" #include "hardware/structs/uart.h" +#include "hardware/regs/dreq.h" // PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_UART, Enable/disable assertions in the UART module, type=bool, default=0, group=hardware_uart #ifndef PARAM_ASSERTIONS_ENABLED_UART @@ -29,26 +30,15 @@ extern "C" { #define PICO_UART_DEFAULT_CRLF 0 #endif -// PICO_CONFIG: PICO_DEFAULT_UART, Define the default UART used for printf etc, default=0, group=hardware_uart -#ifndef PICO_DEFAULT_UART -#define PICO_DEFAULT_UART 0 ///< Default UART instance -#endif +// PICO_CONFIG: PICO_DEFAULT_UART, Define the default UART used for printf etc, min=0, max=1, group=hardware_uart +// PICO_CONFIG: PICO_DEFAULT_UART_TX_PIN, Define the default UART TX pin, min=0, max=29, group=hardware_uart +// PICO_CONFIG: PICO_DEFAULT_UART_RX_PIN, Define the default UART RX pin, min=0, max=29, group=hardware_uart // PICO_CONFIG: PICO_DEFAULT_UART_BAUD_RATE, Define the default UART baudrate, max=921600, default=115200, group=hardware_uart #ifndef PICO_DEFAULT_UART_BAUD_RATE #define PICO_DEFAULT_UART_BAUD_RATE 115200 ///< Default baud rate #endif -// PICO_CONFIG: PICO_DEFAULT_UART_TX_PIN, Define the default UART TX pin, min=0, max=29, default=0, group=hardware_uart -#ifndef PICO_DEFAULT_UART_TX_PIN -#define PICO_DEFAULT_UART_TX_PIN 0 ///< Default TX pin -#endif - -// PICO_CONFIG: PICO_DEFAULT_UART_RX_PIN, Define the default UART RX pin, min=0, max=29, default=1, group=hardware_uart -#ifndef PICO_DEFAULT_UART_RX_PIN -#define PICO_DEFAULT_UART_RX_PIN 1 ///< Default RX pin -#endif - /** \file hardware/uart.h * \defgroup hardware_uart hardware_uart * @@ -93,11 +83,13 @@ typedef struct uart_inst uart_inst_t; /** @} */ -#ifndef PICO_DEFAULT_UART_INSTANCE +#if !defined(PICO_DEFAULT_UART_INSTANCE) && defined(PICO_DEFAULT_UART) #define PICO_DEFAULT_UART_INSTANCE (__CONCAT(uart,PICO_DEFAULT_UART)) #endif +#ifdef PICO_DEFAULT_UART_INSTANCE #define uart_default PICO_DEFAULT_UART_INSTANCE +#endif /*! \brief Convert UART instance to hardware instance number * \ingroup hardware_uart @@ -110,6 +102,12 @@ static inline uint uart_get_index(uart_inst_t *uart) { return uart == uart1 ? 1 : 0; } +static inline uart_inst_t *uart_get_instance(uint instance) { + static_assert(NUM_UARTS == 2, ""); + invalid_params_if(UART, instance >= NUM_UARTS); + return instance ? uart1 : uart0; +} + static inline uart_hw_t *uart_get_hw(uart_inst_t *uart) { uart_get_index(uart); // check it is a hw uart return (uart_hw_t *)uart; @@ -172,7 +170,7 @@ uint uart_set_baudrate(uart_inst_t *uart, uint baudrate); */ static inline void uart_set_hw_flow(uart_inst_t *uart, bool cts, bool rts) { hw_write_masked(&uart_get_hw(uart)->cr, - (!!cts << UART_UARTCR_CTSEN_LSB) | (!!rts << UART_UARTCR_RTSEN_LSB), + (bool_to_bit(cts) << UART_UARTCR_CTSEN_LSB) | (bool_to_bit(rts) << UART_UARTCR_RTSEN_LSB), UART_UARTCR_RTSEN_BITS | UART_UARTCR_CTSEN_BITS); } @@ -191,10 +189,10 @@ static inline void uart_set_format(uart_inst_t *uart, uint data_bits, uint stop_ invalid_params_if(UART, stop_bits != 1 && stop_bits != 2); invalid_params_if(UART, parity != UART_PARITY_NONE && parity != UART_PARITY_EVEN && parity != UART_PARITY_ODD); hw_write_masked(&uart_get_hw(uart)->lcr_h, - ((data_bits - 5) << UART_UARTLCR_H_WLEN_LSB) | - ((stop_bits - 1) << UART_UARTLCR_H_STP2_LSB) | - ((parity != UART_PARITY_NONE) << UART_UARTLCR_H_PEN_LSB) | - ((parity == UART_PARITY_EVEN) << UART_UARTLCR_H_EPS_LSB), + ((data_bits - 5u) << UART_UARTLCR_H_WLEN_LSB) | + ((stop_bits - 1u) << UART_UARTLCR_H_STP2_LSB) | + (bool_to_bit(parity != UART_PARITY_NONE) << UART_UARTLCR_H_PEN_LSB) | + (bool_to_bit(parity == UART_PARITY_EVEN) << UART_UARTLCR_H_EPS_LSB), UART_UARTLCR_H_WLEN_BITS | UART_UARTLCR_H_STP2_BITS | UART_UARTLCR_H_PEN_BITS | @@ -208,13 +206,17 @@ static inline void uart_set_format(uart_inst_t *uart, uint data_bits, uint stop_ * this function. * * \param uart UART instance. \ref uart0 or \ref uart1 - * \param rx_has_data If true an interrupt will be fired when the RX FIFO contain data. + * \param rx_has_data If true an interrupt will be fired when the RX FIFO contains data. * \param tx_needs_data If true an interrupt will be fired when the TX FIFO needs data. */ static inline void uart_set_irq_enables(uart_inst_t *uart, bool rx_has_data, bool tx_needs_data) { - uart_get_hw(uart)->imsc = (!!tx_needs_data << UART_UARTIMSC_TXIM_LSB) | - (!!rx_has_data << UART_UARTIMSC_RXIM_LSB) | - (1 << UART_UARTIMSC_RTIM_LSB); + // Both UARTRXINTR (RX) and UARTRTINTR (RX timeout) interrupts are + // required for rx_has_data. RX asserts when >=4 characters are in the RX + // FIFO (for RXIFLSEL=0). RT asserts when there are >=1 characters and no + // more have been received for 32 bit periods. + uart_get_hw(uart)->imsc = (bool_to_bit(tx_needs_data) << UART_UARTIMSC_TXIM_LSB) | + (bool_to_bit(rx_has_data) << UART_UARTIMSC_RXIM_LSB) | + (bool_to_bit(rx_has_data) << UART_UARTIMSC_RTIM_LSB); if (rx_has_data) { // Set minimum threshold hw_write_masked(&uart_get_hw(uart)->ifls, 0 << UART_UARTIFLS_RXIFLSEL_LSB, @@ -245,7 +247,7 @@ static inline bool uart_is_enabled(uart_inst_t *uart) { */ static inline void uart_set_fifo_enabled(uart_inst_t *uart, bool enabled) { hw_write_masked(&uart_get_hw(uart)->lcr_h, - (!!enabled << UART_UARTLCR_H_FEN_LSB), + (bool_to_bit(enabled) << UART_UARTLCR_H_FEN_LSB), UART_UARTLCR_H_FEN_BITS); } @@ -315,7 +317,7 @@ static inline void uart_read_blocking(uart_inst_t *uart, uint8_t *dst, size_t le for (size_t i = 0; i < len; ++i) { while (!uart_is_readable(uart)) tight_loop_contents(); - *dst++ = uart_get_hw(uart)->dr; + *dst++ = (uint8_t) uart_get_hw(uart)->dr; } } @@ -325,7 +327,7 @@ static inline void uart_read_blocking(uart_inst_t *uart, uint8_t *dst, size_t le /*! \brief Write single character to UART for transmission. * \ingroup hardware_uart * - * This function will block until all the character has been sent + * This function will block until the entire character has been sent * * \param uart UART instance. \ref uart0 or \ref uart1 * \param c The character to send @@ -411,11 +413,15 @@ static inline void uart_set_break(uart_inst_t *uart, bool en) { */ void uart_set_translate_crlf(uart_inst_t *uart, bool translate); -/*! \brief Wait for the default UART'S TX fifo to be drained +/*! \brief Wait for the default UART's TX FIFO to be drained * \ingroup hardware_uart */ -static inline void uart_default_tx_wait_blocking() { +static inline void uart_default_tx_wait_blocking(void) { +#ifdef uart_default uart_tx_wait_blocking(uart_default); +#else + assert(false); +#endif } /*! \brief Wait for up to a certain number of microseconds for the RX FIFO to be non empty @@ -427,6 +433,19 @@ static inline void uart_default_tx_wait_blocking() { */ bool uart_is_readable_within_us(uart_inst_t *uart, uint32_t us); +/*! \brief Return the DREQ to use for pacing transfers to/from a particular UART instance + * \ingroup hardware_uart + * + * \param uart UART instance. \ref uart0 or \ref uart1 + * \param is_tx true for sending data to the UART instance, false for receiving data from the UART instance + */ +static inline uint uart_get_dreq(uart_inst_t *uart, bool is_tx) { + static_assert(DREQ_UART0_RX == DREQ_UART0_TX + 1, ""); + static_assert(DREQ_UART1_RX == DREQ_UART1_TX + 1, ""); + static_assert(DREQ_UART1_TX == DREQ_UART0_TX + 2, ""); + return DREQ_UART0_TX + uart_get_index(uart) * 2 + !is_tx; +} + #ifdef __cplusplus } #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_watchdog/include/hardware/watchdog.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_watchdog/include/hardware/watchdog.h index ae5ccdc86..747838be8 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_watchdog/include/hardware/watchdog.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_watchdog/include/hardware/watchdog.h @@ -8,6 +8,7 @@ #define _HARDWARE_WATCHDOG_H #include "pico.h" +#include "hardware/structs/watchdog.h" /** \file hardware/watchdog.h * \defgroup hardware_watchdog hardware_watchdog @@ -25,10 +26,14 @@ * \include hello_watchdog.c */ +#ifdef __cplusplus +extern "C" { +#endif + /*! \brief Define actions to perform at watchdog timeout * \ingroup hardware_watchdog * - * \note If \ref watchdog_start_tick value does not give a 1MHz clock to the watchdog system, then the \ref delay_ms + * \note If \ref watchdog_start_tick value does not give a 1MHz clock to the watchdog system, then the \p delay_ms * parameter will not be in microseconds. See the datasheet for more details. * * By default the SDK assumes a 12MHz XOSC and sets the \ref watchdog_start_tick appropriately. @@ -57,11 +62,16 @@ void watchdog_update(void); * \brief Enable the watchdog * \ingroup hardware_watchdog * - * \note If \ref watchdog_start_tick value does not give a 1MHz clock to the watchdog system, then the \ref delay_ms + * \note If \ref watchdog_start_tick value does not give a 1MHz clock to the watchdog system, then the \p delay_ms * parameter will not be in microseconds. See the datasheet for more details. * * By default the SDK assumes a 12MHz XOSC and sets the \ref watchdog_start_tick appropriately. * + * This method sets a marker in the watchdog scratch register 4 that is checked by \ref watchdog_enable_caused_reboot. + * If the device is subsequently reset via a call to watchdog_reboot (including for example by dragging a UF2 + * onto the RPI-RP2), then this value will be cleared, and so \ref watchdog_enable_caused_reboot will + * return false. + * * \param delay_ms Number of milliseconds before watchdog will reboot without watchdog_update being called. Maximum of 0x7fffff, which is approximately 8.3 seconds * \param pause_on_debug If the watchdog should be paused when the debugger is stepping through code */ @@ -71,11 +81,30 @@ void watchdog_enable(uint32_t delay_ms, bool pause_on_debug); * \brief Did the watchdog cause the last reboot? * \ingroup hardware_watchdog * - * @return true if the watchdog timer or a watchdog force caused the last reboot - * @return false there has been no watchdog reboot since run has been + * @return true If the watchdog timer or a watchdog force caused the last reboot + * @return false If there has been no watchdog reboot since the last power on reset. A power on reset is typically caused by a power cycle or the run pin (reset button) being toggled. */ bool watchdog_caused_reboot(void); +/** + * \brief Did watchdog_enable cause the last reboot? + * \ingroup hardware_watchdog + * + * Perform additional checking along with \ref watchdog_caused_reboot to determine if a watchdog timeout initiated by + * \ref watchdog_enable caused the last reboot. + * + * This method checks for a special value in watchdog scratch register 4 placed there by \ref watchdog_enable. + * This would not be present if a watchdog reset is initiated by \ref watchdog_reboot or by the RP2040 bootrom + * (e.g. dragging a UF2 onto the RPI-RP2 drive). + * + * @return true If the watchdog timer or a watchdog force caused (see \reg watchdog_caused_reboot) the last reboot + * and the watchdog reboot happened after \ref watchdog_enable was called + * @return false If there has been no watchdog reboot since the last power on reset, or the watchdog reboot was not caused + * by a watchdog timeout after \ref watchdog_enable was called. + * A power on reset is typically caused by a power cycle or the run pin (reset button) being toggled. + */ +bool watchdog_enable_caused_reboot(void); + /** * @brief Returns the number of microseconds before the watchdog will reboot the chip. * \ingroup hardware_watchdog @@ -84,4 +113,8 @@ bool watchdog_caused_reboot(void); */ uint32_t watchdog_get_count(void); +#ifdef __cplusplus +} +#endif + #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_xosc/include/hardware/xosc.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_xosc/include/hardware/xosc.h index 0aa0842db..a5e33b037 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_xosc/include/hardware/xosc.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_xosc/include/hardware/xosc.h @@ -10,6 +10,15 @@ #include "pico.h" #include "hardware/structs/xosc.h" + +// Allow lengthening startup delay to accommodate slow-starting oscillators + +// PICO_CONFIG: PICO_XOSC_STARTUP_DELAY_MULTIPLIER, Multiplier to lengthen xosc startup delay to accommodate slow-starting oscillators, type=int, min=1, default=1, group=hardware_xosc +#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER +#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 1 +#endif + + #ifdef __cplusplus extern "C" { #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom.h index 1aa12973e..e55789315 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_bootrom/include/pico/bootrom.h @@ -12,20 +12,75 @@ /** \file bootrom.h * \defgroup pico_bootrom pico_bootrom * Access to functions and data in the RP2040 bootrom + * + * This header may be included by assembly code */ +// ROM FUNCTIONS + +#define ROM_FUNC_POPCOUNT32 ROM_TABLE_CODE('P', '3') +#define ROM_FUNC_REVERSE32 ROM_TABLE_CODE('R', '3') +#define ROM_FUNC_CLZ32 ROM_TABLE_CODE('L', '3') +#define ROM_FUNC_CTZ32 ROM_TABLE_CODE('T', '3') +#define ROM_FUNC_MEMSET ROM_TABLE_CODE('M', 'S') +#define ROM_FUNC_MEMSET4 ROM_TABLE_CODE('S', '4') +#define ROM_FUNC_MEMCPY ROM_TABLE_CODE('M', 'C') +#define ROM_FUNC_MEMCPY44 ROM_TABLE_CODE('C', '4') +#define ROM_FUNC_RESET_USB_BOOT ROM_TABLE_CODE('U', 'B') +#define ROM_FUNC_CONNECT_INTERNAL_FLASH ROM_TABLE_CODE('I', 'F') +#define ROM_FUNC_FLASH_EXIT_XIP ROM_TABLE_CODE('E', 'X') +#define ROM_FUNC_FLASH_RANGE_ERASE ROM_TABLE_CODE('R', 'E') +#define ROM_FUNC_FLASH_RANGE_PROGRAM ROM_TABLE_CODE('R', 'P') +#define ROM_FUNC_FLASH_FLUSH_CACHE ROM_TABLE_CODE('F', 'C') +#define ROM_FUNC_FLASH_ENTER_CMD_XIP ROM_TABLE_CODE('C', 'X') /*! \brief Return a bootrom lookup code based on two ASCII characters * \ingroup pico_bootrom * * These codes are uses to lookup data or function addresses in the bootrom - * + * * \param c1 the first character * \param c2 the second character * \return the 'code' to use in rom_func_lookup() or rom_data_lookup() */ -static inline uint32_t rom_table_code(char c1, char c2) { - return (c2 << 8u) | c1; +#define ROM_TABLE_CODE(c1, c2) ((c1) | ((c2) << 8)) + +#ifndef __ASSEMBLER__ + +// ROM FUNCTION SIGNATURES + +typedef uint32_t (*rom_popcount32_fn)(uint32_t); +typedef uint32_t (*rom_reverse32_fn)(uint32_t); +typedef uint32_t (*rom_clz32_fn)(uint32_t); +typedef uint32_t (*rom_ctz32_fn)(uint32_t); +typedef uint8_t *(*rom_memset_fn)(uint8_t *, uint8_t, uint32_t); +typedef uint32_t *(*rom_memset4_fn)(uint32_t *, uint8_t, uint32_t); +typedef uint32_t *(*rom_memcpy_fn)(uint8_t *, const uint8_t *, uint32_t); +typedef uint32_t *(*rom_memcpy44_fn)(uint32_t *, const uint32_t *, uint32_t); +typedef void __attribute__((noreturn)) (*rom_reset_usb_boot_fn)(uint32_t, uint32_t); +typedef rom_reset_usb_boot_fn reset_usb_boot_fn; // kept for backwards compatibility +typedef void (*rom_connect_internal_flash_fn)(void); +typedef void (*rom_flash_exit_xip_fn)(void); +typedef void (*rom_flash_range_erase_fn)(uint32_t, size_t, uint32_t, uint8_t); +typedef void (*rom_flash_range_program_fn)(uint32_t, const uint8_t*, size_t); +typedef void (*rom_flash_flush_cache_fn)(void); +typedef void (*rom_flash_enter_cmd_xip_fn)(void); + +#ifdef __cplusplus +extern "C" { +#endif + +/*! \brief Return a bootrom lookup code based on two ASCII characters + * \ingroup pico_bootrom + * + * These codes are uses to lookup data or function addresses in the bootrom + * + * \param c1 the first character + * \param c2 the second character + * \return the 'code' to use in rom_func_lookup() or rom_data_lookup() + */ +static inline uint32_t rom_table_code(uint8_t c1, uint8_t c2) { + return ROM_TABLE_CODE((uint32_t) c1, (uint32_t) c2); } /*! @@ -57,7 +112,24 @@ void *rom_data_lookup(uint32_t code); */ bool rom_funcs_lookup(uint32_t *table, unsigned int count); -typedef void __attribute__((noreturn)) (*reset_usb_boot_fn)(uint32_t, uint32_t); +// Bootrom function: rom_table_lookup +// Returns the 32 bit pointer into the ROM if found or NULL otherwise. +typedef void *(*rom_table_lookup_fn)(uint16_t *table, uint32_t code); + +// Convert a 16 bit pointer stored at the given rom address into a 32 bit pointer +#define rom_hword_as_ptr(rom_address) (void *)(uintptr_t)(*(uint16_t *)rom_address) + +/*! + * \brief Lookup a bootrom function by code. This method is forceably inlined into the caller for FLASH/RAM sensitive code usage + * \ingroup pico_bootrom + * \param code the code + * \return a pointer to the function, or NULL if the code does not match any bootrom function + */ +static __force_inline void *rom_func_lookup_inline(uint32_t code) { + rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) rom_hword_as_ptr(0x18); + uint16_t *func_table = (uint16_t *) rom_hword_as_ptr(0x14); + return rom_table_lookup(func_table, code); +} /*! * \brief Reboot the device into BOOTSEL mode @@ -78,8 +150,13 @@ typedef void __attribute__((noreturn)) (*reset_usb_boot_fn)(uint32_t, uint32_t); */ static inline void __attribute__((noreturn)) reset_usb_boot(uint32_t usb_activity_gpio_pin_mask, uint32_t disable_interface_mask) { - reset_usb_boot_fn func = (reset_usb_boot_fn) rom_func_lookup(rom_table_code('U', 'B')); + rom_reset_usb_boot_fn func = (rom_reset_usb_boot_fn) rom_func_lookup(ROM_FUNC_RESET_USB_BOOT); func(usb_activity_gpio_pin_mask, disable_interface_mask); } +#ifdef __cplusplus +} +#endif + +#endif // !__ASSEMBLER__ #endif diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/include/pico/multicore.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/include/pico/multicore.h index bc0c64d21..6f12f412b 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/include/pico/multicore.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_multicore/include/pico/multicore.h @@ -9,6 +9,7 @@ #include "pico/types.h" #include "pico/sync.h" +#include "hardware/structs/sio.h" #ifdef __cplusplus extern "C" { @@ -16,14 +17,14 @@ extern "C" { /** \file multicore.h * \defgroup pico_multicore pico_multicore - * Adds support for running code on the second processor core (core1) + * Adds support for running code on the second processor core (core 1) * * \subsection multicore_example Example * \addtogroup pico_multicore * \include multicore.c */ -// PICO_CONFIG: PICO_CORE1_STACK_SIZE, Stack size for core 1, min=0x100, max=0x10000, default=PICO_STACK_SIZE/0x800, group=pico_multicore +// PICO_CONFIG: PICO_CORE1_STACK_SIZE, Stack size for core 1, min=0x100, max=0x10000, default=PICO_STACK_SIZE (0x800), group=pico_multicore #ifndef PICO_CORE1_STACK_SIZE #ifdef PICO_STACK_SIZE #define PICO_CORE1_STACK_SIZE PICO_STACK_SIZE @@ -32,140 +33,276 @@ extern "C" { #endif #endif -/*! \brief Reset Core 1 +/*! \brief Reset core 1 * \ingroup pico_multicore * + * This function can be used to reset core 1 into its initial state (ready for launching code against via \ref multicore_launch_core1 and similar methods) + * + * \note this function should only be called from core 0 */ -void multicore_reset_core1(); +void multicore_reset_core1(void); /*! \brief Run code on core 1 * \ingroup pico_multicore * - * Reset core1 and enter the given function on core 1 using the default core 1 stack (below core 0 stack) + * Wake up (a previously reset) core 1 and enter the given function on core 1 using the default core 1 stack (below core 0 stack). + * + * core 1 must previously have been reset either as a result of a system reset or by calling \ref multicore_reset_core1 * - * \param entry Function entry point, this function should not return. + * core 1 will use the same vector table as core 0 + * + * \param entry Function entry point + * \see multicore_reset_core1 */ void multicore_launch_core1(void (*entry)(void)); /*! \brief Launch code on core 1 with stack * \ingroup pico_multicore * - * Reset core1 and enter the given function on core 1 using the passed stack for core 1 - */ -void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes); - -/*! \brief Send core 1 to sleep. - * \ingroup pico_multicore + * Wake up (a previously reset) core 1 and enter the given function on core 1 using the passed stack for core 1 + * + * core 1 must previously have been reset either as a result of a system reset or by calling \ref multicore_reset_core1 * + * core 1 will use the same vector table as core 0 + * + * \param entry Function entry point + * \param stack_bottom The bottom (lowest address) of the stack + * \param stack_size_bytes The size of the stack in bytes (must be a multiple of 4) + * \see multicore_reset_core1 */ -void multicore_sleep_core1(); +void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes); /*! \brief Launch code on core 1 with no stack protection * \ingroup pico_multicore * - * Reset core1 and enter the given function using the passed sp as the initial stack pointer. - * This is a bare bones functions that does not provide a stack guard even if USE_STACK_GUARDS is defined + * Wake up (a previously reset) core 1 and start it executing with a specific entry point, stack pointer + * and vector table. + * + * This is a low level function that does not provide a stack guard even if USE_STACK_GUARDS is defined + * + * core 1 must previously have been reset either as a result of a system reset or by calling \ref multicore_reset_core1 * + * \param entry Function entry point + * \param sp Pointer to the top of the core 1 stack + * \param vector_table address of the vector table to use for core 1 + * \see multicore_reset_core1 */ void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table); /*! * \defgroup multicore_fifo fifo * \ingroup pico_multicore - * \brief Functions for inter-core FIFO + * \brief Functions for the inter-core FIFOs * * The RP2040 contains two FIFOs for passing data, messages or ordered events between the two cores. Each FIFO is 32 bits * wide, and 8 entries deep. One of the FIFOs can only be written by core 0, and read by core 1. The other can only be written * by core 1, and read by core 0. + * + * \note The inter-core FIFOs are a very precious resource and are frequently used for SDK functionality (e.g. during + * core 1 launch or by the \ref multicore_lockout functions). Additionally they are often required for the exclusive use + * of an RTOS (e.g. FreeRTOS SMP). For these reasons it is suggested that you do not use the FIFO for your own purposes + * unless none of the above concerns apply; the majority of cases for transferring data between cores can be eqaully + * well handled by using a \ref queue */ - -/*! \brief Check the read FIFO to see if there is data waiting +/*! \brief Check the read FIFO to see if there is data available (sent by the other core) * \ingroup multicore_fifo * + * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs + * * \return true if the FIFO has data in it, false otherwise */ -static inline bool multicore_fifo_rvalid() { +static inline bool multicore_fifo_rvalid(void) { return !!(sio_hw->fifo_st & SIO_FIFO_ST_VLD_BITS); } -/*! \brief Check the FIFO to see if the write FIFO is full +/*! \brief Check the write FIFO to see if it has space for more data * \ingroup multicore_fifo * - * @return true if the FIFO is full, false otherwise + * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs + * + * @return true if the FIFO has room for more data, false otherwise */ -static inline bool multicore_fifo_wready() { +static inline bool multicore_fifo_wready(void) { return !!(sio_hw->fifo_st & SIO_FIFO_ST_RDY_BITS); } -/*! \brief Push data on to the FIFO. +/*! \brief Push data on to the write FIFO (data to the other core). * \ingroup multicore_fifo * * This function will block until there is space for the data to be sent. * Use multicore_fifo_wready() to check if it is possible to write to the * FIFO if you don't want to block. * + * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs + * * \param data A 32 bit value to push on to the FIFO */ void multicore_fifo_push_blocking(uint32_t data); +/*! \brief Push data on to the write FIFO (data to the other core) with timeout. + * \ingroup multicore_fifo + * + * This function will block until there is space for the data to be sent + * or the timeout is reached + * + * \param data A 32 bit value to push on to the FIFO + * \param timeout_us the timeout in microseconds + * \return true if the data was pushed, false if the timeout occurred before data could be pushed + */ bool multicore_fifo_push_timeout_us(uint32_t data, uint64_t timeout_us); -/*! \brief Pop data from the FIFO. +/*! \brief Pop data from the read FIFO (data from the other core). * \ingroup multicore_fifo * * This function will block until there is data ready to be read * Use multicore_fifo_rvalid() to check if data is ready to be read if you don't * want to block. * - * \return 32 bit unsigned data from the FIFO. + * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs + * + * \return 32 bit data from the read FIFO. */ -uint32_t multicore_fifo_pop_blocking(); +uint32_t multicore_fifo_pop_blocking(void); +/*! \brief Pop data from the read FIFO (data from the other core) with timeout. + * \ingroup multicore_fifo + * + * This function will block until there is data ready to be read or the timeout is reached + * + * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs + * + * \param timeout_us the timeout in microseconds + * \param out the location to store the popped data if available + * \return true if the data was popped and a value copied into `out`, false if the timeout occurred before data could be popped + */ bool multicore_fifo_pop_timeout_us(uint64_t timeout_us, uint32_t *out); -/*! \brief Flush any data in the outgoing FIFO +/*! \brief Discard any data in the read FIFO * \ingroup multicore_fifo * + * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs */ -static inline void multicore_fifo_drain() { +static inline void multicore_fifo_drain(void) { while (multicore_fifo_rvalid()) (void) sio_hw->fifo_rd; } /*! \brief Clear FIFO interrupt * \ingroup multicore_fifo + * + * Note that this only clears an interrupt that was caused by the ROE or WOF flags. + * To clear the VLD flag you need to use one of the 'pop' or 'drain' functions. + * + * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs + * + * \see multicore_fifo_get_status */ -static inline void multicore_fifo_clear_irq() { - // Write any value to clear any interrupts +static inline void multicore_fifo_clear_irq(void) { + // Write any value to clear the error flags sio_hw->fifo_st = 0xff; } -/*! \brief Get FIFO status +/*! \brief Get FIFO statuses * \ingroup multicore_fifo * - * \return The status as a bitfield + * \return The statuses as a bitfield * * Bit | Description * ----|------------ - * 3 | Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. - * 2 | Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. + * 3 | Sticky flag indicating the RX FIFO was read when empty (ROE). This read was ignored by the FIFO. + * 2 | Sticky flag indicating the TX FIFO was written when full (WOF). This write was ignored by the FIFO. * 1 | Value is 1 if this core’s TX FIFO is not full (i.e. if FIFO_WR is ready for more data) * 0 | Value is 1 if this core’s RX FIFO is not empty (i.e. if FIFO_RD is valid) + * + * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs + * */ -static inline int32_t multicore_fifo_get_status() { +static inline uint32_t multicore_fifo_get_status(void) { return sio_hw->fifo_st; } -// call this from the lockout victim thread -void multicore_lockout_victim_init(); +/*! + * \defgroup multicore_lockout lockout + * \ingroup pico_multicore + * \brief Functions to enable one core to force the other core to pause execution in a known state. + * + * Sometimes it is useful to enter a critical section on both cores at once. On a single + * core system a critical section can trivially be entered by disabling interrupts, however on a multi-core + * system that is not sufficient, and unless the other core is polling in some way, then it will need to be interrupted + * in order to cooperatively enter a blocked state. + * + * These "lockout" functions use the inter core FIFOs to cause an interrupt on one core from the other, and manage + * waiting for the other core to enter the "locked out" state. + * + * The usage is that the "victim" core ... i.e the core that can be "locked out" by the other core calls + * \ref multicore_lockout_victim_init to hook the FIFO interrupt. Note that either or both cores may do this. + * + * \note When "locked out" the victim core is paused (it is actually executing a tight loop with code in RAM) and has interrupts disabled. + * This makes the lockout functions suitable for use by code that wants to write to flash (at which point no code may be executing + * from flash) + * + * The core which wishes to lockout the other core calls \ref multicore_lockout_start_blocking or + * \ref multicore_lockout_start_timeout_us to interrupt the other "victim" core and wait for it to be in a + * "locked out" state. Once the lockout is no longer needed it calls \ref multicore_lockout_end_blocking or + * \ref multicore_lockout_end_timeout_us to release the lockout and wait for confirmation. + * + * \note Because multicore lockout uses the intercore FIFOs, the FIFOs cannot be used for any other purpose + */ + +/*! \brief Initialize the current core such that it can be a "victim" of lockout (i.e. forced to pause in a known state by the other core) + * \ingroup multicore_lockout + * + * This code hooks the intercore FIFO IRQ, and the FIFO may not be used for any other purpose after this. + */ +void multicore_lockout_victim_init(void); + +/*! \brief Request the other core to pause in a known state and wait for it to do so + * \ingroup multicore_lockout + * + * The other (victim) core must have previously executed \ref multicore_lockout_victim_init() + * + * \note multicore_lockout_start_ functions are not nestable, and must be paired with a call to a corresponding + * \ref multicore_lockout_end_blocking + */ +void multicore_lockout_start_blocking(void); -// start locking out the other core (it will be +/*! \brief Request the other core to pause in a known state and wait up to a time limit for it to do so + * \ingroup multicore_lockout + * + * The other core must have previously executed \ref multicore_lockout_victim_init() + * + * \note multicore_lockout_start_ functions are not nestable, and must be paired with a call to a corresponding + * \ref multicore_lockout_end_blocking + * + * \param timeout_us the timeout in microseconds + * \return true if the other core entered the locked out state within the timeout, false otherwise + */ bool multicore_lockout_start_timeout_us(uint64_t timeout_us); -void multicore_lockout_start_blocking(); +/*! \brief Release the other core from a locked out state amd wait for it to acknowledge + * \ingroup multicore_lockout + * + * \note The other core must previously have been "locked out" by calling a `multicore_lockout_start_` function + * from this core + */ +void multicore_lockout_end_blocking(void); + +/*! \brief Release the other core from a locked out state amd wait up to a time limit for it to acknowledge + * \ingroup multicore_lockout + * + * The other core must previously have been "locked out" by calling a `multicore_lockout_start_` function + * from this core + * + * \note be very careful using small timeout values, as a timeout here will leave the "lockout" functionality + * in a bad state. It is probably preferable to use \ref multicore_lockout_end_blocking anyway as if you have + * already waited for the victim core to enter the lockout state, then the victim core will be ready to exit + * the lockout state very quickly. + * + * \param timeout_us the timeout in microseconds + * \return true if the other core successfully exited locked out state within the timeout, false otherwise + */ bool multicore_lockout_end_timeout_us(uint64_t timeout_us); -void multicore_lockout_end_blocking(); #ifdef __cplusplus } diff --git a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/include/pico/platform.h b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/include/pico/platform.h index 718a5ecab..ee1d360ce 100644 --- a/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/include/pico/platform.h +++ b/cores/arduino/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/pico_platform/include/pico/platform.h @@ -7,94 +7,405 @@ #ifndef _PICO_PLATFORM_H_ #define _PICO_PLATFORM_H_ +/** \file platform.h + * \defgroup pico_platform pico_platform + * + * Macros and definitions (and functions when included by non assembly code) for the RP2 family device / architecture + * to provide a common abstraction over low level compiler / platform specifics. + * + * This header may be included by assembly code + */ + +#include "hardware/platform_defs.h" + +// Marker for builds targeting the RP2040 +#define PICO_RP2040 1 + +// PICO_CONFIG: PICO_STACK_SIZE, Stack Size, min=0x100, default=0x800, advanced=true, group=pico_platform +#ifndef PICO_STACK_SIZE +#define PICO_STACK_SIZE _u(0x800) +#endif + +// PICO_CONFIG: PICO_HEAP_SIZE, Heap size to reserve, min=0x100, default=0x800, advanced=true, group=pico_platform +#ifndef PICO_HEAP_SIZE +#define PICO_HEAP_SIZE _u(0x800) +#endif + +// PICO_CONFIG: PICO_NO_RAM_VECTOR_TABLE, Enable/disable the RAM vector table, type=bool, default=0, advanced=true, group=pico_platform +#ifndef PICO_NO_RAM_VECTOR_TABLE +#define PICO_NO_RAM_VECTOR_TABLE 0 +#endif + +// PICO_CONFIG: PICO_RP2040_B0_SUPPORTED, Whether to include any specific software support for RP2040 B0 revision, type=bool, default=1, advanced=true, group=pico_platform +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 1 +#endif + +// PICO_CONFIG: PICO_FLOAT_SUPPORT_ROM_V1, Include float support code for RP2040 B0 when that chip revision is supported , type=bool, default=1, advanced=true, group=pico_platform +#ifndef PICO_FLOAT_SUPPORT_ROM_V1 +#define PICO_FLOAT_SUPPORT_ROM_V1 1 +#endif + +// PICO_CONFIG: PICO_DOUBLE_SUPPORT_ROM_V1, Include double support code for RP2040 B0 when that chip revision is supported , type=bool, default=1, advanced=true, group=pico_platform +#ifndef PICO_DOUBLE_SUPPORT_ROM_V1 +#define PICO_DOUBLE_SUPPORT_ROM_V1 1 +#endif + + +// PICO_CONFIG: PICO_RP2040_B1_SUPPORTED, Whether to include any specific software support for RP2040 B1 revision, type=bool, default=1, advanced=true, group=pico_platform +#ifndef PICO_RP2040_B1_SUPPORTED +#define PICO_RP2040_B1_SUPPORTED 1 +#endif + +// PICO_CONFIG: PICO_RP2040_B2_SUPPORTED, Whether to include any specific software support for RP2040 B2 revision, type=bool, default=1, advanced=true, group=pico_platform +#ifndef PICO_RP2040_B2_SUPPORTED +#define PICO_RP2040_B2_SUPPORTED 1 +#endif + +// --- remainder of file is not included by assembly code --- + +#ifndef __ASSEMBLER__ + #include #include "pico/types.h" -#include "hardware/platform_defs.h" #ifdef __cplusplus extern "C" { #endif -/** \file platform.h -* \defgroup pico_platform pico_platform -* Compiler definitions for the selected PICO_PLATFORM -*/ - +/*! \brief Marker for an interrupt handler + * \ingroup pico_platform + * For example an IRQ handler function called my_interrupt_handler: + * + * void __isr my_interrupt_handler(void) { + */ #define __isr -#define __not_in_flash(group) __attribute__((section(".time_critical." group))) -#define __not_in_flash_func(x) __not_in_flash(__STRING(x)) x -#define __no_inline_not_in_flash_func(x) __attribute__((noinline)) __not_in_flash_func(x) +/*! \brief Section attribute macro for placement in RAM after the `.data` section + * \ingroup pico_platform + * + * For example a 400 element `uint32_t` array placed after the .data section + * + * uint32_t __after_data("my_group_name") a_big_array[400]; + * + * The section attribute is `.after_data.` + * + * \param group a string suffix to use in the section name to distinguish groups that can be linker + * garbage-collected independently + */ +#define __after_data(group) __attribute__((section(".after_data." group))) -// For use with PICO_COPY_TO_RAM: -#define __in_flash(group) __attribute__((section(".flashdata" group))) +/*! \brief Section attribute macro for placement not in flash (i.e in RAM) + * \ingroup pico_platform + * + * For example a 3 element `uint32_t` array placed in RAM (even though it is `static const`) + * + * static const uint32_t __not_in_flash("my_group_name") an_array[3]; + * + * The section attribute is `.time_critical.` + * + * \param group a string suffix to use in the section name to distinguish groups that can be linker + * garbage-collected independently + */ +#define __not_in_flash(group) __attribute__((section(".time_critical." group))) +/*! \brief Section attribute macro for placement in the SRAM bank 4 (known as "scratch X") + * \ingroup pico_platform + * + * Scratch X is commonly used for critical data and functions accessed only by one core (when only + * one core is accessing the RAM bank, there is no opportunity for stalls) + * + * For example a `uint32_t` variable placed in "scratch X" + * + * uint32_t __scratch_x("my_group_name") foo = 23; + * + * The section attribute is `.scratch_x.` + * + * \param group a string suffix to use in the section name to distinguish groups that can be linker + * garbage-collected independently + */ #define __scratch_x(group) __attribute__((section(".scratch_x." group))) + +/*! \brief Section attribute macro for placement in the SRAM bank 5 (known as "scratch Y") + * \ingroup pico_platform + * + * Scratch Y is commonly used for critical data and functions accessed only by one core (when only + * one core is accessing the RAM bank, there is no opportunity for stalls) + * + * For example a `uint32_t` variable placed in "scratch Y" + * + * uint32_t __scratch_y("my_group_name") foo = 23; + * + * The section attribute is `.scratch_y.` + * + * \param group a string suffix to use in the section name to distinguish groups that can be linker + * garbage-collected independently + */ #define __scratch_y(group) __attribute__((section(".scratch_y." group))) -#define __time_critical_func(x) __not_in_flash_func(x) -#define __after_data(group) __attribute__((section(".after_data." group))) +/*! \brief Section attribute macro for data that is to be left uninitialized + * \ingroup pico_platform + * + * Data marked this way will retain its value across a reset (normally uninitialized data - in the .bss + * section) is initialized to zero during runtime initialization + * + * For example a `uint32_t` foo that will retain its value if the program is restarted by reset. + * + * uint32_t __uninitialized_ram("my_group_name") foo; + * + * The section attribute is `.uninitialized_ram.` + * + * \param group a string suffix to use in the section name to distinguish groups that can be linker + * garbage-collected independently + */ +#define __uninitialized_ram(group) __attribute__((section(".uninitialized_ram." #group))) group + +/*! \brief Section attribute macro for placement in flash even in a COPY_TO_RAM binary + * \ingroup pico_platform + * + * For example a `uint32_t` variable explicitly placed in flash (it will hard fault if you attempt to write it!) + * + * uint32_t __in_flash("my_group_name") foo = 23; + * + * The section attribute is `.flashdata.` + * + * \param group a string suffix to use in the section name to distinguish groups that can be linker + * garbage-collected independently + */ +#define __in_flash(group) __attribute__((section(".flashdata" group))) + +/*! \brief Indicates a function should not be stored in flash + * \ingroup pico_platform + * + * Decorates a function name, such that the function will execute from RAM (assuming it is not inlined + * into a flash function by the compiler) + * + * For example a function called my_func taking an int parameter: + * + * void __not_in_flash_func(my_func)(int some_arg) { + * + * The function is placed in the `.time_critical.` linker section + * + * \see __no_inline_not_in_flash_func + */ +#define __not_in_flash_func(func_name) __not_in_flash(__STRING(func_name)) func_name + +/*! \brief Indicates a function is time/latency critical and should not run from flash + * \ingroup pico_platform + * + * Decorates a function name, such that the function will execute from RAM (assuming it is not inlined + * into a flash function by the compiler) to avoid possible flash latency. Currently this macro is identical + * in implementation to `__not_in_flash_func`, however the semantics are distinct and a `__time_critical_func` + * may in the future be treated more specially to reduce the overhead when calling such function from a flash + * function. + * + * For example a function called my_func taking an int parameter: + * + * void __time_critical(my_func)(int some_arg) { + * + * The function is placed in the `.time_critical.` linker section + * + * \see __not_in_flash_func + */ +#define __time_critical_func(func_name) __not_in_flash_func(func_name) + +/*! \brief Indicate a function should not be stored in flash and should not be inlined + * \ingroup pico_platform + * + * Decorates a function name, such that the function will execute from RAM, explicitly marking it as + * noinline to prevent it being inlined into a flash function by the compiler + * + * For example a function called my_func taking an int parameter: + * + * void __no_inline_not_in_flash_func(my_func)(int some_arg) { + * + * The function is placed in the `.time_critical.` linker section + */ +#define __no_inline_not_in_flash_func(func_name) __noinline __not_in_flash_func(func_name) + #define __packed_aligned __packed __aligned(4) +/*! \brief Attribute to force inlining of a function regardless of optimization level + * \ingroup pico_platform + * + * For example my_function here will always be inlined: + * + * int __force_inline my_function(int x) { + * + */ +#if defined(__GNUC__) && __GNUC__ <= 7 +#define __force_inline inline __always_inline +#else +#define __force_inline __always_inline +#endif + +/*! \brief Macro to determine the number of elements in an array + * \ingroup pico_platform + */ #ifndef count_of #define count_of(a) (sizeof(a)/sizeof((a)[0])) #endif +/*! \brief Macro to return the maximum of two comparable values + * \ingroup pico_platform + */ #ifndef MAX #define MAX(a, b) ((a)>(b)?(a):(b)) #endif +/*! \brief Macro to return the minimum of two comparable values + * \ingroup pico_platform + */ #ifndef MIN #define MIN(a, b) ((b)>(a)?(a):(b)) #endif -#define __uninitialized_ram(group) __attribute__((section(".uninitialized_ram." #group))) group - -inline static void __breakpoint() { +/*! \brief Execute a breakpoint instruction + * \ingroup pico_platform + */ +static inline void __breakpoint(void) { __asm__("bkpt #0"); } -// return a 32 bit handle for a raw ptr; DMA chaining for example embeds pointers in 32 bit values -// which of course does not work if we're running the code natively on a 64 bit platforms. Therefore -// we provide this macro which allows that code to provide a 64->32 bit mapping in host mode +/*! \brief Ensure that the compiler does not move memory access across this method call + * \ingroup pico_platform + * + * For example in the following code: + * + * *some_memory_location = var_a; + * __compiler_memory_barrier(); + * uint32_t var_b = *some_other_memory_location + * + * The compiler will not move the load from `some_other_memory_location` above the memory barrier (which it otherwise + * might - even above the memory store!) + */ +__force_inline static void __compiler_memory_barrier(void) { + __asm__ volatile ("" : : : "memory"); +} + +/*! \brief Macro for converting memory addresses to 32 bit addresses suitable for DMA + * \ingroup pico_platform + * + * This is just a cast to `uintptr_t` on the RP2040, however you may want to use this when developing code + * that also runs in "host" mode. If the host mode is 64 bit and you are embedding data pointers + * in other data (e.g. DMA chaining), then there is a need in "host" mode to convert a 64 bit native + * pointer to a 32 bit value for storage, which can be done using this macro. + */ #define host_safe_hw_ptr(x) ((uintptr_t)(x)) +#define native_safe_hw_ptr(x) host_safe_hw_ptr(x) + -void __attribute__((noreturn)) panic_unsupported(); +/*! \brief Panics with the message "Unsupported" + * \ingroup pico_platform + * \see panic + */ +void __attribute__((noreturn)) panic_unsupported(void); +/*! \brief Displays a panic message and halts execution + * \ingroup pico_platform + * + * An attempt is made to output the message to all registered STDOUT drivers + * after which this method executes a BKPT instruction. + * + * @param fmt format string (printf-like) + * @param ... printf-like arguments + */ void __attribute__((noreturn)) panic(const char *fmt, ...); -bool running_on_fpga(); -uint8_t rp2040_chip_version(); +// PICO_CONFIG: PICO_NO_FPGA_CHECK, Remove the FPGA platform check for small code size reduction, type=bool, default=0, advanced=true, group=pico_runtime +#ifndef PICO_NO_FPGA_CHECK +#define PICO_NO_FPGA_CHECK 0 +#endif -static inline uint8_t rp2040_rom_version() { +#if PICO_NO_FPGA_CHECK +static inline bool running_on_fpga(void) {return false;} +#else +bool running_on_fpga(void); +#endif + +/*! \brief Returns the RP2040 chip revision number + * \ingroup pico_platform + * @return the RP2040 chip revision number (1 for B0/B1, 2 for B2) + */ +uint8_t rp2040_chip_version(void); + +/*! \brief Returns the RP2040 rom version number + * \ingroup pico_platform + * @return the RP2040 rom version number (1 for RP2040-B0, 2 for RP2040-B1, 3 for RP2040-B2) + */ +static inline uint8_t rp2040_rom_version(void) { return *(uint8_t*)0x13; } -// called by any tight hardware polling loop... nominally empty, but can be modified for debugging -static inline void tight_loop_contents() {} - -// return a 32 bit handle for a raw ptr; DMA chaining for example embeds pointers in 32 bit values -// which of course does not work if we're running the code natively on a 64 bit platform for testing. -// Therefore we provide this function which allows the host runtime to provide a mapping -#define native_safe_hw_ptr(x) ((uintptr_t)(x)) +/*! \brief No-op function for the body of tight loops + * \ingroup pico_platform + * + * Np-op function intended to be called by any tight hardware polling loop. Using this ubiquitously + * makes it much easier to find tight loops, but also in the future \#ifdef-ed support for lockup + * debugging might be added + */ +static __force_inline void tight_loop_contents(void) {} -// multiplies a by b using multiply instruction using the ARM mul instruction regardless of values -inline static int32_t __mul_instruction(int32_t a, int32_t b) { -asm ("mul %0, %1" : "+l" (a) : "l" (b) : ); -return a; +/*! \brief Multiply two integers using an assembly `MUL` instruction + * \ingroup pico_platform + * + * This multiplies a by b using multiply instruction using the ARM mul instruction regardless of values (the compiler + * might otherwise choose to perform shifts/adds), i.e. this is a 1 cycle operation. + * + * \param a the first operand + * \param b the second operand + * \return a * b + */ +__force_inline static int32_t __mul_instruction(int32_t a, int32_t b) { + asm ("mul %0, %1" : "+l" (a) : "l" (b) : ); + return a; } -#define WRAPPER_FUNC(x) __wrap_ ## x -#define REAL_FUNC(x) __real_ ## x - -// macro to multiply value a by possibly constant value b -// if b is known to be constant and not zero or a power of 2, then a mul instruction is used rather than gcc's default +/*! \brief multiply two integer values using the fastest method possible + * \ingroup pico_platform + * + * Efficiently multiplies value a by possibly constant value b. + * + * If b is known to be constant and not zero or a power of 2, then a mul instruction is used rather than gcc's default + * which is often a slow combination of shifts and adds. If b is a power of 2 then a single shift is of course preferable + * and will be used + * + * \param a the first operand + * \param b the second operand + * \return a * b + */ #define __fast_mul(a, b) __builtin_choose_expr(__builtin_constant_p(b) && !__builtin_constant_p(a), \ (__builtin_popcount(b) >= 2 ? __mul_instruction(a,b) : (a)*(b)), \ (a)*(b)) +/*! \brief Utility macro to assert two types are equivalent. + * \ingroup pico_platform + * + * This macro can be useful in other macros along with `typeof` to assert that two parameters are of equivalent type + * (or that a single parameter is of an expected type) + */ #define __check_type_compatible(type_a, type_b) static_assert(__builtin_types_compatible_p(type_a, type_b), __STRING(type_a) " is not compatible with " __STRING(type_b)); + +/*! \brief Get the current exception level on this core + * \ingroup pico_platform + * + * \return the exception number if the CPU is handling an exception, or 0 otherwise + */ +uint __get_current_exception(void); + +#define WRAPPER_FUNC(x) __wrap_ ## x +#define REAL_FUNC(x) __real_ ## x + #ifdef __cplusplus } #endif + +#else // __ASSEMBLER__ + +#define WRAPPER_FUNC_NAME(x) __wrap_##x +#define SECTION_NAME(x) .text.##x +#define RAM_SECTION_NAME(x) .time_critical.##x + +#endif // !__ASSEMBLER__ + #endif diff --git a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F0/objects.h b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F0/objects.h index 140b06048..dbdadf962 100644 --- a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F0/objects.h +++ b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F0/objects.h @@ -100,8 +100,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F1/objects.h b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F1/objects.h index c3610186e..491cdd2e0 100644 --- a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F1/objects.h +++ b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F1/objects.h @@ -124,8 +124,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F2/objects.h b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F2/objects.h index 2bbc6f572..e30629a09 100644 --- a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F2/objects.h +++ b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F2/objects.h @@ -129,8 +129,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F3/objects.h b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F3/objects.h index 01d77e9aa..d69e9e7b6 100644 --- a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F3/objects.h +++ b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F3/objects.h @@ -115,8 +115,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F4/objects.h b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F4/objects.h index 507ca3be7..a71b3030b 100644 --- a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F4/objects.h +++ b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F4/objects.h @@ -113,8 +113,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F7/objects.h b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F7/objects.h index d49ab8c1c..ef8dc2919 100644 --- a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F7/objects.h +++ b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32F7/objects.h @@ -131,8 +131,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32G0/objects.h b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32G0/objects.h index 3673f6e75..55dea741c 100644 --- a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32G0/objects.h +++ b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32G0/objects.h @@ -114,8 +114,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32G4/PeripheralNames.h b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32G4/PeripheralNames.h index 348507996..76442d0b9 100644 --- a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32G4/PeripheralNames.h +++ b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32G4/PeripheralNames.h @@ -51,7 +51,9 @@ typedef enum { UART_1 = (int)USART1_BASE, UART_2 = (int)USART2_BASE, UART_3 = (int)USART3_BASE, +#if defined UART4_BASE UART_4 = (int)UART4_BASE, +#endif #if defined UART5_BASE UART_5 = (int)UART5_BASE, #endif diff --git a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32G4/i2c_device.h b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32G4/i2c_device.h index b41fc591d..7427b2a52 100644 --- a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32G4/i2c_device.h +++ b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32G4/i2c_device.h @@ -25,10 +25,10 @@ extern "C" { /* Define I2C Device */ #if DEVICE_I2C -// Common settings: I2C clock = 64 MHz, Analog filter = ON, Digital filter coefficient = 0 -#define TIMING_VAL_160M_CLK_100KHZ 0xC0311319 // Standard mode with Rise Time = 400ns and Fall Time = 100ns -#define TIMING_VAL_160M_CLK_400KHZ 0x10B1102E // Fast mode with Rise Time = 250ns and Fall Time = 100ns -#define TIMING_VAL_160M_CLK_1MHZ 0x00710B1E // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns +// Common settings: I2C clock = 160 MHz, Analog filter = ON, Digital filter coefficient = 0 +#define TIMING_VAL_160M_CLK_100KHZ 0x90A13E56 // Standard mode with Rise Time = 400ns and Fall Time = 100ns +#define TIMING_VAL_160M_CLK_400KHZ 0x30D2153A // Fast mode with Rise Time = 250ns and Fall Time = 100ns +#define TIMING_VAL_160M_CLK_1MHZ 0x10830F28 // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns #define I2C_PCLK_160M 160000000 // 160 MHz /* Define IP version */ diff --git a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32G4/objects.h b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32G4/objects.h index 53098ec6b..647c45253 100644 --- a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32G4/objects.h +++ b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32G4/objects.h @@ -113,8 +113,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; @@ -155,6 +155,19 @@ struct trng_s { RNG_HandleTypeDef handle; }; +#if DEVICE_QSPI +struct qspi_s { + QSPI_HandleTypeDef handle; + QSPIName qspi; + PinName io0; + PinName io1; + PinName io2; + PinName io3; + PinName sclk; + PinName ssel; +}; +#endif + //#include "common_objects.h" #include "gpio_object.h" diff --git a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/cmsis_nvic.h b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/cmsis_nvic.h new file mode 100644 index 000000000..05f9eacac --- /dev/null +++ b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/cmsis_nvic.h @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +// 0x0x08000000-0x080FFFFF Bank1 (8 x 128K sectors) +// 0x0x08100000-0x081FFFFF Bank2 (8 x 128K sectors) +#define MBED_ROM_SIZE 0x200000 // 2.0 MB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) +// 0x38000000 - 0x3800FFFF 64K SRAM4 +// 0x30040000 - 0x30047FFF 32K SRAM3 +// 0x30020000 - 0x3003FFFF 128K SRAM2 +// 0x30000000 - 0x3001FFFF 128K SRAM1 +// 0x24000000 - 0x2407FFFF 512K AXI SRAM +// 0x20000000 - 0x2001FFFF 128K DTCM +#define MBED_RAM_SIZE 0x20000 // 128 KB +#endif + +#if !defined(MBED_RAM1_START) +#define MBED_RAM1_START 0x24000000 +#endif + +#if !defined(MBED_RAM1_SIZE) +#define MBED_RAM1_SIZE 0x80000 // 512 KB +#endif + +#define NVIC_NUM_VECTORS 166 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START + +#endif diff --git a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32H7/objects.h b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32H7/objects.h index 8415007dd..628ffa747 100644 --- a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32H7/objects.h +++ b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32H7/objects.h @@ -126,8 +126,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32L0/objects.h b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32L0/objects.h index a94dd3f04..8ed217b88 100644 --- a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32L0/objects.h +++ b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32L0/objects.h @@ -116,8 +116,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32L1/objects.h b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32L1/objects.h index 91589c9a5..148be365a 100644 --- a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32L1/objects.h +++ b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32L1/objects.h @@ -111,8 +111,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32L4/objects.h b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32L4/objects.h index 1748be211..136a582b3 100644 --- a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32L4/objects.h +++ b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32L4/objects.h @@ -112,8 +112,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32L5/objects.h b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32L5/objects.h index c29d8cf34..c06bdd717 100644 --- a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32L5/objects.h +++ b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32L5/objects.h @@ -120,8 +120,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32U5/objects.h b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32U5/objects.h index c3adc4bc5..a5e3d328e 100644 --- a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32U5/objects.h +++ b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32U5/objects.h @@ -120,8 +120,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32WB/objects.h b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32WB/objects.h index 7fb437dc5..515846edc 100644 --- a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32WB/objects.h +++ b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32WB/objects.h @@ -103,8 +103,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32WL/objects.h b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32WL/objects.h index 66f06eab2..a8fd7b93d 100644 --- a/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32WL/objects.h +++ b/cores/arduino/mbed/targets/TARGET_STM/TARGET_STM32WL/objects.h @@ -106,8 +106,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/extras/package_index.json.NewTag.template b/extras/package_index.json.NewTag.template index 51b912fb0..75381c12b 100644 --- a/extras/package_index.json.NewTag.template +++ b/extras/package_index.json.NewTag.template @@ -76,7 +76,7 @@ }, { "packager": "arduino", - "version": "1.8.0-arduino.1", + "version": "1.8.0-arduino.2", "name": "imgtool" } ] @@ -123,11 +123,6 @@ "packager": "arduino", "version": "1.0.6", "name": "rp2040tools" - }, - { - "packager": "arduino", - "version": "1.8.0-arduino.1", - "name": "imgtool" } ] }, @@ -179,11 +174,6 @@ "packager": "arduino", "version": "1.0.6", "name": "rp2040tools" - }, - { - "packager": "arduino", - "version": "1.8.0-arduino.1", - "name": "imgtool" } ] }, @@ -225,7 +215,7 @@ }, { "packager": "arduino", - "version": "1.8.0-arduino.1", + "version": "1.8.0-arduino.2", "name": "imgtool" }, { @@ -277,11 +267,6 @@ "packager": "arduino", "version": "1.0.6", "name": "rp2040tools" - }, - { - "packager": "arduino", - "version": "1.8.0-arduino.1", - "name": "imgtool" } ] }, @@ -330,11 +315,6 @@ "packager": "arduino", "version": "1.0.6", "name": "rp2040tools" - }, - { - "packager": "arduino", - "version": "1.8.0-arduino.1", - "name": "imgtool" } ] } diff --git a/libraries/Camera/src/camera.h b/libraries/Camera/src/camera.h index 41853c82f..5d84c9185 100644 --- a/libraries/Camera/src/camera.h +++ b/libraries/Camera/src/camera.h @@ -21,6 +21,7 @@ #include "Wire.h" #define HM01B0_I2C_ADDR (0x24) +#define HM0360_I2C_ADDR (0x24) #define GC2145_I2C_ADDR (0x3C) enum { diff --git a/libraries/Ethernet/src/Ethernet.cpp b/libraries/Ethernet/src/Ethernet.cpp index fb34b33ef..26d63e5a2 100644 --- a/libraries/Ethernet/src/Ethernet.cpp +++ b/libraries/Ethernet/src/Ethernet.cpp @@ -42,14 +42,14 @@ int arduino::EthernetClass::begin(uint8_t *mac, IPAddress ip, IPAddress dns, IPA return ret; } -int arduino::EthernetClass::begin(uint8_t *mac, IPAddress ip, IPAddress dns, IPAddress gateway, IPAddress subnet) { +int arduino::EthernetClass::begin(uint8_t *mac, IPAddress ip, IPAddress dns, IPAddress gateway, IPAddress subnet, unsigned long timeout, unsigned long responseTimeout) { config(ip, dns, gateway, subnet); eth_if->set_dhcp(false); eth_if->set_network(_ip, _netmask, _gateway); eth_if->add_dns_server(_dnsServer1, nullptr); - auto ret = begin(mac); + auto ret = begin(mac, timeout, responseTimeout); return ret; } diff --git a/libraries/Ethernet/src/Ethernet.h b/libraries/Ethernet/src/Ethernet.h index 3b86e7601..bd0c7f9e8 100644 --- a/libraries/Ethernet/src/Ethernet.h +++ b/libraries/Ethernet/src/Ethernet.h @@ -65,7 +65,7 @@ class EthernetClass : public MbedSocketClass { int begin(uint8_t *mac, IPAddress ip); int begin(uint8_t *mac, IPAddress ip, IPAddress dns); int begin(uint8_t *mac, IPAddress ip, IPAddress dns, IPAddress gateway); - int begin(uint8_t *mac, IPAddress ip, IPAddress dns, IPAddress gateway, IPAddress subnet); + int begin(uint8_t *mac, IPAddress ip, IPAddress dns, IPAddress gateway, IPAddress subnet, unsigned long timeout = 60000, unsigned long responseTimeout = 4000); int begin(IPAddress ip) { return begin(nullptr, ip); diff --git a/libraries/GPS/src/GPS.cpp b/libraries/GPS/src/GPS.cpp index f8030710c..0861a9885 100644 --- a/libraries/GPS/src/GPS.cpp +++ b/libraries/GPS/src/GPS.cpp @@ -197,7 +197,7 @@ void arduino::GPSClass::end() _engine = !checkGNSSEngine("^SGPSC: \"Engine\",\"0\""); } - _serial->write("^SSIO=7,0\r\n", sizeof("^SSIO=7,0\r\n")); + _serial->write("AT^SSIO=7,0\r\n", sizeof("AT^SSIO=7,0\r\n")); readAndDrop(); } diff --git a/libraries/Himax_HM0360/hm0360.cpp b/libraries/Himax_HM0360/hm0360.cpp new file mode 100644 index 000000000..8cd0b3703 --- /dev/null +++ b/libraries/Himax_HM0360/hm0360.cpp @@ -0,0 +1,789 @@ +/* + * Copyright 2021 Arduino SA + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program. If not, see . + * + * HM0360 driver. + */ +#include "Wire.h" +#include "hm0360.h" + +// Register set +// Read only registers +#define MODEL_ID_H 0x0000 +#define MODEL_ID_L 0x0001 +#define SILICON_REV 0x0002 +#define FRAME_COUNT_H 0x0005 +#define FRAME_COUNT_L 0x0006 +#define PIXEL_ORDER 0x0007 +// Sensor mode control +#define MODE_SELECT 0x0100 +#define IMG_ORIENTATION 0x0101 +#define EMBEDDED_LINE_EN 0x0102 +#define SW_RESET 0x0103 +#define COMMAND_UPDATE 0x0104 +// Sensor exposure gain control +#define INTEGRATION_H 0x0202 +#define INTEGRATION_L 0x0203 +#define ANALOG_GAIN 0x0205 +#define DIGITAL_GAIN_H 0x020E +#define DIGITAL_GAIN_L 0x020F +// Clock control +#define PLL1_CONFIG 0x0300 +#define PLL2_CONFIG 0x0301 +#define PLL3_CONFIG 0x0302 +// Frame timing control +#define FRAME_LEN_LINES_H 0x0340 +#define FRAME_LEN_LINES_L 0x0341 +#define LINE_LEN_PCK_H 0x0342 +#define LINE_LEN_PCK_L 0x0343 +// Monochrome programming +#define MONO_MODE 0x0370 +#define MONO_MODE_ISP 0x0371 +#define MONO_MODE_SEL 0x0372 +// Binning mode control +#define H_SUBSAMPLE 0x0380 +#define V_SUBSAMPLE 0x0381 +#define BINNING_MODE 0x0382 +// Test pattern control +#define TEST_PATTERN_MODE 0x0601 +// Black level control +#define BLC_TGT 0x1004 +#define BLC2_TGT 0x1009 +#define MONO_CTRL 0x100A +// VSYNC / HSYNC / pixel shift registers +#define OPFM_CTRL 0x1014 +// Tone mapping registers +#define CMPRS_CTRL 0x102F +#define CMPRS_01 0x1030 +#define CMPRS_02 0x1031 +#define CMPRS_03 0x1032 +#define CMPRS_04 0x1033 +#define CMPRS_05 0x1034 +#define CMPRS_06 0x1035 +#define CMPRS_07 0x1036 +#define CMPRS_08 0x1037 +#define CMPRS_09 0x1038 +#define CMPRS_10 0x1039 +#define CMPRS_11 0x103A +#define CMPRS_12 0x103B +#define CMPRS_13 0x103C +#define CMPRS_14 0x103D +#define CMPRS_15 0x103E +#define CMPRS_16 0x103F +// Automatic exposure control +#define AE_CTRL 0x2000 +#define AE_CTRL1 0x2001 +#define CNT_ORGH_H 0x2002 +#define CNT_ORGH_L 0x2003 +#define CNT_ORGV_H 0x2004 +#define CNT_ORGV_L 0x2005 +#define CNT_STH_H 0x2006 +#define CNT_STH_L 0x2007 +#define CNT_STV_H 0x2008 +#define CNT_STV_L 0x2009 +#define CTRL_PG_SKIPCNT 0x200A +#define BV_WIN_WEIGHT_EN 0x200D +#define MAX_INTG_H 0x2029 +#define MAX_INTG_L 0x202A +#define MAX_AGAIN 0x202B +#define MAX_DGAIN_H 0x202C +#define MAX_DGAIN_L 0x202D +#define MIN_INTG 0x202E +#define MIN_AGAIN 0x202F +#define MIN_DGAIN 0x2030 +#define T_DAMPING 0x2031 +#define N_DAMPING 0x2032 +#define ALC_TH 0x2033 +#define AE_TARGET_MEAN 0x2034 +#define AE_MIN_MEAN 0x2035 +#define AE_TARGET_ZONE 0x2036 +#define CONVERGE_IN_TH 0x2037 +#define CONVERGE_OUT_TH 0x2038 +#define FS_CTRL 0x203B +#define FS_60HZ_H 0x203C +#define FS_60HZ_L 0x203D +#define FS_50HZ_H 0x203E +#define FS_50HZ_L 0x203F +#define FRAME_CNT_TH 0x205B +#define AE_MEAN 0x205D +#define AE_CONVERGE 0x2060 +#define AE_BLI_TGT 0x2070 +// Interrupt control +#define PULSE_MODE 0x2061 +#define PULSE_TH_H 0x2062 +#define PULSE_TH_L 0x2063 +#define INT_INDIC 0x2064 +#define INT_CLEAR 0x2065 +// Motion detection control +#define MD_CTRL 0x2080 +#define ROI_START_END_V 0x2081 +#define ROI_START_END_H 0x2082 +#define MD_TH_MIN 0x2083 +#define MD_TH_STR_L 0x2084 +#define MD_TH_STR_H 0x2085 +#define MD_LIGHT_COEF 0x2099 +#define MD_BLOCK_NUM_TH 0x209B +#define MD_LATENCY 0x209C +#define MD_LATENCY_TH 0x209D +#define MD_CTRL1 0x209E +// Context switch control registers +#define PMU_CFG_3 0x3024 +#define PMU_CFG_4 0x3025 +// Operation mode control +#define WIN_MODE 0x3030 +// IO and clock control +#define PAD_REGISTER_07 0x3112 + +// Register bits/values +#define HIMAX_RESET 0x01 +#define HIMAX_MODE_STANDBY 0x00 +#define HIMAX_MODE_STREAMING 0x01 // I2C triggered streaming enable +#define HIMAX_MODE_STREAMING_NFRAMES 0x03 // Output N frames +#define HIMAX_MODE_STREAMING_TRIG 0x05 // Hardware Trigger +#define HIMAX_SET_HMIRROR(r, x) ((r&0xFE)|((x&1)<<0)) +#define HIMAX_SET_VMIRROR(r, x) ((r&0xFD)|((x&1)<<1)) + +#define PCLK_RISING_EDGE 0x00 +#define PCLK_FALLING_EDGE 0x01 +#define AE_CTRL_ENABLE 0x00 +#define AE_CTRL_DISABLE 0x01 + +/** + * @} + */ +/* Private variables ---------------------------------------------------------*/ + +/** @defgroup GAPUINO_HIMAX_Private_Variables I2C Private Variables + * @{ + */ +#define HIMAX_BOOT_RETRY (10) +#define HIMAX_LINE_LEN_PCK_VGA 0x300 +#define HIMAX_FRAME_LENGTH_VGA 0x214 + +#define HIMAX_LINE_LEN_PCK_QVGA 0x178 +#define HIMAX_FRAME_LENGTH_QVGA 0x109 + +#define HIMAX_LINE_LEN_PCK_QQVGA 0x178 +#define HIMAX_FRAME_LENGTH_QQVGA 0x084 + +#define HIMAX_MD_ROI_VGA_W 40 +#define HIMAX_MD_ROI_VGA_H 30 + +#define HIMAX_MD_ROI_QVGA_W 20 +#define HIMAX_MD_ROI_QVGA_H 15 + +#define HIMAX_MD_ROI_QQVGA_W 10 +#define HIMAX_MD_ROI_QQVGA_H 8 + +#ifndef MIN +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif +#ifndef MAX +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +enum { + HIMAX_Standby = 0x0, + HIMAX_Streaming = 0x1, // I2C triggered streaming enable + HIMAX_Streaming2 = 0x3, // Output N frames + HIMAX_Streaming3 = 0x5 // Hardware Trigger +}; + +typedef struct regval_list_ { + uint16_t reg_num; + uint8_t value; +} regval_list_t; + +static uint16_t himax_default_regs[][2] = { + {SW_RESET, 0x00}, + {MONO_MODE, 0x00}, + {MONO_MODE_ISP, 0x01}, + {MONO_MODE_SEL, 0x01}, + + // BLC control + {0x1000, 0x01}, + {0x1003, 0x04}, + {BLC_TGT, 0x04}, + {0x1007, 0x01}, + {0x1008, 0x04}, + {BLC2_TGT, 0x04}, + {MONO_CTRL, 0x01}, + + // Output format control + {OPFM_CTRL, 0x0C}, + + // Reserved regs + {0x101D, 0x00}, + {0x101E, 0x01}, + {0x101F, 0x00}, + {0x1020, 0x01}, + {0x1021, 0x00}, + + {CMPRS_CTRL, 0x00}, + {CMPRS_01, 0x09}, + {CMPRS_02, 0x12}, + {CMPRS_03, 0x23}, + {CMPRS_04, 0x31}, + {CMPRS_05, 0x3E}, + {CMPRS_06, 0x4B}, + {CMPRS_07, 0x56}, + {CMPRS_08, 0x5E}, + {CMPRS_09, 0x65}, + {CMPRS_10, 0x72}, + {CMPRS_11, 0x7F}, + {CMPRS_12, 0x8C}, + {CMPRS_13, 0x98}, + {CMPRS_14, 0xB2}, + {CMPRS_15, 0xCC}, + {CMPRS_16, 0xE6}, + + {0x3112, 0x00}, // PCLKO_polarity falling + + {PLL1_CONFIG, 0x08}, // Core = 24MHz PCLKO = 24MHz I2C = 12MHz + {PLL2_CONFIG, 0x0A}, // MIPI pre-dev (default) + {PLL3_CONFIG, 0x77}, // PMU/MIPI pre-dev (default) + + {PMU_CFG_3, 0x08}, // Disable context switching + {PAD_REGISTER_07, 0x00}, // PCLKO_polarity falling + + {AE_CTRL, 0x5F}, // Automatic Exposure (NOTE: Auto framerate enabled) + {AE_CTRL1, 0x00}, + {T_DAMPING, 0x20}, // AE T damping factor + {N_DAMPING, 0x00}, // AE N damping factor + {AE_TARGET_MEAN, 0x64}, // AE target + {AE_MIN_MEAN, 0x0A}, // AE min target mean + {AE_TARGET_ZONE, 0x23}, // AE target zone + {CONVERGE_IN_TH, 0x03}, // AE converge in threshold + {CONVERGE_OUT_TH, 0x05}, // AE converge out threshold + {MAX_INTG_H, (HIMAX_FRAME_LENGTH_QVGA-4)>>8}, + {MAX_INTG_L, (HIMAX_FRAME_LENGTH_QVGA-4)&0xFF}, + + {MAX_AGAIN, 0x04}, // Maximum analog gain + {MAX_DGAIN_H, 0x03}, + {MAX_DGAIN_L, 0x3F}, + {INTEGRATION_H, 0x01}, + {INTEGRATION_L, 0x08}, + + {MD_CTRL, 0x6A}, + {MD_TH_MIN, 0x01}, + {MD_BLOCK_NUM_TH, 0x01}, + {MD_CTRL1, 0x06}, + {PULSE_MODE, 0x00}, // Interrupt in level mode. + {ROI_START_END_V, 0xF0}, + {ROI_START_END_H, 0xF0}, + + {FRAME_LEN_LINES_H, HIMAX_FRAME_LENGTH_QVGA>>8}, + {FRAME_LEN_LINES_L, HIMAX_FRAME_LENGTH_QVGA&0xFF}, + {LINE_LEN_PCK_H, HIMAX_LINE_LEN_PCK_QVGA>>8}, + {LINE_LEN_PCK_L, HIMAX_LINE_LEN_PCK_QVGA&0xFF}, + {H_SUBSAMPLE, 0x01}, + {V_SUBSAMPLE, 0x01}, + {BINNING_MODE, 0x00}, + {WIN_MODE, 0x00}, + {IMG_ORIENTATION, 0x00}, + {COMMAND_UPDATE, 0x01}, + + /// SYNC function config. + {0x3010, 0x00}, + {0x3013, 0x01}, + {0x3019, 0x00}, + {0x301A, 0x00}, + {0x301B, 0x20}, + {0x301C, 0xFF}, + + // PREMETER config. + {0x3026, 0x03}, + {0x3027, 0x81}, + {0x3028, 0x01}, + {0x3029, 0x00}, + {0x302A, 0x30}, + {0x302E, 0x00}, + {0x302F, 0x00}, + + // Magic regs 🪄. + {0x302B, 0x2A}, + {0x302C, 0x00}, + {0x302D, 0x03}, + {0x3031, 0x01}, + {0x3051, 0x00}, + {0x305C, 0x03}, + {0x3060, 0x00}, + {0x3061, 0xFA}, + {0x3062, 0xFF}, + {0x3063, 0xFF}, + {0x3064, 0xFF}, + {0x3065, 0xFF}, + {0x3066, 0xFF}, + {0x3067, 0xFF}, + {0x3068, 0xFF}, + {0x3069, 0xFF}, + {0x306A, 0xFF}, + {0x306B, 0xFF}, + {0x306C, 0xFF}, + {0x306D, 0xFF}, + {0x306E, 0xFF}, + {0x306F, 0xFF}, + {0x3070, 0xFF}, + {0x3071, 0xFF}, + {0x3072, 0xFF}, + {0x3073, 0xFF}, + {0x3074, 0xFF}, + {0x3075, 0xFF}, + {0x3076, 0xFF}, + {0x3077, 0xFF}, + {0x3078, 0xFF}, + {0x3079, 0xFF}, + {0x307A, 0xFF}, + {0x307B, 0xFF}, + {0x307C, 0xFF}, + {0x307D, 0xFF}, + {0x307E, 0xFF}, + {0x307F, 0xFF}, + {0x3080, 0x01}, + {0x3081, 0x01}, + {0x3082, 0x03}, + {0x3083, 0x20}, + {0x3084, 0x00}, + {0x3085, 0x20}, + {0x3086, 0x00}, + {0x3087, 0x20}, + {0x3088, 0x00}, + {0x3089, 0x04}, + {0x3094, 0x02}, + {0x3095, 0x02}, + {0x3096, 0x00}, + {0x3097, 0x02}, + {0x3098, 0x00}, + {0x3099, 0x02}, + {0x309E, 0x05}, + {0x309F, 0x02}, + {0x30A0, 0x02}, + {0x30A1, 0x00}, + {0x30A2, 0x08}, + {0x30A3, 0x00}, + {0x30A4, 0x20}, + {0x30A5, 0x04}, + {0x30A6, 0x02}, + {0x30A7, 0x02}, + {0x30A8, 0x01}, + {0x30A9, 0x00}, + {0x30AA, 0x02}, + {0x30AB, 0x34}, + {0x30B0, 0x03}, + {0x30C4, 0x10}, + {0x30C5, 0x01}, + {0x30C6, 0xBF}, + {0x30C7, 0x00}, + {0x30C8, 0x00}, + {0x30CB, 0xFF}, + {0x30CC, 0xFF}, + {0x30CD, 0x7F}, + {0x30CE, 0x7F}, + {0x30D3, 0x01}, + {0x30D4, 0xFF}, + {0x30D5, 0x00}, + {0x30D6, 0x40}, + {0x30D7, 0x00}, + {0x30D8, 0xA7}, + {0x30D9, 0x05}, + {0x30DA, 0x01}, + {0x30DB, 0x40}, + {0x30DC, 0x00}, + {0x30DD, 0x27}, + {0x30DE, 0x05}, + {0x30DF, 0x07}, + {0x30E0, 0x40}, + {0x30E1, 0x00}, + {0x30E2, 0x27}, + {0x30E3, 0x05}, + {0x30E4, 0x47}, + {0x30E5, 0x30}, + {0x30E6, 0x00}, + {0x30E7, 0x27}, + {0x30E8, 0x05}, + {0x30E9, 0x87}, + {0x30EA, 0x30}, + {0x30EB, 0x00}, + {0x30EC, 0x27}, + {0x30ED, 0x05}, + {0x30EE, 0x00}, + {0x30EF, 0x40}, + {0x30F0, 0x00}, + {0x30F1, 0xA7}, + {0x30F2, 0x05}, + {0x30F3, 0x01}, + {0x30F4, 0x40}, + {0x30F5, 0x00}, + {0x30F6, 0x27}, + {0x30F7, 0x05}, + {0x30F8, 0x07}, + {0x30F9, 0x40}, + {0x30FA, 0x00}, + {0x30FB, 0x27}, + {0x30FC, 0x05}, + {0x30FD, 0x47}, + {0x30FE, 0x30}, + {0x30FF, 0x00}, + {0x3100, 0x27}, + {0x3101, 0x05}, + {0x3102, 0x87}, + {0x3103, 0x30}, + {0x3104, 0x00}, + {0x3105, 0x27}, + {0x3106, 0x05}, + {0x310B, 0x10}, + {0x3113, 0xA0}, + {0x3114, 0x67}, + {0x3115, 0x42}, + {0x3116, 0x10}, + {0x3117, 0x0A}, + {0x3118, 0x3F}, + {0x311C, 0x10}, + {0x311D, 0x06}, + {0x311E, 0x0F}, + {0x311F, 0x0E}, + {0x3120, 0x0D}, + {0x3121, 0x0F}, + {0x3122, 0x00}, + {0x3123, 0x1D}, + {0x3126, 0x03}, + {0x3128, 0x57}, + {0x312A, 0x11}, + {0x312B, 0x41}, + {0x312E, 0x00}, + {0x312F, 0x00}, + {0x3130, 0x0C}, + {0x3141, 0x2A}, + {0x3142, 0x9F}, + {0x3147, 0x18}, + {0x3149, 0x18}, + {0x314B, 0x01}, + {0x3150, 0x50}, + {0x3152, 0x00}, + {0x3156, 0x2C}, + {0x315A, 0x0A}, + {0x315B, 0x2F}, + {0x315C, 0xE0}, + {0x315F, 0x02}, + {0x3160, 0x1F}, + {0x3163, 0x1F}, + {0x3164, 0x7F}, + {0x3165, 0x7F}, + {0x317B, 0x94}, + {0x317C, 0x00}, + {0x317D, 0x02}, + {0x318C, 0x00}, + + {COMMAND_UPDATE, 0x01}, + {0x0000, 0x00}, +}; + +static const uint16_t himax_vga_regs[][2] = { + {PLL1_CONFIG, 0x08}, // Core = 24MHz PCLKO = 24MHz I2C = 12MHz + {H_SUBSAMPLE, 0x00}, + {V_SUBSAMPLE, 0x00}, + {BINNING_MODE, 0x00}, + {WIN_MODE, 0x00}, + {MAX_INTG_H, (HIMAX_FRAME_LENGTH_VGA-4)>>8}, + {MAX_INTG_L, (HIMAX_FRAME_LENGTH_VGA-4)&0xFF}, + {FRAME_LEN_LINES_H, (HIMAX_FRAME_LENGTH_VGA>>8)}, + {FRAME_LEN_LINES_L, (HIMAX_FRAME_LENGTH_VGA&0xFF)}, + {LINE_LEN_PCK_H, (HIMAX_LINE_LEN_PCK_VGA>>8)}, + {LINE_LEN_PCK_L, (HIMAX_LINE_LEN_PCK_VGA&0xFF)}, + {ROI_START_END_H, 0xF0}, + {ROI_START_END_V, 0xE0}, + {COMMAND_UPDATE, 0x01}, + {0x0000, 0x00}, +}; + +static const uint16_t himax_qvga_regs[][2] = { + {PLL1_CONFIG, 0x09}, // Core = 12MHz PCLKO = 24MHz I2C = 12MHz + {H_SUBSAMPLE, 0x01}, + {V_SUBSAMPLE, 0x01}, + {BINNING_MODE, 0x00}, + {WIN_MODE, 0x00}, + {MAX_INTG_H, (HIMAX_FRAME_LENGTH_QVGA-4)>>8}, + {MAX_INTG_L, (HIMAX_FRAME_LENGTH_QVGA-4)&0xFF}, + {FRAME_LEN_LINES_H, (HIMAX_FRAME_LENGTH_QVGA>>8)}, + {FRAME_LEN_LINES_L, (HIMAX_FRAME_LENGTH_QVGA&0xFF)}, + {LINE_LEN_PCK_H, (HIMAX_LINE_LEN_PCK_QVGA>>8)}, + {LINE_LEN_PCK_L, (HIMAX_LINE_LEN_PCK_QVGA&0xFF)}, + {ROI_START_END_H, 0xF0}, + {ROI_START_END_V, 0xE0}, + {COMMAND_UPDATE, 0x01}, + {0x0000, 0x00}, +}; + +static const uint16_t himax_qqvga_regs[][2] = { + {PLL1_CONFIG, 0x09}, // Core = 12MHz PCLKO = 24MHz I2C = 12MHz + {H_SUBSAMPLE, 0x02}, + {V_SUBSAMPLE, 0x02}, + {BINNING_MODE, 0x00}, + {WIN_MODE, 0x00}, + {MAX_INTG_H, (HIMAX_FRAME_LENGTH_QQVGA-4)>>8}, + {MAX_INTG_L, (HIMAX_FRAME_LENGTH_QQVGA-4)&0xFF}, + {FRAME_LEN_LINES_H, (HIMAX_FRAME_LENGTH_QQVGA>>8)}, + {FRAME_LEN_LINES_L, (HIMAX_FRAME_LENGTH_QQVGA&0xFF)}, + {LINE_LEN_PCK_H, (HIMAX_LINE_LEN_PCK_QQVGA>>8)}, + {LINE_LEN_PCK_L, (HIMAX_LINE_LEN_PCK_QQVGA&0xFF)}, + {ROI_START_END_H, 0xF0}, + {ROI_START_END_V, 0xD0}, + {COMMAND_UPDATE, 0x01}, + {0x0000, 0x00}, +}; + +HM0360::HM0360(arduino::MbedI2C &i2c) : + _i2c(&i2c), + md_irq(PC_15), + _md_callback(NULL) +{ +} + +void HM0360::irqHandler() +{ + if (_md_callback) { + _md_callback(); + } +} + +int HM0360::init() +{ + _i2c->begin(); + _i2c->setClock(100000); + + if (reset() != 0 ) { + return -1; + } + + for (uint32_t i=0; himax_default_regs[i][0]; i++) { + regWrite(HM0360_I2C_ADDR, himax_default_regs[i][0], himax_default_regs[i][1], true); + } + + regWrite(HM0360_I2C_ADDR, MODE_SELECT, HIMAX_Streaming, true); + return 0; +} + +int HM0360::reset() +{ + uint32_t max_timeout=100; + do { + regWrite(HM0360_I2C_ADDR, SW_RESET, HIMAX_RESET, true); + delay(1); + } while (regRead(HM0360_I2C_ADDR, MODE_SELECT, true) != HIMAX_Standby && ((--max_timeout) > 0) ); + + return (max_timeout > 0) ? 0 : -1; +} + +int HM0360::setResolution(int32_t resolution) +{ + int ret = 0; + + switch (resolution) { + case CAMERA_R160x120: + for(uint32_t i = 0; himax_qqvga_regs[i][0]; i++) { + ret |= regWrite(HM0360_I2C_ADDR, himax_qqvga_regs[i][0], himax_qqvga_regs[i][1], true); + } + break; + case CAMERA_R320x240: + case CAMERA_R320x320: + for(uint32_t i = 0; himax_qvga_regs[i][0]; i++) { + ret |= regWrite(HM0360_I2C_ADDR, himax_qvga_regs[i][0], himax_qvga_regs[i][1], true); + } + break; + case CAMERA_R640x480: + for(uint32_t i = 0; himax_vga_regs[i][0]; i++) { + ret |= regWrite(HM0360_I2C_ADDR, himax_vga_regs[i][0], himax_vga_regs[i][1], true); + } + break; + default: + return -1; + } + + return ret; +} + +int HM0360::setFrameRate(int32_t framerate) +{ + uint8_t pll_cfg = 0; + uint8_t osc_div = 0; + uint8_t highres = false; + + highres = ((regRead(HM0360_I2C_ADDR, H_SUBSAMPLE, true) & 0x03) + | (regRead(HM0360_I2C_ADDR, V_SUBSAMPLE, true) & 0x03)); + + if (framerate <= 10) { + osc_div = (highres == true) ? 0x03 : 0x03; + } else if (framerate <= 15) { + osc_div = (highres == true) ? 0x02 : 0x03; + } else if (framerate <= 30) { + osc_div = (highres == true) ? 0x01 : 0x02; + } else { + // Set to the max possible FPS at this resolution. + osc_div = (highres == true) ? 0x00 : 0x01; + } + + pll_cfg = regRead(HM0360_I2C_ADDR, PLL1_CONFIG, true); + return regWrite(HM0360_I2C_ADDR, PLL1_CONFIG, (pll_cfg & 0xFC) | osc_div, true); +} + +int HM0360::setPixelFormat(int32_t pixformat) +{ + return (pixformat == CAMERA_GRAYSCALE) ? 0 : -1; +} + +int HM0360::setTestPattern(bool enable, bool walking) +{ + return regWrite(HM0360_I2C_ADDR, 0x0601, (walking ? (2 << 4) : 0) | 1, true); +} + +int HM0360::setMotionDetectionThreshold(uint32_t threshold) +{ + // Set motion detection threshold/sensitivity. + int ret = 0; + ret |= regWrite(HM0360_I2C_ADDR, MD_TH_STR_L, threshold, true); + ret |= regWrite(HM0360_I2C_ADDR, MD_TH_STR_H, threshold, true); + ret |= regWrite(HM0360_I2C_ADDR, MD_LIGHT_COEF, threshold, true); + return ret; +} + +int HM0360::setMotionDetectionWindow(uint32_t x, uint32_t y, uint32_t w, uint32_t h) +{ + int ret = 0; + int32_t roi_w = 0; + int32_t roi_h = 0; + int32_t roi_max_h = 14; + + int32_t x1 = x; + int32_t y1 = y; + int32_t x2 = x + w; + int32_t y2 = y + h; + + uint8_t hsub = regRead(HM0360_I2C_ADDR, H_SUBSAMPLE, true) & 0x03; + uint8_t vsub = regRead(HM0360_I2C_ADDR, V_SUBSAMPLE, true) & 0x03; + + if (hsub == 0 && vsub == 0) { // VGA + roi_w = HIMAX_MD_ROI_VGA_W; + roi_h = HIMAX_MD_ROI_VGA_H; + roi_max_h = 14; + } else if (hsub == 1 && vsub == 1) { // QVGA + roi_w = HIMAX_MD_ROI_QVGA_W; + roi_h = HIMAX_MD_ROI_QVGA_H; + roi_max_h = 14; + } else if (hsub == 2 && vsub == 2) { // QQVGA + roi_w = HIMAX_MD_ROI_QQVGA_W; + roi_h = HIMAX_MD_ROI_QQVGA_H; + roi_max_h = 13; + } else { + return -1; + } + + x1 = MAX((x1 / roi_w - 1), 0); + y1 = MAX((y1 / roi_h - 1), 0); + x2 = MIN((x2 / roi_w) + !!(x2 % roi_w), 0xF); + y2 = MIN((y2 / roi_h) + !!(y2 % roi_h), roi_max_h); + ret |= regWrite(HM0360_I2C_ADDR, ROI_START_END_H, ((x2 & 0xF) << 4) | (x1 & 0x0F), true); + ret |= regWrite(HM0360_I2C_ADDR, ROI_START_END_V, ((y2 & 0xF) << 4) | (y1 & 0x0F), true); + return ret; +} + +int HM0360::enableMotionDetection(md_callback_t callback) +{ + md_irq.rise(0); + _md_callback = callback; + md_irq.rise(mbed::Callback(this, &HM0360::irqHandler)); + md_irq.enable_irq(); + + int ret = clearMotionDetection(); + uint8_t md_ctrl = regRead(HM0360_I2C_ADDR, MD_CTRL, true); + ret |= regWrite(HM0360_I2C_ADDR, MD_CTRL, (md_ctrl & 0xFE) | 1, true); + return ret; +} + +int HM0360::disableMotionDetection() +{ + _md_callback = NULL; + int ret = clearMotionDetection(); + uint8_t md_ctrl = regRead(HM0360_I2C_ADDR, MD_CTRL, true); + ret |= regWrite(HM0360_I2C_ADDR, MD_CTRL, (md_ctrl & 0xFE) | 0, true); + return ret; +} + +int HM0360::motionDetected() +{ + uint8_t ret = pollMotionDetection(); + if (ret) { + clearMotionDetection(); + } + return ret; +} + +int HM0360::pollMotionDetection() +{ + return regRead(HM0360_I2C_ADDR, INT_INDIC, true) & 0x08; +} + +int HM0360::clearMotionDetection() +{ + return regWrite(HM0360_I2C_ADDR, INT_CLEAR, (1 << 3), true); +} + +uint8_t HM0360::printRegs() +{ + for (uint32_t i=0; himax_default_regs[i][0]; i++) { + printf("0x%04X: 0x%02X 0x%02X \n", + himax_default_regs[i][0], + himax_default_regs[i][1], + regRead(HM0360_I2C_ADDR, himax_default_regs[i][0], true)); + } + return 0; +} + +int HM0360::regWrite(uint8_t dev_addr, uint16_t reg_addr, uint8_t reg_data, bool wide_addr) +{ + _i2c->beginTransmission(dev_addr); + uint8_t buf[3] = {(uint8_t) (reg_addr >> 8), (uint8_t) (reg_addr & 0xFF), reg_data}; + if (wide_addr == true) { + _i2c->write(buf, 1); + } + _i2c->write(&buf[1], 2); + return _i2c->endTransmission(); +} + +uint8_t HM0360::regRead(uint8_t dev_addr, uint16_t reg_addr, bool wide_addr) +{ + uint8_t reg_data = 0; + uint8_t buf[2] = {(uint8_t) (reg_addr >> 8), (uint8_t) (reg_addr & 0xFF)}; + _i2c->beginTransmission(dev_addr); + if (wide_addr) { + _i2c->write(buf, 2); + } else { + _i2c->write(&buf[1], 1); + } + _i2c->endTransmission(false); + _i2c->requestFrom(dev_addr, 1); + if (_i2c->available()) { + reg_data = _i2c->read(); + } + while (_i2c->available()) { + _i2c->read(); + } + return reg_data; +} + +void HM0360::debug(Stream &stream) +{ + _debug = &stream; +} + diff --git a/libraries/Himax_HM0360/hm0360.h b/libraries/Himax_HM0360/hm0360.h new file mode 100644 index 000000000..eb2d06c41 --- /dev/null +++ b/libraries/Himax_HM0360/hm0360.h @@ -0,0 +1,56 @@ +/* + * Copyright 2021 Arduino SA + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program. If not, see . + * + * HM0360 driver. + */ +#ifndef __HIMAX_H +#define __HIMAX_H + +#include "camera.h" +#include "drivers/InterruptIn.h" + +class HM0360: public ImageSensor { + private: + Stream *_debug; + arduino::MbedI2C *_i2c; + mbed::InterruptIn md_irq; + md_callback_t _md_callback; + void irqHandler(); + int regWrite(uint8_t dev_addr, uint16_t reg_addr, uint8_t reg_data, bool wide_addr = false); + uint8_t regRead(uint8_t dev_addr, uint16_t reg_addr, bool wide_addr = false); + + public: + HM0360(arduino::MbedI2C &i2c = CameraWire); + int init(); + int reset(); + int getID() { return HM0360_I2C_ADDR; }; + uint32_t getClockFrequency() { return 24000000; }; + int setFrameRate(int32_t framerate); + int setResolution(int32_t resolution); + int setPixelFormat(int32_t pixformat); + int setTestPattern(bool enable, bool walking); + int enableMotionDetection(md_callback_t callback=NULL); + int disableMotionDetection(); + int setMotionDetectionWindow(uint32_t x, uint32_t y, uint32_t w, uint32_t h); + int setMotionDetectionThreshold(uint32_t threshold); + int motionDetected(); + int pollMotionDetection(); + int clearMotionDetection(); + + uint8_t printRegs(); + void debug(Stream &stream); +}; +#endif /* __HIMAX_H */ diff --git a/libraries/SocketWrapper/src/MbedClient.cpp b/libraries/SocketWrapper/src/MbedClient.cpp index 538005799..dfd856f77 100644 --- a/libraries/SocketWrapper/src/MbedClient.cpp +++ b/libraries/SocketWrapper/src/MbedClient.cpp @@ -60,6 +60,7 @@ void arduino::MbedClient::setSocket(Socket *_sock) { void arduino::MbedClient::configureSocket(Socket *_s) { _s->set_timeout(_timeout); _s->set_blocking(false); + _s->getpeername(&address); if (event == nullptr) { event = new rtos::EventFlags; @@ -99,7 +100,6 @@ int arduino::MbedClient::connect(SocketAddress socketAddress) { return 0; } - address = socketAddress; nsapi_error_t returnCode = static_cast(sock)->connect(socketAddress); int ret = 0; @@ -150,8 +150,6 @@ int arduino::MbedClient::connectSSL(SocketAddress socketAddress) { return 0; } - address = socketAddress; - restart_connect: nsapi_error_t returnCode = static_cast(sock)->connect(socketAddress); int ret = 0; @@ -304,7 +302,7 @@ IPAddress arduino::MbedClient::remoteIP() { } uint16_t arduino::MbedClient::remotePort() { - return 0; + return address.get_port(); } void arduino::MbedClient::setTimeout(unsigned long timeout) { diff --git a/libraries/WiFi/src/WiFi.cpp b/libraries/WiFi/src/WiFi.cpp index 858fa56aa..da6102a33 100644 --- a/libraries/WiFi/src/WiFi.cpp +++ b/libraries/WiFi/src/WiFi.cpp @@ -17,6 +17,8 @@ int arduino::WiFiClass::begin(const char* ssid, const char* passphrase) { return 0; } + wifi_if->attach(&arduino::WiFiClass::statusCallback); + scanNetworks(); // use scan result to populate security field if (!isVisible(ssid)) { @@ -26,7 +28,11 @@ int arduino::WiFiClass::begin(const char* ssid, const char* passphrase) { nsapi_error_t result = wifi_if->connect(ssid, passphrase, ap_list[connected_ap].get_security()); + if(result == NSAPI_ERROR_IS_CONNECTED) { + wifi_if->disconnect(); + } _currentNetworkStatus = (result == NSAPI_ERROR_OK && setSSID(ssid)) ? WL_CONNECTED : WL_CONNECT_FAILED; + return _currentNetworkStatus; } @@ -160,9 +166,10 @@ static uint8_t sec2enum(nsapi_security_t sec) { int8_t arduino::WiFiClass::scanNetworks() { uint8_t count = 10; - if (ap_list == nullptr) { - ap_list = new WiFiAccessPoint[count]; + if (ap_list != nullptr) { + free(ap_list); } + ap_list = new WiFiAccessPoint[count]; return wifi_if->scan(ap_list, count); } @@ -210,6 +217,15 @@ unsigned long arduino::WiFiClass::getTime() { return 0; } +void arduino::WiFiClass::statusCallback(nsapi_event_t status, intptr_t param) +{ + if (((param == NSAPI_STATUS_DISCONNECTED) || + (param == NSAPI_STATUS_CONNECTING)) && + (WiFi.status() == WL_CONNECTED)) { + WiFi._currentNetworkStatus = WL_CONNECTION_LOST; + } +} + #if defined(COMPONENT_4343W_FS) #define WIFI_FIRMWARE_PATH "/wlan/4343WA1.BIN" diff --git a/libraries/WiFi/src/WiFi.h b/libraries/WiFi/src/WiFi.h index 96e66c19b..d6fd69765 100644 --- a/libraries/WiFi/src/WiFi.h +++ b/libraries/WiFi/src/WiFi.h @@ -209,6 +209,7 @@ class WiFiClass : public MbedSocketClass { void ensureDefaultAPNetworkConfiguration(); static void* handleAPEvents(whd_interface_t ifp, const whd_event_header_t* event_header, const uint8_t* event_data, void* handler_user_data); bool isVisible(const char* ssid); + static void statusCallback(nsapi_event_t status, intptr_t param); }; } diff --git a/libraries/Wire/Wire.cpp b/libraries/Wire/Wire.cpp index a17bb019a..5091f44a2 100644 --- a/libraries/Wire/Wire.cpp +++ b/libraries/Wire/Wire.cpp @@ -28,11 +28,13 @@ arduino::MbedI2C::MbedI2C(int sda, int scl) : _sda(digitalPinToPinName(sda)), _s arduino::MbedI2C::MbedI2C(PinName sda, PinName scl) : _sda(sda), _scl(scl), usedTxBuffer(0), slave_th(osPriorityNormal, 2048, nullptr, "I2CSlave") {} void arduino::MbedI2C::begin() { + end(); master = new mbed::I2C(_sda, _scl); } void arduino::MbedI2C::begin(uint8_t slaveAddr) { #ifdef DEVICE_I2CSLAVE + end(); slave = new mbed::I2CSlave((PinName)_sda, (PinName)_scl); slave->address(slaveAddr << 1); slave_th.start(mbed::callback(this, &arduino::MbedI2C::receiveThd)); diff --git a/libraries/doom/examples/Doom/Doom.ino b/libraries/doom/examples/Doom/Doom.ino index 2c6b25f21..ae9a99dae 100644 --- a/libraries/doom/examples/Doom/Doom.ino +++ b/libraries/doom/examples/Doom/Doom.ino @@ -2,7 +2,7 @@ Arduino wrapper for DoomGeneric Mouse and keyboard controls are not implemented at the moment. - To use the internal QSPI flash as storage, run WiFiFirmwareUpdater + To use the internal QSPI flash as storage, run QSPIFormat sketch once to create the partitions, AccessFlashAsUSBDisk to expose the QSPI flash as a USB disk, copy DOOM1.WAD in the biggest partition, flash this sketch and you are ready to go :) */ diff --git a/mbed-os-to-arduino b/mbed-os-to-arduino index 1c077227a..244ccba80 100755 --- a/mbed-os-to-arduino +++ b/mbed-os-to-arduino @@ -198,15 +198,21 @@ generate_flags () { .pdm_section (NOLOAD) : {\n \ . = ABSOLUTE(0x3800FC00);\n \ *(.pdm_buffer)\n \ - } > RAM_D3" + } > RAM_D3\n \ + _dtcm_lma = __etext + SIZEOF(.data);\n \ + .dtcm : AT(_dtcm_lma) {\n \ + _sdtcm = .;\n \ + *(.dtcm*)\n \ + _edtcm = .;\n \ + } > DTCMRAM" sed -i "s?.heap (COPY):?${OPENAMP_SECTION}\n .heap (COPY):?g" $ARDUINOVARIANT/linker_script.ld OPENAMP_REGIONS="__OPENAMP_region_start__ = 0x38000400;\n__OPENAMP_region_end__ = 0x38000400 + LENGTH(RAM_D3) - 1K;" sed -i "s?ENTRY(Reset_Handler)?${OPENAMP_REGIONS}\nENTRY(Reset_Handler)?g" $ARDUINOVARIANT/linker_script.ld fi echo "Patching linker scripts" sed -i 's/0x8100000/CM4_BINARY_START/g' "$ARDUINOVARIANT"/linker_script.ld - sed -i 's/LENGTH = 0x100000/LENGTH = CM4_BINARY_END - CM4_BINARY_START/g' "$ARDUINOVARIANT"/linker_script.ld - sed -i 's/LENGTH = 0xc0000/LENGTH = CM4_BINARY_START - 0x8040000/g' "$ARDUINOVARIANT"/linker_script.ld + sed -i 's/LENGTH = 0x200000/LENGTH = CM4_BINARY_END - CM4_BINARY_START/g' "$ARDUINOVARIANT"/linker_script.ld + sed -i 's/LENGTH = 0x1c0000/LENGTH = CM4_BINARY_START - 0x8040000/g' "$ARDUINOVARIANT"/linker_script.ld fi if [[ $ARDUINOVARIANT == *NANO_RP2040* ]]; then set +e diff --git a/package_full.sh b/package_full.sh index dc4d8d669..76bf46de8 100755 --- a/package_full.sh +++ b/package_full.sh @@ -1,5 +1,5 @@ #Get version from git(hub) tag -export VERSION="3.2.0" +export VERSION="3.3.0" FLAVOURS=`ls *.variables` diff --git a/patches/0173-STM32H7-arduino-give-full-2MB-flash-for-pure-CM7-app.patch b/patches/0173-STM32H7-arduino-give-full-2MB-flash-for-pure-CM7-app.patch new file mode 100644 index 000000000..70d748487 --- /dev/null +++ b/patches/0173-STM32H7-arduino-give-full-2MB-flash-for-pure-CM7-app.patch @@ -0,0 +1,44 @@ +From 7ef7506b2752eb14d9f5c08ea079e809e43c97fc Mon Sep 17 00:00:00 2001 +From: Martino Facchin +Date: Tue, 19 Jul 2022 11:18:08 +0200 +Subject: [PATCH] STM32H7: arduino: give full 2MB flash for pure CM7 + applications + +--- + targets/targets.json | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/targets/targets.json b/targets/targets.json +index fa9880e3ca..c998e1d8f0 100644 +--- a/targets/targets.json ++++ b/targets/targets.json +@@ -3362,7 +3362,7 @@ + ], + "core": "Cortex-M7FD", + "mbed_rom_start": "0x08000000", +- "mbed_rom_size": "0x100000", ++ "mbed_rom_size": "0x200000", + "mbed_ram_start": "0x24000000", + "mbed_ram_size": "0x80000", + "macros_add": [ +@@ -3494,7 +3494,7 @@ + "inherits": ["PORTENTA_H7"], + "core": "Cortex-M7FD", + "mbed_rom_start": "0x08000000", +- "mbed_rom_size" : "0x100000", ++ "mbed_rom_size" : "0x200000", + "mbed_ram_start": "0x24000000", + "mbed_ram_size" : "0x80000", + "extra_labels_add": [ +@@ -3540,7 +3540,7 @@ + "overrides": { + "system_power_supply": "PWR_LDO_SUPPLY", + "clock_source": "USE_PLL_HSE_EXTC", +- "lse_available": 0, ++ "lse_available": 1, + "lpticker_delay_ticks": 0, + "network-default-interface-type": "WIFI", + "i2c_timing_value_algo": true, +-- +2.36.0 + diff --git a/patches/0174-WHD-force-disconnect-on-roamed-due-to-low-RSSI.patch b/patches/0174-WHD-force-disconnect-on-roamed-due-to-low-RSSI.patch new file mode 100644 index 000000000..059350e93 --- /dev/null +++ b/patches/0174-WHD-force-disconnect-on-roamed-due-to-low-RSSI.patch @@ -0,0 +1,28 @@ +From 7d59d1e04f2cc6872d07c30cb6f66457dbd383f2 Mon Sep 17 00:00:00 2001 +From: pennam +Date: Thu, 11 Aug 2022 10:29:34 +0200 +Subject: [PATCH] WHD: force disconnect on roamed due to low RSSI + +--- + .../drivers/emac/COMPONENT_WHD/interface/WhdSTAInterface.cpp | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/connectivity/drivers/emac/COMPONENT_WHD/interface/WhdSTAInterface.cpp b/connectivity/drivers/emac/COMPONENT_WHD/interface/WhdSTAInterface.cpp +index 6fec15adb0..509a2c0981 100644 +--- a/connectivity/drivers/emac/COMPONENT_WHD/interface/WhdSTAInterface.cpp ++++ b/connectivity/drivers/emac/COMPONENT_WHD/interface/WhdSTAInterface.cpp +@@ -178,7 +178,10 @@ static void *whd_wifi_link_state_change_handler(whd_interface_t ifp, + (event_header->event_type == WLC_E_DISASSOC_IND) || + ((event_header->event_type == WLC_E_PSK_SUP) && + (event_header->status == WLC_SUP_KEYED) && +- (event_header->reason == WLC_E_SUP_DEAUTH))) { ++ (event_header->reason == WLC_E_SUP_DEAUTH)) || ++ ((event_header->event_type == WLC_E_LINK) && ++ (event_header->status == WLC_E_STATUS_SUCCESS) && ++ (event_header->reason == WLC_E_REASON_LOW_RSSI))) { + whd_emac_wifi_link_state_changed(ifp, WHD_FALSE); + return handler_user_data; + } +-- +2.37.1 + diff --git a/patches/0175-STM32-lpticker-allow-dynamic-configuration.patch b/patches/0175-STM32-lpticker-allow-dynamic-configuration.patch new file mode 100644 index 000000000..e4d296a2d --- /dev/null +++ b/patches/0175-STM32-lpticker-allow-dynamic-configuration.patch @@ -0,0 +1,194 @@ +From ff38953e8e678c697b52ddbe62bc99fe445a1c74 Mon Sep 17 00:00:00 2001 +From: Martino Facchin +Date: Thu, 7 Oct 2021 17:00:27 +0200 +Subject: [PATCH 175/176] STM32: lpticker: allow dynamic configuration + +Step1: allow automatic fallback to LSI if LSE is not functional +Step2: expose two reconfiguration APIs, so the user can check if LSE is precise enough and eventually revert to LSI +--- + targets/TARGET_STM/lp_ticker.c | 121 ++++++++++++++++++++++----------- + 1 file changed, 83 insertions(+), 38 deletions(-) + +diff --git a/targets/TARGET_STM/lp_ticker.c b/targets/TARGET_STM/lp_ticker.c +index d5292566e5..6dc806ccf6 100644 +--- a/targets/TARGET_STM/lp_ticker.c ++++ b/targets/TARGET_STM/lp_ticker.c +@@ -126,20 +126,35 @@ + + + LPTIM_HandleTypeDef LptimHandle; ++static uint8_t using_lse = MBED_CONF_TARGET_LSE_AVAILABLE; + +-const ticker_info_t *lp_ticker_get_info() ++static const ticker_info_t *lp_ticker_get_info_lse() + { +- static const ticker_info_t info = { +-#if MBED_CONF_TARGET_LSE_AVAILABLE ++ const static ticker_info_t info = { + LSE_VALUE / MBED_CONF_TARGET_LPTICKER_LPTIM_CLOCK, +-#else ++ 16 ++ }; ++ return &info; ++} ++ ++static const ticker_info_t *lp_ticker_get_info_lsi() ++{ ++ const static ticker_info_t info = { + LSI_VALUE / MBED_CONF_TARGET_LPTICKER_LPTIM_CLOCK, +-#endif + 16 + }; + return &info; + } + ++const ticker_info_t *lp_ticker_get_info() ++{ ++ if (using_lse) { ++ return lp_ticker_get_info_lse(); ++ } else { ++ return lp_ticker_get_info_lsi(); ++ } ++} ++ + volatile uint8_t lp_Fired = 0; + /* Flag and stored counter to handle delayed programing at low level */ + volatile bool lp_delayed_prog = false; +@@ -154,71 +169,101 @@ volatile bool sleep_manager_locked = false; + static int LPTICKER_inited = 0; + static void LPTIM_IRQHandler(void); + +-void lp_ticker_init(void) +-{ +- /* Check if LPTIM is already configured */ +- if (LPTICKER_inited) { +- lp_ticker_disable_interrupt(); +- return; +- } +- LPTICKER_inited = 1; +- +- RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = {0}; +- RCC_OscInitTypeDef RCC_OscInitStruct = {0}; +- +-#if MBED_CONF_TARGET_LSE_AVAILABLE ++static void configureClocksLSE(RCC_PeriphCLKInitTypeDef* RCC_PeriphCLKInitStruct, ++ RCC_OscInitTypeDef* RCC_OscInitStruct){ + + /* Enable LSE clock */ +- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; ++ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_LSE; + #if MBED_CONF_TARGET_LSE_BYPASS +- RCC_OscInitStruct.LSEState = RCC_LSE_BYPASS; ++ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + #else +- RCC_OscInitStruct.LSEState = RCC_LSE_ON; ++ RCC_OscInitStruct->LSEState = RCC_LSE_ON; + #endif +- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; ++ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_NONE; + + /* Select the LSE clock as LPTIM peripheral clock */ +- RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM; ++ RCC_PeriphCLKInitStruct->PeriphClockSelection = RCC_PERIPHCLK_LPTIM; + #if (TARGET_STM32L0) +- RCC_PeriphCLKInitStruct.LptimClockSelection = RCC_LPTIMCLKSOURCE_LSE; ++ RCC_PeriphCLKInitStruct->LptimClockSelection = RCC_LPTIMCLKSOURCE_LSE; + #else + #if (LPTIM_MST_BASE == LPTIM1_BASE) +- RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIMCLKSOURCE_LSE; ++ RCC_PeriphCLKInitStruct->Lptim1ClockSelection = RCC_LPTIMCLKSOURCE_LSE; + #elif (LPTIM_MST_BASE == LPTIM3_BASE) || (LPTIM_MST_BASE == LPTIM4_BASE) || (LPTIM_MST_BASE == LPTIM5_BASE) +- RCC_PeriphCLKInitStruct.Lptim345ClockSelection = RCC_LPTIMCLKSOURCE_LSE; ++ RCC_PeriphCLKInitStruct->Lptim345ClockSelection = RCC_LPTIMCLKSOURCE_LSE; + #endif /* LPTIM_MST_BASE == LPTIM1 */ + #endif /* TARGET_STM32L0 */ +-#else /* MBED_CONF_TARGET_LSE_AVAILABLE */ ++} ++ ++static void configureClocksLSI(RCC_PeriphCLKInitTypeDef* RCC_PeriphCLKInitStruct, ++ RCC_OscInitTypeDef* RCC_OscInitStruct){ + + /* Enable LSI clock */ + #if TARGET_STM32WB +- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1; ++ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_LSI1; + #else +- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; ++ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_LSI; + #endif +- RCC_OscInitStruct.LSIState = RCC_LSI_ON; +- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; ++ RCC_OscInitStruct->LSIState = RCC_LSI_ON; ++ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_NONE; + + /* Select the LSI clock as LPTIM peripheral clock */ +- RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM; ++ RCC_PeriphCLKInitStruct->PeriphClockSelection = RCC_PERIPHCLK_LPTIM; + #if (TARGET_STM32L0) +- RCC_PeriphCLKInitStruct.LptimClockSelection = RCC_LPTIMCLKSOURCE_LSI; ++ RCC_PeriphCLKInitStruct->LptimClockSelection = RCC_LPTIMCLKSOURCE_LSI; + #else + #if (LPTIM_MST_BASE == LPTIM1_BASE) +- RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIMCLKSOURCE_LSI; ++ RCC_PeriphCLKInitStruct->Lptim1ClockSelection = RCC_LPTIMCLKSOURCE_LSI; + #elif (LPTIM_MST_BASE == LPTIM3_BASE) || (LPTIM_MST_BASE == LPTIM4_BASE) || (LPTIM_MST_BASE == LPTIM5_BASE) +- RCC_PeriphCLKInitStruct.Lptim345ClockSelection = RCC_LPTIMCLKSOURCE_LSI; ++ RCC_PeriphCLKInitStruct->Lptim345ClockSelection = RCC_LPTIMCLKSOURCE_LSI; + #endif /* LPTIM_MST_BASE == LPTIM1 */ + #endif /* TARGET_STM32L0 */ ++} ++ ++void lp_ticker_reconfigure_with_lsi() { ++ lp_ticker_disable_interrupt(); ++ LPTICKER_inited = 0; ++ using_lse = 0; ++ lp_ticker_init(); ++} ++ ++void lp_ticker_reconfigure_with_lse() { ++ lp_ticker_disable_interrupt(); ++ LPTICKER_inited = 0; ++ using_lse = 1; ++ lp_ticker_init(); ++} ++ ++void lp_ticker_init(void) ++{ ++ /* Check if LPTIM is already configured */ ++ if (LPTICKER_inited) { ++ lp_ticker_disable_interrupt(); ++ return; ++ } ++ LPTICKER_inited = 1; ++ ++ RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = {0}; ++ RCC_OscInitTypeDef RCC_OscInitStruct = {0}; ++ ++ if (using_lse) { ++ configureClocksLSE(&RCC_PeriphCLKInitStruct, &RCC_OscInitStruct); ++ } else { ++ configureClocksLSI(&RCC_PeriphCLKInitStruct, &RCC_OscInitStruct); ++ } + +-#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ + #if defined(DUAL_CORE) && (TARGET_STM32H7) + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { + } + #endif /* DUAL_CORE */ + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { +- error("HAL_RCC_OscConfig ERROR\n"); +- return; ++ ++ // retry with LSI ++ using_lse = 0; ++ configureClocksLSI(&RCC_PeriphCLKInitStruct, &RCC_OscInitStruct); ++ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { ++ error("HAL_RCC_OscConfig ERROR\n"); ++ return; ++ } + } + + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct) != HAL_OK) { +-- +2.37.1 + diff --git a/patches/0176-Portenta-use-LSE-for-low-power-ticker.patch b/patches/0176-Portenta-use-LSE-for-low-power-ticker.patch new file mode 100644 index 000000000..3f4ef2873 --- /dev/null +++ b/patches/0176-Portenta-use-LSE-for-low-power-ticker.patch @@ -0,0 +1,25 @@ +From 0c7a86e2041971dc3d247c54e85870b6056c03fb Mon Sep 17 00:00:00 2001 +From: Martino Facchin +Date: Thu, 7 Oct 2021 17:02:45 +0200 +Subject: [PATCH 176/176] Portenta: use LSE for low power ticker + +--- + targets/targets.json | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/targets/targets.json b/targets/targets.json +index c998e1d8f0..7274f5d03e 100644 +--- a/targets/targets.json ++++ b/targets/targets.json +@@ -3483,7 +3483,7 @@ + "overrides": { + "system_power_supply": "PWR_SMPS_1V8_SUPPLIES_LDO", + "clock_source": "USE_PLL_HSE_EXTC", +- "lse_available": 0, ++ "lse_available": 1, + "lpticker_delay_ticks": 0, + "network-default-interface-type": "ETHERNET", + "i2c_timing_value_algo": true +-- +2.37.1 + diff --git a/platform.txt b/platform.txt index ae0e4d83d..ae7acc43b 100644 --- a/platform.txt +++ b/platform.txt @@ -96,8 +96,6 @@ recipe.objcopy.bin.pattern="{compiler.path}{compiler.elf2hex.cmd}" {compiler.elf ## Create output (hex file) recipe.objcopy.hex.pattern="{compiler.path}{compiler.elf2hex.cmd}" {compiler.elf2hex.hex.flags} {compiler.elf2hex.extra_flags} "{build.path}/{build.project_name}.elf" "{build.path}/{build.project_name}.hex" -## Create output secure image (bin file) -recipe.hooks.objcopy.postobjcopy.1.pattern={build.postbuild.cmd} ## Compute size recipe.size.pattern="{compiler.path}{compiler.size.cmd}" -A "{build.path}/{build.project_name}.elf" recipe.size.regex.data=^(?:\.data|\.bss)\s+([0-9]+).* diff --git a/variants/ARDUINO_NANO33BLE/defines.txt b/variants/ARDUINO_NANO33BLE/defines.txt index 327e156db..18bcf0e82 100644 --- a/variants/ARDUINO_NANO33BLE/defines.txt +++ b/variants/ARDUINO_NANO33BLE/defines.txt @@ -28,12 +28,13 @@ -DDEVICE_TRNG=1 -DDEVICE_USBDEVICE=1 -DDEVICE_USTICKER=1 +-DDEVICE_WATCHDOG=1 -DFEATURE_BLE=1 -DFEATURE_CRYPTOCELL310=1 -DFEATURE_STORAGE=1 -D__FPU_PRESENT=1 -D__MBED__=1 --DMBED_BUILD_TIMESTAMP=1648633245.220674 +-DMBED_BUILD_TIMESTAMP=1662124743.5782256 -D__MBED_CMSIS_RTOS_CM -DMBED_MPU_CUSTOM -DMBED_TICKLESS @@ -65,6 +66,6 @@ -DWSF_MAX_HANDLERS=10 -DMBED_NO_GLOBAL_USING_DIRECTIVE=1 -DCORE_MAJOR=3 --DCORE_MINOR=0 --DCORE_PATCH=1 +-DCORE_MINOR=3 +-DCORE_PATCH=0 -DUSE_ARDUINO_PINOUT diff --git a/variants/ARDUINO_NANO33BLE/libs/libmbed.a b/variants/ARDUINO_NANO33BLE/libs/libmbed.a index c254fff98..7214053f5 100644 Binary files a/variants/ARDUINO_NANO33BLE/libs/libmbed.a and b/variants/ARDUINO_NANO33BLE/libs/libmbed.a differ diff --git a/variants/ARDUINO_NANO33BLE/mbed_config.h b/variants/ARDUINO_NANO33BLE/mbed_config.h index 3fd3d405e..5cf0ce054 100644 --- a/variants/ARDUINO_NANO33BLE/mbed_config.h +++ b/variants/ARDUINO_NANO33BLE/mbed_config.h @@ -223,6 +223,7 @@ #define MBED_CONF_LWIP_MEM_SIZE 1600 // set by library:lwip #define MBED_CONF_LWIP_ND6_QUEUEING 0 // set by library:lwip #define MBED_CONF_LWIP_ND6_RDNSS_MAX_DNS_SERVERS 0 // set by library:lwip +#define MBED_CONF_LWIP_NETBUF_RECVINFO_ENABLED 0 // set by library:lwip #define MBED_CONF_LWIP_NUM_NETBUF 8 // set by library:lwip #define MBED_CONF_LWIP_NUM_PBUF 8 // set by library:lwip #define MBED_CONF_LWIP_PBUF_POOL_SIZE 5 // set by library:lwip @@ -383,6 +384,7 @@ #define LL_MAX_PER_SCAN 3 // defined by library:cordio-nordic-ll #define MBEDTLS_CIPHER_MODE_CTR // defined by library:SecureStore #define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 8 // defined by application +#define NRFX_WDT_ENABLED 1 // defined by application #define NSAPI_PPP_AVAILABLE (MBED_CONF_PPP_ENABLED || MBED_CONF_LWIP_PPP_ENABLED) // defined by library:ppp #define NSDYNMEM_TRACKER_ENABLED MBED_CONF_NANOSTACK_LIBSERVICE_NSDYNMEM_TRACKER_ENABLED // defined by library:nanostack-libservice #define UNITY_INCLUDE_CONFIG_H // defined by library:utest diff --git a/variants/EDGE_CONTROL/defines.txt b/variants/EDGE_CONTROL/defines.txt index 60b9aeee0..8ecae3c93 100644 --- a/variants/EDGE_CONTROL/defines.txt +++ b/variants/EDGE_CONTROL/defines.txt @@ -38,7 +38,7 @@ -DFEATURE_STORAGE=1 -D__FPU_PRESENT=1 -D__MBED__=1 --DMBED_BUILD_TIMESTAMP=1648633439.992252 +-DMBED_BUILD_TIMESTAMP=1662124896.2555702 -D__MBED_CMSIS_RTOS_CM -DMBED_MPU_CUSTOM -DMBED_TICKLESS @@ -70,6 +70,6 @@ -DWSF_MAX_HANDLERS=10 -DMBED_NO_GLOBAL_USING_DIRECTIVE=1 -DCORE_MAJOR=3 --DCORE_MINOR=0 --DCORE_PATCH=1 +-DCORE_MINOR=3 +-DCORE_PATCH=0 -DUSE_ARDUINO_PINOUT diff --git a/variants/EDGE_CONTROL/libs/libmbed.a b/variants/EDGE_CONTROL/libs/libmbed.a index 223a1fc99..f048e8a3d 100644 Binary files a/variants/EDGE_CONTROL/libs/libmbed.a and b/variants/EDGE_CONTROL/libs/libmbed.a differ diff --git a/variants/EDGE_CONTROL/mbed_config.h b/variants/EDGE_CONTROL/mbed_config.h index 8ebeb47d4..bbaf8eed7 100644 --- a/variants/EDGE_CONTROL/mbed_config.h +++ b/variants/EDGE_CONTROL/mbed_config.h @@ -222,6 +222,7 @@ #define MBED_CONF_LWIP_MEM_SIZE 1600 // set by library:lwip #define MBED_CONF_LWIP_ND6_QUEUEING 0 // set by library:lwip #define MBED_CONF_LWIP_ND6_RDNSS_MAX_DNS_SERVERS 0 // set by library:lwip +#define MBED_CONF_LWIP_NETBUF_RECVINFO_ENABLED 0 // set by library:lwip #define MBED_CONF_LWIP_NUM_NETBUF 8 // set by library:lwip #define MBED_CONF_LWIP_NUM_PBUF 8 // set by library:lwip #define MBED_CONF_LWIP_PBUF_POOL_SIZE 5 // set by library:lwip diff --git a/variants/NANO_RP2040_CONNECT/defines.txt b/variants/NANO_RP2040_CONNECT/defines.txt index 8f2364922..f7b1b20d9 100644 --- a/variants/NANO_RP2040_CONNECT/defines.txt +++ b/variants/NANO_RP2040_CONNECT/defines.txt @@ -20,9 +20,10 @@ -DDEVICE_USTICKER=1 -DDEVICE_WATCHDOG=1 -D__MBED__=1 --DMBED_BUILD_TIMESTAMP=1648633222.737337 +-DMBED_BUILD_TIMESTAMP=1662124722.8055787 -D__MBED_CMSIS_RTOS_CM -DMBED_MPU_CUSTOM +-DMBEDTLS_ENTROPY_NV_SEED -DPICO_FLASH_SIZE_BYTES=16*1024*1024 -DPICO_NO_BINARY_INFO=1 -DPICO_ON_DEVICE=1 @@ -44,6 +45,6 @@ -DTOOLCHAIN_GCC_ARM -DMBED_NO_GLOBAL_USING_DIRECTIVE=1 -DCORE_MAJOR=3 --DCORE_MINOR=0 --DCORE_PATCH=1 +-DCORE_MINOR=3 +-DCORE_PATCH=0 -DUSE_ARDUINO_PINOUT diff --git a/variants/NANO_RP2040_CONNECT/includes.txt b/variants/NANO_RP2040_CONNECT/includes.txt index baf81951d..f42afe795 100644 --- a/variants/NANO_RP2040_CONNECT/includes.txt +++ b/variants/NANO_RP2040_CONNECT/includes.txt @@ -233,6 +233,9 @@ -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include +-iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_usb_reset_interface +-iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_usb_reset_interface/include +-iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_usb_reset_interface/include/pico -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico @@ -262,6 +265,9 @@ -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/include -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/include/hardware +-iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_exception +-iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_exception/include +-iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_exception/include/hardware -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/include -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/include/hardware diff --git a/variants/NANO_RP2040_CONNECT/libs/libmbed.a b/variants/NANO_RP2040_CONNECT/libs/libmbed.a index 78b13b7ac..ce083bacb 100644 Binary files a/variants/NANO_RP2040_CONNECT/libs/libmbed.a and b/variants/NANO_RP2040_CONNECT/libs/libmbed.a differ diff --git a/variants/NANO_RP2040_CONNECT/mbed_config.h b/variants/NANO_RP2040_CONNECT/mbed_config.h index de0e79601..08a14dc14 100644 --- a/variants/NANO_RP2040_CONNECT/mbed_config.h +++ b/variants/NANO_RP2040_CONNECT/mbed_config.h @@ -162,6 +162,7 @@ #define MBED_CONF_LWIP_MEM_SIZE 1600 // set by library:lwip #define MBED_CONF_LWIP_ND6_QUEUEING 0 // set by library:lwip #define MBED_CONF_LWIP_ND6_RDNSS_MAX_DNS_SERVERS 0 // set by library:lwip +#define MBED_CONF_LWIP_NETBUF_RECVINFO_ENABLED 0 // set by library:lwip #define MBED_CONF_LWIP_NUM_NETBUF 8 // set by library:lwip #define MBED_CONF_LWIP_NUM_PBUF 8 // set by library:lwip #define MBED_CONF_LWIP_PBUF_POOL_SIZE 5 // set by library:lwip diff --git a/variants/NICLA/defines.txt b/variants/NICLA/defines.txt index ec2d27a11..7978fc480 100644 --- a/variants/NICLA/defines.txt +++ b/variants/NICLA/defines.txt @@ -29,10 +29,11 @@ -DDEVICE_SYSTICK_CLK_OFF_DURING_SLEEP=1 -DDEVICE_TRNG=1 -DDEVICE_USTICKER=1 +-DDEVICE_WATCHDOG=1 -DFEATURE_BLE=1 -D__FPU_PRESENT=1 -D__MBED__=1 --DMBED_BUILD_TIMESTAMP=1648633481.6325634 +-DMBED_BUILD_TIMESTAMP=1662124928.8471718 -D__MBED_CMSIS_RTOS_CM -DMBED_MPU_CUSTOM -DMBED_TICKLESS @@ -75,6 +76,6 @@ -DTOOLCHAIN_GCC_ARM -DMBED_NO_GLOBAL_USING_DIRECTIVE=1 -DCORE_MAJOR=3 --DCORE_MINOR=0 --DCORE_PATCH=1 +-DCORE_MINOR=3 +-DCORE_PATCH=0 -DUSE_ARDUINO_PINOUT diff --git a/variants/NICLA/libs/libmbed.a b/variants/NICLA/libs/libmbed.a index 7d3b7b61e..3125ef77e 100644 Binary files a/variants/NICLA/libs/libmbed.a and b/variants/NICLA/libs/libmbed.a differ diff --git a/variants/NICLA/mbed_config.h b/variants/NICLA/mbed_config.h index a87e1f3de..0f7a8772d 100644 --- a/variants/NICLA/mbed_config.h +++ b/variants/NICLA/mbed_config.h @@ -220,6 +220,7 @@ #define MBED_CONF_LWIP_MEM_SIZE 1600 // set by library:lwip #define MBED_CONF_LWIP_ND6_QUEUEING 0 // set by library:lwip #define MBED_CONF_LWIP_ND6_RDNSS_MAX_DNS_SERVERS 0 // set by library:lwip +#define MBED_CONF_LWIP_NETBUF_RECVINFO_ENABLED 0 // set by library:lwip #define MBED_CONF_LWIP_NUM_NETBUF 8 // set by library:lwip #define MBED_CONF_LWIP_NUM_PBUF 8 // set by library:lwip #define MBED_CONF_LWIP_PBUF_POOL_SIZE 5 // set by library:lwip @@ -388,6 +389,7 @@ #define MBED_MEM_TRACING_ENABLED 1 // defined by application #define MBED_STACK_STATS_ENABLED 1 // defined by application #define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 8 // defined by application +#define NRFX_WDT_ENABLED 1 // defined by application #define NSAPI_PPP_AVAILABLE (MBED_CONF_PPP_ENABLED || MBED_CONF_LWIP_PPP_ENABLED) // defined by library:ppp #define NSDYNMEM_TRACKER_ENABLED MBED_CONF_NANOSTACK_LIBSERVICE_NSDYNMEM_TRACKER_ENABLED // defined by library:nanostack-libservice #define UNITY_INCLUDE_CONFIG_H // defined by library:utest diff --git a/variants/NICLA_VISION/cflags.txt b/variants/NICLA_VISION/cflags.txt index 465365d9a..ac9f710b6 100644 --- a/variants/NICLA_VISION/cflags.txt +++ b/variants/NICLA_VISION/cflags.txt @@ -1,10 +1,14 @@ -c -std=gnu11 -DAPPLICATION_ADDR=0x8040000 --DAPPLICATION_SIZE=0xc0000 +-DAPPLICATION_RAM_ADDR=0x24000000 +-DAPPLICATION_RAM_SIZE=0x80000 +-DAPPLICATION_SIZE=0x1c0000 +-DMBED_RAM1_SIZE=0x80000 +-DMBED_RAM1_START=0x24000000 -DMBED_RAM_SIZE=0x80000 -DMBED_RAM_START=0x24000000 --DMBED_ROM_SIZE=0x100000 +-DMBED_ROM_SIZE=0x200000 -DMBED_ROM_START=0x8000000 -DMBED_TRAP_ERRORS_ENABLED=1 -Os diff --git a/variants/NICLA_VISION/cxxflags.txt b/variants/NICLA_VISION/cxxflags.txt index 11ebe5d4d..2dec88933 100644 --- a/variants/NICLA_VISION/cxxflags.txt +++ b/variants/NICLA_VISION/cxxflags.txt @@ -3,10 +3,14 @@ -fno-rtti -std=gnu++14 -DAPPLICATION_ADDR=0x8040000 --DAPPLICATION_SIZE=0xc0000 +-DAPPLICATION_RAM_ADDR=0x24000000 +-DAPPLICATION_RAM_SIZE=0x80000 +-DAPPLICATION_SIZE=0x1c0000 +-DMBED_RAM1_SIZE=0x80000 +-DMBED_RAM1_START=0x24000000 -DMBED_RAM_SIZE=0x80000 -DMBED_RAM_START=0x24000000 --DMBED_ROM_SIZE=0x100000 +-DMBED_ROM_SIZE=0x200000 -DMBED_ROM_START=0x8000000 -DMBED_TRAP_ERRORS_ENABLED=1 -Os diff --git a/variants/NICLA_VISION/defines.txt b/variants/NICLA_VISION/defines.txt index e27303940..034ce4fee 100644 --- a/variants/NICLA_VISION/defines.txt +++ b/variants/NICLA_VISION/defines.txt @@ -45,7 +45,7 @@ -DFLOW_SILENT -D__FPU_PRESENT=1 -D__MBED__=1 --DMBED_BUILD_TIMESTAMP=1648633520.2281349 +-DMBED_BUILD_TIMESTAMP=1662124959.407307 -D__MBED_CMSIS_RTOS_CM -DMBED_TICKLESS -DMBEDTLS_FS_IO @@ -84,6 +84,6 @@ -DVIRTIO_MASTER_ONLY -DMBED_NO_GLOBAL_USING_DIRECTIVE=1 -DCORE_MAJOR=3 --DCORE_MINOR=0 --DCORE_PATCH=1 +-DCORE_MINOR=3 +-DCORE_PATCH=0 -DUSE_ARDUINO_PINOUT diff --git a/variants/NICLA_VISION/ldflags.txt b/variants/NICLA_VISION/ldflags.txt index 8a5233107..383d6ec49 100644 --- a/variants/NICLA_VISION/ldflags.txt +++ b/variants/NICLA_VISION/ldflags.txt @@ -1,9 +1,11 @@ --DMBED_APP_SIZE=0xc0000 +-DMBED_APP_SIZE=0x1c0000 -DMBED_APP_START=0x8040000 -DMBED_BOOT_STACK_SIZE=1024 +-DMBED_RAM1_SIZE=0x80000 +-DMBED_RAM1_START=0x24000000 -DMBED_RAM_SIZE=0x80000 -DMBED_RAM_START=0x24000000 --DMBED_ROM_SIZE=0x100000 +-DMBED_ROM_SIZE=0x200000 -DMBED_ROM_START=0x8000000 -DXIP_ENABLE=0 -Wl,--gc-sections diff --git a/variants/NICLA_VISION/libs/libmbed.a b/variants/NICLA_VISION/libs/libmbed.a index 8d98fd678..ad50cc08f 100644 Binary files a/variants/NICLA_VISION/libs/libmbed.a and b/variants/NICLA_VISION/libs/libmbed.a differ diff --git a/variants/NICLA_VISION/linker_script.ld b/variants/NICLA_VISION/linker_script.ld index aa812677c..0901b516c 100644 --- a/variants/NICLA_VISION/linker_script.ld +++ b/variants/NICLA_VISION/linker_script.ld @@ -1,6 +1,6 @@ MEMORY { - FLASH (rx) : ORIGIN = 0x8040000, LENGTH = 0xc0000 + FLASH (rx) : ORIGIN = 0x8040000, LENGTH = 0x1c0000 DTCMRAM (rwx) : ORIGIN = 0x20000000 + (((166 * 4) + 7) & 0xFFFFFFF8), LENGTH = 128K - (((166 * 4) + 7) & 0xFFFFFFF8) RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 0x80000 RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K diff --git a/variants/NICLA_VISION/mbed_config.h b/variants/NICLA_VISION/mbed_config.h index 42f18a8f1..3cb8deaa9 100644 --- a/variants/NICLA_VISION/mbed_config.h +++ b/variants/NICLA_VISION/mbed_config.h @@ -216,6 +216,7 @@ #define MBED_CONF_LWIP_MEM_SIZE 16000 // set by library:lwip[NICLA_VISION] #define MBED_CONF_LWIP_ND6_QUEUEING 0 // set by library:lwip #define MBED_CONF_LWIP_ND6_RDNSS_MAX_DNS_SERVERS 0 // set by library:lwip +#define MBED_CONF_LWIP_NETBUF_RECVINFO_ENABLED 0 // set by library:lwip #define MBED_CONF_LWIP_NUM_NETBUF 8 // set by library:lwip #define MBED_CONF_LWIP_NUM_PBUF 8 // set by library:lwip #define MBED_CONF_LWIP_PBUF_POOL_SIZE 5 // set by library:lwip @@ -379,7 +380,7 @@ #define MBED_CONF_TARGET_LPTICKER_LPTIM 1 // set by target:MCU_STM32H7 #define MBED_CONF_TARGET_LPTICKER_LPTIM_CLOCK 1 // set by target:MCU_STM32 #define MBED_CONF_TARGET_LPUART_CLOCK_SOURCE USE_LPUART_CLK_HSI // set by target:NICLA_VISION -#define MBED_CONF_TARGET_LSE_AVAILABLE 0 // set by target:NICLA_VISION +#define MBED_CONF_TARGET_LSE_AVAILABLE 1 // set by target:NICLA_VISION #define MBED_CONF_TARGET_LSE_BYPASS 1 // set by target:NICLA_VISION #define MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL RCC_LSEDRIVE_LOW // set by target:MCU_STM32H7 #define MBED_CONF_TARGET_MPU_ROM_END 0x0fffffff // set by target:Target diff --git a/variants/PORTENTA_H7_M4/defines.txt b/variants/PORTENTA_H7_M4/defines.txt index e07df3bd5..8131b1a11 100644 --- a/variants/PORTENTA_H7_M4/defines.txt +++ b/variants/PORTENTA_H7_M4/defines.txt @@ -44,7 +44,7 @@ -DFEATURE_BLE=1 -D__FPU_PRESENT=1 -D__MBED__=1 --DMBED_BUILD_TIMESTAMP=1648633376.427339 +-DMBED_BUILD_TIMESTAMP=1662124845.668187 -D__MBED_CMSIS_RTOS_CM -DMBED_MPU_CUSTOM -DMBED_TICKLESS @@ -83,6 +83,6 @@ -DVIRTIO_SLAVE_ONLY -DMBED_NO_GLOBAL_USING_DIRECTIVE=1 -DCORE_MAJOR=3 --DCORE_MINOR=0 --DCORE_PATCH=1 +-DCORE_MINOR=3 +-DCORE_PATCH=0 -DUSE_ARDUINO_PINOUT diff --git a/variants/PORTENTA_H7_M4/libs/libmbed.a b/variants/PORTENTA_H7_M4/libs/libmbed.a index e54b9fe4f..d85231438 100644 Binary files a/variants/PORTENTA_H7_M4/libs/libmbed.a and b/variants/PORTENTA_H7_M4/libs/libmbed.a differ diff --git a/variants/PORTENTA_H7_M4/linker_script.ld b/variants/PORTENTA_H7_M4/linker_script.ld index 33fc73c17..4c2af2ee9 100644 --- a/variants/PORTENTA_H7_M4/linker_script.ld +++ b/variants/PORTENTA_H7_M4/linker_script.ld @@ -1,6 +1,6 @@ MEMORY { - FLASH (rx) : ORIGIN = CM4_BINARY_START, LENGTH = CM4_BINARY_END - CM4_BINARY_START + FLASH (rx) : ORIGIN = CM4_BINARY_START, LENGTH = 0x100000 RAM (rwx) : ORIGIN = 0x10000000 + (((166 * 4) + 7) & 0xFFFFFFF8), LENGTH = 0x48000 - (((166 * 4) + 7) & 0xFFFFFFF8) RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K } @@ -93,6 +93,12 @@ SECTIONS . = ABSOLUTE(0x3800FC00); *(.pdm_buffer) } > RAM_D3 + _dtcm_lma = __etext + SIZEOF(.data); + .dtcm : AT(_dtcm_lma) { + _sdtcm = .; + *(.dtcm*) + _edtcm = .; + } > DTCMRAM .heap (COPY): { __end__ = .; diff --git a/variants/PORTENTA_H7_M4/mbed_config.h b/variants/PORTENTA_H7_M4/mbed_config.h index 7a5ffc8d1..4fa4b5d51 100644 --- a/variants/PORTENTA_H7_M4/mbed_config.h +++ b/variants/PORTENTA_H7_M4/mbed_config.h @@ -216,6 +216,7 @@ #define MBED_CONF_LWIP_MEM_SIZE 16000 // set by library:lwip[PORTENTA_H7] #define MBED_CONF_LWIP_ND6_QUEUEING 0 // set by library:lwip #define MBED_CONF_LWIP_ND6_RDNSS_MAX_DNS_SERVERS 0 // set by library:lwip +#define MBED_CONF_LWIP_NETBUF_RECVINFO_ENABLED 0 // set by library:lwip #define MBED_CONF_LWIP_NUM_NETBUF 8 // set by library:lwip #define MBED_CONF_LWIP_NUM_PBUF 8 // set by library:lwip #define MBED_CONF_LWIP_PBUF_POOL_SIZE 5 // set by library:lwip @@ -379,7 +380,7 @@ #define MBED_CONF_TARGET_LPTICKER_LPTIM 1 // set by target:MCU_STM32H7 #define MBED_CONF_TARGET_LPTICKER_LPTIM_CLOCK 1 // set by target:MCU_STM32 #define MBED_CONF_TARGET_LPUART_CLOCK_SOURCE USE_LPUART_CLK_LSE|USE_LPUART_CLK_PCLK1|USE_LPUART_CLK_PCLK3 // set by target:MCU_STM32 -#define MBED_CONF_TARGET_LSE_AVAILABLE 0 // set by target:PORTENTA_H7 +#define MBED_CONF_TARGET_LSE_AVAILABLE 1 // set by target:PORTENTA_H7 #define MBED_CONF_TARGET_LSE_BYPASS 1 // set by target:PORTENTA_H7 #define MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL RCC_LSEDRIVE_LOW // set by target:MCU_STM32H7 #define MBED_CONF_TARGET_MPU_ROM_END 0x0fffffff // set by target:Target diff --git a/variants/PORTENTA_H7_M7/cflags.txt b/variants/PORTENTA_H7_M7/cflags.txt index f60f946b2..8c5eb01b0 100644 --- a/variants/PORTENTA_H7_M7/cflags.txt +++ b/variants/PORTENTA_H7_M7/cflags.txt @@ -3,12 +3,12 @@ -DAPPLICATION_ADDR=0x8040000 -DAPPLICATION_RAM_ADDR=0x24000000 -DAPPLICATION_RAM_SIZE=0x80000 --DAPPLICATION_SIZE=0xc0000 +-DAPPLICATION_SIZE=0x1c0000 -DMBED_RAM1_SIZE=0x80000 -DMBED_RAM1_START=0x24000000 -DMBED_RAM_SIZE=0x80000 -DMBED_RAM_START=0x24000000 --DMBED_ROM_SIZE=0x100000 +-DMBED_ROM_SIZE=0x200000 -DMBED_ROM_START=0x8000000 -DMBED_TRAP_ERRORS_ENABLED=1 -Os diff --git a/variants/PORTENTA_H7_M7/conf/mbed_app.json b/variants/PORTENTA_H7_M7/conf/mbed_app.json index 6cc069773..5ac9c9bb7 100644 --- a/variants/PORTENTA_H7_M7/conf/mbed_app.json +++ b/variants/PORTENTA_H7_M7/conf/mbed_app.json @@ -22,7 +22,8 @@ "VIRTIO_MASTER_ONLY", "NO_ATOMIC_64_SUPPORT", "METAL_MAX_DEVICE_REGIONS=2", - "RPMSG_BUFFER_SIZE=2048" + "RPMSG_BUFFER_SIZE=2048", + "LSE_STARTUP_TIMEOUT=200" ] } } diff --git a/variants/PORTENTA_H7_M7/cxxflags.txt b/variants/PORTENTA_H7_M7/cxxflags.txt index 8e09c00ef..24d860cfa 100644 --- a/variants/PORTENTA_H7_M7/cxxflags.txt +++ b/variants/PORTENTA_H7_M7/cxxflags.txt @@ -5,12 +5,12 @@ -DAPPLICATION_ADDR=0x8040000 -DAPPLICATION_RAM_ADDR=0x24000000 -DAPPLICATION_RAM_SIZE=0x80000 --DAPPLICATION_SIZE=0xc0000 +-DAPPLICATION_SIZE=0x1c0000 -DMBED_RAM1_SIZE=0x80000 -DMBED_RAM1_START=0x24000000 -DMBED_RAM_SIZE=0x80000 -DMBED_RAM_START=0x24000000 --DMBED_ROM_SIZE=0x100000 +-DMBED_ROM_SIZE=0x200000 -DMBED_ROM_START=0x8000000 -DMBED_TRAP_ERRORS_ENABLED=1 -Os diff --git a/variants/PORTENTA_H7_M7/defines.txt b/variants/PORTENTA_H7_M7/defines.txt index 0f098cba9..2ec564f29 100644 --- a/variants/PORTENTA_H7_M7/defines.txt +++ b/variants/PORTENTA_H7_M7/defines.txt @@ -44,8 +44,9 @@ -DEXTRA_IDLE_STACK_REQUIRED -DFEATURE_BLE=1 -D__FPU_PRESENT=1 +-DLSE_STARTUP_TIMEOUT=200 -D__MBED__=1 --DMBED_BUILD_TIMESTAMP=1648633310.1874359 +-DMBED_BUILD_TIMESTAMP=1662124795.1873505 -D__MBED_CMSIS_RTOS_CM -DMBED_TICKLESS -DMBEDTLS_FS_IO @@ -83,6 +84,6 @@ -DVIRTIO_MASTER_ONLY -DMBED_NO_GLOBAL_USING_DIRECTIVE=1 -DCORE_MAJOR=3 --DCORE_MINOR=0 --DCORE_PATCH=1 +-DCORE_MINOR=3 +-DCORE_PATCH=0 -DUSE_ARDUINO_PINOUT diff --git a/variants/PORTENTA_H7_M7/ldflags.txt b/variants/PORTENTA_H7_M7/ldflags.txt index efb55dcc0..383d6ec49 100644 --- a/variants/PORTENTA_H7_M7/ldflags.txt +++ b/variants/PORTENTA_H7_M7/ldflags.txt @@ -1,11 +1,11 @@ --DMBED_APP_SIZE=0xc0000 +-DMBED_APP_SIZE=0x1c0000 -DMBED_APP_START=0x8040000 -DMBED_BOOT_STACK_SIZE=1024 -DMBED_RAM1_SIZE=0x80000 -DMBED_RAM1_START=0x24000000 -DMBED_RAM_SIZE=0x80000 -DMBED_RAM_START=0x24000000 --DMBED_ROM_SIZE=0x100000 +-DMBED_ROM_SIZE=0x200000 -DMBED_ROM_START=0x8000000 -DXIP_ENABLE=0 -Wl,--gc-sections diff --git a/variants/PORTENTA_H7_M7/libs/libmbed.a b/variants/PORTENTA_H7_M7/libs/libmbed.a index 3c48413ea..0165be54e 100644 Binary files a/variants/PORTENTA_H7_M7/libs/libmbed.a and b/variants/PORTENTA_H7_M7/libs/libmbed.a differ diff --git a/variants/PORTENTA_H7_M7/linker_script.ld b/variants/PORTENTA_H7_M7/linker_script.ld index 24a1d9c2c..4c87d33cd 100644 --- a/variants/PORTENTA_H7_M7/linker_script.ld +++ b/variants/PORTENTA_H7_M7/linker_script.ld @@ -96,6 +96,12 @@ SECTIONS . = ABSOLUTE(0x3800FC00); *(.pdm_buffer) } > RAM_D3 + _dtcm_lma = __etext + SIZEOF(.data); + .dtcm : AT(_dtcm_lma) { + _sdtcm = .; + *(.dtcm*) + _edtcm = .; + } > DTCMRAM .heap (COPY): { __end__ = .; diff --git a/variants/PORTENTA_H7_M7/mbed_config.h b/variants/PORTENTA_H7_M7/mbed_config.h index 9eafe0175..5eb2392ed 100644 --- a/variants/PORTENTA_H7_M7/mbed_config.h +++ b/variants/PORTENTA_H7_M7/mbed_config.h @@ -217,6 +217,7 @@ #define MBED_CONF_LWIP_MEM_SIZE 16000 // set by library:lwip[PORTENTA_H7] #define MBED_CONF_LWIP_ND6_QUEUEING 0 // set by library:lwip #define MBED_CONF_LWIP_ND6_RDNSS_MAX_DNS_SERVERS 0 // set by library:lwip +#define MBED_CONF_LWIP_NETBUF_RECVINFO_ENABLED 0 // set by library:lwip #define MBED_CONF_LWIP_NUM_NETBUF 8 // set by library:lwip #define MBED_CONF_LWIP_NUM_PBUF 8 // set by library:lwip #define MBED_CONF_LWIP_PBUF_POOL_SIZE 5 // set by library:lwip @@ -381,7 +382,7 @@ #define MBED_CONF_TARGET_LPTICKER_LPTIM 1 // set by target:MCU_STM32H7 #define MBED_CONF_TARGET_LPTICKER_LPTIM_CLOCK 1 // set by target:MCU_STM32 #define MBED_CONF_TARGET_LPUART_CLOCK_SOURCE USE_LPUART_CLK_LSE|USE_LPUART_CLK_PCLK1|USE_LPUART_CLK_PCLK3 // set by target:MCU_STM32 -#define MBED_CONF_TARGET_LSE_AVAILABLE 0 // set by target:PORTENTA_H7 +#define MBED_CONF_TARGET_LSE_AVAILABLE 1 // set by target:PORTENTA_H7 #define MBED_CONF_TARGET_LSE_BYPASS 1 // set by target:PORTENTA_H7 #define MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL RCC_LSEDRIVE_LOW // set by target:MCU_STM32H7 #define MBED_CONF_TARGET_MPU_ROM_END 0x0fffffff // set by target:Target diff --git a/variants/PORTENTA_H7_M7/variant.cpp b/variants/PORTENTA_H7_M7/variant.cpp index 52cf947e2..f17a33059 100644 --- a/variants/PORTENTA_H7_M7/variant.cpp +++ b/variants/PORTENTA_H7_M7/variant.cpp @@ -235,6 +235,8 @@ void fixup3V1Rail() { i2c.write(8 << 1, data, sizeof(data)); } +extern "C" void lp_ticker_reconfigure_with_lsi(); + void initVariant() { RTCHandle.Instance = RTC; // Turn off LED from bootloader @@ -244,6 +246,19 @@ void initVariant() { // Disable the FMC bank1 (enabled after reset) // See https://github.com/STMicroelectronics/STM32CubeH7/blob/beced99ac090fece04d1e0eb6648b8075e156c6c/Projects/STM32H747I-DISCO/Applications/OpenAMP/OpenAMP_RTOS_PingPong/Common/Src/system_stm32h7xx.c#L215 FMC_Bank1_R->BTCR[0] = 0x000030D2; + // Check that the selected lsi clock is ok + if (__HAL_RCC_GET_LPTIM4_SOURCE() == RCC_LPTIM4CLKSOURCE_LSI) { + // rtc is not mounted, no need to do other actions + return; + } + // Use micros() to check the lptim precision + // if the error is > 1% , reconfigure the clock using lsi + uint32_t start_ms = millis(); + uint32_t start_us = micros(); + while (micros() - start_us < 100000); + if (millis() - start_ms != 100) { + lp_ticker_reconfigure_with_lsi(); + } } #ifdef SERIAL_CDC diff --git a/variants/PORTENTA_X8/cflags.txt b/variants/PORTENTA_X8/cflags.txt index 5ea7d6111..846011196 100644 --- a/variants/PORTENTA_X8/cflags.txt +++ b/variants/PORTENTA_X8/cflags.txt @@ -1,11 +1,7 @@ -c -std=gnu11 -DAPPLICATION_ADDR=0x8100000 --DAPPLICATION_RAM_ADDR=0x10000000 --DAPPLICATION_RAM_SIZE=0x48000 -DAPPLICATION_SIZE=0x100000 --DMBED_RAM1_SIZE=0x80000 --DMBED_RAM1_START=0x24000000 -DMBED_RAM_SIZE=0x48000 -DMBED_RAM_START=0x10000000 -DMBED_ROM_SIZE=0x100000 diff --git a/variants/PORTENTA_X8/cxxflags.txt b/variants/PORTENTA_X8/cxxflags.txt index 0787fe177..fd71297d0 100644 --- a/variants/PORTENTA_X8/cxxflags.txt +++ b/variants/PORTENTA_X8/cxxflags.txt @@ -3,11 +3,7 @@ -fno-rtti -std=gnu++14 -DAPPLICATION_ADDR=0x8100000 --DAPPLICATION_RAM_ADDR=0x10000000 --DAPPLICATION_RAM_SIZE=0x48000 -DAPPLICATION_SIZE=0x100000 --DMBED_RAM1_SIZE=0x80000 --DMBED_RAM1_START=0x24000000 -DMBED_RAM_SIZE=0x48000 -DMBED_RAM_START=0x10000000 -DMBED_ROM_SIZE=0x100000 diff --git a/variants/PORTENTA_X8/defines.txt b/variants/PORTENTA_X8/defines.txt index 37744313d..3e5f73a2f 100644 --- a/variants/PORTENTA_X8/defines.txt +++ b/variants/PORTENTA_X8/defines.txt @@ -34,7 +34,7 @@ -DEXTRA_IDLE_STACK_REQUIRED -D__FPU_PRESENT=1 -D__MBED__=1 --DMBED_BUILD_TIMESTAMP=1643127518.8108099 +-DMBED_BUILD_TIMESTAMP=1662125012.238662 -D__MBED_CMSIS_RTOS_CM -DMBED_MPU_CUSTOM -DMBED_TICKLESS @@ -70,4 +70,7 @@ -DUSE_HAL_DRIVER -DVIRTIO_SLAVE_ONLY -DMBED_NO_GLOBAL_USING_DIRECTIVE=1 +-DCORE_MAJOR=3 +-DCORE_MINOR=3 +-DCORE_PATCH=0 -DUSE_ARDUINO_PINOUT diff --git a/variants/PORTENTA_X8/ldflags.txt b/variants/PORTENTA_X8/ldflags.txt index e3666931b..914e1deff 100644 --- a/variants/PORTENTA_X8/ldflags.txt +++ b/variants/PORTENTA_X8/ldflags.txt @@ -1,8 +1,6 @@ -DMBED_APP_SIZE=0x100000 -DMBED_APP_START=0x8100000 -DMBED_BOOT_STACK_SIZE=1024 --DMBED_RAM1_SIZE=0x80000 --DMBED_RAM1_START=0x24000000 -DMBED_RAM_SIZE=0x48000 -DMBED_RAM_START=0x10000000 -DMBED_ROM_SIZE=0x100000 diff --git a/variants/PORTENTA_X8/libs/libmbed.a b/variants/PORTENTA_X8/libs/libmbed.a index 919632130..adfcb08b8 100644 Binary files a/variants/PORTENTA_X8/libs/libmbed.a and b/variants/PORTENTA_X8/libs/libmbed.a differ diff --git a/variants/PORTENTA_X8/linker_script.ld b/variants/PORTENTA_X8/linker_script.ld index 33fc73c17..4c2af2ee9 100644 --- a/variants/PORTENTA_X8/linker_script.ld +++ b/variants/PORTENTA_X8/linker_script.ld @@ -1,6 +1,6 @@ MEMORY { - FLASH (rx) : ORIGIN = CM4_BINARY_START, LENGTH = CM4_BINARY_END - CM4_BINARY_START + FLASH (rx) : ORIGIN = CM4_BINARY_START, LENGTH = 0x100000 RAM (rwx) : ORIGIN = 0x10000000 + (((166 * 4) + 7) & 0xFFFFFFF8), LENGTH = 0x48000 - (((166 * 4) + 7) & 0xFFFFFFF8) RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K } @@ -93,6 +93,12 @@ SECTIONS . = ABSOLUTE(0x3800FC00); *(.pdm_buffer) } > RAM_D3 + _dtcm_lma = __etext + SIZEOF(.data); + .dtcm : AT(_dtcm_lma) { + _sdtcm = .; + *(.dtcm*) + _edtcm = .; + } > DTCMRAM .heap (COPY): { __end__ = .; diff --git a/variants/PORTENTA_X8/mbed_config.h b/variants/PORTENTA_X8/mbed_config.h index 1839607fb..07c548a8b 100644 --- a/variants/PORTENTA_X8/mbed_config.h +++ b/variants/PORTENTA_X8/mbed_config.h @@ -171,6 +171,7 @@ #define MBED_CONF_LWIP_MEM_SIZE 2310 // set by library:lwip[STM] #define MBED_CONF_LWIP_ND6_QUEUEING 0 // set by library:lwip #define MBED_CONF_LWIP_ND6_RDNSS_MAX_DNS_SERVERS 0 // set by library:lwip +#define MBED_CONF_LWIP_NETBUF_RECVINFO_ENABLED 0 // set by library:lwip #define MBED_CONF_LWIP_NUM_NETBUF 8 // set by library:lwip #define MBED_CONF_LWIP_NUM_PBUF 8 // set by library:lwip #define MBED_CONF_LWIP_PBUF_POOL_SIZE 5 // set by library:lwip @@ -213,6 +214,7 @@ #define MBED_CONF_PLATFORM_CALLBACK_NONTRIVIAL 1 // set by application[*] #define MBED_CONF_PLATFORM_CRASH_CAPTURE_ENABLED 0 // set by library:platform #define MBED_CONF_PLATFORM_CTHUNK_COUNT_MAX 8 // set by library:platform +#define MBED_CONF_PLATFORM_DEEPSLEEP_STATS_VERBOSE 0 // set by library:platform[STM] #define MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE 115200 // set by application[*] #define MBED_CONF_PLATFORM_ERROR_ALL_THREADS_INFO 0 // set by library:platform #define MBED_CONF_PLATFORM_ERROR_FILENAME_CAPTURE_ENABLED 0 // set by library:platform diff --git a/variants/RASPBERRY_PI_PICO/defines.txt b/variants/RASPBERRY_PI_PICO/defines.txt index bca7c7ffa..c801b1e30 100644 --- a/variants/RASPBERRY_PI_PICO/defines.txt +++ b/variants/RASPBERRY_PI_PICO/defines.txt @@ -20,9 +20,10 @@ -DDEVICE_USTICKER=1 -DDEVICE_WATCHDOG=1 -D__MBED__=1 --DMBED_BUILD_TIMESTAMP=1648633283.9288557 +-DMBED_BUILD_TIMESTAMP=1662124773.2915711 -D__MBED_CMSIS_RTOS_CM -DMBED_MPU_CUSTOM +-DMBEDTLS_ENTROPY_NV_SEED -DPICO_NO_BINARY_INFO=1 -DPICO_ON_DEVICE=1 -DPICO_RP2040_USB_DEVICE_ENUMERATION_FIX=1 @@ -43,6 +44,6 @@ -DTOOLCHAIN_GCC_ARM -DMBED_NO_GLOBAL_USING_DIRECTIVE=1 -DCORE_MAJOR=3 --DCORE_MINOR=0 --DCORE_PATCH=1 +-DCORE_MINOR=3 +-DCORE_PATCH=0 -DUSE_ARDUINO_PINOUT diff --git a/variants/RASPBERRY_PI_PICO/includes.txt b/variants/RASPBERRY_PI_PICO/includes.txt index 155d186a9..d538e6c6d 100644 --- a/variants/RASPBERRY_PI_PICO/includes.txt +++ b/variants/RASPBERRY_PI_PICO/includes.txt @@ -233,6 +233,9 @@ -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_sync/include/pico -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_time/include +-iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_usb_reset_interface +-iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_usb_reset_interface/include +-iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_usb_reset_interface/include/pico -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/common/pico_util/include/pico @@ -262,6 +265,9 @@ -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/include -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_dma/include/hardware +-iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_exception +-iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_exception/include +-iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_exception/include/hardware -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/include -iwithprefixbefore/mbed/targets/TARGET_RASPBERRYPI/TARGET_RP2040/pico-sdk/rp2_common/hardware_flash/include/hardware diff --git a/variants/RASPBERRY_PI_PICO/libs/libmbed.a b/variants/RASPBERRY_PI_PICO/libs/libmbed.a index 22b49f0b6..221f1ee27 100644 Binary files a/variants/RASPBERRY_PI_PICO/libs/libmbed.a and b/variants/RASPBERRY_PI_PICO/libs/libmbed.a differ diff --git a/variants/RASPBERRY_PI_PICO/mbed_config.h b/variants/RASPBERRY_PI_PICO/mbed_config.h index de0e79601..08a14dc14 100644 --- a/variants/RASPBERRY_PI_PICO/mbed_config.h +++ b/variants/RASPBERRY_PI_PICO/mbed_config.h @@ -162,6 +162,7 @@ #define MBED_CONF_LWIP_MEM_SIZE 1600 // set by library:lwip #define MBED_CONF_LWIP_ND6_QUEUEING 0 // set by library:lwip #define MBED_CONF_LWIP_ND6_RDNSS_MAX_DNS_SERVERS 0 // set by library:lwip +#define MBED_CONF_LWIP_NETBUF_RECVINFO_ENABLED 0 // set by library:lwip #define MBED_CONF_LWIP_NUM_NETBUF 8 // set by library:lwip #define MBED_CONF_LWIP_NUM_PBUF 8 // set by library:lwip #define MBED_CONF_LWIP_PBUF_POOL_SIZE 5 // set by library:lwip