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Add standalone SDRAM library
This allows running graphical applications on M7. About this, extra care must be take to ensure cache coherency, otherwise all kind of graphical errors could happen. Take a look at #ifdef CORE_CM7 in doom example to see where to place the invalidation and extra delays.
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13 files changed

+450
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13 files changed

+450
-14
lines changed

‎libraries/ENVIE_SDRAM/SDRAM.cpp

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#include "SDRAM.h"
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extern "C" {
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#include "ram_internal.h"
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}
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int SDRAMClass::begin(uint32_t start_address) {
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if (FMC_SDRAM_DEVICE->SDCMR == 0x00000000U) {
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printf("initializing external ram\n");
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bool ret = sdram_init();
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if (ret == false) {
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return 0;
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}
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/* Enable MPU for the SDRAM Memory Region to allow non-aligned
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accesses (hard-fault otherwise)
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Initially disable all access for the entire SDRAM memory space,
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then enable access/caching for the size used
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*/
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mpu_config_start();
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mpu_config_region(MPU_REGION_SDRAM1, SDRAM_START_ADDRESS, MPU_CONFIG_DISABLE(0x00, MPU_REGION_SIZE_512MB));
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mpu_config_region(MPU_REGION_SDRAM2, SDRAM_START_ADDRESS, MPU_CONFIG_SDRAM(SDRAM_MPU_REGION_SIZE));
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mpu_config_end();
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}
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printf("malloc_addblock: allocate %d bytes\n", SDRAM_END_ADDRESS - start_address);
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malloc_addblock((void*)start_address, SDRAM_END_ADDRESS - start_address);
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return 1;
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}
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void* SDRAMClass::malloc(size_t size) {
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return ea_malloc(size);
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}
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void SDRAMClass::free(void* ptr) {
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ea_free(ptr);
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}
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SDRAMClass SDRAM;

‎libraries/ENVIE_SDRAM/SDRAM.h

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#include "ea_malloc.h"
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#ifdef __cplusplus
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#include "Arduino.h"
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#define SDRAM_END_ADDRESS (0xC0800000)
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#define SDRAM_START_ADDRESS (0xC0000000)
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class SDRAMClass {
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public:
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SDRAMClass() {}
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int begin(uint32_t start_address = SDRAM_START_ADDRESS);
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void* malloc(size_t size);
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void free(void* ptr);
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private:
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void mpu_config_start(void) {
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__disable_irq();
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}
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void mpu_config_region(uint32_t region, uint32_t base_addr, uint32_t attr_size) {
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MPU->RNR = region;
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MPU->RBAR = base_addr;
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MPU->RASR = attr_size;
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}
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void mpu_config_end(void) {
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__ISB();
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__DSB();
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__DMB();
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__enable_irq();
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}
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};
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extern SDRAMClass SDRAM;
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#endif

‎libraries/doom/malloc.h renamed to ‎libraries/ENVIE_SDRAM/ea_malloc.h

File renamed without changes.

‎libraries/doom/ll.h renamed to ‎libraries/ENVIE_SDRAM/ll.h

File renamed without changes.

‎libraries/doom/malloc_freelist.c renamed to ‎libraries/ENVIE_SDRAM/malloc_freelist.c

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*/
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#include <ll.h>
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#include <malloc.h>
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#include <ea_malloc.h>
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#include <memory.h>
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#include <stdint.h>
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‎libraries/ENVIE_SDRAM/ram_internal.c

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/*
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* This file is part of the OpenMV project.
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* Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
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* This work is licensed under the MIT license, see the file LICENSE for details.
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*
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* SDRAM Driver.
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*
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*/
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#include <stdio.h>
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#include <stdbool.h>
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#include <string.h>
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#include "ram_internal.h"
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#include <stm32h7xx_hal.h>
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#include <stm32h7xx_hal_sdram.h>
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#include <stm32h7xx_hal_mdma.h>
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#define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
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#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
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#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
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#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
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#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
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#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
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#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
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#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
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#ifdef FMC_SDRAM_BANK
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static void sdram_init_seq(SDRAM_HandleTypeDef
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*hsdram, FMC_SDRAM_CommandTypeDef *command);
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extern void __fatal_error(const char *msg);
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bool sdram_init(void) {
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SDRAM_HandleTypeDef hsdram;
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FMC_SDRAM_TimingTypeDef SDRAM_Timing;
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FMC_SDRAM_CommandTypeDef command;
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static MDMA_HandleTypeDef mdma_handle;
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GPIO_InitTypeDef gpio_init_structure;
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/* Enable FMC clock */
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__HAL_RCC_FMC_CLK_ENABLE();
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/* Enable chosen MDMAx clock */
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__HAL_RCC_MDMA_CLK_ENABLE();
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/* Enable GPIOs clock */
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__HAL_RCC_GPIOD_CLK_ENABLE();
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__HAL_RCC_GPIOE_CLK_ENABLE();
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__HAL_RCC_GPIOF_CLK_ENABLE();
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__HAL_RCC_GPIOG_CLK_ENABLE();
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__HAL_RCC_GPIOH_CLK_ENABLE();
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/* Common GPIO configuration */
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gpio_init_structure.Mode = GPIO_MODE_AF_PP;
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gpio_init_structure.Pull = GPIO_PULLUP;
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gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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gpio_init_structure.Alternate = GPIO_AF12_FMC;
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/* GPIOD configuration */
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gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8| GPIO_PIN_9 | GPIO_PIN_10 |\
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GPIO_PIN_14 | GPIO_PIN_15;
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HAL_GPIO_Init(GPIOD, &gpio_init_structure);
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/* GPIOE configuration */
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gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
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GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
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GPIO_PIN_15;
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HAL_GPIO_Init(GPIOE, &gpio_init_structure);
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/* GPIOF configuration */
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gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
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GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
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GPIO_PIN_15;
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HAL_GPIO_Init(GPIOF, &gpio_init_structure);
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/* GPIOG configuration */
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gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 /*| GPIO_PIN_3 */|\
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GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15;
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HAL_GPIO_Init(GPIOG, &gpio_init_structure);
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/* GPIOH configuration */
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gpio_init_structure.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5;
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HAL_GPIO_Init(GPIOH, &gpio_init_structure);
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/* Configure common MDMA parameters */
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mdma_handle.Init.Request = MDMA_REQUEST_SW;
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mdma_handle.Init.TransferTriggerMode = MDMA_BLOCK_TRANSFER;
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mdma_handle.Init.Priority = MDMA_PRIORITY_HIGH;
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mdma_handle.Init.Endianness = MDMA_LITTLE_ENDIANNESS_PRESERVE;
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mdma_handle.Init.SourceInc = MDMA_SRC_INC_WORD;
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mdma_handle.Init.DestinationInc = MDMA_DEST_INC_WORD;
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mdma_handle.Init.SourceDataSize = MDMA_SRC_DATASIZE_WORD;
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mdma_handle.Init.DestDataSize = MDMA_DEST_DATASIZE_WORD;
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mdma_handle.Init.DataAlignment = MDMA_DATAALIGN_PACKENABLE;
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mdma_handle.Init.SourceBurst = MDMA_SOURCE_BURST_SINGLE;
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mdma_handle.Init.DestBurst = MDMA_DEST_BURST_SINGLE;
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mdma_handle.Init.BufferTransferLength = 128;
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mdma_handle.Init.SourceBlockAddressOffset = 0;
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mdma_handle.Init.DestBlockAddressOffset = 0;
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mdma_handle.Instance = MDMA_Channel1;
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/* Associate the DMA handle */
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__HAL_LINKDMA(&hsdram, hmdma, mdma_handle);
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/* Deinitialize the stream for new transfer */
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HAL_MDMA_DeInit(&mdma_handle);
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/* Configure the DMA stream */
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HAL_MDMA_Init(&mdma_handle);
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/* NVIC configuration for DMA transfer complete interrupt */
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HAL_NVIC_SetPriority(MDMA_IRQn, 0x0F, 0);
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HAL_NVIC_EnableIRQ(MDMA_IRQn);
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/* SDRAM device configuration */
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hsdram.Instance = FMC_SDRAM_DEVICE;
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/* Timing configuration for 90 Mhz of SD clock frequency (180Mhz/2) */
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/* TMRD: 2 Clock cycles */
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SDRAM_Timing.LoadToActiveDelay = MICROPY_HW_SDRAM_TIMING_TMRD;
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/* TXSR: min=70ns (6x11.90ns) */
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SDRAM_Timing.ExitSelfRefreshDelay = MICROPY_HW_SDRAM_TIMING_TXSR;
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/* TRAS */
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SDRAM_Timing.SelfRefreshTime = MICROPY_HW_SDRAM_TIMING_TRAS;
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/* TRC */
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SDRAM_Timing.RowCycleDelay = MICROPY_HW_SDRAM_TIMING_TRC;
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/* TWR */
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SDRAM_Timing.WriteRecoveryTime = MICROPY_HW_SDRAM_TIMING_TWR;
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/* TRP */
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SDRAM_Timing.RPDelay = MICROPY_HW_SDRAM_TIMING_TRP;
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/* TRCD */
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SDRAM_Timing.RCDDelay = MICROPY_HW_SDRAM_TIMING_TRCD;
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#define _FMC_INIT(x, n) x ## _ ## n
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#define FMC_INIT(x, n) _FMC_INIT(x, n)
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hsdram.Init.SDBank = FMC_SDRAM_BANK;
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hsdram.Init.ColumnBitsNumber = FMC_INIT(FMC_SDRAM_COLUMN_BITS_NUM, MICROPY_HW_SDRAM_COLUMN_BITS_NUM);
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hsdram.Init.RowBitsNumber = FMC_INIT(FMC_SDRAM_ROW_BITS_NUM, MICROPY_HW_SDRAM_ROW_BITS_NUM);
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hsdram.Init.MemoryDataWidth = FMC_INIT(FMC_SDRAM_MEM_BUS_WIDTH, MICROPY_HW_SDRAM_MEM_BUS_WIDTH);
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hsdram.Init.InternalBankNumber = FMC_INIT(FMC_SDRAM_INTERN_BANKS_NUM, MICROPY_HW_SDRAM_INTERN_BANKS_NUM);
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hsdram.Init.CASLatency = FMC_INIT(FMC_SDRAM_CAS_LATENCY, MICROPY_HW_SDRAM_CAS_LATENCY);
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hsdram.Init.SDClockPeriod = FMC_INIT(FMC_SDRAM_CLOCK_PERIOD, MICROPY_HW_SDRAM_CLOCK_PERIOD);
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hsdram.Init.ReadPipeDelay = FMC_INIT(FMC_SDRAM_RPIPE_DELAY, MICROPY_HW_SDRAM_RPIPE_DELAY);
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hsdram.Init.ReadBurst = (MICROPY_HW_SDRAM_RBURST) ? FMC_SDRAM_RBURST_ENABLE : FMC_SDRAM_RBURST_DISABLE;
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hsdram.Init.WriteProtection = (MICROPY_HW_SDRAM_WRITE_PROTECTION) ? FMC_SDRAM_WRITE_PROTECTION_ENABLE : FMC_SDRAM_WRITE_PROTECTION_DISABLE;
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/* Initialize the SDRAM controller */
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if(HAL_SDRAM_Init(&hsdram, &SDRAM_Timing) != HAL_OK) {
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return false;
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}
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sdram_init_seq(&hsdram, &command);
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return true;
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}
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static void sdram_init_seq(SDRAM_HandleTypeDef
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*hsdram, FMC_SDRAM_CommandTypeDef *command)
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{
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/* Program the SDRAM external device */
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__IO uint32_t tmpmrd =0;
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/* Step 3: Configure a clock configuration enable command */
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command->CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
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command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK;
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command->AutoRefreshNumber = 1;
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command->ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, command, 0x1000);
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/* Step 4: Insert 100 ms delay */
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HAL_Delay(100);
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/* Step 5: Configure a PALL (precharge all) command */
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command->CommandMode = FMC_SDRAM_CMD_PALL;
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command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK;
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command->AutoRefreshNumber = 1;
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command->ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, command, 0x1000);
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/* Step 6 : Configure a Auto-Refresh command */
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command->CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
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command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK;
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command->AutoRefreshNumber = MICROPY_HW_SDRAM_AUTOREFRESH_NUM;
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command->ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, command, 0x1000);
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/* Step 7: Program the external memory mode register */
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tmpmrd = (uint32_t)FMC_INIT(SDRAM_MODEREG_BURST_LENGTH, MICROPY_HW_SDRAM_BURST_LENGTH) |
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SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
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FMC_INIT(SDRAM_MODEREG_CAS_LATENCY, MICROPY_HW_SDRAM_CAS_LATENCY) |
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SDRAM_MODEREG_OPERATING_MODE_STANDARD |
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SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
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command->CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
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command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK;
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command->AutoRefreshNumber = 1;
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command->ModeRegisterDefinition = tmpmrd;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, command, 0x1000);
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/* Step 8: Set the refresh rate counter
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RefreshRate = 64 ms / 8192 cyc = 7.8125 us/cyc
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RefreshCycles = 7.8125 us * 90 MHz = 703
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According to the formula on p.1665 of the reference manual,
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we also need to subtract 20 from the value, so the target
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refresh rate is 703 - 20 = 683.
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*/
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#define REFRESH_COUNT (MICROPY_HW_SDRAM_REFRESH_RATE * 90000 / 8192 - 20)
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HAL_SDRAM_ProgramRefreshRate(hsdram, REFRESH_COUNT);
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}
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bool __attribute__((optimize("O0"))) sdram_test(bool fast) {
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uint8_t const pattern = 0xaa;
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uint8_t const antipattern = 0x55;
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uint8_t *const mem_base = (uint8_t*)sdram_start();
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/* test data bus */
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for (uint8_t i = 1; i; i <<= 1) {
233+
*mem_base = i;
234+
if (*mem_base != i) {
235+
printf("data bus lines test failed! data (%d)\n", i);
236+
__asm__ volatile ("BKPT");
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}
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}
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/* test address bus */
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/* Check individual address lines */
242+
for (uint32_t i = 1; i < HW_SDRAM_SIZE; i <<= 1) {
243+
mem_base[i] = pattern;
244+
if (mem_base[i] != pattern) {
245+
printf("address bus lines test failed! address (%p)\n", &mem_base[i]);
246+
__asm__ volatile ("BKPT");
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}
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}
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/* Check for aliasing (overlaping addresses) */
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mem_base[0] = antipattern;
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for (uint32_t i = 1; i < HW_SDRAM_SIZE; i <<= 1) {
253+
if (mem_base[i] != pattern) {
254+
printf("address bus overlap %p\n", &mem_base[i]);
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__asm__ volatile ("BKPT");
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}
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}
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/* test all ram cells */
260+
if (!fast) {
261+
for (uint32_t i = 0; i < HW_SDRAM_SIZE; ++i) {
262+
mem_base[i] = pattern;
263+
if (mem_base[i] != pattern) {
264+
printf("address bus test failed! address (%p)\n", &mem_base[i]);
265+
__asm__ volatile ("BKPT");
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}
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}
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} else {
269+
memset(mem_base, pattern, HW_SDRAM_SIZE);
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}
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return true;
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}
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#endif // FMC_SDRAM_BANK

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