Updates to kernel MRI library

Pulling over changes from MRI repository, many of which were made to
ease future porting efforts and better integrate thread support.

Switch __mri prefix to mri:
* Dropping the initial "__" from MRI symbols with external scope so
  that they don't conflict with the Standard C Library reserved prefix.

Refactor context as scatter gather list:
* Rather than copying the thread context from the various portions of
  its stack, use a scatter gather list of pointers into the stack
  itself. It requires less assembly language code in
  mriExceptionHandler() since most of the context can be prepared in
  the mriCortexMExceptionHandler() C code now.
* I updated code to use existing Platform_Get/SetProgramCounter() to
  manipulate the value of the PC register rather than grabbing it
  directly from the context which is now a bit more involved as it has
  to go through the scatter gather data structure.
* Added unit tests to get 100% code coverage of the new ScatterGather
  code.

I also pulled mriCortexMDebuggerStack and mriCortexMFlags objects out
of CortexMState object to make it easier for assembly language code to
access. Before the assembly language code needed to know the offset of
these fields in the structure when accessing them. Now it can just
refer to the individual globals directly.

Differentiate CortexM code to support both Thread and Handler mode
debugging based on setting of MRI_THREAD_MRI macro. Thread mode MRI
is used to debug user mode code in an RTOS environment, leaving core
code to run in the background. The updates includes:
* Added fields to mriCortexMState to hold the value of the SP pointed
  to in the context scatter gather structure. Also added fields to
  track the fault cause such as exceptionNumber, DFSR, HFSR, etc. since
  for ThreadMRI it is better to capture these earlier in the exception
  handler before handing off to the main debugger thread as was done
  before in armv7-m.c  Not a bad idea to do it earlier in the case of
  handler mode MRI either.
* Handler mode MRI will still include system registers like MSP, PSP,
  etc. in the context while ThreadMRI will not.
* In mriCortexMInit(), skip the setting of SVCall, SysTick, and PendSV
  priorities for ThreadMRI. ThreadMRI also sets DebugMon to the lowest
  priority while handler mode MRI sets it to the highest priority.

Suppress fault display on startup:
* If GDB is just attaching, we don't want to send the verbose output
  indicating the cause of a fault since GDB gets very confused by it.
  This confusion will even result in a 2 second timeout before MRI and
  GDB re-synchronize.

Now uses the CORTEXM_FLAGS_CTRL_C flag to determine if SIGINT should
be returned from Platform_DetermineCauseOfException() as the cause of a
debug halt. Previously it was hardcoded to use the exception numbers
of the LPC176x UART handlers.

Platform_EnteringDebugger() in armv7-m.c now takes care of setting the
the CORTEXM_FLAGS_ACTIVE_DEBUG and Platform_LeavingDebugger() takes
care of clearing it so that handler/thread mode specific code doesn't
have to anymore.

mriCortexMInit() now takes a highestExternalIrq parameter that can be
passed in from device specific init routines to indicate how many
external interrupt sources should be defaulted to sub-zero priorities.
Previously each particular device had its own loop to lower the
priority of its external interrupts. That duplicate code across
multiple devices is now gone.

Add debugMonPriority parameter mriCortexMInit() function to allow
port to specify the priority it desires for the DebugMonitor
interrupt handler. Typically this will be 0, the highest priority,
but there are cases when you might have code that should continue
to run at the highest priority in the background, even when halted
in GDB. In these cases, it makes sense for the background ISRs to be
given a priority of 0 and DebugMonitor a priority of 1. The other
default handler priorities are lowered to fall below DebugMonitor by
mriCortexMInit() so that they can be debugged.

Expose mriCortexMSetPriority() API which can be used by device/board
specific code to set interrupt priority using MRI code that doesn't
rely on __NVIC_PRIO_BITS being set correctly in the CMSIS headers. It
instead determines the number of sub-priority bits at runtime.

Expose the mriCortexMGetPriority() API publicly. This function also
uses the runtime calculated sub-priority bit count.

Increase size of mriCortexMDebuggerStack now that more of the context
is pushed onto the stack to be later pointed to by ScatterGatherEntry
objects. The debugger stack also now has different sizes based on
whether a particular device has a FPU or not.

Increased size of g_fakeStack for devices with FPU as its exception
stack may need more room for autostacked floats.

Updated target XML to mark LR as a code pointer as well so that GDB
knows to try looking up the matching symbol when dumping it.

Default baud rate to 230400. Largest supported across macOS, Windows,
and Linux.

Simplify device porting:
* Now handle spurious UART interrupts in CortexM code rather than
  having all CortexM devices contain duplicated code to handle it.
  This means that ports no longer need to implement:
  * Platform_CommCausedInterrupt()
  * Platform_CommClearInterrupt()
* Ports no longer need to implement:
    mriPlatform_CommUartIndex()
* Remove com. port sharing and autobaud. Ports no longer need to
  implement:
  * mriPlatform_CommShouldWaitForGdbConnect()
  * mriPlatform_CommSharingWithApplication()
  * mriPlatform_CommPrepareToWaitForGdbConnection()
  * mriPlatform_CommIsWaitingForGdbToConnect()
  * mriPlatform_CommWaitForReceiveDataToStop()

* Cortex-M7 names their system handler priority register array SHPR
  instead of SHP like the rest of the ARMv7-M family for some reason.
  Added a macro to take care of this name change.

Author: adamgreen

libraries/MRI/src/architectures/armv7-m/armv7-m.c

@@ -14,33 +14,17 @@
 */
 /* Routines and globals which expose the Cortex-M functionality to the mri debugger.  Also describes global architecture
   state which is shared between cortex-m.c and cortex-m_asm.S */
-#ifndef _CORTEXM_H_
-#define _CORTEXM_H_
+#ifndef CORTEXM_H_
+#define CORTEXM_H_
 
-/* Definitions used by C and Assembler code. */
-/* Flag bits used in CortexMState::flags field. */
-#define CORTEXM_FLAGS_ACTIVE_DEBUG          1
-#define CORTEXM_FLAGS_FAULT_DURING_DEBUG    2
-#define CORTEXM_FLAGS_SINGLE_STEPPING       4
-#define CORTEXM_FLAGS_RESTORE_BASEPRI       8
-#define CORTEXM_FLAGS_SVC_STEP              16
-
-/* Constants related to special memory area used by the debugger for its stack so that it doesn't interfere with
-   the task's stack contents. */
-#define CORTEXM_DEBUGGER_STACK_SIZE            39
-#define CORTEXM_DEBUGGER_STACK_SIZE_IN_BYTES   (CORTEXM_DEBUGGER_STACK_SIZE * 8)
-#define CORTEXM_DEBUGGER_STACK_FILL            0xDEADBEEF
 
-/* Offsets of fields within the CortexMState structure defined below.  These are used to access the fields of the
-   structure from within assembly language code. */
-#define CORTEXM_STATE_DEBUGGER_STACK_OFFSET 0
-#define CORTEXM_STATE_FLAGS_OFFSET          (CORTEXM_STATE_DEBUGGER_STACK_OFFSET + CORTEXM_DEBUGGER_STACK_SIZE_IN_BYTES)
-#define CORTEXM_STATE_TASK_SP_OFFSET        (CORTEXM_STATE_FLAGS_OFFSET + 4)
-#define CORTEXM_STATE_CONTEXT_OFFSET        (CORTEXM_STATE_TASK_SP_OFFSET + 4)
-#define CORTEXM_STATE_SAVED_MSP_OFFSET      (CORTEXM_STATE_CONTEXT_OFFSET + 17 * 4)
+// UNDONE:
+#define MRI_THREAD_MRI 0
 
-// In some other build systems, MRI_DEVICE_HAS_FPU won't be passed in on compiler's command line so use the
-// target Cortex-M type to determine if it has a FPU or not.
+/* Definitions used by C and Assembler code. */
+/* In some other build systems, MRI_DEVICE_HAS_FPU won't be passed in on compiler's command line so use the
+   target Cortex-M type to determine if it has a FPU or not.
+*/
 #ifndef MRI_DEVICE_HAS_FPU
     #ifdef __ARM_ARCH_7EM__
         #define MRI_DEVICE_HAS_FPU 1
@@ -49,101 +33,92 @@
     #endif
 #endif
 
+/* Flag bits used in mriCortexMFlags global. */
+#define CORTEXM_FLAGS_ACTIVE_DEBUG          (1 << 0)
+#define CORTEXM_FLAGS_FAULT_DURING_DEBUG    (1 << 1)
+#define CORTEXM_FLAGS_SINGLE_STEPPING       (1 << 2)
+#define CORTEXM_FLAGS_RESTORE_BASEPRI       (1 << 3)
+#define CORTEXM_FLAGS_SVC_STEP              (1 << 4)
+#define CORTEXM_FLAGS_CTRL_C                (1 << 5)
+
+/* Special memory area used by the debugger for its stack so that it doesn't interfere with the task's
+   stack contents.
+
+   The stack sizes below are based on actual test runs on LPC1768 (non-FPU) and LPC4330 (FPU) based boards with a
+   roughly 25% reservation for future growth.
+*/
+#define CORTEXM_DEBUGGER_STACK_FILL            0xDEADBEEF
+#if MRI_DEVICE_HAS_FPU
+    #define CORTEXM_DEBUGGER_STACK_SIZE        90
+#else
+    #define CORTEXM_DEBUGGER_STACK_SIZE        45
+#endif
+
+
+
 /* Definitions only required from C code. */
 #if !__ASSEMBLER__
 
 #include <stdint.h>
 #include <core/token.h>
-
-/* NOTE: The MriExceptionHandler function definition in mriasm.S is dependent on the layout of this structure.  It
-         is also dictated by the version of gdb which supports the ARM processors.  It should only be changed if the
-         gdb ARM support code is modified and then the context saving and restoring code will need to be modified to
-         use the correct offsets as well.
-*/
-typedef struct
-{
-    uint32_t    R0;
-    uint32_t    R1;
-    uint32_t    R2;
-    uint32_t    R3;
-    uint32_t    R4;
-    uint32_t    R5;
-    uint32_t    R6;
-    uint32_t    R7;
-    uint32_t    R8;
-    uint32_t    R9;
-    uint32_t    R10;
-    uint32_t    R11;
-    uint32_t    R12;
-    uint32_t    SP;
-    uint32_t    LR;
-    uint32_t    PC;
-    uint32_t    CPSR;
-    uint32_t    MSP;
-    uint32_t    PSP;
-    uint32_t    PRIMASK;
-    uint32_t    BASEPRI;
-    uint32_t    FAULTMASK;
-    uint32_t    CONTROL;
+#include <core/scatter_gather.h>
+
+
+/* Give friendly names to the indices of important registers in the context scatter gather list. */
+#define R0      0
+#define R1      1
+#define R2      2
+#define R3      3
+#define R7      7
+#define SP      13
+#define LR      14
+#define PC      15
+#define CPSR    16
+#define BASEPRI 20
+
+
+#if MRI_THREAD_MRI
+    #define SPECIAL_REGISTER_COUNT      0
+#else
+    #define SPECIAL_REGISTER_COUNT      6
+#endif
 #if MRI_DEVICE_HAS_FPU
-    uint32_t    S0;
-    uint32_t    S1;
-    uint32_t    S2;
-    uint32_t    S3;
-    uint32_t    S4;
-    uint32_t    S5;
-    uint32_t    S6;
-    uint32_t    S7;
-    uint32_t    S8;
-    uint32_t    S9;
-    uint32_t    S10;
-    uint32_t    S11;
-    uint32_t    S12;
-    uint32_t    S13;
-    uint32_t    S14;
-    uint32_t    S15;
-    uint32_t    S16;
-    uint32_t    S17;
-    uint32_t    S18;
-    uint32_t    S19;
-    uint32_t    S20;
-    uint32_t    S21;
-    uint32_t    S22;
-    uint32_t    S23;
-    uint32_t    S24;
-    uint32_t    S25;
-    uint32_t    S26;
-    uint32_t    S27;
-    uint32_t    S28;
-    uint32_t    S29;
-    uint32_t    S30;
-    uint32_t    S31;
-    uint32_t    FPSCR;
+    #define CONTEXT_SIZE    (17 + 33 + SPECIAL_REGISTER_COUNT)
+#else
+    #define CONTEXT_SIZE    (17 + SPECIAL_REGISTER_COUNT)
 #endif
-} Context;
 
 /* NOTE: The largest buffer is required for receiving the 'G' command which receives the contents of the registers from
    the debugger as two hex digits per byte.  Also need a character for the 'G' command itself. */
-#define CORTEXM_PACKET_BUFFER_SIZE (1 + 2 * sizeof(Context))
+#define CORTEXM_PACKET_BUFFER_SIZE  (1 + 2 * sizeof(uint32_t) * CONTEXT_SIZE)
 
 typedef struct
 {
-    uint64_t            debuggerStack[CORTEXM_DEBUGGER_STACK_SIZE];
-    volatile uint32_t   flags;
-    volatile uint32_t   taskSP;
-    Context             context;
+    ScatterGather       context;
+    uint32_t            taskSP;
+    uint32_t            sp;
+    uint32_t            exceptionNumber;
+    uint32_t            dfsr;
+    uint32_t            hfsr;
+    uint32_t            cfsr;
+    uint32_t            mmfar;
+    uint32_t            bfar;
     uint32_t            originalPC;
     uint32_t            originalBasePriority;
+    uint32_t            subPriorityBitCount;
     int                 maxStackUsed;
     char                packetBuffer[CORTEXM_PACKET_BUFFER_SIZE];
 } CortexMState;
 
-extern CortexMState     __mriCortexMState;
-extern const uint32_t   __mriCortexMFakeStack[8];
+extern uint64_t             mriCortexMDebuggerStack[CORTEXM_DEBUGGER_STACK_SIZE];
+extern volatile uint32_t    mriCortexMFlags;
+extern CortexMState         mriCortexMState;
 
-void     __mriCortexMInit(Token* pParameterTokens);
+void    mriCortexMInit(Token* pParameterTokens, uint8_t debugMonPriority, IRQn_Type highestExternalIrq);
+void    mriCortexMSetPriority(IRQn_Type irq, uint8_t priority, uint8_t subPriority);
+uint8_t mriCortexMGetPriority(IRQn_Type irq);
 
-#endif /* !__ASSEMBLER__ */
 
+#endif /* !__ASSEMBLER__ */
 
-#endif /* _CORTEXM_H_ */
+#endif /* CORTEXM_H_ */