-
-
Notifications
You must be signed in to change notification settings - Fork 212
/
Copy path0008-Add-Arduino-Portenta-H7-target.patch
4748 lines (4705 loc) · 209 KB
/
0008-Add-Arduino-Portenta-H7-target.patch
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
From f047a7a75560af5465fd79bcb12de5455efc8eaf Mon Sep 17 00:00:00 2001
From: Martino Facchin <m.facchin@arduino.cc>
Date: Fri, 9 Aug 2019 16:29:30 +0200
Subject: [PATCH 08/31] Add Arduino Portenta H7 target
Add some defines for Envie
Change Envie base clock
Add QSPI support
Add Envie support
Fix some pinmux
Add ENVIE folder in TARGET_WICED
Add ethernet support
Partially port Envie to mainline
Add USBDEVICE support to H747
Declare USB pins for Envie
[ENVIE] Add pin definitions
Envie: restore HSEM irq handlers
ENVIE: enable setting an app offset
Envie: make Ethernet support mainlineable
Envie: ETH: set GPIo speed as very high
ENVIE: fix power tree
Envie: use complete pin_peripheral from ST
Envie: Adjust PLL
EnvieM4: fix available RAM
Envie: fix OTG USB functionality
Envie: remove fake arduino pins
ENVIE: fix build after removing Arduino pins
Envie: fix analog pinmux
Envie: force using external crystal
Enable oscillator at startup
Envie: Fix clock
EnvieM4: move OpenAMP defines to library
Envie: M4: eth: don't try to disable nonexisting caches
Envie: Cordio: restore functionality
Portenta: ETH: reset phy and add sw pinstrap
Envie: fix MCU name and remove SERIAL_ASYNC
Portenta: ethernet: set pinstrap to autonegoziation, 100Mbit
Portenta: fix HSI PLL multiplier
Portenta: use PWR_SMPS_1V8_SUPPLIES_LDO power scheme
Envie: delay oscillator start for Abracom
added initialization for HSICalibrationValue to prevent random clock setting
Added mbed original LED naming
---
components/wifi/esp8266-driver/mbed_lib.json | 4 +
.../TARGET_STM/TARGET_CYW4343X/HCIDriver.cpp | 465 +++++++++++
.../TARGET_PORTENTA_H7/stm32h7_eth_init.c | 170 ++++
.../emac-drivers/TARGET_STM/stm32xx_emac.cpp | 2 +
.../TARGET_PORTENTA_H7/PeripheralNames.h | 106 +++
.../TARGET_PORTENTA_H7/PeripheralPins.c | 599 +++++++++++++
.../TARGET_PORTENTA_H7/PinNames.h | 448 ++++++++++
.../TARGET_PORTENTA_H7/system_clock.c | 227 +++++
.../TARGET_PORTENTA_H7/system_stm32h7xx.c | 390 +++++++++
.../TOOLCHAIN_GCC_ARM/STM32H747xI.ld | 202 +++++
.../TOOLCHAIN_GCC_ARM/startup_stm32h747xx.S | 787 ++++++++++++++++++
.../TOOLCHAIN_GCC_ARM/STM32H747xI.ld | 220 +++++
.../TOOLCHAIN_GCC_ARM/startup_stm32h747xx.S | 787 ++++++++++++++++++
targets/TARGET_STM/TARGET_STM32H7/objects.h | 1 +
targets/TARGET_STM/USBPhy_STM32.cpp | 4 +
targets/targets.json | 92 ++
16 files changed, 4504 insertions(+)
create mode 100644 features/FEATURE_BLE/targets/TARGET_STM/TARGET_CYW4343X/HCIDriver.cpp
create mode 100644 features/netsocket/emac-drivers/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c
create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PeripheralNames.h
create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PeripheralPins.c
create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PinNames.h
create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock.c
create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_stm32h7xx.c
create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7_M4/TOOLCHAIN_GCC_ARM/STM32H747xI.ld
create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7_M4/TOOLCHAIN_GCC_ARM/startup_stm32h747xx.S
create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7_M7/TOOLCHAIN_GCC_ARM/STM32H747xI.ld
create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7_M7/TOOLCHAIN_GCC_ARM/startup_stm32h747xx.S
diff --git a/components/wifi/esp8266-driver/mbed_lib.json b/components/wifi/esp8266-driver/mbed_lib.json
index 6eefffc00f..c65c7a63f4 100644
--- a/components/wifi/esp8266-driver/mbed_lib.json
+++ b/components/wifi/esp8266-driver/mbed_lib.json
@@ -103,6 +103,10 @@
"NUCLEO_F411RE": {
"tx": "D8",
"rx": "D2"
+ },
+ "PORTENTA_H7": {
+ "tx": "PA_9",
+ "rx": "PA_10"
}
}
}
diff --git a/features/FEATURE_BLE/targets/TARGET_STM/TARGET_CYW4343X/HCIDriver.cpp b/features/FEATURE_BLE/targets/TARGET_STM/TARGET_CYW4343X/HCIDriver.cpp
new file mode 100644
index 0000000000..dc6062a216
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_STM/TARGET_CYW4343X/HCIDriver.cpp
@@ -0,0 +1,465 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdio.h>
+#include "CordioBLE.h"
+#include "CordioHCIDriver.h"
+#include "hci_api.h"
+#include "hci_cmd.h"
+#include "hci_core.h"
+#include "bstream.h"
+#include <stdbool.h>
+#include "hci_mbed_os_adaptation.h"
+#include "H4TransportDriver.h"
+
+extern const int brcm_patch_ram_length;
+extern const uint8_t brcm_patchram_buf[];
+
+static const uint8_t pre_brcm_patchram_buf[] = {
+ // RESET followed by download mini driver cmd
+ 0x03, 0x0C, 0x00,
+ 0x2E, 0xFC, 0x00,
+};
+static const int pre_brcm_patch_ram_length = sizeof(pre_brcm_patchram_buf);
+
+#define HCI_RESET_RAND_CNT 4
+#define HCI_VS_CMD_SET_SLEEP_MODE 0xFC27
+
+
+extern "C" uint32_t Set_GPIO_Clock(uint32_t port_idx);
+
+// 0: push pull
+// 1: open drain
+static void output_mode(PinName pin, int mode)
+{
+ MBED_ASSERT(pin != (PinName)NC);
+ uint32_t port_index = STM_PORT(pin);
+ uint32_t pin_index = STM_PIN(pin);
+
+ // Enable GPIO clock
+ uint32_t gpio_add = Set_GPIO_Clock(port_index);
+ GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+#if defined(STM32H7)
+ #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
+#endif
+
+ /* Output mode configuration*/
+ gpio->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pin_index)) ;
+ gpio->OTYPER |= (uint16_t)(((uint16_t)mode) << ((uint16_t)pin_index));
+}
+
+namespace ble {
+namespace vendor {
+namespace wise1530 {
+
+class HCIDriver : public cordio::CordioHCIDriver {
+public:
+ HCIDriver(
+ cordio::CordioHCITransportDriver& transport_driver,
+ PinName bt_host_wake_name,
+ PinName bt_device_wake_name,
+ PinName bt_power_name
+ ) : cordio::CordioHCIDriver(transport_driver),
+ bt_host_wake_name(bt_host_wake_name),
+ bt_device_wake_name(bt_device_wake_name),
+ bt_power_name(bt_power_name),
+ bt_host_wake(bt_host_wake_name, PIN_INPUT, PullNone, 0),
+ bt_device_wake(bt_device_wake_name, PIN_OUTPUT, PullDefault, 1),
+ bt_power(bt_power_name, PIN_OUTPUT, PullUp, 0),
+ service_pack_index(0),
+ service_pack_ptr(0),
+ service_pack_length(0),
+ service_pack_next(),
+ service_pack_transfered(false) {
+ }
+
+ virtual cordio::buf_pool_desc_t get_buffer_pool_description()
+ {
+ // Use default buffer pool
+ return cordio::CordioHCIDriver::get_default_buffer_pool_description();
+ }
+
+ virtual void do_initialize()
+ {
+ output_mode(bt_host_wake_name, 1);
+ output_mode(bt_device_wake_name, 0);
+ output_mode(bt_power_name, 1);
+
+ ThisThread::sleep_for(500);
+
+ bt_device_wake = 0;
+ ThisThread::sleep_for(500);
+
+ bt_power = 1;
+ ThisThread::sleep_for(500);
+ }
+
+ virtual void do_terminate() { }
+
+ virtual void start_reset_sequence()
+ {
+ prepare_service_pack_transfert();
+ }
+
+ virtual void handle_reset_sequence(uint8_t *pMsg)
+ {
+ uint16_t opcode;
+ static uint8_t randCnt;
+
+ /* if event is a command complete event */
+ if (*pMsg == HCI_CMD_CMPL_EVT) {
+ /* parse parameters */
+ pMsg += HCI_EVT_HDR_LEN;
+ pMsg++; /* skip num packets */
+ BSTREAM_TO_UINT16(opcode, pMsg);
+ pMsg++; /* skip status */
+
+ if (service_pack_transfered == false) {
+ randCnt = 0;
+ ack_service_pack_command(opcode, pMsg);
+ return;
+ }
+
+ /* decode opcode */
+ switch (opcode) {
+ // Note: Reset is handled by ack_service_pack.
+ case HCI_VS_CMD_SET_SLEEP_MODE:
+ HciWriteLeHostSupport();
+ break;
+
+ case HCI_OPCODE_WRITE_LE_HOST_SUPPORT:
+ randCnt = 0;
+ /* send next command in sequence */
+ HciSetEventMaskCmd((uint8_t *) hciEventMask);
+ break;
+
+ case HCI_OPCODE_SET_EVENT_MASK:
+ randCnt = 0;
+ /* send next command in sequence */
+ HciLeSetEventMaskCmd((uint8_t *) hciLeEventMask);
+ break;
+
+ case HCI_OPCODE_LE_SET_EVENT_MASK:
+ /* send next command in sequence */
+ HciSetEventMaskPage2Cmd((uint8_t *) hciEventMaskPage2);
+ break;
+
+ case HCI_OPCODE_SET_EVENT_MASK_PAGE2:
+ /* send next command in sequence */
+ HciReadBdAddrCmd();
+ break;
+
+ case HCI_OPCODE_READ_BD_ADDR:
+ /* parse and store event parameters */
+ BdaCpy(hciCoreCb.bdAddr, pMsg);
+ HciLeReadBufSizeCmd();
+ break;
+
+ case HCI_OPCODE_LE_READ_BUF_SIZE:
+ /* parse and store event parameters */
+ BSTREAM_TO_UINT16(hciCoreCb.bufSize, pMsg);
+ BSTREAM_TO_UINT8(hciCoreCb.numBufs, pMsg);
+
+ // FixMe: The number of ACL buffer returned by the chip is
+ // incorrect. If more than two ACL packets are present in
+ // the controller, it may block the controller.
+ // Important: The ACL overflow event is **not** reported
+ // by the controller.
+ hciCoreCb.numBufs = 2;
+
+ /* initialize ACL buffer accounting */
+ hciCoreCb.availBufs = hciCoreCb.numBufs;
+
+ /* send next command in sequence */
+ HciLeReadSupStatesCmd();
+ break;
+
+ case HCI_OPCODE_LE_READ_SUP_STATES:
+ /* parse and store event parameters */
+ memcpy(hciCoreCb.leStates, pMsg, HCI_LE_STATES_LEN);
+
+ /* send next command in sequence */
+ HciLeReadWhiteListSizeCmd();
+ break;
+
+ case HCI_OPCODE_LE_READ_WHITE_LIST_SIZE:
+ /* parse and store event parameters */
+ BSTREAM_TO_UINT8(hciCoreCb.whiteListSize, pMsg);
+
+ /* send next command in sequence */
+ HciLeReadLocalSupFeatCmd();
+ break;
+
+ case HCI_OPCODE_LE_READ_LOCAL_SUP_FEAT:
+ /* parse and store event parameters */
+ BSTREAM_TO_UINT16(hciCoreCb.leSupFeat, pMsg);
+
+ /* send next command in sequence */
+ hciCoreReadResolvingListSize();
+ break;
+
+ case HCI_OPCODE_LE_READ_RES_LIST_SIZE:
+ /* parse and store event parameters */
+ BSTREAM_TO_UINT8(hciCoreCb.resListSize, pMsg);
+
+ /* send next command in sequence */
+ hciCoreReadMaxDataLen();
+ break;
+
+ case HCI_OPCODE_LE_READ_MAX_DATA_LEN: {
+ uint16_t maxTxOctets;
+ uint16_t maxTxTime;
+
+ BSTREAM_TO_UINT16(maxTxOctets, pMsg);
+ BSTREAM_TO_UINT16(maxTxTime, pMsg);
+
+ /* use Controller's maximum supported payload octets and packet duration times
+ * for transmission as Host's suggested values for maximum transmission number
+ * of payload octets and maximum packet transmission time for new connections.
+ */
+ HciLeWriteDefDataLen(maxTxOctets, maxTxTime);
+ } break;
+
+ case HCI_OPCODE_LE_WRITE_DEF_DATA_LEN:
+ if (hciCoreCb.extResetSeq) {
+ /* send first extended command */
+ (*hciCoreCb.extResetSeq)(pMsg, opcode);
+ } else {
+ /* initialize extended parameters */
+ hciCoreCb.maxAdvDataLen = 0;
+ hciCoreCb.numSupAdvSets = 0;
+ hciCoreCb.perAdvListSize = 0;
+
+ /* send next command in sequence */
+ HciLeRandCmd();
+ }
+ break;
+
+ case HCI_OPCODE_LE_READ_MAX_ADV_DATA_LEN:
+ case HCI_OPCODE_LE_READ_NUM_SUP_ADV_SETS:
+ case HCI_OPCODE_LE_READ_PER_ADV_LIST_SIZE:
+ if (hciCoreCb.extResetSeq) {
+ /* send next extended command in sequence */
+ (*hciCoreCb.extResetSeq)(pMsg, opcode);
+ }
+ break;
+
+ case HCI_OPCODE_LE_RAND:
+ /* check if need to send second rand command */
+ if (randCnt < (HCI_RESET_RAND_CNT-1)) {
+ randCnt++;
+ HciLeRandCmd();
+ } else {
+ uint8_t addr[6] = { 0 };
+ memcpy(addr, pMsg, sizeof(addr));
+ DM_RAND_ADDR_SET(addr, DM_RAND_ADDR_STATIC);
+ // note: will invoke set rand address
+ set_random_static_address(addr);
+ }
+ break;
+
+ case HCI_OPCODE_LE_SET_RAND_ADDR:
+ /* send next command in sequence */
+ signal_reset_sequence_done();
+ break;
+
+ default:
+ break;
+ }
+ }
+ }
+
+private:
+
+ // send pre_brcm_patchram_buf
+ void prepare_service_pack_transfert(void)
+ {
+ service_pack_ptr = pre_brcm_patchram_buf;
+ service_pack_length = pre_brcm_patch_ram_length;
+ service_pack_next = &HCIDriver::start_service_pack_transfert;
+ service_pack_index = 0;
+ service_pack_transfered = false;
+ send_service_pack_command();
+ }
+
+ // Called once pre_brcm_patchram_buf has been transferred; send brcm_patchram_buf
+ void start_service_pack_transfert(void)
+ {
+ service_pack_ptr = brcm_patchram_buf;
+ service_pack_length = brcm_patch_ram_length;
+ service_pack_next = &HCIDriver::terminate_service_pack_transfert;
+ service_pack_index = 0;
+ service_pack_transfered = false;
+ send_service_pack_command();
+ }
+
+ // Called once post_brcm_patchram_buf has been transferred; start regular initialization.
+ void terminate_service_pack_transfert(void)
+ {
+ service_pack_ptr = NULL;
+ service_pack_length = 0;
+ service_pack_next = NULL;
+ service_pack_index = 0;
+ service_pack_transfered = true;
+ ThisThread::sleep_for(1000);
+ set_sleep_mode();
+ }
+
+ void send_service_pack_command(void)
+ {
+ uint16_t cmd_len = service_pack_ptr[service_pack_index + 2];
+ uint16_t cmd_opcode = (service_pack_ptr[service_pack_index + 1] << 8) | service_pack_ptr[service_pack_index + 0];
+ uint8_t *pBuf = hciCmdAlloc(cmd_opcode, cmd_len);
+ if (pBuf) {
+ memcpy(pBuf + HCI_CMD_HDR_LEN, service_pack_ptr + service_pack_index + HCI_CMD_HDR_LEN, cmd_len);
+ hciCmdSend(pBuf);
+ } else {
+ }
+ }
+
+ void ack_service_pack_command(uint16_t opcode, uint8_t* msg)
+ {
+ uint16_t cmd_opcode = (service_pack_ptr[service_pack_index + 1] << 8) | service_pack_ptr[service_pack_index + 0];
+
+ if (cmd_opcode != opcode) {
+ // DO something in case of error
+
+ while (true);
+
+ }
+
+ // update service pack index
+ service_pack_index += (HCI_CMD_HDR_LEN + service_pack_ptr[service_pack_index + 2]);
+
+ if (service_pack_index < service_pack_length) {
+ send_service_pack_command();
+ } else {
+ (this->*service_pack_next)();
+ }
+ }
+
+ void set_sleep_mode()
+ {
+ uint8_t *pBuf;
+ if ((pBuf = hciCmdAlloc(HCI_VS_CMD_SET_SLEEP_MODE, 12)) != NULL)
+ {
+ pBuf[HCI_CMD_HDR_LEN] = 0x00; // no sleep moode
+ pBuf[HCI_CMD_HDR_LEN + 1] = 0x00; // no idle threshold host (N/A)
+ pBuf[HCI_CMD_HDR_LEN + 2] = 0x00; // no idle threshold HC (N/A)
+ pBuf[HCI_CMD_HDR_LEN + 3] = 0x00; // BT WAKE
+ pBuf[HCI_CMD_HDR_LEN + 4] = 0x00; // HOST WAKE
+ pBuf[HCI_CMD_HDR_LEN + 5] = 0x00; // Sleep during SCO
+ pBuf[HCI_CMD_HDR_LEN + 6] = 0x00; // Combining sleep mode and SCM
+ pBuf[HCI_CMD_HDR_LEN + 7] = 0x00; // Tristate TX
+ pBuf[HCI_CMD_HDR_LEN + 8] = 0x00; // Active connection handling on suspend
+ pBuf[HCI_CMD_HDR_LEN + 9] = 0x00; // resume timeout
+ pBuf[HCI_CMD_HDR_LEN + 10] = 0x00; // break to host
+ pBuf[HCI_CMD_HDR_LEN + 10] = 0x00; // Pulsed host wake
+ hciCmdSend(pBuf);
+ }
+ }
+
+ static const uint16_t HCI_OPCODE_WRITE_LE_HOST_SUPPORT = 0x0C6D;
+
+ void HciWriteLeHostSupport()
+ {
+ uint8_t *pBuf;
+ if ((pBuf = hciCmdAlloc(HCI_OPCODE_WRITE_LE_HOST_SUPPORT, 2)) != NULL)
+ {
+ pBuf[HCI_CMD_HDR_LEN] = 0x01;
+ pBuf[HCI_CMD_HDR_LEN + 1] = 0x00;
+ hciCmdSend(pBuf);
+ }
+ }
+
+ void hciCoreReadResolvingListSize(void)
+ {
+ /* if LL Privacy is supported by Controller and included */
+ if ((hciCoreCb.leSupFeat & HCI_LE_SUP_FEAT_PRIVACY) &&
+ (hciLeSupFeatCfg & HCI_LE_SUP_FEAT_PRIVACY))
+ {
+ /* send next command in sequence */
+ HciLeReadResolvingListSize();
+ }
+ else
+ {
+ hciCoreCb.resListSize = 0;
+
+ /* send next command in sequence */
+ hciCoreReadMaxDataLen();
+ }
+ }
+
+ void hciCoreReadMaxDataLen(void)
+ {
+ /* if LE Data Packet Length Extensions is supported by Controller and included */
+ if ((hciCoreCb.leSupFeat & HCI_LE_SUP_FEAT_DATA_LEN_EXT) &&
+ (hciLeSupFeatCfg & HCI_LE_SUP_FEAT_DATA_LEN_EXT))
+ {
+ /* send next command in sequence */
+ HciLeReadMaxDataLen();
+ }
+ else
+ {
+ /* send next command in sequence */
+ HciLeRandCmd();
+ }
+ }
+
+ PinName bt_host_wake_name;
+ PinName bt_device_wake_name;
+ PinName bt_power_name;
+ DigitalInOut bt_host_wake;
+ DigitalInOut bt_device_wake;
+ DigitalInOut bt_power;
+ size_t service_pack_index;
+ const uint8_t* service_pack_ptr;
+ int service_pack_length;
+ void (HCIDriver::*service_pack_next)();
+ bool service_pack_transfered;
+
+};
+
+} // namespace wise1530
+} // namespace vendor
+} // namespace ble
+
+#if defined(STM32H7)
+
+ble::vendor::cordio::CordioHCIDriver& ble_cordio_get_hci_driver() {
+ static ble::vendor::cordio::H4TransportDriver transport_driver(
+ /* TX */ PA_15, /* RX */ PF_6, /* cts */ PF_9, /* rts */ PF_8, 115200
+ );
+ static ble::vendor::wise1530::HCIDriver hci_driver(
+ transport_driver, /* host wake */ PJ_13, /* device wake */ PJ_14, /* bt_power */ PJ_12
+ );
+ return hci_driver;
+}
+
+#else
+
+ble::vendor::cordio::CordioHCIDriver& ble_cordio_get_hci_driver() {
+ static ble::vendor::cordio::H4TransportDriver transport_driver(
+ /* TX */ PA_2, /* RX */ PA_3, /* cts */ PA_0, /* rts */ PA_1, 115200
+ );
+ static ble::vendor::wise1530::HCIDriver hci_driver(
+ transport_driver, /* host wake */ PC_0, /* device wake */ PB_8, /* bt_power */ PC_6
+ );
+ return hci_driver;
+}
+
+#endif
\ No newline at end of file
diff --git a/features/netsocket/emac-drivers/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c b/features/netsocket/emac-drivers/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c
new file mode 100644
index 0000000000..38d9611ba4
--- /dev/null
+++ b/features/netsocket/emac-drivers/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c
@@ -0,0 +1,170 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define ETHERNET 1
+
+#ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT
+
+#include "stm32h7xx_hal.h"
+
+#define ETH_TX_EN_Pin GPIO_PIN_11
+#define ETH_TX_EN_GPIO_Port GPIOG
+#define ETH_TXD1_Pin GPIO_PIN_12
+#define ETH_TXD1_GPIO_Port GPIOG
+#define ETH_TXD0_Pin GPIO_PIN_13
+#define ETH_TXD0_GPIO_Port GPIOG
+#define ETH_MDC_SAI4_D1_Pin GPIO_PIN_1
+#define ETH_MDC_SAI4_D1_GPIO_Port GPIOC
+#define ETH_MDIO_Pin GPIO_PIN_2
+#define ETH_MDIO_GPIO_Port GPIOA
+#define ETH_REF_CLK_Pin GPIO_PIN_1
+#define ETH_REF_CLK_GPIO_Port GPIOA
+#define ETH_CRS_DV_Pin GPIO_PIN_7
+#define ETH_CRS_DV_GPIO_Port GPIOA
+#define ETH_RXD0_Pin GPIO_PIN_4
+#define ETH_RXD0_GPIO_Port GPIOC
+#define ETH_RXD1_Pin GPIO_PIN_5
+#define ETH_RXD1_GPIO_Port GPIOC
+
+/**
+ * Override HAL Eth Init function
+ */
+void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
+{
+ GPIO_InitTypeDef GPIO_InitStruct;
+ if(heth->Instance == ETH)
+ {
+ #if !(defined(DUAL_CORE) && defined(CORE_CM4))
+ /* Disable DCache for STM32H7 family */
+ SCB_DisableDCache();
+ #endif
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ // __HAL_RCC_GPIOB_CLK_ENABLE();
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOG_CLK_ENABLE();
+ // __HAL_RCC_GPIOH_CLK_ENABLE();
+
+ /* Enable Peripheral clock */
+ __HAL_RCC_ETH1MAC_CLK_ENABLE();
+ __HAL_RCC_ETH1TX_CLK_ENABLE();
+ __HAL_RCC_ETH1RX_CLK_ENABLE();
+
+ /* Set pinstrap for 100mbit */
+ // TODO
+
+ /* Reset ETH Phy */
+ __HAL_RCC_GPIOJ_CLK_ENABLE();
+ GPIO_InitTypeDef gpio_eth_rst_init_structure;
+ gpio_eth_rst_init_structure.Pin = GPIO_PIN_15;
+ gpio_eth_rst_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
+ gpio_eth_rst_init_structure.Pull = GPIO_NOPULL;
+ gpio_eth_rst_init_structure.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(GPIOJ, &gpio_eth_rst_init_structure);
+
+ gpio_eth_rst_init_structure.Pin = ETH_RXD0_Pin | ETH_RXD1_Pin;
+ HAL_GPIO_Init(GPIOC, &gpio_eth_rst_init_structure);
+ HAL_GPIO_WritePin(GPIOC, ETH_RXD0_Pin, 1);
+ HAL_GPIO_WritePin(GPIOC, ETH_RXD1_Pin, 1);
+ gpio_eth_rst_init_structure.Pin = ETH_CRS_DV_Pin;
+ HAL_GPIO_Init(GPIOA, &gpio_eth_rst_init_structure);
+ HAL_GPIO_WritePin(GPIOA, ETH_CRS_DV_Pin, 1);
+
+ HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 0);
+ HAL_Delay(100);
+ HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 1);
+
+ /**ETH GPIO Configuration
+ PG11 ------> ETH_TX_EN
+ PG12 ------> ETH_TXD1
+ PG13 ------> ETH_TXD0
+ PC1 ------> ETH_MDC
+ PA2 ------> ETH_MDIO
+ PA1 ------> ETH_REF_CLK
+ PA7 ------> ETH_CRS_DV
+ PC4 ------> ETH_RXD0
+ PC5 ------> ETH_RXD1
+ */
+ GPIO_InitStruct.Pin = ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+ HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+ HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ }
+}
+
+/**
+ * Override HAL Eth DeInit function
+ */
+void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
+{
+ if(heth->Instance == ETH)
+ {
+ /* Peripheral clock disable */
+ __HAL_RCC_ETH1MAC_CLK_DISABLE();
+ __HAL_RCC_ETH1TX_CLK_DISABLE();
+ __HAL_RCC_ETH1RX_CLK_DISABLE();
+
+ /**ETH GPIO Configuration
+ PG11 ------> ETH_TX_EN
+ PG12 ------> ETH_TXD1
+ PG13 ------> ETH_TXD0
+ PC1 ------> ETH_MDC
+ PA2 ------> ETH_MDIO
+ PA1 ------> ETH_REF_CLK
+ PA7 ------> ETH_CRS_DV
+ PC4 ------> ETH_RXD0
+ PC5 ------> ETH_RXD1
+ */
+ HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin);
+
+ HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin);
+
+ HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin);
+
+ HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 0);
+ }
+}
+
+#endif /* USE_USER_DEFINED_HAL_ETH_MSPINIT */
diff --git a/features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.cpp b/features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.cpp
index 7ae8276cf6..950ef4a1dd 100644
--- a/features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.cpp
+++ b/features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.cpp
@@ -654,8 +654,10 @@ int STM32_EMAC::low_level_input(emac_mem_buf_t **buf)
/* Build Rx descriptor to be ready for next data reception */
HAL_ETH_BuildRxDescriptors(&EthHandle);
+#if !(defined(DUAL_CORE) && defined(CORE_CM4))
/* Invalidate data cache for ETH Rx Buffers */
SCB_InvalidateDCache_by_Addr((uint32_t *)RxBuff.buffer, frameLength);
+#endif
*buf = pbuf_alloc(PBUF_RAW, frameLength, PBUF_POOL);
if (*buf) {
diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PeripheralNames.h
new file mode 100644
index 0000000000..e52003787f
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PeripheralNames.h
@@ -0,0 +1,106 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE,
+ ADC_2 = (int)ADC2_BASE,
+ ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+ DAC_1 = DAC1_BASE
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_3 = (int)USART3_BASE,
+ UART_4 = (int)UART4_BASE,
+ UART_5 = (int)UART5_BASE,
+ UART_6 = (int)USART6_BASE,
+ UART_7 = (int)UART7_BASE,
+ UART_8 = (int)UART8_BASE,
+ LPUART_1 = (int)LPUART1_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE,
+ SPI_5 = (int)SPI5_BASE,
+ SPI_6 = (int)SPI6_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE,
+ I2C_4 = (int)I2C4_BASE
+} I2CName;
+
+typedef enum {
+ PWM_I = (int)HRTIM1_BASE,
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_8 = (int)TIM8_BASE,
+ PWM_12 = (int)TIM12_BASE,
+ PWM_13 = (int)TIM13_BASE,
+ PWM_14 = (int)TIM14_BASE,
+ PWM_15 = (int)TIM15_BASE,
+ PWM_16 = (int)TIM16_BASE,
+ PWM_17 = (int)TIM17_BASE
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)FDCAN1_BASE,
+ CAN_2 = (int)FDCAN2_BASE
+} CANName;
+
+typedef enum {
+ QSPI_1 = (int)QSPI_R_BASE,
+} QSPIName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PeripheralPins.c
new file mode 100644
index 0000000000..7fe76b5bfc
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PeripheralPins.c
@@ -0,0 +1,599 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2019, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ *
+ * Automatically generated from STM32H747XIHx.xml
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+// HW peripheral instances. You can use them the same way as any other "normal"
+// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+// pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+// the comment "Connected to xxx". The pin function may not work properly in this
+// case. These pins may not be displayed on the board pinout image on mbed.org.
+// Please read the board reference manual and schematic for more information.
+//
+// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
+// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//
+//==============================================================================
+
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_INP16 // Connected to PMOD\#1- USART2_CTS_NSS
+ {PA_0_C, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INN1 // Connected to ARD_A2
+ {PA_0_C_ALT0,ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 // Connected to ARD_A2
+ {PA_0_C_ALT1,ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INN1 // Connected to ARD_A2
+ {PA_0_C_ALT2,ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 // Connected to ARD_A2
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_INN16 // Connected to ETH_REF_CLK
+ {PA_1_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_INP17 // Connected to ETH_REF_CLK
+ {PA_1_C, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 // Connected to ARD_A3
+ {PA_1_C_ALT0,ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 // Connected to ARD_A3
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 // Connected to ETH_MDIO
+ {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 // Connected to ETH_MDIO
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 // Connected to ULPI_D0
+ {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 // Connected to ULPI_D0
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18
+ {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INN18 // Connected to ULPI_CK
+ {PA_5_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 // Connected to ULPI_CK
+ {PA_5_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INN18 // Connected to ULPI_CK
+ {PA_5_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 // Connected to ULPI_CK
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3
+ {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INN3 // Connected to ETH_CRS_DV
+ {PA_7_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 // Connected to ETH_CRS_DV
+ {PA_7_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INN3 // Connected to ETH_CRS_DV
+ {PA_7_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 // Connected to ETH_CRS_DV
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INN5 // Connected to ULPI_D1
+ {PB_0_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 // Connected to ULPI_D1
+ {PB_0_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INN5 // Connected to ULPI_D1
+ {PB_0_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 // Connected to ULPI_D1
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 // Connected to ULPI_D2
+ {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 // Connected to ULPI_D2
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 // Connected to ULPI_STP
+ {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 // Connected to ULPI_STP
+ {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INP10 // Connected to ULPI_STP
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INN10 // Connected to SAI4_D1 (default: SB8 off/SB21 on), ETH_MDC (SB8 on/SB21 off)
+ {PC_1_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 // Connected to SAI4_D1 (default: SB8 off/SB21 on), ETH_MDC (SB8 on/SB21 off)
+ {PC_1_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INN10 // Connected to SAI4_D1 (default: SB8 off/SB21 on), ETH_MDC (SB8 on/SB21 off)
+ {PC_1_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 // Connected to SAI4_D1 (default: SB8 off/SB21 on), ETH_MDC (SB8 on/SB21 off)
+ {PC_1_ALT3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INN10 // Connected to SAI4_D1 (default: SB8 off/SB21 on), ETH_MDC (SB8 on/SB21 off)