@@ -319,8 +319,7 @@ static void soc_i2c_master_init_transfer(i2c_internal_data_t *dev)
319319 ic_con = MMIO_REG_VAL_FROM_BASE (dev -> BASE , IC_CON );
320320
321321 /* Set addressing mode - (initialisation = 7 bit) */
322- //if (I2C_10_Bit == dev->addr_mode) {
323- if (dev -> slave_addr > 127 ) {
322+ if (I2C_10_Bit == dev -> addr_mode ) {
324323 ic_con |= IC_MASTER_ADDR_MODE_BIT ;
325324 ic_tar = IC_TAR_10BITADDR_MASTER ;
326325 } else {
@@ -357,6 +356,7 @@ static DRIVER_API_RC soc_i2c_init(i2c_internal_data_t *dev)
357356 soc_i2c_enable_device (dev , false);
358357
359358 /* Setup IC_CON */
359+ ic_con = IC_STOP_DET_IFADDRESSED ;
360360
361361 /* Set master or slave mode - (initialisation = slave) */
362362 if (I2C_MASTER == dev -> mode ) {
@@ -532,8 +532,7 @@ DRIVER_API_RC soc_i2c_deconfig(SOC_I2C_CONTROLLER controller_id)
532532 return DRV_RC_FAIL ;
533533 }
534534
535- if (!dev -> send_stop )
536- {
535+ if (!dev -> send_stop ) {
537536 soc_i2c_abort_transfer (dev );
538537 }
539538
@@ -584,6 +583,92 @@ DRIVER_API_RC soc_i2c_clock_disable(SOC_I2C_CONTROLLER controller_id)
584583 return DRV_RC_OK ;
585584}
586585
586+ DRIVER_API_RC soc_i2c_set_transfer_speed (SOC_I2C_CONTROLLER controller_id ,
587+ uint32_t speed )
588+ {
589+ volatile uint32_t ic_con = 0 ;
590+ i2c_internal_data_t * dev = NULL ;
591+
592+ if (controller_id == SOC_I2C_0 ) {
593+ dev = & devices [0 ];
594+ } else if (controller_id == SOC_I2C_1 ) {
595+ dev = & devices [1 ];
596+ } else {
597+ return DRV_RC_FAIL ;
598+ }
599+
600+ dev -> speed = speed ;
601+
602+ soc_i2c_enable_device (dev , false);
603+
604+ /* Setup IC_CON */
605+ ic_con = MMIO_REG_VAL_FROM_BASE (dev -> BASE , IC_CON );
606+
607+ ic_con |= (dev -> speed << 1 );
608+
609+ MMIO_REG_VAL_FROM_BASE (dev -> BASE , IC_CON ) = ic_con ;
610+
611+ if (I2C_SLOW ==
612+ dev -> speed ) /* This is setter so prefering readability above speed */
613+ {
614+ /* Set HCNT */
615+ MMIO_REG_VAL_FROM_BASE (dev -> BASE , IC_STD_SCL_HCNT ) = I2C_STD_HCNT ;
616+ /* Set LCNT */
617+ MMIO_REG_VAL_FROM_BASE (dev -> BASE , IC_STD_SCL_LCNT ) = I2C_STD_LCNT ;
618+ } else if (I2C_FAST == dev -> speed ) {
619+ /* Set HCNT */
620+ MMIO_REG_VAL_FROM_BASE (dev -> BASE , IC_FS_SCL_HCNT ) = I2C_FS_HCNT ;
621+ /* Set LCNT */
622+ MMIO_REG_VAL_FROM_BASE (dev -> BASE , IC_FS_SCL_LCNT ) = I2C_FS_LCNT ;
623+ } else if (I2C_HS == dev -> speed ) {
624+ /* Set HCNT */
625+ MMIO_REG_VAL_FROM_BASE (dev -> BASE , IC_HS_SCL_HCNT ) = I2C_HS_HCNT ;
626+ /* Set LCNT */
627+ MMIO_REG_VAL_FROM_BASE (dev -> BASE , IC_HS_SCL_LCNT ) = I2C_HS_LCNT ;
628+ } else {
629+ return DRV_RC_FAIL ;
630+ }
631+
632+ return DRV_RC_OK ;
633+ }
634+
635+ DRIVER_API_RC soc_i2c_set_transfer_mode (SOC_I2C_CONTROLLER controller_id ,
636+ uint32_t mode )
637+ {
638+ i2c_internal_data_t * dev = NULL ;
639+
640+ if (controller_id == SOC_I2C_0 ) {
641+ dev = & devices [0 ];
642+ } else if (controller_id == SOC_I2C_1 ) {
643+ dev = & devices [1 ];
644+ } else {
645+ return DRV_RC_FAIL ;
646+ }
647+
648+ dev -> addr_mode = mode ;
649+
650+ if (dev -> mode == I2C_SLAVE ) {
651+ volatile uint32_t ic_con = 0 ;
652+
653+ soc_i2c_enable_device (dev , false);
654+
655+ /* Setup IC_CON */
656+ ic_con = MMIO_REG_VAL_FROM_BASE (dev -> BASE , IC_CON );
657+
658+ if (I2C_10_Bit == dev -> addr_mode ) {
659+ ic_con |= IC_SLAVE_ADDR_MODE_BIT ;
660+ } else {
661+ ic_con &= ~IC_SLAVE_ADDR_MODE_BIT ;
662+ }
663+
664+ MMIO_REG_VAL_FROM_BASE (dev -> BASE , IC_CON ) = ic_con ;
665+
666+ soc_i2c_enable_device (dev , true);
667+ }
668+
669+ return DRV_RC_OK ;
670+ }
671+
587672DRIVER_API_RC soc_i2c_slave_enable_tx (SOC_I2C_CONTROLLER controller_id ,
588673 uint8_t * data_write ,
589674 uint32_t data_write_len )
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