diff --git a/.gitignore b/.gitignore index 2903585..3bc3825 100644 --- a/.gitignore +++ b/.gitignore @@ -1,6 +1,8 @@ *.rbf_r *.zip dist/**/*.rev +dist/**/*.bin +src/**/*.bin src/sim/work/ src/sim/*.hex src/sim/*.mem diff --git a/README.md b/README.md index 2cc9391..fa2d035 100644 --- a/README.md +++ b/README.md @@ -15,11 +15,7 @@ To install the core, copy the `Assets`, `Cores`, and `Platform` folders over to ## Usage -**NOTE:** ROM files must not contain a SMC header. If a ROM isn't loading and you think it should, check if it has a header with a tool like [Advanced SNES ROM Utility](https://www.romhacking.net/utilities/1638/) and remove it if so. - -ROMs should be placed in `/Assets/snes/common` - -PAL ROMs should boot, but there may be timing issues as the core currently doesn't properly support PAL (proper support coming soon). +ROMs should be placed in `/Assets/snes/common`. Both headered and unheadered ROMs are now supported. ## Features @@ -29,9 +25,11 @@ Core supports four players/controllers via the Analogue Dock. To enable four pla ### Expansion Chips -The currently supported expansion chips are SA-1 (Super Mario RPG), Super FX (GSU-1/2; Star Fox), DSP (Super Mario Kart), and CX4 (Mega Man X 2). Additional chip support will come in the future once several new firmware features are released. +All original expansion chips supported by MiSTer are also supported on the Pocket. The full list is: SA-1 (Super Mario RPG), Super FX/GSU-1/2 (Star Fox), DSP (Super Mario Kart), CX4 (Mega Man X 2), S-DD1 (Star Ocean), SPC7110 (Far East of Eden), ST1010 (F1 Roc 2), and BSX (Satellaview). The Super Game Boy, ST011 (Hayazashi Nidan Morita Shougi), and ST018 (Hayazashi Nidan Morita Shougi 2) are not supported in the MiSTer core, and therefore are not supported here. Additionally, the homebrew MSU expansion chip is not currently supported. + +#### BSX -**NOTE:** The S-DD1 chip was dropped in release 0.2.0 due to sizing and popularity issues. Support will resume in a future release. In the meantime, you can [use this hack to remove the S-DD1 requirement](https://www.romhacking.net/hacks/614/). +BSX ROMs must be patched to run without BIOS. The BSX BIOS is not currently supported ### Video Modes diff --git a/dist/Cores/agg23.SNES/core.json b/dist/Cores/agg23.SNES/core.json index d55d325..95949d1 100644 --- a/dist/Cores/agg23.SNES/core.json +++ b/dist/Cores/agg23.SNES/core.json @@ -7,8 +7,8 @@ "description": "Super Nintendo and Super Famicom. Nintendo's second major home console", "author": "agg23", "url": "https://github.com/agg23/openfpga-snes", - "version": "0.3.2", - "date_release": "2022-10-10" + "version": "0.4.0-pre", + "date_release": "2022-10-27" }, "framework": { "target_product": "Analogue Pocket", @@ -21,13 +21,19 @@ "hardware": { "link_port": false, "cartridge_adapter": -1 - } + }, + "chip32_vm": "loader.bin" }, "cores": [ { - "name": "default", + "name": "main", "id": 0, "filename": "snes_main.rev" + }, + { + "name": "SPCSDD1", + "id": 1, + "filename": "snes_spc.rev" } ] } diff --git a/dist/Cores/agg23.SNES/data.json b/dist/Cores/agg23.SNES/data.json index 4bccf04..89df44c 100644 --- a/dist/Cores/agg23.SNES/data.json +++ b/dist/Cores/agg23.SNES/data.json @@ -3,11 +3,11 @@ "magic": "APF_VER_1", "data_slots": [ { - "name": "SMC", + "name": "Cartridge", "id": 0, "required": true, "parameters": "0x109", - "extensions": ["smc", "sfc"], + "extensions": ["smc", "sfc", "bs"], "address": "0x10000000" }, { diff --git a/generate.tcl b/generate.tcl new file mode 100644 index 0000000..9014a3f --- /dev/null +++ b/generate.tcl @@ -0,0 +1,54 @@ +# Run with quartus_sh -t generate.tcl + +# Load Quartus II Tcl Project package +package require ::quartus::project + +# Required for compilation +package require ::quartus::flow + +if { $argc != 1 } { + puts "Exactly 1 argument required" + exit +} + +project_open src/fpga/ap_core.qpf + +if { [lindex $argv 0] == "ntsc" } { + puts "NTSC" + set_parameter -name USE_CX4 -entity MAIN_SNES 1 + set_parameter -name USE_SDD1 -entity MAIN_SNES 0 + set_parameter -name USE_GSU -entity MAIN_SNES 1 + set_parameter -name USE_SA1 -entity MAIN_SNES 1 + set_parameter -name USE_DSPn -entity MAIN_SNES 1 + set_parameter -name USE_SPC7110 -entity MAIN_SNES 0 + set_parameter -name USE_BSX -entity MAIN_SNES 0 + set_parameter -name USE_MSU -entity MAIN_SNES 0 +} elseif { [lindex $argv 0] == "pal" } { + puts "PAL" + set_parameter -name USE_CX4 -entity MAIN_SNES 1 + set_parameter -name USE_SDD1 -entity MAIN_SNES 0 + set_parameter -name USE_GSU -entity MAIN_SNES 1 + set_parameter -name USE_SA1 -entity MAIN_SNES 1 + set_parameter -name USE_DSPn -entity MAIN_SNES 1 + set_parameter -name USE_SPC7110 -entity MAIN_SNES 0 + set_parameter -name USE_BSX -entity MAIN_SNES 0 + set_parameter -name USE_MSU -entity MAIN_SNES 0 +} elseif { [lindex $argv 0] == "ntsc_spc" } { + puts "NTSC SPC" + set_parameter -name USE_CX4 -entity MAIN_SNES 0 + set_parameter -name USE_SDD1 -entity MAIN_SNES 1 + set_parameter -name USE_GSU -entity MAIN_SNES 0 + set_parameter -name USE_SA1 -entity MAIN_SNES 0 + set_parameter -name USE_DSPn -entity MAIN_SNES 0 + set_parameter -name USE_SPC7110 -entity MAIN_SNES 1 + set_parameter -name USE_BSX -entity MAIN_SNES 1 + set_parameter -name USE_MSU -entity MAIN_SNES 0 +} else { + puts "Unknown bitstream type [lindex $argv 0]" + project_close + exit +} + +execute_flow -compile + +project_close \ No newline at end of file diff --git a/src/fpga/ap_core.qsf b/src/fpga/ap_core.qsf index 909b932..5b28fc2 100644 --- a/src/fpga/ap_core.qsf +++ b/src/fpga/ap_core.qsf @@ -741,6 +741,11 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 +set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name SYSTEMVERILOG_FILE core/rtl/mister_top/scanline_filler.sv +set_global_assignment -name SYSTEMVERILOG_FILE core/core_top.sv set_global_assignment -name SYSTEMVERILOG_FILE core/rtl/mister_top/sync_fifo.sv set_global_assignment -name MIF_FILE core/rtl/chip/DSP/dsp11b23410_p.mif set_global_assignment -name MIF_FILE core/rtl/chip/DSP/dsp11b23410_d.mif @@ -772,11 +777,18 @@ set_global_assignment -name VHDL_FILE core/rtl/CEGen.vhd set_global_assignment -name VHDL_FILE core/rtl/bram.vhd set_global_assignment -name QIP_FILE core/rtl/chip/chip.qip set_global_assignment -name QIP_FILE apf/apf.qip -set_global_assignment -name VERILOG_FILE core/core_top.v set_global_assignment -name VERILOG_FILE core/core_bridge_cmd.v set_global_assignment -name SDC_FILE core/core_constraints.sdc set_global_assignment -name SIGNALTAP_FILE core/stp1.stp set_global_assignment -name QIP_FILE core/mf_pllbase.qip set_global_assignment -name SIP_FILE core/mf_pllbase.sip -set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_global_assignment -name QIP_FILE core/pll_reconfig.qip +set_global_assignment -name SIP_FILE core/pll_reconfig.sip +set_parameter -name USE_CX4 0 -entity MAIN_SNES +set_parameter -name USE_SDD1 1 -entity MAIN_SNES +set_parameter -name USE_GSU 0 -entity MAIN_SNES +set_parameter -name USE_SA1 0 -entity MAIN_SNES +set_parameter -name USE_DSPn 0 -entity MAIN_SNES +set_parameter -name USE_SPC7110 1 -entity MAIN_SNES +set_parameter -name USE_BSX 1 -entity MAIN_SNES +set_parameter -name USE_MSU 0 -entity MAIN_SNES \ No newline at end of file diff --git a/src/fpga/apf/build_id.mif b/src/fpga/apf/build_id.mif index 866b9cf..c377630 100644 --- a/src/fpga/apf/build_id.mif +++ b/src/fpga/apf/build_id.mif @@ -9,8 +9,8 @@ DATA_RADIX = HEX; CONTENT BEGIN - 0E0 : 20220928; - 0E1 : 00121250; - 0E2 : 7a851a82; + 0E0 : 20221101; + 0E1 : 00085822; + 0E2 : d8065c9a; END; diff --git a/src/fpga/core/core_bridge_cmd.v b/src/fpga/core/core_bridge_cmd.v index 75c4395..c315c15 100644 --- a/src/fpga/core/core_bridge_cmd.v +++ b/src/fpga/core/core_bridge_cmd.v @@ -45,6 +45,10 @@ input wire dataslot_requestwrite_ok, output reg dataslot_allcomplete, +output reg [31:0] rtc_seconds, +output reg [31:0] rtc_date, +output reg [31:0] rtc_time, + input wire savestate_supported, input wire [31:0] savestate_addr, input wire [31:0] savestate_size, @@ -325,6 +329,13 @@ always @(posedge clk) begin dataslot_allcomplete <= 1; hstate <= ST_DONE_OK; end + 16'h0090: begin + // RTC + rtc_seconds <= host_20; + rtc_date <= host_24; + rtc_time <= host_28; + hstate <= ST_DONE_OK; + end 16'h00A0: begin // Savestate: Start/Query host_40 <= savestate_supported; diff --git a/src/fpga/core/core_constraints.sdc b/src/fpga/core/core_constraints.sdc index b65ffe9..86bd2d8 100644 --- a/src/fpga/core/core_constraints.sdc +++ b/src/fpga/core/core_constraints.sdc @@ -8,10 +8,10 @@ set_clock_groups -asynchronous \ -group { bridge_spiclk } \ -group { clk_74a } \ -group { clk_74b } \ - -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk } \ - -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk } \ - -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk } \ - -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk } + -group { ic|mp1|mf_pllbase_inst|altera_pll_i|*[0].*|divclk } \ + -group { ic|mp1|mf_pllbase_inst|altera_pll_i|*[1].*|divclk } \ + -group { ic|mp1|mf_pllbase_inst|altera_pll_i|*[2].*|divclk } \ + -group { ic|mp1|mf_pllbase_inst|altera_pll_i|*[3].*|divclk } create_generated_clock -name GSU_CACHE_CLK -source [get_pins -compatibility_mode {*|mp1|mf_pllbase_inst|altera_pll_i|*[1].*|divclk}] \ -invert [get_pins {ic|snes|main|GSUMap|GSU|CACHE|altsyncram_component|auto_generated|*|clk0}] @@ -20,14 +20,6 @@ create_generated_clock -name CX4_MEM_CLK -source [get_pins -compatibility_mode { -invert [get_pins {ic|snes|main|CX4Map|CX4|DATA_RAM|altsyncram_component|auto_generated|*|clk0 \ ic|snes|main|CX4Map|CX4|DATA_ROM|spram_sz|altsyncram_component|auto_generated|altsyncram1|*|clk0 }] -# Audio clocks (don't work) -#create_generated_clock -name AUDIO_CLK -source [get_ports clk_74a] \ -# -divide_by 6.04248046875 [get_pins {ic|sound_i2s|audio_mclk*}] - -#create_generated_clock -name AUDIO_CLK -source [get_ports clk_74a] \ -# -divide_by 24.169921875 [get_pins {ic|sound_i2s|aud_mclk_divider[1]*}] - -# TODO: There are additional expansion clocks here derive_clock_uncertainty set_clock_groups -asynchronous -group [get_clocks { GSU_CACHE_CLK CX4_MEM_CLK }] @@ -53,4 +45,7 @@ set_max_delay 23 -from [get_registers { ic|snes|sdram|* }] \ ic|snes|wram|* \ ic|snes|vram*|* }] +set_max_delay 23 -from [get_registers { ic|snes|main|SNES|DSP|* }] \ + -to [get_registers { ic|sound_i2s|* }] + set_false_path -to [get_registers { ic|snes|sdram|ds ic|snes|sdram|data[*]}] diff --git a/src/fpga/core/core_top.v b/src/fpga/core/core_top.sv similarity index 81% rename from src/fpga/core/core_top.v rename to src/fpga/core/core_top.sv index 458cbf4..5d0217a 100644 --- a/src/fpga/core/core_top.v +++ b/src/fpga/core/core_top.sv @@ -335,6 +335,21 @@ module core_top ( if (bridge_wr) begin casex (bridge_addr) + 32'h00000000: begin + ioctl_download <= bridge_wr_data[0]; + end + 32'h00000004: begin + rom_size <= bridge_wr_data[3:0]; + end + 32'h00000008: begin + rom_type <= bridge_wr_data[7:0]; + end + 32'h0000000C: begin + ram_size <= bridge_wr_data[3:0]; + end + 32'h00000010: begin + PAL <= bridge_wr_data[0]; + end 32'h00000050: begin reset_delay <= 32'h100000; end @@ -399,6 +414,9 @@ module core_top ( wire osnotify_inmenu; + wire [31:0] rtc_date; + wire [31:0] rtc_time; + // bridge target commands // synchronous to clk_74a @@ -438,6 +456,9 @@ module core_top ( .dataslot_allcomplete(dataslot_allcomplete), + .rtc_date(rtc_date), + .rtc_time(rtc_time), + .savestate_supported (savestate_supported), .savestate_addr (savestate_addr), .savestate_size (savestate_size), @@ -460,8 +481,7 @@ module core_top ( .datatable_addr(datatable_addr), .datatable_wren(datatable_wren), .datatable_data(datatable_data), - .datatable_q (datatable_q), - + .datatable_q (datatable_q) ); reg ioctl_download = 0; @@ -475,13 +495,18 @@ module core_top ( always @(posedge clk_74a) begin dataslot_allcomplete_prev <= dataslot_allcomplete; - if (dataslot_requestwrite) ioctl_download <= 1; - else if (dataslot_allcomplete) ioctl_download <= 0; + // if (dataslot_requestwrite) ioctl_download <= 1; + // else if (dataslot_allcomplete) ioctl_download <= 0; if (dataslot_requestread || dataslot_requestwrite) save_download <= 1; else if (dataslot_allcomplete && ~dataslot_allcomplete_prev) save_download <= 0; end + reg [7:0] rom_type; + reg [3:0] rom_size; + reg [3:0] ram_size; + reg PAL; + wire save_download_s; synch_3 save_s ( @@ -561,33 +586,18 @@ module core_top ( .read_data(sd_buff_din) ); - reg [ 2:0] datatable_div = 0; - reg [31:0] rom_file_size = 0; - always @(posedge clk_74a or negedge pll_core_locked) begin if (~pll_core_locked) begin datatable_addr <= 0; datatable_data <= 0; datatable_wren <= 0; end else begin - if (datatable_div > 4) begin - // Write sram size half of the time - datatable_wren <= 1; - // sram_size is the size of the config value in the ROM. Convert to actual size - datatable_data <= sram_size ? 32'd1024 << sram_size : 32'h0; - // Data slot index 1, not id 1 - datatable_addr <= 1 * 2 + 1; - end else begin - datatable_wren <= 0; - // Read ROM size rest of the time - datatable_addr <= 1; - - if (datatable_div == 4) begin - rom_file_size <= datatable_q; - end - end - - datatable_div <= datatable_div + 1; + // Write sram size half of the time + datatable_wren <= 1; + // sram_size is the size of the config value in the ROM. Convert to actual size + datatable_data <= sram_size ? 32'd1024 << sram_size : 32'h0; + // Data slot index 1, not id 1 + datatable_addr <= 1 * 2 + 1; end end @@ -642,8 +652,6 @@ module core_top ( clk_sys_21_48 ); - wire PAL; - // Settings reg multitap_enabled; reg lightgun_enabled; @@ -653,11 +661,47 @@ module core_top ( reg [31:0] reset_delay = 0; + reg new_rtc = 0; + reg [31:0] prev_time = 0; + + always @(posedge clk_74a) begin + if (rtc_time != prev_time) begin + prev_time <= rtc_time; + new_rtc <= ~new_rtc; + end + end + + wire [64:0] rtc = { + new_rtc, + 8'b0, // Empty + 8'b1, // Week day (not supported) + rtc_date[23:16], // Year (lower byte) + rtc_date[15:8], // Month + rtc_date[7:0], // Day + rtc_time[23:16], // Hour + rtc_time[15:8], // Minute + rtc_time[7:0] // Second + }; + + // initial begin + // $info("Instantiated PSRAM with the following settings:"); + // $info("Value", TEST_PARAM); + // if (TEST_PARAM == 1'b1) begin + // $error("Test param set"); + // end else begin + // $error("Test param unset"); + // end + // end + MAIN_SNES snes ( .clk_mem_85_9 (clk_mem_85_9), .clk_sys_21_48(clk_sys_21_48), - .core_reset(~pll_core_locked || reset_delay > 0), + .core_reset(~pll_core_locked || pal_transitioning || reset_delay > 0), + + .rtc(rtc), + + .rtc(rtc), // Settings .multitap_enabled(multitap_enabled), @@ -722,12 +766,16 @@ module core_top ( .p4_dpad_right(cont4_key_s[3]), // ROM loading - .rom_file_size(rom_file_size), .ioctl_download(ioctl_download), .ioctl_wr(ioctl_wr), .ioctl_addr(ioctl_addr), .ioctl_dout(ioctl_dout), + .rom_type(rom_type), + .rom_size(rom_size), + .ram_size(ram_size), + .PAL(PAL), + // Save input/output .save_download(save_download_s), .sd_rd(sd_rd), @@ -785,8 +833,6 @@ module core_top ( .video_g(video_rgb_snes[15:8]), .video_b(video_rgb_snes[7:0]), - .PAL(PAL), - // Audio .audio_l(audio_l), .audio_r(audio_r) @@ -800,46 +846,61 @@ module core_top ( wire video_vs_snes; wire [23:0] video_rgb_snes; - reg video_de_reg; - reg video_hs_reg; - reg video_vs_reg; - reg [23:0] video_rgb_reg; - assign video_rgb_clock = clk_video_5_37; assign video_rgb_clock_90 = clk_video_5_37_90deg; - assign video_de = video_de_reg; - assign video_hs = video_hs_reg; - assign video_vs = video_vs_reg; - assign video_rgb = video_rgb_reg; + assign video_rgb = rgb; + assign video_de = de; + + reg de; + reg [23:0] rgb; + wire [7:0] snap_index; + wire [23:0] rgb_out; + wire de_out; + + scanline_filler #( + .SNAP_COUNT (2), + .SNAP_POINTS('{240, 224}), + .HSYNC_DELAY(1) + ) scanline_filler ( + .clk(clk_video_5_37), + + .hsync_in(video_hs_snes), + .vsync_in(video_vs_snes), + + .vblank_in(v_blank), + .hblank_in(h_blank), + .rgb_in(video_rgb_snes), - reg hs_prev; - reg [2:0] hs_delay; - reg vs_prev; - reg de_prev; + .hsync(video_hs), + .vsync(video_vs), - wire de = ~(h_blank || v_blank); - wire [23:0] video_slot_rgb = {9'b0, PAL, use_4_3_video, 10'b0, 3'b0}; + .de (de_out), + .rgb(rgb_out), + + .snap_index(snap_index) + ); + + reg prev_de; + reg prev_vs; + reg [7:0] latched_snap_index; always @(posedge clk_video_5_37) begin - video_hs_reg <= 0; - video_de_reg <= 0; - video_rgb_reg <= 24'h0; + prev_de <= de_out; + prev_vs <= video_vs; - if (de) begin - video_de_reg <= 1; + de <= 0; - video_rgb_reg <= video_rgb_snes; - end else if (de_prev && ~de) begin - // Last clock was last pixel. Set end of line bits - video_rgb_reg <= video_slot_rgb; + if (video_vs && ~prev_vs) begin + latched_snap_index <= snap_index; end - // Set VSync to be high for a single cycle on the rising edge of the VSync coming out of the core - video_hs_reg <= ~hs_prev && video_hs_snes; - video_vs_reg <= ~vs_prev && video_vs_snes; - hs_prev <= video_hs_snes; - vs_prev <= video_vs_snes; - de_prev <= de; + if (~de_out && prev_de) begin + // Write video slot + rgb <= {9'b0, ~latched_snap_index[0], use_4_3_video, 10'b0, 3'b0}; + end else if (de_out) begin + de <= 1; + rgb <= rgb_out; + end end sound_i2s #( @@ -866,16 +927,104 @@ module core_top ( wire pll_core_locked; + wire [63:0] reconfig_to_pll; + wire [63:0] reconfig_from_pll; + + reg pll_reset = 0; + mf_pllbase mp1 ( .refclk(clk_74a), - .rst (0), + .rst (pll_reset), .outclk_0(clk_mem_85_9), .outclk_1(clk_sys_21_48), .outclk_2(clk_video_5_37), .outclk_3(clk_video_5_37_90deg), - .locked(pll_core_locked) + .locked(pll_core_locked), + + .reconfig_to_pll (reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll) ); + wire cfg_waitrequest; + reg cfg_write; + reg [ 5:0] cfg_address; + reg [31:0] cfg_data; + + pll_reconfig pll_reconfig ( + .mgmt_clk(clk_74a), + .mgmt_reset(0), + .mgmt_waitrequest(cfg_waitrequest), + .mgmt_read(0), + // .mgmt_readdata(), + .mgmt_write(cfg_write), + .mgmt_address(cfg_address), + .mgmt_writedata(cfg_data), + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll) + ); + + localparam PLL_MODE = 1; + localparam PLL_MIF_ADDR = PLL_MODE + 2; + localparam PLL_START = PLL_MIF_ADDR + 2; + localparam PLL_RECONFIG = PLL_START + 2; + localparam PLL_RESET_START = PLL_RECONFIG + 1; + localparam PLL_RESET_END = PLL_RESET_START + 20; + + reg [7:0] pal_state = 0; + + wire pal_transitioning = pal_state > 0 || cfg_waitrequest || cfg_write || ~pll_core_locked /* synthesis keep */; + + always @(posedge clk_74a) begin + reg pald = 0, pald2 = 0; + + pald <= PAL; + pald2 <= pald; + + cfg_write <= 0; + if (pald2 != pald) begin + // Begin fractional PLL reconfig + pal_state <= 1; + end + + if (pal_state > 0) pal_state <= pal_state + 1; + + case (pal_state) + PLL_MODE: begin + // Set mode to waitrequest + cfg_address <= 0; + cfg_data <= 0; + cfg_write <= 1; + end + PLL_MIF_ADDR: begin + cfg_address <= 6'b11111; + cfg_data <= 0; + cfg_write <= 1; + end + PLL_START: begin + // Start PLL reconfig + cfg_address <= 2; + cfg_data <= 0; + cfg_write <= 1; + end + PLL_RECONFIG: begin + pal_state <= PLL_RECONFIG; + + // Wait for reconfig end + if (~cfg_waitrequest) begin + pal_state <= PLL_RESET_START; + end + end + PLL_RESET_START: begin + pll_reset <= 1; + end + PLL_RESET_END: begin + pal_state <= 0; + + pll_reset <= 0; + end + endcase + end + endmodule diff --git a/src/fpga/core/mf_pllbase.bsf b/src/fpga/core/mf_pllbase.bsf index b9ebf0b..39ebf9c 100644 --- a/src/fpga/core/mf_pllbase.bsf +++ b/src/fpga/core/mf_pllbase.bsf @@ -21,95 +21,117 @@ https://fpgasoftware.intel.com/eula. */ (header "symbol" (version "1.1")) (symbol - (rect 0 0 160 264) - (text "mf_pllbase" (rect 48 -1 91 11)(font "Arial" (font_size 10))) - (text "inst" (rect 8 248 20 260)(font "Arial" )) + (rect 0 0 400 304) + (text "mf_pllbase" (rect 168 -1 211 11)(font "Arial" (font_size 10))) + (text "inst" (rect 8 288 20 300)(font "Arial" )) (port (pt 0 72) (input) (text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8))) (text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 48 72)(line_width 1)) + (line (pt 0 72)(pt 112 72)(line_width 1)) ) (port (pt 0 112) (input) (text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8))) (text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8))) - (line (pt 0 112)(pt 48 112)(line_width 1)) + (line (pt 0 112)(pt 112 112)(line_width 1)) ) (port - (pt 160 72) + (pt 0 152) + (input) + (text "reconfig_to_pll[63..0]" (rect 0 0 82 12)(font "Arial" (font_size 8))) + (text "reconfig_to_pll[63..0]" (rect 4 141 136 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 112 152)(line_width 3)) + ) + (port + (pt 400 72) (output) (text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8))) - (text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8))) - (line (pt 160 72)(pt 112 72)(line_width 1)) + (text "outclk_0" (rect 357 61 405 72)(font "Arial" (font_size 8))) + (line (pt 400 72)(pt 272 72)(line_width 1)) ) (port - (pt 160 112) + (pt 400 112) (output) (text "outclk_1" (rect 0 0 31 12)(font "Arial" (font_size 8))) - (text "outclk_1" (rect 119 101 167 112)(font "Arial" (font_size 8))) - (line (pt 160 112)(pt 112 112)(line_width 1)) + (text "outclk_1" (rect 359 101 407 112)(font "Arial" (font_size 8))) + (line (pt 400 112)(pt 272 112)(line_width 1)) ) (port - (pt 160 152) + (pt 400 152) (output) (text "outclk_2" (rect 0 0 33 12)(font "Arial" (font_size 8))) - (text "outclk_2" (rect 117 141 165 152)(font "Arial" (font_size 8))) - (line (pt 160 152)(pt 112 152)(line_width 1)) + (text "outclk_2" (rect 357 141 405 152)(font "Arial" (font_size 8))) + (line (pt 400 152)(pt 272 152)(line_width 1)) ) (port - (pt 160 192) + (pt 400 192) (output) (text "outclk_3" (rect 0 0 33 12)(font "Arial" (font_size 8))) - (text "outclk_3" (rect 117 181 165 192)(font "Arial" (font_size 8))) - (line (pt 160 192)(pt 112 192)(line_width 1)) + (text "outclk_3" (rect 357 181 405 192)(font "Arial" (font_size 8))) + (line (pt 400 192)(pt 272 192)(line_width 1)) ) (port - (pt 160 232) + (pt 400 232) (output) (text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8))) - (text "locked" (rect 127 221 163 232)(font "Arial" (font_size 8))) - (line (pt 160 232)(pt 112 232)(line_width 1)) + (text "locked" (rect 367 221 403 232)(font "Arial" (font_size 8))) + (line (pt 400 232)(pt 272 232)(line_width 1)) + ) + (port + (pt 400 272) + (output) + (text "reconfig_from_pll[63..0]" (rect 0 0 95 12)(font "Arial" (font_size 8))) + (text "reconfig_from_pll[63..0]" (rect 280 261 424 272)(font "Arial" (font_size 8))) + (line (pt 400 272)(pt 272 272)(line_width 3)) ) (drawing - (text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9))) - (text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0))) - (text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9))) - (text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0))) - (text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9))) - (text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0))) - (text "outclk1" (rect 113 83 268 179)(font "Arial" (color 128 0 0)(font_size 9))) - (text "clk" (rect 97 107 212 224)(font "Arial" (color 0 0 0))) - (text "outclk2" (rect 113 123 268 259)(font "Arial" (color 128 0 0)(font_size 9))) - (text "clk" (rect 97 147 212 304)(font "Arial" (color 0 0 0))) - (text "outclk3" (rect 113 163 268 339)(font "Arial" (color 128 0 0)(font_size 9))) - (text "clk" (rect 97 187 212 384)(font "Arial" (color 0 0 0))) - (text "locked" (rect 113 203 262 419)(font "Arial" (color 128 0 0)(font_size 9))) - (text "export" (rect 82 227 200 464)(font "Arial" (color 0 0 0))) - (text " altera_pll " (rect 118 248 308 506)(font "Arial" )) - (line (pt 48 32)(pt 112 32)(line_width 1)) - (line (pt 112 32)(pt 112 248)(line_width 1)) - (line (pt 48 248)(pt 112 248)(line_width 1)) - (line (pt 48 32)(pt 48 248)(line_width 1)) - (line (pt 49 52)(pt 49 76)(line_width 1)) - (line (pt 50 52)(pt 50 76)(line_width 1)) - (line (pt 49 92)(pt 49 116)(line_width 1)) - (line (pt 50 92)(pt 50 116)(line_width 1)) - (line (pt 111 52)(pt 111 76)(line_width 1)) - (line (pt 110 52)(pt 110 76)(line_width 1)) - (line (pt 111 92)(pt 111 116)(line_width 1)) - (line (pt 110 92)(pt 110 116)(line_width 1)) - (line (pt 111 132)(pt 111 156)(line_width 1)) - (line (pt 110 132)(pt 110 156)(line_width 1)) - (line (pt 111 172)(pt 111 196)(line_width 1)) - (line (pt 110 172)(pt 110 196)(line_width 1)) - (line (pt 111 212)(pt 111 236)(line_width 1)) - (line (pt 110 212)(pt 110 236)(line_width 1)) - (line (pt 0 0)(pt 160 0)(line_width 1)) - (line (pt 160 0)(pt 160 264)(line_width 1)) - (line (pt 0 264)(pt 160 264)(line_width 1)) - (line (pt 0 0)(pt 0 264)(line_width 1)) + (text "refclk" (rect 80 43 196 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 117 67 252 144)(font "Arial" (color 0 0 0))) + (text "reset" (rect 83 83 196 179)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reset" (rect 117 107 264 224)(font "Arial" (color 0 0 0))) + (text "outclk0" (rect 273 43 588 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 257 67 532 144)(font "Arial" (color 0 0 0))) + (text "outclk1" (rect 273 83 588 179)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 257 107 532 224)(font "Arial" (color 0 0 0))) + (text "outclk2" (rect 273 123 588 259)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 257 147 532 304)(font "Arial" (color 0 0 0))) + (text "outclk3" (rect 273 163 588 339)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 257 187 532 384)(font "Arial" (color 0 0 0))) + (text "locked" (rect 273 203 582 419)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 242 227 520 464)(font "Arial" (color 0 0 0))) + (text "reconfig_to_pll" (rect 26 123 142 259)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reconfig_to_pll" (rect 117 147 324 304)(font "Arial" (color 0 0 0))) + (text "reconfig_from_pll" (rect 273 243 648 499)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reconfig_from_pll" (rect 192 267 486 544)(font "Arial" (color 0 0 0))) + (text " altera_pll " (rect 358 288 788 586)(font "Arial" )) + (line (pt 112 32)(pt 272 32)(line_width 1)) + (line (pt 272 32)(pt 272 288)(line_width 1)) + (line (pt 112 288)(pt 272 288)(line_width 1)) + (line (pt 112 32)(pt 112 288)(line_width 1)) + (line (pt 113 52)(pt 113 76)(line_width 1)) + (line (pt 114 52)(pt 114 76)(line_width 1)) + (line (pt 113 92)(pt 113 116)(line_width 1)) + (line (pt 114 92)(pt 114 116)(line_width 1)) + (line (pt 271 52)(pt 271 76)(line_width 1)) + (line (pt 270 52)(pt 270 76)(line_width 1)) + (line (pt 271 92)(pt 271 116)(line_width 1)) + (line (pt 270 92)(pt 270 116)(line_width 1)) + (line (pt 271 132)(pt 271 156)(line_width 1)) + (line (pt 270 132)(pt 270 156)(line_width 1)) + (line (pt 271 172)(pt 271 196)(line_width 1)) + (line (pt 270 172)(pt 270 196)(line_width 1)) + (line (pt 271 212)(pt 271 236)(line_width 1)) + (line (pt 270 212)(pt 270 236)(line_width 1)) + (line (pt 113 132)(pt 113 156)(line_width 1)) + (line (pt 114 132)(pt 114 156)(line_width 1)) + (line (pt 271 252)(pt 271 276)(line_width 1)) + (line (pt 270 252)(pt 270 276)(line_width 1)) + (line (pt 0 0)(pt 400 0)(line_width 1)) + (line (pt 400 0)(pt 400 304)(line_width 1)) + (line (pt 0 304)(pt 400 304)(line_width 1)) + (line (pt 0 0)(pt 0 304)(line_width 1)) ) ) diff --git a/src/fpga/core/mf_pllbase.ppf b/src/fpga/core/mf_pllbase.ppf index c9218c2..c53eb63 100644 --- a/src/fpga/core/mf_pllbase.ppf +++ b/src/fpga/core/mf_pllbase.ppf @@ -12,5 +12,7 @@ + + diff --git a/src/fpga/core/mf_pllbase.qip b/src/fpga/core/mf_pllbase.qip index cd98262..496795d 100644 --- a/src/fpga/core/mf_pllbase.qip +++ b/src/fpga/core/mf_pllbase.qip @@ -22,8 +22,7 @@ set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_C set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::VW5rbm93bg==::ZGV2aWNl" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RldmljZV9zcGVlZF9ncmFkZQ==::Mg==::RGV2aWNlIFNwZWVkIEdyYWRl" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NzQuMjU=::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ==" @@ -32,7 +31,9 @@ set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_C set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX2ZyYWN0aW9uYWxfY291dA==::MzI=::cGxsX2ZyYWN0aW9uYWxfY291dA==" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::cGxsX2RzbV9vdXRfc2Vs" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" @@ -42,10 +43,10 @@ set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_C set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::ODUuOTA5MDcy::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::ODUuOTA5MDg=::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::NDI1OTM2MjE2::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::NDI1OTQyNzUz::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Nw==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" @@ -54,10 +55,10 @@ set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_C set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MjEuNDc3MjY4::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MjEuNDc3Mjc=::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::NDI1OTM2MjE2::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::NDI1OTQyNzUz::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::Mjg=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::Mjc2Ljc0MDY0MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM=" @@ -66,10 +67,10 @@ set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_C set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAuNzM4NjMz::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAuNzM4NjM1::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::NDI1OTM2MjE2::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::NDI1OTQyNzUz::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::NTY=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM=" @@ -78,10 +79,10 @@ set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_C set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ==" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAuNzM4NjMz::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAuNzM4NjM1::RGVzaXJlZCBGcmVxdWVuY3k=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::NDI1OTM2MjE2::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::NDI1OTQyNzUz::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::NTY=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM=" @@ -257,16 +258,16 @@ set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_C set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::ODUuOTA5MDY0IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::ODUuOTA5MDgwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MjEuNDc3MjY2IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MjEuNDc3MjcwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MTAuNzM4NjMzIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MTAuNzM4NjM1IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MTAuNzM4NjMzIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MTAuNzM4NjM1IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MjMyODAgcHM=::cGhhc2Vfc2hpZnQz" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" @@ -311,16 +312,160 @@ set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_C set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw==" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T2Zm::UExMIEF1dG8gUmVzZXQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::dHJ1ZQ==::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::Q3ljbG9uZSBW::UExMIFRZUEU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::UmVjb25maWd1cmFibGU=::UExMIFNVQlRZUEU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "bV9jbnRfaGlfZGl2::NA==::bV9jbnRfaGlfZGl2" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "bV9jbnRfbG9fZGl2::NA==::bV9jbnRfbG9fZGl2" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "bl9jbnRfaGlfZGl2::MjU2::bl9jbnRfaGlfZGl2" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "bl9jbnRfbG9fZGl2::MjU2::bl9jbnRfbG9fZGl2" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "bV9jbnRfYnlwYXNzX2Vu::ZmFsc2U=::bV9jbnRfYnlwYXNzX2Vu" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "bl9jbnRfYnlwYXNzX2Vu::dHJ1ZQ==::bl9jbnRfYnlwYXNzX2Vu" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu::ZmFsc2U=::bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "bl9jbnRfb2RkX2Rpdl9kdXR5X2Vu::ZmFsc2U=::bl9jbnRfb2RkX2Rpdl9kdXR5X2Vu" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MA==::NA==::Y19jbnRfaGlfZGl2MA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MA==::Mw==::Y19jbnRfbG9fZGl2MA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDA=::MQ==::Y19jbnRfcHJzdDA=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qw::MA==::Y19jbnRfcGhfbXV4X3Byc3Qw" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMA==::ZmFsc2U=::Y19jbnRfYnlwYXNzX2VuMA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA==::dHJ1ZQ==::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MQ==::MTQ=::Y19jbnRfaGlfZGl2MQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MQ==::MTQ=::Y19jbnRfbG9fZGl2MQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE=::MQ==::Y19jbnRfcHJzdDE=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qx::MA==::Y19jbnRfcGhfbXV4X3Byc3Qx" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMQ==::ZmFsc2U=::Y19jbnRfYnlwYXNzX2VuMQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Mg==::Mjg=::Y19jbnRfaGlfZGl2Mg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Mg==::Mjg=::Y19jbnRfbG9fZGl2Mg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDI=::MQ==::Y19jbnRfcHJzdDI=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qy::MA==::Y19jbnRfcGhfbXV4X3Byc3Qy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMg==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMg==::ZmFsc2U=::Y19jbnRfYnlwYXNzX2VuMg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMg==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Mw==::Mjg=::Y19jbnRfaGlfZGl2Mw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Mw==::Mjg=::Y19jbnRfbG9fZGl2Mw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDM=::MTU=::Y19jbnRfcHJzdDM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qz::MA==::Y19jbnRfcGhfbXV4X3Byc3Qz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMw==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMw==::ZmFsc2U=::Y19jbnRfYnlwYXNzX2VuMw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMw==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2NA==::MQ==::Y19jbnRfaGlfZGl2NA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2NA==::MQ==::Y19jbnRfbG9fZGl2NA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDQ=::MQ==::Y19jbnRfcHJzdDQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q0::MA==::Y19jbnRfcGhfbXV4X3Byc3Q0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNA==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNA==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2NQ==::MQ==::Y19jbnRfaGlfZGl2NQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2NQ==::MQ==::Y19jbnRfbG9fZGl2NQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDU=::MQ==::Y19jbnRfcHJzdDU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q1::MA==::Y19jbnRfcGhfbXV4X3Byc3Q1" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Ng==::MQ==::Y19jbnRfaGlfZGl2Ng==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Ng==::MQ==::Y19jbnRfbG9fZGl2Ng==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDY=::MQ==::Y19jbnRfcHJzdDY=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q2::MA==::Y19jbnRfcGhfbXV4X3Byc3Q2" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNg==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNg==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNg==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Nw==::MQ==::Y19jbnRfaGlfZGl2Nw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Nw==::MQ==::Y19jbnRfbG9fZGl2Nw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDc=::MQ==::Y19jbnRfcHJzdDc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q3::MA==::Y19jbnRfcGhfbXV4X3Byc3Q3" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNw==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNw==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNw==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2OA==::MQ==::Y19jbnRfaGlfZGl2OA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2OA==::MQ==::Y19jbnRfbG9fZGl2OA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDg=::MQ==::Y19jbnRfcHJzdDg=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q4::MA==::Y19jbnRfcGhfbXV4X3Byc3Q4" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjOA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjOA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuOA==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuOA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOA==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2OQ==::MQ==::Y19jbnRfaGlfZGl2OQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2OQ==::MQ==::Y19jbnRfbG9fZGl2OQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDk=::MQ==::Y19jbnRfcHJzdDk=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q5::MA==::Y19jbnRfcGhfbXV4X3Byc3Q5" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjOQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjOQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuOQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuOQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTA=::MQ==::Y19jbnRfaGlfZGl2MTA=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTA=::MQ==::Y19jbnRfbG9fZGl2MTA=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEw::MQ==::Y19jbnRfcHJzdDEw" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMA==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTA=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTA=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTA=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTA=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTA=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTA=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTE=::MQ==::Y19jbnRfaGlfZGl2MTE=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTE=::MQ==::Y19jbnRfbG9fZGl2MTE=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEx::MQ==::Y19jbnRfcHJzdDEx" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMQ==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTE=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTE=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTE=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTE=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTE=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTE=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTI=::MQ==::Y19jbnRfaGlfZGl2MTI=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTI=::MQ==::Y19jbnRfbG9fZGl2MTI=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEy::MQ==::Y19jbnRfcHJzdDEy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMg==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTI=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTI=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTI=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTI=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTI=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTI=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTM=::MQ==::Y19jbnRfaGlfZGl2MTM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTM=::MQ==::Y19jbnRfbG9fZGl2MTM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEz::MQ==::Y19jbnRfcHJzdDEz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMw==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTM=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTM=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTM=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTQ=::MQ==::Y19jbnRfaGlfZGl2MTQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTQ=::MQ==::Y19jbnRfbG9fZGl2MTQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE0::MQ==::Y19jbnRfcHJzdDE0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNA==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTQ=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTQ=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTQ=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTU=::MQ==::Y19jbnRfaGlfZGl2MTU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTU=::MQ==::Y19jbnRfbG9fZGl2MTU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE1::MQ==::Y19jbnRfcHJzdDE1" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNQ==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTU=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTU=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTU=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTY=::MQ==::Y19jbnRfaGlfZGl2MTY=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTY=::MQ==::Y19jbnRfbG9fZGl2MTY=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE2::MQ==::Y19jbnRfcHJzdDE2" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNg==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTY=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTY=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTY=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTY=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTY=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTY=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTc=::MQ==::Y19jbnRfaGlfZGl2MTc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTc=::MQ==::Y19jbnRfbG9fZGl2MTc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE3::MQ==::Y19jbnRfcHJzdDE3" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNw==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTc=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTc=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTc=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX3Zjb19kaXY=::MQ==::cGxsX3Zjb19kaXY=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX2NwX2N1cnJlbnQ=::MzA=::cGxsX2NwX2N1cnJlbnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX2J3Y3RybA==::MjAwMA==::cGxsX2J3Y3RybA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5::NjAxLjM2MzU2IE1Ieg==::cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24=::NDI1OTQyNzUz::cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "bWltaWNfZmJjbGtfdHlwZQ==::Z2Nsaw==::bWltaWNfZmJjbGtfdHlwZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX2ZiY2xrX211eF8x::Z2xi::cGxsX2ZiY2xrX211eF8x" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX2ZiY2xrX211eF8y::ZmJfMQ==::cGxsX2ZiY2xrX211eF8y" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX21fY250X2luX3NyYw==::cGhfbXV4X2Nsaw==::cGxsX21fY250X2luX3NyYw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX3NsZl9yc3Q=::dHJ1ZQ==::cGxsX3NsZl9yc3Q=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSw0LDMsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwxNCwxNCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwyOCwyOCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwyOCwyOCwxNSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMSwzMCwyMDAwLDYwMS4zNjM0NDcgTUh6LDQyNTkzNjIxNixnY2xrLGdsYixmYl8xLHBoX211eF9jbGssZmFsc2U=::UGFyYW1ldGVyIFZhbHVlcw==" -set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSw0LDMsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwxNCwxNCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwyOCwyOCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwyOCwyOCwxNSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMSwzMCwyMDAwLDYwMS4zNjM1NiBNSHosNDI1OTQyNzUzLGdjbGssZ2xiLGZiXzEscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::dHJ1ZQ==::R2VuZXJhdGUgTUlGIGZpbGU=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz" @@ -332,6 +477,7 @@ set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_C set_global_assignment -library "mf_pllbase" -name VERILOG_FILE [file join $::quartus(qip_path) "mf_pllbase.v"] set_global_assignment -library "mf_pllbase" -name VERILOG_FILE [file join $::quartus(qip_path) "mf_pllbase/mf_pllbase_0002.v"] set_global_assignment -library "mf_pllbase" -name QIP_FILE [file join $::quartus(qip_path) "mf_pllbase/mf_pllbase_0002.qip"] +set_global_assignment -library "mf_pllbase" -name SOURCE_FILE [file join $::quartus(qip_path) "mf_pllbase/mf_pllbase.mif"] set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_TOOL_NAME "altera_pll" set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_TOOL_VERSION "21.1" diff --git a/src/fpga/core/mf_pllbase.v b/src/fpga/core/mf_pllbase.v index 66b0bab..7b4e0ec 100644 --- a/src/fpga/core/mf_pllbase.v +++ b/src/fpga/core/mf_pllbase.v @@ -6,23 +6,27 @@ `timescale 1 ps / 1 ps module mf_pllbase ( - input wire refclk, // refclk.clk - input wire rst, // reset.reset - output wire outclk_0, // outclk0.clk - output wire outclk_1, // outclk1.clk - output wire outclk_2, // outclk2.clk - output wire outclk_3, // outclk3.clk - output wire locked // locked.export + input wire refclk, // refclk.clk + input wire rst, // reset.reset + output wire outclk_0, // outclk0.clk + output wire outclk_1, // outclk1.clk + output wire outclk_2, // outclk2.clk + output wire outclk_3, // outclk3.clk + output wire locked, // locked.export + input wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll + output wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll ); mf_pllbase_0002 mf_pllbase_inst ( - .refclk (refclk), // refclk.clk - .rst (rst), // reset.reset - .outclk_0 (outclk_0), // outclk0.clk - .outclk_1 (outclk_1), // outclk1.clk - .outclk_2 (outclk_2), // outclk2.clk - .outclk_3 (outclk_3), // outclk3.clk - .locked (locked) // locked.export + .refclk (refclk), // refclk.clk + .rst (rst), // reset.reset + .outclk_0 (outclk_0), // outclk0.clk + .outclk_1 (outclk_1), // outclk1.clk + .outclk_2 (outclk_2), // outclk2.clk + .outclk_3 (outclk_3), // outclk3.clk + .locked (locked), // locked.export + .reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll + .reconfig_from_pll (reconfig_from_pll) // reconfig_from_pll.reconfig_from_pll ); endmodule @@ -56,7 +60,7 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: @@ -72,7 +76,7 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: @@ -81,7 +85,7 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: @@ -90,7 +94,7 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: @@ -99,7 +103,7 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: @@ -233,13 +237,13 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: diff --git a/src/fpga/core/mf_pllbase/mf_pllbase.mif b/src/fpga/core/mf_pllbase/mf_pllbase.mif new file mode 100644 index 0000000..e46b8e6 --- /dev/null +++ b/src/fpga/core/mf_pllbase/mf_pllbase.mif @@ -0,0 +1,519 @@ +DEPTH = 512; +WIDTH = 32; +ADDRESS_RADIX = UNS; +DATA_RADIX = BIN; +CONTENT +BEGIN +0 : 00000000000000000000000000111110; -- START OF MIF +1 : 00000000000000000000000000000100; -- M COUNTER +2 : 00000000000000000000010000000100; +3 : 00000000000000000000000000000011; -- N COUNTER +4 : 00000000000000010000000000000000; +5 : 00000000000000000000000000000101; -- C0 COUNTER +6 : 00000000000000100000010000000011; +7 : 00000000000000000000000000000101; -- C1 COUNTER +8 : 00000000000001000000111000001110; +9 : 00000000000000000000000000000101; -- C2 COUNTER +10 : 00000000000010000001110000011100; +11 : 00000000000000000000000000000101; -- C3 COUNTER +12 : 00000000000011000001110000011100; +13 : 00000000000000000000000000000101; -- C4 COUNTER +14 : 00000000000100010000000100000001; +15 : 00000000000000000000000000000101; -- C5 COUNTER +16 : 00000000000101010000000100000001; +17 : 00000000000000000000000000000101; -- C6 COUNTER +18 : 00000000000110010000000100000001; +19 : 00000000000000000000000000000101; -- C7 COUNTER +20 : 00000000000111010000000100000001; +21 : 00000000000000000000000000000101; -- C8 COUNTER +22 : 00000000001000010000000100000001; +23 : 00000000000000000000000000000101; -- C9 COUNTER +24 : 00000000001001010000000100000001; +25 : 00000000000000000000000000000101; -- C10 COUNTER +26 : 00000000001010010000000100000001; +27 : 00000000000000000000000000000101; -- C11 COUNTER +28 : 00000000001011010000000100000001; +29 : 00000000000000000000000000000101; -- C12 COUNTER +30 : 00000000001100010000000100000001; +31 : 00000000000000000000000000000101; -- C13 COUNTER +32 : 00000000001101010000000100000001; +33 : 00000000000000000000000000000101; -- C14 COUNTER +34 : 00000000001110010000000100000001; +35 : 00000000000000000000000000000101; -- C15 COUNTER +36 : 00000000001111010000000100000001; +37 : 00000000000000000000000000000101; -- C16 COUNTER +38 : 00000000010000010000000100000001; +39 : 00000000000000000000000000000101; -- C17 COUNTER +40 : 00000000010001010000000100000001; +41 : 00000000000000000000000000001001; -- CHARGE PUMP +42 : 00000000000000000000000000000011; +43 : 00000000000000000000000000001000; -- BANDWIDTH SETTING +44 : 00000000000000000000000000001000; +45 : 00000000000000000000000000000111; -- M COUNTER FRACTIONAL VALUE +46 : 00011001011000110101111011100001; +47 : 00000000000000000000000000111111; -- END OF MIF +48 : 00000000000000000000000000000000; +49 : 00000000000000000000000000000000; +50 : 00000000000000000000000000000000; +51 : 00000000000000000000000000000000; +52 : 00000000000000000000000000000000; +53 : 00000000000000000000000000000000; +54 : 00000000000000000000000000000000; +55 : 00000000000000000000000000000000; +56 : 00000000000000000000000000000000; +57 : 00000000000000000000000000000000; +58 : 00000000000000000000000000000000; +59 : 00000000000000000000000000000000; +60 : 00000000000000000000000000000000; +61 : 00000000000000000000000000000000; +62 : 00000000000000000000000000000000; +63 : 00000000000000000000000000000000; +64 : 00000000000000000000000000000000; +65 : 00000000000000000000000000000000; +66 : 00000000000000000000000000000000; +67 : 00000000000000000000000000000000; +68 : 00000000000000000000000000000000; +69 : 00000000000000000000000000000000; +70 : 00000000000000000000000000000000; +71 : 00000000000000000000000000000000; +72 : 00000000000000000000000000000000; +73 : 00000000000000000000000000000000; +74 : 00000000000000000000000000000000; +75 : 00000000000000000000000000000000; +76 : 00000000000000000000000000000000; +77 : 00000000000000000000000000000000; +78 : 00000000000000000000000000000000; +79 : 00000000000000000000000000000000; +80 : 00000000000000000000000000000000; +81 : 00000000000000000000000000000000; +82 : 00000000000000000000000000000000; +83 : 00000000000000000000000000000000; +84 : 00000000000000000000000000000000; +85 : 00000000000000000000000000000000; +86 : 00000000000000000000000000000000; +87 : 00000000000000000000000000000000; +88 : 00000000000000000000000000000000; +89 : 00000000000000000000000000000000; +90 : 00000000000000000000000000000000; +91 : 00000000000000000000000000000000; +92 : 00000000000000000000000000000000; +93 : 00000000000000000000000000000000; +94 : 00000000000000000000000000000000; +95 : 00000000000000000000000000000000; +96 : 00000000000000000000000000000000; +97 : 00000000000000000000000000000000; +98 : 00000000000000000000000000000000; +99 : 00000000000000000000000000000000; +100 : 00000000000000000000000000000000; +101 : 00000000000000000000000000000000; +102 : 00000000000000000000000000000000; +103 : 00000000000000000000000000000000; +104 : 00000000000000000000000000000000; +105 : 00000000000000000000000000000000; +106 : 00000000000000000000000000000000; +107 : 00000000000000000000000000000000; +108 : 00000000000000000000000000000000; +109 : 00000000000000000000000000000000; +110 : 00000000000000000000000000000000; +111 : 00000000000000000000000000000000; +112 : 00000000000000000000000000000000; +113 : 00000000000000000000000000000000; +114 : 00000000000000000000000000000000; +115 : 00000000000000000000000000000000; +116 : 00000000000000000000000000000000; +117 : 00000000000000000000000000000000; +118 : 00000000000000000000000000000000; +119 : 00000000000000000000000000000000; +120 : 00000000000000000000000000000000; +121 : 00000000000000000000000000000000; +122 : 00000000000000000000000000000000; +123 : 00000000000000000000000000000000; +124 : 00000000000000000000000000000000; +125 : 00000000000000000000000000000000; +126 : 00000000000000000000000000000000; +127 : 00000000000000000000000000000000; +128 : 00000000000000000000000000000000; +129 : 00000000000000000000000000000000; +130 : 00000000000000000000000000000000; +131 : 00000000000000000000000000000000; +132 : 00000000000000000000000000000000; +133 : 00000000000000000000000000000000; +134 : 00000000000000000000000000000000; +135 : 00000000000000000000000000000000; +136 : 00000000000000000000000000000000; +137 : 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-set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_AUTO_RESET OFF -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" -set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" diff --git a/src/fpga/core/mf_pllbase/mf_pllbase_0002.v b/src/fpga/core/mf_pllbase/mf_pllbase_0002.v index 44da297..10e551b 100644 --- a/src/fpga/core/mf_pllbase/mf_pllbase_0002.v +++ b/src/fpga/core/mf_pllbase/mf_pllbase_0002.v @@ -20,24 +20,32 @@ module mf_pllbase_0002( output wire outclk_3, // interface 'locked' - output wire locked + output wire locked, + + // interface 'reconfig_to_pll' + input wire [63:0] reconfig_to_pll, + + // interface 'reconfig_from_pll' + output wire [63:0] reconfig_from_pll ); altera_pll #( .fractional_vco_multiplier("true"), .reference_clock_frequency("74.25 MHz"), + .pll_fractional_cout(32), + .pll_dsm_out_sel("1st_order"), .operation_mode("normal"), .number_of_clocks(4), - .output_clock_frequency0("85.909064 MHz"), + .output_clock_frequency0("85.909080 MHz"), .phase_shift0("0 ps"), .duty_cycle0(50), - .output_clock_frequency1("21.477266 MHz"), + .output_clock_frequency1("21.477270 MHz"), .phase_shift1("0 ps"), .duty_cycle1(50), - .output_clock_frequency2("10.738633 MHz"), + .output_clock_frequency2("10.738635 MHz"), .phase_shift2("0 ps"), .duty_cycle2(50), - .output_clock_frequency3("10.738633 MHz"), + .output_clock_frequency3("10.738635 MHz"), .phase_shift3("23280 ps"), .duty_cycle3(50), .output_clock_frequency4("0 MHz"), @@ -82,15 +90,161 @@ module mf_pllbase_0002( .output_clock_frequency17("0 MHz"), .phase_shift17("0 ps"), .duty_cycle17(50), - .pll_type("General"), - .pll_subtype("General") + .pll_type("Cyclone V"), + .pll_subtype("Reconfigurable"), + .m_cnt_hi_div(4), + .m_cnt_lo_div(4), + .n_cnt_hi_div(256), + .n_cnt_lo_div(256), + .m_cnt_bypass_en("false"), + .n_cnt_bypass_en("true"), + .m_cnt_odd_div_duty_en("false"), + .n_cnt_odd_div_duty_en("false"), + .c_cnt_hi_div0(4), + .c_cnt_lo_div0(3), + .c_cnt_prst0(1), + .c_cnt_ph_mux_prst0(0), + .c_cnt_in_src0("ph_mux_clk"), + .c_cnt_bypass_en0("false"), + .c_cnt_odd_div_duty_en0("true"), + .c_cnt_hi_div1(14), + .c_cnt_lo_div1(14), + .c_cnt_prst1(1), + .c_cnt_ph_mux_prst1(0), + .c_cnt_in_src1("ph_mux_clk"), + .c_cnt_bypass_en1("false"), + .c_cnt_odd_div_duty_en1("false"), + .c_cnt_hi_div2(28), + .c_cnt_lo_div2(28), + .c_cnt_prst2(1), + .c_cnt_ph_mux_prst2(0), + .c_cnt_in_src2("ph_mux_clk"), + .c_cnt_bypass_en2("false"), + .c_cnt_odd_div_duty_en2("false"), + .c_cnt_hi_div3(28), + .c_cnt_lo_div3(28), + .c_cnt_prst3(15), + .c_cnt_ph_mux_prst3(0), + .c_cnt_in_src3("ph_mux_clk"), + .c_cnt_bypass_en3("false"), + .c_cnt_odd_div_duty_en3("false"), + .c_cnt_hi_div4(1), + .c_cnt_lo_div4(1), + .c_cnt_prst4(1), + .c_cnt_ph_mux_prst4(0), + .c_cnt_in_src4("ph_mux_clk"), + .c_cnt_bypass_en4("true"), + .c_cnt_odd_div_duty_en4("false"), + .c_cnt_hi_div5(1), + .c_cnt_lo_div5(1), + .c_cnt_prst5(1), + .c_cnt_ph_mux_prst5(0), + .c_cnt_in_src5("ph_mux_clk"), + .c_cnt_bypass_en5("true"), + .c_cnt_odd_div_duty_en5("false"), + .c_cnt_hi_div6(1), + .c_cnt_lo_div6(1), + .c_cnt_prst6(1), + .c_cnt_ph_mux_prst6(0), + .c_cnt_in_src6("ph_mux_clk"), + .c_cnt_bypass_en6("true"), + .c_cnt_odd_div_duty_en6("false"), + .c_cnt_hi_div7(1), + .c_cnt_lo_div7(1), + .c_cnt_prst7(1), + .c_cnt_ph_mux_prst7(0), + .c_cnt_in_src7("ph_mux_clk"), + .c_cnt_bypass_en7("true"), + .c_cnt_odd_div_duty_en7("false"), + .c_cnt_hi_div8(1), + .c_cnt_lo_div8(1), + .c_cnt_prst8(1), + .c_cnt_ph_mux_prst8(0), + .c_cnt_in_src8("ph_mux_clk"), + .c_cnt_bypass_en8("true"), + .c_cnt_odd_div_duty_en8("false"), + .c_cnt_hi_div9(1), + .c_cnt_lo_div9(1), + .c_cnt_prst9(1), + .c_cnt_ph_mux_prst9(0), + .c_cnt_in_src9("ph_mux_clk"), + .c_cnt_bypass_en9("true"), + .c_cnt_odd_div_duty_en9("false"), + .c_cnt_hi_div10(1), + .c_cnt_lo_div10(1), + .c_cnt_prst10(1), + .c_cnt_ph_mux_prst10(0), + .c_cnt_in_src10("ph_mux_clk"), + .c_cnt_bypass_en10("true"), + .c_cnt_odd_div_duty_en10("false"), + .c_cnt_hi_div11(1), + .c_cnt_lo_div11(1), + .c_cnt_prst11(1), + .c_cnt_ph_mux_prst11(0), + .c_cnt_in_src11("ph_mux_clk"), + .c_cnt_bypass_en11("true"), + .c_cnt_odd_div_duty_en11("false"), + .c_cnt_hi_div12(1), + .c_cnt_lo_div12(1), + .c_cnt_prst12(1), + .c_cnt_ph_mux_prst12(0), + .c_cnt_in_src12("ph_mux_clk"), + .c_cnt_bypass_en12("true"), + .c_cnt_odd_div_duty_en12("false"), + .c_cnt_hi_div13(1), + .c_cnt_lo_div13(1), + .c_cnt_prst13(1), + .c_cnt_ph_mux_prst13(0), + .c_cnt_in_src13("ph_mux_clk"), + .c_cnt_bypass_en13("true"), + .c_cnt_odd_div_duty_en13("false"), + .c_cnt_hi_div14(1), + .c_cnt_lo_div14(1), + .c_cnt_prst14(1), + .c_cnt_ph_mux_prst14(0), + .c_cnt_in_src14("ph_mux_clk"), + .c_cnt_bypass_en14("true"), + .c_cnt_odd_div_duty_en14("false"), + .c_cnt_hi_div15(1), + .c_cnt_lo_div15(1), + .c_cnt_prst15(1), + .c_cnt_ph_mux_prst15(0), + .c_cnt_in_src15("ph_mux_clk"), + .c_cnt_bypass_en15("true"), + .c_cnt_odd_div_duty_en15("false"), + .c_cnt_hi_div16(1), + .c_cnt_lo_div16(1), + .c_cnt_prst16(1), + .c_cnt_ph_mux_prst16(0), + .c_cnt_in_src16("ph_mux_clk"), + .c_cnt_bypass_en16("true"), + .c_cnt_odd_div_duty_en16("false"), + .c_cnt_hi_div17(1), + .c_cnt_lo_div17(1), + .c_cnt_prst17(1), + .c_cnt_ph_mux_prst17(0), + .c_cnt_in_src17("ph_mux_clk"), + .c_cnt_bypass_en17("true"), + .c_cnt_odd_div_duty_en17("false"), + .pll_vco_div(1), + .pll_cp_current(30), + .pll_bwctrl(2000), + .pll_output_clk_frequency("601.36356 MHz"), + .pll_fractional_division("425942753"), + .mimic_fbclk_type("gclk"), + .pll_fbclk_mux_1("glb"), + .pll_fbclk_mux_2("fb_1"), + .pll_m_cnt_in_src("ph_mux_clk"), + .pll_slf_rst("true") ) altera_pll_i ( .rst (rst), .outclk ({outclk_3, outclk_2, outclk_1, outclk_0}), .locked (locked), + .reconfig_to_pll (reconfig_to_pll), .fboutclk ( ), .fbclk (1'b0), - .refclk (refclk) + .refclk (refclk), + .reconfig_from_pll (reconfig_from_pll) ); endmodule diff --git a/src/fpga/core/mf_pllbase_sim/aldec/rivierapro_setup.tcl b/src/fpga/core/mf_pllbase_sim/aldec/rivierapro_setup.tcl index 57a4858..9e6ee21 100644 --- a/src/fpga/core/mf_pllbase_sim/aldec/rivierapro_setup.tcl +++ b/src/fpga/core/mf_pllbase_sim/aldec/rivierapro_setup.tcl @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 21.1 850 win32 2022.09.19.15:27:26 +# ACDS 21.1 850 win32 2022.10.28.12:12:40 # ---------------------------------------- # Auto-generated simulation script rivierapro_setup.tcl # ---------------------------------------- diff --git a/src/fpga/core/mf_pllbase_sim/cadence/ncsim_setup.sh b/src/fpga/core/mf_pllbase_sim/cadence/ncsim_setup.sh index 44863ea..47ca8d5 100644 --- a/src/fpga/core/mf_pllbase_sim/cadence/ncsim_setup.sh +++ b/src/fpga/core/mf_pllbase_sim/cadence/ncsim_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 21.1 850 win32 2022.09.19.15:27:26 +# ACDS 21.1 850 win32 2022.10.28.12:12:40 # ---------------------------------------- # ncsim - auto-generated simulation script @@ -106,7 +106,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 21.1 850 win32 2022.09.19.15:27:26 +# ACDS 21.1 850 win32 2022.10.28.12:12:40 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="mf_pllbase" diff --git a/src/fpga/core/mf_pllbase_sim/mentor/msim_setup.tcl b/src/fpga/core/mf_pllbase_sim/mentor/msim_setup.tcl index e4278b2..88beaa8 100644 --- a/src/fpga/core/mf_pllbase_sim/mentor/msim_setup.tcl +++ b/src/fpga/core/mf_pllbase_sim/mentor/msim_setup.tcl @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 21.1 850 win32 2022.09.19.15:27:26 +# ACDS 21.1 850 win32 2022.10.28.12:12:40 # ---------------------------------------- # Initialize variables diff --git a/src/fpga/core/mf_pllbase_sim/mf_pllbase.vo b/src/fpga/core/mf_pllbase_sim/mf_pllbase.vo index 236dff6..59c1e8c 100644 --- a/src/fpga/core/mf_pllbase_sim/mf_pllbase.vo +++ b/src/fpga/core/mf_pllbase_sim/mf_pllbase.vo @@ -36,6 +36,8 @@ module mf_pllbase outclk_1, outclk_2, outclk_3, + reconfig_from_pll, + reconfig_to_pll, refclk, rst) /* synthesis synthesis_clearbox=1 */; output locked; @@ -43,264 +45,270 @@ module mf_pllbase output outclk_1; output outclk_2; output outclk_3; + output [63:0] reconfig_from_pll; + input [63:0] reconfig_to_pll; input refclk; input rst; - wire wire_mf_pllbase_altera_pll_altera_pll_i_2016_locked; - wire [3:0] wire_mf_pllbase_altera_pll_altera_pll_i_2016_outclk; + wire wire_mf_pllbase_altera_pll_altera_pll_i_661_locked; + wire [3:0] wire_mf_pllbase_altera_pll_altera_pll_i_661_outclk; + wire [63:0] wire_mf_pllbase_altera_pll_altera_pll_i_661_reconfig_from_pll; - altera_pll mf_pllbase_altera_pll_altera_pll_i_2016 + altera_pll mf_pllbase_altera_pll_altera_pll_i_661 ( .fbclk(1'b0), - .locked(wire_mf_pllbase_altera_pll_altera_pll_i_2016_locked), - .outclk(wire_mf_pllbase_altera_pll_altera_pll_i_2016_outclk), + .locked(wire_mf_pllbase_altera_pll_altera_pll_i_661_locked), + .outclk(wire_mf_pllbase_altera_pll_altera_pll_i_661_outclk), + .reconfig_from_pll(wire_mf_pllbase_altera_pll_altera_pll_i_661_reconfig_from_pll), + .reconfig_to_pll({reconfig_to_pll[63:0]}), .refclk(refclk), .rst(rst)); defparam - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_bypass_en0 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_bypass_en1 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_bypass_en10 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_bypass_en11 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_bypass_en12 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_bypass_en13 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_bypass_en14 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_bypass_en15 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_bypass_en16 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_bypass_en17 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_bypass_en2 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_bypass_en3 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_bypass_en4 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_bypass_en5 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_bypass_en6 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_bypass_en7 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_bypass_en8 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_bypass_en9 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_hi_div0 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_hi_div1 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_hi_div10 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_hi_div11 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_hi_div12 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_hi_div13 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_hi_div14 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_hi_div15 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_hi_div16 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_hi_div17 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_hi_div2 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_hi_div3 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_hi_div4 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_hi_div5 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_hi_div6 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_hi_div7 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_hi_div8 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_hi_div9 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_in_src0 = "ph_mux_clk", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_in_src1 = "ph_mux_clk", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_in_src10 = "ph_mux_clk", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_in_src11 = "ph_mux_clk", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_in_src12 = "ph_mux_clk", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_in_src13 = "ph_mux_clk", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_in_src14 = "ph_mux_clk", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_in_src15 = "ph_mux_clk", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_in_src16 = "ph_mux_clk", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_in_src17 = "ph_mux_clk", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_in_src2 = "ph_mux_clk", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_in_src3 = "ph_mux_clk", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_in_src4 = "ph_mux_clk", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_in_src5 = "ph_mux_clk", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_in_src6 = "ph_mux_clk", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_in_src7 = "ph_mux_clk", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_in_src8 = "ph_mux_clk", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_in_src9 = "ph_mux_clk", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_lo_div0 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_lo_div1 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_lo_div10 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_lo_div11 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_lo_div12 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_lo_div13 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_lo_div14 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_lo_div15 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_lo_div16 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_lo_div17 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_lo_div2 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_lo_div3 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_lo_div4 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_lo_div5 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_lo_div6 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_lo_div7 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_lo_div8 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_lo_div9 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_odd_div_duty_en0 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_odd_div_duty_en1 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_odd_div_duty_en10 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_odd_div_duty_en11 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_odd_div_duty_en12 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_odd_div_duty_en13 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_odd_div_duty_en14 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_odd_div_duty_en15 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_odd_div_duty_en16 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_odd_div_duty_en17 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_odd_div_duty_en2 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_odd_div_duty_en3 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_odd_div_duty_en4 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_odd_div_duty_en5 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_odd_div_duty_en6 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_odd_div_duty_en7 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_odd_div_duty_en8 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_odd_div_duty_en9 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_ph_mux_prst0 = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_ph_mux_prst1 = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_ph_mux_prst10 = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_ph_mux_prst11 = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_ph_mux_prst12 = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_ph_mux_prst13 = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_ph_mux_prst14 = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_ph_mux_prst15 = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_ph_mux_prst16 = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_ph_mux_prst17 = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_ph_mux_prst2 = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_ph_mux_prst3 = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_ph_mux_prst4 = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_ph_mux_prst5 = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_ph_mux_prst6 = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_ph_mux_prst7 = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_ph_mux_prst8 = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_ph_mux_prst9 = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_prst0 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_prst1 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_prst10 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_prst11 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_prst12 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_prst13 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_prst14 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_prst15 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_prst16 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_prst17 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_prst2 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_prst3 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_prst4 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_prst5 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_prst6 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_prst7 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_prst8 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.c_cnt_prst9 = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.clock_name_0 = "UNUSED", - mf_pllbase_altera_pll_altera_pll_i_2016.clock_name_1 = "UNUSED", - mf_pllbase_altera_pll_altera_pll_i_2016.clock_name_2 = "UNUSED", - mf_pllbase_altera_pll_altera_pll_i_2016.clock_name_3 = "UNUSED", - mf_pllbase_altera_pll_altera_pll_i_2016.clock_name_4 = "UNUSED", - mf_pllbase_altera_pll_altera_pll_i_2016.clock_name_5 = "UNUSED", - mf_pllbase_altera_pll_altera_pll_i_2016.clock_name_6 = "UNUSED", - mf_pllbase_altera_pll_altera_pll_i_2016.clock_name_7 = "UNUSED", - mf_pllbase_altera_pll_altera_pll_i_2016.clock_name_8 = "UNUSED", - mf_pllbase_altera_pll_altera_pll_i_2016.clock_name_global_0 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.clock_name_global_1 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.clock_name_global_2 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.clock_name_global_3 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.clock_name_global_4 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.clock_name_global_5 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.clock_name_global_6 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.clock_name_global_7 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.clock_name_global_8 = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.data_rate = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.deserialization_factor = 4, - mf_pllbase_altera_pll_altera_pll_i_2016.duty_cycle0 = 50, - mf_pllbase_altera_pll_altera_pll_i_2016.duty_cycle1 = 50, - mf_pllbase_altera_pll_altera_pll_i_2016.duty_cycle10 = 50, - mf_pllbase_altera_pll_altera_pll_i_2016.duty_cycle11 = 50, - mf_pllbase_altera_pll_altera_pll_i_2016.duty_cycle12 = 50, - mf_pllbase_altera_pll_altera_pll_i_2016.duty_cycle13 = 50, - mf_pllbase_altera_pll_altera_pll_i_2016.duty_cycle14 = 50, - mf_pllbase_altera_pll_altera_pll_i_2016.duty_cycle15 = 50, - mf_pllbase_altera_pll_altera_pll_i_2016.duty_cycle16 = 50, - mf_pllbase_altera_pll_altera_pll_i_2016.duty_cycle17 = 50, - mf_pllbase_altera_pll_altera_pll_i_2016.duty_cycle2 = 50, - mf_pllbase_altera_pll_altera_pll_i_2016.duty_cycle3 = 50, - mf_pllbase_altera_pll_altera_pll_i_2016.duty_cycle4 = 50, - mf_pllbase_altera_pll_altera_pll_i_2016.duty_cycle5 = 50, - mf_pllbase_altera_pll_altera_pll_i_2016.duty_cycle6 = 50, - mf_pllbase_altera_pll_altera_pll_i_2016.duty_cycle7 = 50, - mf_pllbase_altera_pll_altera_pll_i_2016.duty_cycle8 = 50, - mf_pllbase_altera_pll_altera_pll_i_2016.duty_cycle9 = 50, - mf_pllbase_altera_pll_altera_pll_i_2016.fractional_vco_multiplier = "true", - mf_pllbase_altera_pll_altera_pll_i_2016.m_cnt_bypass_en = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.m_cnt_hi_div = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.m_cnt_lo_div = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.m_cnt_odd_div_duty_en = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.mimic_fbclk_type = "gclk", - mf_pllbase_altera_pll_altera_pll_i_2016.n_cnt_bypass_en = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.n_cnt_hi_div = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.n_cnt_lo_div = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.n_cnt_odd_div_duty_en = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.number_of_clocks = 4, - mf_pllbase_altera_pll_altera_pll_i_2016.operation_mode = "normal", - mf_pllbase_altera_pll_altera_pll_i_2016.output_clock_frequency0 = "85.909064 MHz", - mf_pllbase_altera_pll_altera_pll_i_2016.output_clock_frequency1 = "21.477266 MHz", - mf_pllbase_altera_pll_altera_pll_i_2016.output_clock_frequency10 = "0 MHz", - mf_pllbase_altera_pll_altera_pll_i_2016.output_clock_frequency11 = "0 MHz", - mf_pllbase_altera_pll_altera_pll_i_2016.output_clock_frequency12 = "0 MHz", - mf_pllbase_altera_pll_altera_pll_i_2016.output_clock_frequency13 = "0 MHz", - mf_pllbase_altera_pll_altera_pll_i_2016.output_clock_frequency14 = "0 MHz", - mf_pllbase_altera_pll_altera_pll_i_2016.output_clock_frequency15 = "0 MHz", - mf_pllbase_altera_pll_altera_pll_i_2016.output_clock_frequency16 = "0 MHz", - mf_pllbase_altera_pll_altera_pll_i_2016.output_clock_frequency17 = "0 MHz", - mf_pllbase_altera_pll_altera_pll_i_2016.output_clock_frequency2 = "10.738633 MHz", - mf_pllbase_altera_pll_altera_pll_i_2016.output_clock_frequency3 = "10.738633 MHz", - mf_pllbase_altera_pll_altera_pll_i_2016.output_clock_frequency4 = "0 MHz", - mf_pllbase_altera_pll_altera_pll_i_2016.output_clock_frequency5 = "0 MHz", - mf_pllbase_altera_pll_altera_pll_i_2016.output_clock_frequency6 = "0 MHz", - mf_pllbase_altera_pll_altera_pll_i_2016.output_clock_frequency7 = "0 MHz", - mf_pllbase_altera_pll_altera_pll_i_2016.output_clock_frequency8 = "0 MHz", - mf_pllbase_altera_pll_altera_pll_i_2016.output_clock_frequency9 = "0 MHz", - mf_pllbase_altera_pll_altera_pll_i_2016.phase_shift0 = "0 ps", - mf_pllbase_altera_pll_altera_pll_i_2016.phase_shift1 = "0 ps", - mf_pllbase_altera_pll_altera_pll_i_2016.phase_shift10 = "0 ps", - mf_pllbase_altera_pll_altera_pll_i_2016.phase_shift11 = "0 ps", - mf_pllbase_altera_pll_altera_pll_i_2016.phase_shift12 = "0 ps", - mf_pllbase_altera_pll_altera_pll_i_2016.phase_shift13 = "0 ps", - mf_pllbase_altera_pll_altera_pll_i_2016.phase_shift14 = "0 ps", - mf_pllbase_altera_pll_altera_pll_i_2016.phase_shift15 = "0 ps", - mf_pllbase_altera_pll_altera_pll_i_2016.phase_shift16 = "0 ps", - mf_pllbase_altera_pll_altera_pll_i_2016.phase_shift17 = "0 ps", - mf_pllbase_altera_pll_altera_pll_i_2016.phase_shift2 = "0 ps", - mf_pllbase_altera_pll_altera_pll_i_2016.phase_shift3 = "23280 ps", - mf_pllbase_altera_pll_altera_pll_i_2016.phase_shift4 = "0 ps", - mf_pllbase_altera_pll_altera_pll_i_2016.phase_shift5 = "0 ps", - mf_pllbase_altera_pll_altera_pll_i_2016.phase_shift6 = "0 ps", - mf_pllbase_altera_pll_altera_pll_i_2016.phase_shift7 = "0 ps", - mf_pllbase_altera_pll_altera_pll_i_2016.phase_shift8 = "0 ps", - mf_pllbase_altera_pll_altera_pll_i_2016.phase_shift9 = "0 ps", - mf_pllbase_altera_pll_altera_pll_i_2016.pll_auto_clk_sw_en = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.pll_bw_sel = "low", - mf_pllbase_altera_pll_altera_pll_i_2016.pll_bwctrl = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.pll_clk_loss_sw_en = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.pll_clk_sw_dly = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.pll_clkin_0_src = "clk_0", - mf_pllbase_altera_pll_altera_pll_i_2016.pll_clkin_1_src = "clk_0", - mf_pllbase_altera_pll_altera_pll_i_2016.pll_cp_current = 0, - mf_pllbase_altera_pll_altera_pll_i_2016.pll_dsm_out_sel = "1st_order", - mf_pllbase_altera_pll_altera_pll_i_2016.pll_extclk_0_cnt_src = "pll_extclk_cnt_src_vss", - mf_pllbase_altera_pll_altera_pll_i_2016.pll_extclk_1_cnt_src = "pll_extclk_cnt_src_vss", - mf_pllbase_altera_pll_altera_pll_i_2016.pll_fbclk_mux_1 = "glb", - mf_pllbase_altera_pll_altera_pll_i_2016.pll_fbclk_mux_2 = "fb_1", - mf_pllbase_altera_pll_altera_pll_i_2016.pll_fractional_cout = 24, - mf_pllbase_altera_pll_altera_pll_i_2016.pll_fractional_division = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.pll_m_cnt_in_src = "ph_mux_clk", - mf_pllbase_altera_pll_altera_pll_i_2016.pll_manu_clk_sw_en = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.pll_output_clk_frequency = "0 MHz", - mf_pllbase_altera_pll_altera_pll_i_2016.pll_slf_rst = "false", - mf_pllbase_altera_pll_altera_pll_i_2016.pll_subtype = "General", - mf_pllbase_altera_pll_altera_pll_i_2016.pll_type = "General", - mf_pllbase_altera_pll_altera_pll_i_2016.pll_vco_div = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.pll_vcoph_div = 1, - mf_pllbase_altera_pll_altera_pll_i_2016.refclk1_frequency = "0 MHz", - mf_pllbase_altera_pll_altera_pll_i_2016.reference_clock_frequency = "74.25 MHz", - mf_pllbase_altera_pll_altera_pll_i_2016.sim_additional_refclk_cycles_to_lock = 0; + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_bypass_en0 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_bypass_en1 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_bypass_en10 = "true", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_bypass_en11 = "true", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_bypass_en12 = "true", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_bypass_en13 = "true", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_bypass_en14 = "true", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_bypass_en15 = "true", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_bypass_en16 = "true", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_bypass_en17 = "true", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_bypass_en2 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_bypass_en3 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_bypass_en4 = "true", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_bypass_en5 = "true", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_bypass_en6 = "true", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_bypass_en7 = "true", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_bypass_en8 = "true", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_bypass_en9 = "true", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_hi_div0 = 4, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_hi_div1 = 14, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_hi_div10 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_hi_div11 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_hi_div12 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_hi_div13 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_hi_div14 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_hi_div15 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_hi_div16 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_hi_div17 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_hi_div2 = 28, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_hi_div3 = 28, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_hi_div4 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_hi_div5 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_hi_div6 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_hi_div7 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_hi_div8 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_hi_div9 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_in_src0 = "ph_mux_clk", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_in_src1 = "ph_mux_clk", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_in_src10 = "ph_mux_clk", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_in_src11 = "ph_mux_clk", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_in_src12 = "ph_mux_clk", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_in_src13 = "ph_mux_clk", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_in_src14 = "ph_mux_clk", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_in_src15 = "ph_mux_clk", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_in_src16 = "ph_mux_clk", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_in_src17 = "ph_mux_clk", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_in_src2 = "ph_mux_clk", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_in_src3 = "ph_mux_clk", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_in_src4 = "ph_mux_clk", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_in_src5 = "ph_mux_clk", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_in_src6 = "ph_mux_clk", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_in_src7 = "ph_mux_clk", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_in_src8 = "ph_mux_clk", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_in_src9 = "ph_mux_clk", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_lo_div0 = 3, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_lo_div1 = 14, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_lo_div10 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_lo_div11 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_lo_div12 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_lo_div13 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_lo_div14 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_lo_div15 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_lo_div16 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_lo_div17 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_lo_div2 = 28, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_lo_div3 = 28, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_lo_div4 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_lo_div5 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_lo_div6 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_lo_div7 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_lo_div8 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_lo_div9 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_odd_div_duty_en0 = "true", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_odd_div_duty_en1 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_odd_div_duty_en10 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_odd_div_duty_en11 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_odd_div_duty_en12 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_odd_div_duty_en13 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_odd_div_duty_en14 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_odd_div_duty_en15 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_odd_div_duty_en16 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_odd_div_duty_en17 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_odd_div_duty_en2 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_odd_div_duty_en3 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_odd_div_duty_en4 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_odd_div_duty_en5 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_odd_div_duty_en6 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_odd_div_duty_en7 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_odd_div_duty_en8 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_odd_div_duty_en9 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_ph_mux_prst0 = 0, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_ph_mux_prst1 = 0, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_ph_mux_prst10 = 0, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_ph_mux_prst11 = 0, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_ph_mux_prst12 = 0, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_ph_mux_prst13 = 0, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_ph_mux_prst14 = 0, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_ph_mux_prst15 = 0, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_ph_mux_prst16 = 0, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_ph_mux_prst17 = 0, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_ph_mux_prst2 = 0, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_ph_mux_prst3 = 0, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_ph_mux_prst4 = 0, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_ph_mux_prst5 = 0, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_ph_mux_prst6 = 0, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_ph_mux_prst7 = 0, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_ph_mux_prst8 = 0, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_ph_mux_prst9 = 0, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_prst0 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_prst1 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_prst10 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_prst11 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_prst12 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_prst13 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_prst14 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_prst15 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_prst16 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_prst17 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_prst2 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_prst3 = 15, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_prst4 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_prst5 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_prst6 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_prst7 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_prst8 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.c_cnt_prst9 = 1, + mf_pllbase_altera_pll_altera_pll_i_661.clock_name_0 = "UNUSED", + mf_pllbase_altera_pll_altera_pll_i_661.clock_name_1 = "UNUSED", + mf_pllbase_altera_pll_altera_pll_i_661.clock_name_2 = "UNUSED", + mf_pllbase_altera_pll_altera_pll_i_661.clock_name_3 = "UNUSED", + mf_pllbase_altera_pll_altera_pll_i_661.clock_name_4 = "UNUSED", + mf_pllbase_altera_pll_altera_pll_i_661.clock_name_5 = "UNUSED", + mf_pllbase_altera_pll_altera_pll_i_661.clock_name_6 = "UNUSED", + mf_pllbase_altera_pll_altera_pll_i_661.clock_name_7 = "UNUSED", + mf_pllbase_altera_pll_altera_pll_i_661.clock_name_8 = "UNUSED", + mf_pllbase_altera_pll_altera_pll_i_661.clock_name_global_0 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.clock_name_global_1 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.clock_name_global_2 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.clock_name_global_3 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.clock_name_global_4 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.clock_name_global_5 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.clock_name_global_6 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.clock_name_global_7 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.clock_name_global_8 = "false", + mf_pllbase_altera_pll_altera_pll_i_661.data_rate = 0, + mf_pllbase_altera_pll_altera_pll_i_661.deserialization_factor = 4, + mf_pllbase_altera_pll_altera_pll_i_661.duty_cycle0 = 50, + mf_pllbase_altera_pll_altera_pll_i_661.duty_cycle1 = 50, + mf_pllbase_altera_pll_altera_pll_i_661.duty_cycle10 = 50, + mf_pllbase_altera_pll_altera_pll_i_661.duty_cycle11 = 50, + mf_pllbase_altera_pll_altera_pll_i_661.duty_cycle12 = 50, + mf_pllbase_altera_pll_altera_pll_i_661.duty_cycle13 = 50, + mf_pllbase_altera_pll_altera_pll_i_661.duty_cycle14 = 50, + mf_pllbase_altera_pll_altera_pll_i_661.duty_cycle15 = 50, + mf_pllbase_altera_pll_altera_pll_i_661.duty_cycle16 = 50, + mf_pllbase_altera_pll_altera_pll_i_661.duty_cycle17 = 50, + mf_pllbase_altera_pll_altera_pll_i_661.duty_cycle2 = 50, + mf_pllbase_altera_pll_altera_pll_i_661.duty_cycle3 = 50, + mf_pllbase_altera_pll_altera_pll_i_661.duty_cycle4 = 50, + mf_pllbase_altera_pll_altera_pll_i_661.duty_cycle5 = 50, + mf_pllbase_altera_pll_altera_pll_i_661.duty_cycle6 = 50, + mf_pllbase_altera_pll_altera_pll_i_661.duty_cycle7 = 50, + mf_pllbase_altera_pll_altera_pll_i_661.duty_cycle8 = 50, + mf_pllbase_altera_pll_altera_pll_i_661.duty_cycle9 = 50, + mf_pllbase_altera_pll_altera_pll_i_661.fractional_vco_multiplier = "true", + mf_pllbase_altera_pll_altera_pll_i_661.m_cnt_bypass_en = "false", + mf_pllbase_altera_pll_altera_pll_i_661.m_cnt_hi_div = 4, + mf_pllbase_altera_pll_altera_pll_i_661.m_cnt_lo_div = 4, + mf_pllbase_altera_pll_altera_pll_i_661.m_cnt_odd_div_duty_en = "false", + mf_pllbase_altera_pll_altera_pll_i_661.mimic_fbclk_type = "gclk", + mf_pllbase_altera_pll_altera_pll_i_661.n_cnt_bypass_en = "true", + mf_pllbase_altera_pll_altera_pll_i_661.n_cnt_hi_div = 256, + mf_pllbase_altera_pll_altera_pll_i_661.n_cnt_lo_div = 256, + mf_pllbase_altera_pll_altera_pll_i_661.n_cnt_odd_div_duty_en = "false", + mf_pllbase_altera_pll_altera_pll_i_661.number_of_clocks = 4, + mf_pllbase_altera_pll_altera_pll_i_661.operation_mode = "normal", + mf_pllbase_altera_pll_altera_pll_i_661.output_clock_frequency0 = "85.909080 MHz", + mf_pllbase_altera_pll_altera_pll_i_661.output_clock_frequency1 = "21.477270 MHz", + mf_pllbase_altera_pll_altera_pll_i_661.output_clock_frequency10 = "0 MHz", + mf_pllbase_altera_pll_altera_pll_i_661.output_clock_frequency11 = "0 MHz", + mf_pllbase_altera_pll_altera_pll_i_661.output_clock_frequency12 = "0 MHz", + mf_pllbase_altera_pll_altera_pll_i_661.output_clock_frequency13 = "0 MHz", + mf_pllbase_altera_pll_altera_pll_i_661.output_clock_frequency14 = "0 MHz", + mf_pllbase_altera_pll_altera_pll_i_661.output_clock_frequency15 = "0 MHz", + mf_pllbase_altera_pll_altera_pll_i_661.output_clock_frequency16 = "0 MHz", + mf_pllbase_altera_pll_altera_pll_i_661.output_clock_frequency17 = "0 MHz", + mf_pllbase_altera_pll_altera_pll_i_661.output_clock_frequency2 = "10.738635 MHz", + mf_pllbase_altera_pll_altera_pll_i_661.output_clock_frequency3 = "10.738635 MHz", + mf_pllbase_altera_pll_altera_pll_i_661.output_clock_frequency4 = "0 MHz", + mf_pllbase_altera_pll_altera_pll_i_661.output_clock_frequency5 = "0 MHz", + mf_pllbase_altera_pll_altera_pll_i_661.output_clock_frequency6 = "0 MHz", + mf_pllbase_altera_pll_altera_pll_i_661.output_clock_frequency7 = "0 MHz", + mf_pllbase_altera_pll_altera_pll_i_661.output_clock_frequency8 = "0 MHz", + mf_pllbase_altera_pll_altera_pll_i_661.output_clock_frequency9 = "0 MHz", + mf_pllbase_altera_pll_altera_pll_i_661.phase_shift0 = "0 ps", + mf_pllbase_altera_pll_altera_pll_i_661.phase_shift1 = "0 ps", + mf_pllbase_altera_pll_altera_pll_i_661.phase_shift10 = "0 ps", + mf_pllbase_altera_pll_altera_pll_i_661.phase_shift11 = "0 ps", + mf_pllbase_altera_pll_altera_pll_i_661.phase_shift12 = "0 ps", + mf_pllbase_altera_pll_altera_pll_i_661.phase_shift13 = "0 ps", + mf_pllbase_altera_pll_altera_pll_i_661.phase_shift14 = "0 ps", + mf_pllbase_altera_pll_altera_pll_i_661.phase_shift15 = "0 ps", + mf_pllbase_altera_pll_altera_pll_i_661.phase_shift16 = "0 ps", + mf_pllbase_altera_pll_altera_pll_i_661.phase_shift17 = "0 ps", + mf_pllbase_altera_pll_altera_pll_i_661.phase_shift2 = "0 ps", + mf_pllbase_altera_pll_altera_pll_i_661.phase_shift3 = "23280 ps", + mf_pllbase_altera_pll_altera_pll_i_661.phase_shift4 = "0 ps", + mf_pllbase_altera_pll_altera_pll_i_661.phase_shift5 = "0 ps", + mf_pllbase_altera_pll_altera_pll_i_661.phase_shift6 = "0 ps", + mf_pllbase_altera_pll_altera_pll_i_661.phase_shift7 = "0 ps", + mf_pllbase_altera_pll_altera_pll_i_661.phase_shift8 = "0 ps", + mf_pllbase_altera_pll_altera_pll_i_661.phase_shift9 = "0 ps", + mf_pllbase_altera_pll_altera_pll_i_661.pll_auto_clk_sw_en = "false", + mf_pllbase_altera_pll_altera_pll_i_661.pll_bw_sel = "low", + mf_pllbase_altera_pll_altera_pll_i_661.pll_bwctrl = 2000, + mf_pllbase_altera_pll_altera_pll_i_661.pll_clk_loss_sw_en = "false", + mf_pllbase_altera_pll_altera_pll_i_661.pll_clk_sw_dly = 0, + mf_pllbase_altera_pll_altera_pll_i_661.pll_clkin_0_src = "clk_0", + mf_pllbase_altera_pll_altera_pll_i_661.pll_clkin_1_src = "clk_0", + mf_pllbase_altera_pll_altera_pll_i_661.pll_cp_current = 30, + mf_pllbase_altera_pll_altera_pll_i_661.pll_dsm_out_sel = "1st_order", + mf_pllbase_altera_pll_altera_pll_i_661.pll_extclk_0_cnt_src = "pll_extclk_cnt_src_vss", + mf_pllbase_altera_pll_altera_pll_i_661.pll_extclk_1_cnt_src = "pll_extclk_cnt_src_vss", + mf_pllbase_altera_pll_altera_pll_i_661.pll_fbclk_mux_1 = "glb", + mf_pllbase_altera_pll_altera_pll_i_661.pll_fbclk_mux_2 = "fb_1", + mf_pllbase_altera_pll_altera_pll_i_661.pll_fractional_cout = 32, + mf_pllbase_altera_pll_altera_pll_i_661.pll_fractional_division = 425942753, + mf_pllbase_altera_pll_altera_pll_i_661.pll_m_cnt_in_src = "ph_mux_clk", + mf_pllbase_altera_pll_altera_pll_i_661.pll_manu_clk_sw_en = "false", + mf_pllbase_altera_pll_altera_pll_i_661.pll_output_clk_frequency = "601.36356 MHz", + mf_pllbase_altera_pll_altera_pll_i_661.pll_slf_rst = "true", + mf_pllbase_altera_pll_altera_pll_i_661.pll_subtype = "Reconfigurable", + mf_pllbase_altera_pll_altera_pll_i_661.pll_type = "Cyclone V", + mf_pllbase_altera_pll_altera_pll_i_661.pll_vco_div = 1, + mf_pllbase_altera_pll_altera_pll_i_661.pll_vcoph_div = 1, + mf_pllbase_altera_pll_altera_pll_i_661.refclk1_frequency = "0 MHz", + mf_pllbase_altera_pll_altera_pll_i_661.reference_clock_frequency = "74.25 MHz", + mf_pllbase_altera_pll_altera_pll_i_661.sim_additional_refclk_cycles_to_lock = 0; assign - locked = wire_mf_pllbase_altera_pll_altera_pll_i_2016_locked, - outclk_0 = wire_mf_pllbase_altera_pll_altera_pll_i_2016_outclk[0], - outclk_1 = wire_mf_pllbase_altera_pll_altera_pll_i_2016_outclk[1], - outclk_2 = wire_mf_pllbase_altera_pll_altera_pll_i_2016_outclk[2], - outclk_3 = wire_mf_pllbase_altera_pll_altera_pll_i_2016_outclk[3]; + locked = wire_mf_pllbase_altera_pll_altera_pll_i_661_locked, + outclk_0 = wire_mf_pllbase_altera_pll_altera_pll_i_661_outclk[0], + outclk_1 = wire_mf_pllbase_altera_pll_altera_pll_i_661_outclk[1], + outclk_2 = wire_mf_pllbase_altera_pll_altera_pll_i_661_outclk[2], + outclk_3 = wire_mf_pllbase_altera_pll_altera_pll_i_661_outclk[3], + reconfig_from_pll = {wire_mf_pllbase_altera_pll_altera_pll_i_661_reconfig_from_pll[63:0]}; endmodule //mf_pllbase //synopsys translate_on //VALID FILE diff --git a/src/fpga/core/mf_pllbase_sim/synopsys/vcs/vcs_setup.sh b/src/fpga/core/mf_pllbase_sim/synopsys/vcs/vcs_setup.sh index 5e1d9e4..7fb2d44 100644 --- a/src/fpga/core/mf_pllbase_sim/synopsys/vcs/vcs_setup.sh +++ b/src/fpga/core/mf_pllbase_sim/synopsys/vcs/vcs_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 21.1 850 win32 2022.09.19.15:27:26 +# ACDS 21.1 850 win32 2022.10.28.12:12:40 # ---------------------------------------- # vcs - auto-generated simulation script @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 21.1 850 win32 2022.09.19.15:27:26 +# ACDS 21.1 850 win32 2022.10.28.12:12:40 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="mf_pllbase" diff --git a/src/fpga/core/mf_pllbase_sim/synopsys/vcsmx/vcsmx_setup.sh b/src/fpga/core/mf_pllbase_sim/synopsys/vcsmx/vcsmx_setup.sh index 7ba7959..c6795c8 100644 --- a/src/fpga/core/mf_pllbase_sim/synopsys/vcsmx/vcsmx_setup.sh +++ b/src/fpga/core/mf_pllbase_sim/synopsys/vcsmx/vcsmx_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 21.1 850 win32 2022.09.19.15:27:26 +# ACDS 21.1 850 win32 2022.10.28.12:12:40 # ---------------------------------------- # vcsmx - auto-generated simulation script @@ -107,7 +107,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 21.1 850 win32 2022.09.19.15:27:26 +# ACDS 21.1 850 win32 2022.10.28.12:12:40 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="mf_pllbase" diff --git a/src/fpga/core/pal_pllbase.mif b/src/fpga/core/pal_pllbase.mif new file mode 100644 index 0000000..b53d85d --- /dev/null +++ b/src/fpga/core/pal_pllbase.mif @@ -0,0 +1,519 @@ +DEPTH = 512; +WIDTH = 32; +ADDRESS_RADIX = UNS; +DATA_RADIX = BIN; +CONTENT +BEGIN +0 : 00000000000000000000000000111110; -- START OF MIF +1 : 00000000000000000000000000000100; -- M COUNTER +2 : 00000000000000100000010100000100; +3 : 00000000000000000000000000000011; -- N COUNTER +4 : 00000000000000010000000000000000; +5 : 00000000000000000000000000000101; -- C0 COUNTER +6 : 00000000000000000000010000000100; +7 : 00000000000000000000000000000101; -- C1 COUNTER +8 : 00000000000001000001000000010000; +9 : 00000000000000000000000000000101; -- C2 COUNTER +10 : 00000000000010000010000000100000; +11 : 00000000000000000000000000000101; -- C3 COUNTER +12 : 00000000000011000010000000100000; +13 : 00000000000000000000000000000101; -- C4 COUNTER +14 : 00000000000100010000000100000001; +15 : 00000000000000000000000000000101; -- C5 COUNTER +16 : 00000000000101010000000100000001; +17 : 00000000000000000000000000000101; -- C6 COUNTER +18 : 00000000000110010000000100000001; +19 : 00000000000000000000000000000101; -- C7 COUNTER +20 : 00000000000111010000000100000001; +21 : 00000000000000000000000000000101; -- C8 COUNTER +22 : 00000000001000010000000100000001; +23 : 00000000000000000000000000000101; -- C9 COUNTER +24 : 00000000001001010000000100000001; +25 : 00000000000000000000000000000101; -- C10 COUNTER +26 : 00000000001010010000000100000001; +27 : 00000000000000000000000000000101; -- C11 COUNTER +28 : 00000000001011010000000100000001; +29 : 00000000000000000000000000000101; -- C12 COUNTER +30 : 00000000001100010000000100000001; +31 : 00000000000000000000000000000101; -- C13 COUNTER +32 : 00000000001101010000000100000001; +33 : 00000000000000000000000000000101; -- C14 COUNTER +34 : 00000000001110010000000100000001; +35 : 00000000000000000000000000000101; -- C15 COUNTER +36 : 00000000001111010000000100000001; +37 : 00000000000000000000000000000101; -- C16 COUNTER +38 : 00000000010000010000000100000001; +39 : 00000000000000000000000000000101; -- C17 COUNTER +40 : 00000000010001010000000100000001; +41 : 00000000000000000000000000001001; -- CHARGE PUMP +42 : 00000000000000000000000000000011; +43 : 00000000000000000000000000001000; -- BANDWIDTH SETTING +44 : 00000000000000000000000000001000; +45 : 00000000000000000000000000000111; -- M COUNTER FRACTIONAL VALUE +46 : 00101011111110010000101110000110; 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File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2022 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 416 304) + (text "pll_reconfig" (rect 174 -1 218 11)(font "Arial" (font_size 10))) + (text "inst" (rect 8 288 20 300)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "mgmt_clk" (rect 0 0 40 12)(font "Arial" (font_size 8))) + (text "mgmt_clk" (rect 4 61 52 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 128 72)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "mgmt_reset" (rect 0 0 49 12)(font "Arial" (font_size 8))) + (text "mgmt_reset" (rect 4 101 64 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 128 112)(line_width 1)) + ) + (port + (pt 0 168) + (input) + (text "mgmt_read" (rect 0 0 47 12)(font "Arial" (font_size 8))) + (text "mgmt_read" (rect 4 157 58 168)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 128 168)(line_width 1)) + ) + (port + (pt 0 184) + (input) + (text "mgmt_write" (rect 0 0 47 12)(font "Arial" (font_size 8))) + (text "mgmt_write" (rect 4 173 64 184)(font "Arial" (font_size 8))) + (line (pt 0 184)(pt 128 184)(line_width 1)) + ) + (port + (pt 0 216) + (input) + (text "mgmt_address[5..0]" (rect 0 0 81 12)(font "Arial" (font_size 8))) + (text "mgmt_address[5..0]" (rect 4 205 112 216)(font "Arial" (font_size 8))) + (line (pt 0 216)(pt 128 216)(line_width 3)) + ) + (port + (pt 0 232) + (input) + (text "mgmt_writedata[31..0]" (rect 0 0 87 12)(font "Arial" (font_size 8))) + (text "mgmt_writedata[31..0]" (rect 4 221 130 232)(font "Arial" (font_size 8))) + (line (pt 0 232)(pt 128 232)(line_width 3)) + ) + (port + (pt 0 272) + (input) + (text "reconfig_from_pll[63..0]" (rect 0 0 95 12)(font "Arial" (font_size 8))) + (text "reconfig_from_pll[63..0]" (rect 4 261 148 272)(font "Arial" (font_size 8))) + (line (pt 0 272)(pt 128 272)(line_width 3)) + ) + (port + (pt 0 152) + (output) + (text "mgmt_waitrequest" (rect 0 0 73 12)(font "Arial" (font_size 8))) + (text "mgmt_waitrequest" (rect 4 141 100 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 128 152)(line_width 1)) + ) + (port + (pt 0 200) + (output) + (text "mgmt_readdata[31..0]" (rect 0 0 87 12)(font "Arial" (font_size 8))) + (text "mgmt_readdata[31..0]" (rect 4 189 124 200)(font "Arial" (font_size 8))) + (line (pt 0 200)(pt 128 200)(line_width 3)) + ) + (port + (pt 416 72) + (output) + (text "reconfig_to_pll[63..0]" (rect 0 0 82 12)(font "Arial" (font_size 8))) + (text "reconfig_to_pll[63..0]" (rect 310 61 442 72)(font "Arial" (font_size 8))) + (line (pt 416 72)(pt 288 72)(line_width 3)) + ) + (drawing + (text "mgmt_clk" (rect 72 43 192 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 133 67 284 144)(font "Arial" (color 0 0 0))) + (text "mgmt_reset" (rect 58 83 176 179)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reset" (rect 133 107 296 224)(font "Arial" (color 0 0 0))) + (text "mgmt_avalon_slave" (rect 13 123 128 259)(font "Arial" (color 128 0 0)(font_size 9))) + (text "waitrequest" (rect 133 147 332 304)(font "Arial" (color 0 0 0))) + (text "read" (rect 133 163 290 336)(font "Arial" (color 0 0 0))) + (text "write" (rect 133 179 296 368)(font "Arial" (color 0 0 0))) + (text "readdata" (rect 133 195 314 400)(font "Arial" (color 0 0 0))) + (text "address" (rect 133 211 308 432)(font "Arial" (color 0 0 0))) + (text "writedata" (rect 133 227 320 464)(font "Arial" (color 0 0 0))) + (text "reconfig_to_pll" (rect 289 43 668 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reconfig_to_pll" (rect 221 67 532 144)(font "Arial" (color 0 0 0))) + (text "reconfig_from_pll" (rect 25 243 152 499)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reconfig_from_pll" (rect 133 267 368 544)(font "Arial" (color 0 0 0))) + (text " altera_pll_reconfig " (rect 333 288 792 586)(font "Arial" )) + (line (pt 128 32)(pt 288 32)(line_width 1)) + (line (pt 288 32)(pt 288 288)(line_width 1)) + (line (pt 128 288)(pt 288 288)(line_width 1)) + (line (pt 128 32)(pt 128 288)(line_width 1)) + (line (pt 129 52)(pt 129 76)(line_width 1)) + (line (pt 130 52)(pt 130 76)(line_width 1)) + (line (pt 129 92)(pt 129 116)(line_width 1)) + (line (pt 130 92)(pt 130 116)(line_width 1)) + (line (pt 129 132)(pt 129 236)(line_width 1)) + (line (pt 130 132)(pt 130 236)(line_width 1)) + (line (pt 287 52)(pt 287 76)(line_width 1)) + (line (pt 286 52)(pt 286 76)(line_width 1)) + (line (pt 129 252)(pt 129 276)(line_width 1)) + (line (pt 130 252)(pt 130 276)(line_width 1)) + (line (pt 0 0)(pt 416 0)(line_width 1)) + (line (pt 416 0)(pt 416 304)(line_width 1)) + (line (pt 0 304)(pt 416 304)(line_width 1)) + (line (pt 0 0)(pt 0 304)(line_width 1)) + ) +) diff --git a/src/fpga/core/pll_reconfig.ppf b/src/fpga/core/pll_reconfig.ppf new file mode 100644 index 0000000..e6cec87 --- /dev/null +++ b/src/fpga/core/pll_reconfig.ppf @@ -0,0 +1,19 @@ + + + + + + + + + + + + + + + diff --git a/src/fpga/core/pll_reconfig.qip b/src/fpga/core/pll_reconfig.qip new file mode 100644 index 0000000..65861aa --- /dev/null +++ b/src/fpga/core/pll_reconfig.qip @@ -0,0 +1,47 @@ +set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_TOOL_NAME "altera_pll_reconfig" +set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_TOOL_VERSION "21.1" +set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "pll_reconfig" -name MISC_FILE [file join $::quartus(qip_path) "pll_reconfig.cmp"] +set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" +set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_QSYS_MODE "UNKNOWN" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_NAME "cGxsX3JlY29uZmln" +set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_DISPLAY_NAME "UExMIFJlY29uZmlnIEludGVsIEZQR0EgSVA=" +set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_VERSION "MjEuMQ==" +set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3AgUmVjb25maWd1cmF0aW9uIEJsb2Nr" +set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA==" +set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA==" +set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA==" +set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA==" +set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo" +set_global_assignment -entity "pll_reconfig" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw==" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_NAME "YWx0ZXJhX3BsbF9yZWNvbmZpZ190b3A=" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_DISPLAY_NAME "UExMIFJlY29uZmlnIEludGVsIEZQR0EgSVA=" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_VERSION "MjEuMQ==" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3AgUmVjb25maWd1cmF0aW9uIEJsb2Nr" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::ZGV2aWNlX2ZhbWlseQ==" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01JRg==::dHJ1ZQ==::RW5hYmxlIE1JRiBTdHJlYW1pbmc=" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "TUlGX0ZJTEVfTkFNRQ==::Y29yZS9tZl9wbGxiYXNlL21mX3BsbGJhc2UubWlm::UGF0aCB0byBNSUYgZmlsZQ==" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA==" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA==" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA==" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA==" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw==" + +set_global_assignment -library "pll_reconfig" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_reconfig.v"] +set_global_assignment -library "pll_reconfig" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_reconfig/altera_pll_reconfig_top.v"] +set_global_assignment -library "pll_reconfig" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_reconfig/altera_pll_reconfig_mif_reader.v"] +set_global_assignment -library "pll_reconfig" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_reconfig/altera_pll_reconfig_core.v"] +set_global_assignment -library "pll_reconfig" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_reconfig/altera_std_synchronizer.v"] + +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_TOOL_NAME "altera_pll_reconfig" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_TOOL_VERSION "21.1" +set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_reconfig" -name IP_TOOL_ENV "mwpim" diff --git a/src/fpga/core/pll_reconfig.sip b/src/fpga/core/pll_reconfig.sip new file mode 100644 index 0000000..715a1c5 --- /dev/null +++ b/src/fpga/core/pll_reconfig.sip @@ -0,0 +1,10 @@ +set_global_assignment -entity "pll_reconfig" -library "lib_pll_reconfig" -name IP_TOOL_NAME "altera_pll_reconfig" +set_global_assignment -entity "pll_reconfig" -library "lib_pll_reconfig" -name IP_TOOL_VERSION "21.1" +set_global_assignment -entity "pll_reconfig" -library "lib_pll_reconfig" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "lib_pll_reconfig" -name SPD_FILE [file join $::quartus(sip_path) "pll_reconfig.spd"] + +set_global_assignment -library "lib_pll_reconfig" -name MISC_FILE [file join $::quartus(sip_path) "pll_reconfig_sim/pll_reconfig.v"] +set_global_assignment -library "lib_pll_reconfig" -name MISC_FILE [file join $::quartus(sip_path) "pll_reconfig_sim/altera_pll_reconfig/altera_pll_reconfig_top.v"] +set_global_assignment -library "lib_pll_reconfig" -name MISC_FILE [file join $::quartus(sip_path) "pll_reconfig_sim/altera_pll_reconfig/altera_pll_reconfig_mif_reader.v"] +set_global_assignment -library "lib_pll_reconfig" -name MISC_FILE [file join $::quartus(sip_path) "pll_reconfig_sim/altera_pll_reconfig/altera_pll_reconfig_core.v"] +set_global_assignment -library "lib_pll_reconfig" -name MISC_FILE [file join $::quartus(sip_path) "pll_reconfig_sim/altera_pll_reconfig/altera_std_synchronizer.v"] diff --git a/src/fpga/core/pll_reconfig.spd b/src/fpga/core/pll_reconfig.spd new file mode 100644 index 0000000..c64c12f --- /dev/null +++ b/src/fpga/core/pll_reconfig.spd @@ -0,0 +1,22 @@ + + + + + + + + + + diff --git a/src/fpga/core/pll_reconfig.v b/src/fpga/core/pll_reconfig.v new file mode 100644 index 0000000..360c759 --- /dev/null +++ b/src/fpga/core/pll_reconfig.v @@ -0,0 +1,86 @@ +// megafunction wizard: %PLL Reconfig Intel FPGA IP v21.1% +// GENERATION: XML +// pll_reconfig.v + +// Generated using ACDS version 21.1 850 + +`timescale 1 ps / 1 ps +module pll_reconfig #( + parameter ENABLE_BYTEENABLE = 0, + parameter BYTEENABLE_WIDTH = 4, + parameter RECONFIG_ADDR_WIDTH = 6, + parameter RECONFIG_DATA_WIDTH = 32, + parameter reconf_width = 64, + parameter WAIT_FOR_LOCK = 1 + ) ( + input wire mgmt_clk, // mgmt_clk.clk + input wire mgmt_reset, // mgmt_reset.reset + output wire mgmt_waitrequest, // mgmt_avalon_slave.waitrequest + input wire mgmt_read, // .read + input wire mgmt_write, // .write + output wire [31:0] mgmt_readdata, // .readdata + input wire [5:0] mgmt_address, // .address + input wire [31:0] mgmt_writedata, // .writedata + output wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll + input wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll + ); + + altera_pll_reconfig_top #( + .device_family ("Cyclone V"), + .ENABLE_MIF (1), + .MIF_FILE_NAME ("core/pal_pllbase.mif"), + .ENABLE_BYTEENABLE (ENABLE_BYTEENABLE), + .BYTEENABLE_WIDTH (BYTEENABLE_WIDTH), + .RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH), + .RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH), + .reconf_width (reconf_width), + .WAIT_FOR_LOCK (WAIT_FOR_LOCK) + ) pll_reconfig_inst ( + .mgmt_clk (mgmt_clk), // mgmt_clk.clk + .mgmt_reset (mgmt_reset), // mgmt_reset.reset + .mgmt_waitrequest (mgmt_waitrequest), // mgmt_avalon_slave.waitrequest + .mgmt_read (mgmt_read), // .read + .mgmt_write (mgmt_write), // .write + .mgmt_readdata (mgmt_readdata), // .readdata + .mgmt_address (mgmt_address), // .address + .mgmt_writedata (mgmt_writedata), // .writedata + .reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll + .reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll + .mgmt_byteenable (4'b0000) // (terminated) + ); + +endmodule +// Retrieval info: +// +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// IPFS_FILES : pll_reconfig.vo +// RELATED_FILES: pll_reconfig.v, altera_pll_reconfig_top.v, altera_pll_reconfig_mif_reader.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v diff --git a/src/fpga/core/pll_reconfig/altera_pll_reconfig_core.v b/src/fpga/core/pll_reconfig/altera_pll_reconfig_core.v new file mode 100644 index 0000000..01f9dd2 --- /dev/null +++ b/src/fpga/core/pll_reconfig/altera_pll_reconfig_core.v @@ -0,0 +1,2184 @@ +// (C) 2001-2022 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1ps/1ps + +module altera_pll_reconfig_core +#( + parameter reconf_width = 64, + parameter device_family = "Stratix V", + // MIF Streaming parameters + parameter RECONFIG_ADDR_WIDTH = 6, + parameter RECONFIG_DATA_WIDTH = 32, + parameter ROM_ADDR_WIDTH = 9, + parameter ROM_DATA_WIDTH = 32, + parameter ROM_NUM_WORDS = 512 +) ( + + //input + input wire mgmt_clk, + input wire mgmt_reset, + + + //conduits + output wire [reconf_width-1:0] reconfig_to_pll, + input wire [reconf_width-1:0] reconfig_from_pll, + + // user data (avalon-MM slave interface) + output wire [31:0] mgmt_readdata, + output wire mgmt_waitrequest, + input wire [5:0] mgmt_address, + input wire mgmt_read, + input wire mgmt_write, + input wire [31:0] mgmt_writedata, + + //other + output wire mif_start_out, + output reg [ROM_ADDR_WIDTH-1:0] mif_base_addr +); + localparam mode_WR = 1'b0; + localparam mode_POLL = 1'b1; + localparam MODE_REG = 6'b000000; + localparam STATUS_REG = 6'b000001; + localparam START_REG = 6'b000010; + localparam N_REG = 6'b000011; + localparam M_REG = 6'b000100; + localparam C_COUNTERS_REG = 6'b000101; + localparam DPS_REG = 6'b000110; + localparam DSM_REG = 6'b000111; + localparam BWCTRL_REG = 6'b001000; + localparam CP_CURRENT_REG = 6'b001001; + localparam ANY_DPRIO = 6'b100000; + localparam CNT_BASE = 5'b001010; + localparam VCO_REG = 6'b011100; + localparam MIF_REG = 6'b011111; + + //C Counters + localparam number_of_counters = 5'd18; + localparam CNT_0 = 1'd0, CNT_1 = 5'd1, CNT_2 = 5'd2, + CNT_3 = 5'd3, CNT_4 = 5'd4, CNT_5 = 5'd5, + CNT_6 = 5'd6, CNT_7 = 5'd7, CNT_8 = 5'd8, + CNT_9 = 5'd9, CNT_10 = 5'd10, CNT_11 = 5'd11, + CNT_12 = 5'd12, CNT_13 = 5'd13, CNT_14 = 5'd14, + CNT_15 = 5'd15, CNT_16 = 5'd16, CNT_17 = 5'd17; + //C counter addresses + localparam C_CNT_0_DIV_ADDR = 5'h00; + localparam C_CNT_0_DIV_ADDR_DPRIO_1 = 5'h11; + localparam C_CNT_0_3_BYPASS_EN_ADDR = 5'h15; + localparam C_CNT_0_3_ODD_DIV_EN_ADDR = 5'h17; + localparam C_CNT_4_17_BYPASS_EN_ADDR = 5'h14; + localparam C_CNT_4_17_ODD_DIV_EN_ADDR = 5'h16; + //N counter addresses + localparam N_CNT_DIV_ADDR = 5'h13; + localparam N_CNT_BYPASS_EN_ADDR = 5'h15; + localparam N_CNT_ODD_DIV_EN_ADDR = 5'h17; + //M counter addresses + localparam M_CNT_DIV_ADDR = 5'h12; + localparam M_CNT_BYPASS_EN_ADDR = 5'h15; + localparam M_CNT_ODD_DIV_EN_ADDR = 5'h17; + + //DSM address + localparam DSM_K_FRACTIONAL_DIVISION_ADDR_0 = 5'h18; + localparam DSM_K_FRACTIONAL_DIVISION_ADDR_1 = 5'h19; + localparam DSM_K_READY_ADDR = 5'h17; + localparam DSM_K_DITHER_ADDR = 5'h17; + localparam DSM_OUT_SEL_ADDR = 6'h30; + + //Other DSM params + localparam DSM_K_READY_BIT_INDEX = 4'd11; + //BWCTRL address + //Bit 0-3 of addr + localparam BWCTRL_ADDR = 6'h30; + //CP_CURRENT address + //Bit 0-2 of addr + localparam CP_CURRENT_ADDR = 6'h31; + + // VCODIV address + localparam VCO_ADDR = 5'h17; + + localparam DPRIO_IDLE = 3'd0, ONE = 3'd1, TWO = 3'd2, THREE = 3'd3, FOUR = 3'd4, + FIVE = 3'd5, SIX = 3'd6, SEVEN = 3'd7, EIGHT = 4'd8, NINE = 4'd9, TEN = 4'd10, + ELEVEN = 4'd11, TWELVE = 4'd12, THIRTEEN = 4'd13, FOURTEEN = 4'd14, DPRIO_DONE = 4'd15; + localparam IDLE = 2'b00, WAIT_ON_LOCK = 2'b01, LOCKED = 2'b10; + + wire clk; + wire reset; + wire gnd; + + wire [5: 0] slave_address; + wire slave_read; + wire slave_write; + wire [31: 0] slave_writedata; + + reg [31: 0] slave_readdata_d; + reg [31: 0] slave_readdata_q; + wire slave_waitrequest; + reg slave_mode; + + assign clk = mgmt_clk; + + assign slave_address = mgmt_address; + assign slave_read = mgmt_read; + assign slave_write = mgmt_write; + assign slave_writedata = mgmt_writedata; + + reg read_waitrequest; + // Outputs + assign mgmt_readdata = slave_readdata_q; + assign mgmt_waitrequest = slave_waitrequest | read_waitrequest; //Read waitrequest asserted in polling mode + + //internal signals + wire locked_orig; + wire locked; + + wire pll_start; + wire pll_start_valid; + reg status_read; + wire read_slave_mode_asserted; + + wire pll_start_asserted; + + reg [1:0] current_state; + reg [1:0] next_state; + + reg status;//0=busy, 1=ready + //user_mode_init user_mode_init_inst (clk, reset, dprio_mdio_dis, ser_shift_load); + //declaring the init wires. These will have 0 on them for 64 clk cycles + wire [ 5:0] init_dprio_address; + wire init_dprio_read; + wire [ 1:0] init_dprio_byteen; + wire init_dprio_write; + wire [15:0] init_dprio_writedata; + + wire init_atpgmode; + wire init_mdio_dis; + wire init_scanen; + wire init_ser_shift_load; + wire dprio_init_done; + + //DPRIO output signals after initialization is done + wire dprio_clk; + reg avmm_dprio_write; + reg avmm_dprio_read; + reg [5:0] avmm_dprio_address; + reg [15:0] avmm_dprio_writedata; + reg [1:0] avmm_dprio_byteen; + wire avmm_atpgmode; + wire avmm_mdio_dis; + wire avmm_scanen; + + //Final output wires that are muxed between the init and avmm wires. + wire dprio_init_reset; + wire [5:0] dprio_address /*synthesis keep*/; + wire dprio_read/*synthesis keep*/; + wire [1:0] dprio_byteen/*synthesis keep*/; + wire dprio_write/*synthesis keep*/; + wire [15:0] dprio_writedata/*synthesis keep*/; + wire dprio_mdio_dis/*synthesis keep*/; + wire dprio_ser_shift_load/*synthesis keep*/; + wire dprio_atpgmode/*synthesis keep*/; + wire dprio_scanen/*synthesis keep*/; + + + //other PLL signals for dyn ph shift + wire phase_done/*synthesis keep*/; + wire phase_en/*synthesis keep*/; + wire up_dn/*synthesis keep*/; + wire [4:0] cnt_sel; + + //DPRIO input signals + wire [15:0] dprio_readdata; + + //internal logic signals + //storage registers for user sent data + reg dprio_temp_read_1; + reg dprio_temp_read_2; + reg dprio_start; + reg mif_start_assert; + reg dps_start_assert; + wire usr_valid_changes; + reg [3:0] dprio_cur_state; + reg [3:0] dprio_next_state; + reg [15:0] dprio_temp_m_n_c_readdata_1_d; + reg [15:0] dprio_temp_m_n_c_readdata_2_d; + reg [15:0] dprio_temp_m_n_c_readdata_1_q; + reg [15:0] dprio_temp_m_n_c_readdata_2_q; + reg dprio_write_done; + //C counters signals + reg [7:0] usr_c_cnt_lo; + reg [7:0] usr_c_cnt_hi; + reg usr_c_cnt_bypass_en; + reg usr_c_cnt_odd_duty_div_en; + reg [7:0] temp_c_cnt_lo [0:17]; + reg [7:0] temp_c_cnt_hi [0:17]; + reg temp_c_cnt_bypass_en [0:17]; + reg temp_c_cnt_odd_duty_div_en [0:17]; + reg any_c_cnt_changed; + reg all_c_cnt_done_q; + reg all_c_cnt_done_d; + reg [17:0] c_cnt_changed; + reg [17:0] c_cnt_done_d; + reg [17:0] c_cnt_done_q; + //N counter signals + reg [7:0] usr_n_cnt_lo; + reg [7:0] usr_n_cnt_hi; + reg usr_n_cnt_bypass_en; + reg usr_n_cnt_odd_duty_div_en; + reg n_cnt_changed; + reg n_cnt_done_d; + reg n_cnt_done_q; + //M counter signals + reg [7:0] usr_m_cnt_lo; + reg [7:0] usr_m_cnt_hi; + reg usr_m_cnt_bypass_en; + reg usr_m_cnt_odd_duty_div_en; + reg m_cnt_changed; + reg m_cnt_done_d; + reg m_cnt_done_q; + //dyn phase regs + reg [15:0] usr_num_shifts; + reg [4:0] usr_cnt_sel /*synthesis preserve*/; + reg usr_up_dn; + reg dps_changed; + wire dps_changed_valid; + wire dps_done; + + //DSM Signals + reg [31:0] usr_k_value; + reg dsm_k_changed; + reg dsm_k_done_d; + reg dsm_k_done_q; + reg dsm_k_ready_false_done_d; + //BW signals + reg [3:0] usr_bwctrl_value; + reg bwctrl_changed; + reg bwctrl_done_d; + reg bwctrl_done_q; + //CP signals + reg [2:0] usr_cp_current_value; + reg cp_current_changed; + reg cp_current_done_d; + reg cp_current_done_q; + //VCO signals + reg usr_vco_value; + reg vco_changed; + reg vco_done_d; + reg vco_done_q; + //Manual DPRIO signals + reg manual_dprio_done_q; + reg manual_dprio_done_d; + reg manual_dprio_changed; + reg [5:0] usr_dprio_address; + reg [15:0] usr_dprio_writedata_0; + reg usr_r_w; + //keeping track of which operation happened last + reg [5:0] operation_address; + // Address wires for all C_counter DPRIO registers + // These are outputs of LUTS, changing depending + // on whether PLL_0 or PLL_1 being used + + + //Fitter will tell if FPLL1 is being used + wire fpll_1; + + // other + reg mif_reg_asserted; + // MAIN FSM + + // Synchronize locked signal + altera_std_synchronizer #( + .depth(3) + ) altera_std_synchronizer_inst ( + .clk(mgmt_clk), + .reset_n(~mgmt_reset), + .din(locked_orig), + .dout(locked) + ); + + always @(posedge clk) + begin + if (reset) + begin + dprio_cur_state <= DPRIO_IDLE; + current_state <= IDLE; + end + else + begin + current_state <= next_state; + dprio_cur_state <= dprio_next_state; + end + end + + always @(*) + begin + case(current_state) + IDLE: + begin + if (pll_start & !slave_waitrequest & usr_valid_changes) + next_state = WAIT_ON_LOCK; + else + next_state = IDLE; + end + WAIT_ON_LOCK: + begin + if (locked & dps_done & dprio_write_done) // received locked high from PLL + begin + if (slave_mode==mode_WR) //if the mode is waitrequest, then + // goto IDLE state directly + next_state = IDLE; + else + next_state = LOCKED; //otherwise go the locked state + end + else + next_state = WAIT_ON_LOCK; + end + + LOCKED: + begin + if (status_read) // stay in LOCKED until user reads status + next_state = IDLE; + else + next_state = LOCKED; + end + + default: next_state = 2'bxx; + + endcase + end + + + // ask the pll to start reconfig + assign pll_start = (pll_start_asserted & (current_state==IDLE)) ; + assign pll_start_valid = (pll_start & (next_state==WAIT_ON_LOCK)) ; + + + + // WRITE OPERATIONS + assign pll_start_asserted = slave_write & (slave_address == START_REG); + assign mif_start_out = pll_start & mif_reg_asserted; + + //reading the mode register to determine what mode the slave will operate + //in. + always @(posedge clk) + begin + if (reset) + slave_mode <= mode_WR; + else if (slave_write & (slave_address == MODE_REG) & !slave_waitrequest) + slave_mode <= slave_writedata[0]; + end + + //record which values user wants to change. + + //reading in the actual values that need to be reconfigged and sending + //them to the PLL + always @(posedge clk) + begin + if (reset) + begin + //reset all regs here + //BW signals reset + usr_bwctrl_value <= 0; + bwctrl_changed <= 0; + bwctrl_done_q <= 0; + //CP signals reset + usr_cp_current_value <= 0; + cp_current_changed <= 0; + cp_current_done_q <= 0; + //VCO signals reset + usr_vco_value <= 0; + vco_changed <= 0; + vco_done_q <= 0; + //DSM signals reset + usr_k_value <= 0; + dsm_k_changed <= 0; + dsm_k_done_q <= 0; + //N counter signals reset + usr_n_cnt_lo <= 0; + usr_n_cnt_hi <= 0; + usr_n_cnt_bypass_en <= 0; + usr_n_cnt_odd_duty_div_en <= 0; + n_cnt_changed <= 0; + n_cnt_done_q <= 0; + //M counter signals reset + usr_m_cnt_lo <= 0; + usr_m_cnt_hi <= 0; + usr_m_cnt_bypass_en <= 0; + usr_m_cnt_odd_duty_div_en <= 0; + m_cnt_changed <= 0; + m_cnt_done_q <= 0; + //C counter signals reset + usr_c_cnt_lo <= 0; + usr_c_cnt_hi <= 0; + usr_c_cnt_bypass_en <= 0; + usr_c_cnt_odd_duty_div_en <= 0; + any_c_cnt_changed <= 0; + all_c_cnt_done_q <= 0; + c_cnt_done_q <= 0; + //generic signals + dprio_start <= 0; + mif_start_assert <= 0; + dps_start_assert <= 0; + dprio_temp_m_n_c_readdata_1_q <= 0; + dprio_temp_m_n_c_readdata_2_q <= 0; + c_cnt_done_q <= 0; + //DPS signals + usr_up_dn <= 0; + usr_cnt_sel <= 0; + usr_num_shifts <= 0; + dps_changed <= 0; + //manual DPRIO signals + manual_dprio_changed <= 0; + usr_dprio_address <= 0; + usr_dprio_writedata_0 <= 0; + usr_r_w <= 0; + operation_address <= 0; + mif_reg_asserted <= 0; + mif_base_addr <= 0; + end + else + begin + if (dprio_temp_read_1) + begin + dprio_temp_m_n_c_readdata_1_q <= dprio_temp_m_n_c_readdata_1_d; + end + if (dprio_temp_read_2) + begin + dprio_temp_m_n_c_readdata_2_q <= dprio_temp_m_n_c_readdata_2_d; + end + if ((dps_done)) dps_changed <= 0; + if (dsm_k_done_d) dsm_k_done_q <= dsm_k_done_d; + if (n_cnt_done_d) n_cnt_done_q <= n_cnt_done_d; + if (m_cnt_done_d) m_cnt_done_q <= m_cnt_done_d; + if (all_c_cnt_done_d) all_c_cnt_done_q <= all_c_cnt_done_d; + if (c_cnt_done_d != 0) c_cnt_done_q <= c_cnt_done_q | c_cnt_done_d; + if (bwctrl_done_d) bwctrl_done_q <= bwctrl_done_d; + if (cp_current_done_d) cp_current_done_q <= cp_current_done_d; + if (vco_done_d) vco_done_q <= vco_done_d; + if (manual_dprio_done_d) manual_dprio_done_q <= manual_dprio_done_d; + + if (mif_start_out == 1'b1) + mif_start_assert <= 0; // Signaled MIF block to start, so deassert on next cycle + + if (dps_done != 1'b1) + dps_start_assert <= 0; // DPS has started, so dessert its start signal on next cycle + + if (dprio_next_state == ONE) + dprio_start <= 0; + if (dprio_write_done) + begin + bwctrl_done_q <= 0; + cp_current_done_q <= 0; + vco_done_q <= 0; + dsm_k_done_q <= 0; + dsm_k_done_q <= 0; + n_cnt_done_q <= 0; + m_cnt_done_q <= 0; + all_c_cnt_done_q <= 0; + c_cnt_done_q <= 0; + dsm_k_changed <= 0; + n_cnt_changed <= 0; + m_cnt_changed <= 0; + any_c_cnt_changed <= 0; + bwctrl_changed <= 0; + cp_current_changed <= 0; + vco_changed <= 0; + manual_dprio_changed <= 0; + manual_dprio_done_q <= 0; + if (dps_changed | dps_changed_valid | !dps_done ) + begin + usr_cnt_sel <= usr_cnt_sel; + end + else + begin + usr_cnt_sel <= 0; + end + mif_reg_asserted <= 0; + end + else + begin + dsm_k_changed <= dsm_k_changed; + n_cnt_changed <= n_cnt_changed; + m_cnt_changed <= m_cnt_changed; + any_c_cnt_changed <= any_c_cnt_changed; + manual_dprio_changed <= manual_dprio_changed; + mif_reg_asserted <= mif_reg_asserted; + usr_cnt_sel <= usr_cnt_sel; + end + + + if(slave_write & !slave_waitrequest) + begin + case(slave_address) + //read in the values here from the user and act on them + DSM_REG: + begin + operation_address <= DSM_REG; + usr_k_value <= slave_writedata[31:0]; + dsm_k_changed <= 1'b1; + dsm_k_done_q <= 0; + dprio_start <= 1'b1; + end + N_REG: + begin + operation_address <= N_REG; + usr_n_cnt_lo <= slave_writedata[7:0]; + usr_n_cnt_hi <= slave_writedata[15:8]; + usr_n_cnt_bypass_en <= slave_writedata[16]; + usr_n_cnt_odd_duty_div_en <= slave_writedata[17]; + n_cnt_changed <= 1'b1; + n_cnt_done_q <= 0; + dprio_start <= 1'b1; + end + M_REG: + begin + operation_address <= M_REG; + usr_m_cnt_lo <= slave_writedata[7:0]; + usr_m_cnt_hi <= slave_writedata[15:8]; + usr_m_cnt_bypass_en <= slave_writedata[16]; + usr_m_cnt_odd_duty_div_en <= slave_writedata[17]; + m_cnt_changed <= 1'b1; + m_cnt_done_q <= 0; + dprio_start <= 1'b1; + end + DPS_REG: + begin + operation_address <= DPS_REG; + usr_num_shifts <= slave_writedata[15:0]; + usr_cnt_sel <= slave_writedata[20:16]; + usr_up_dn <= slave_writedata[21]; + dps_changed <= 1; + dps_start_assert <= 1; + end + C_COUNTERS_REG: + begin + operation_address <= C_COUNTERS_REG; + usr_c_cnt_lo <= slave_writedata[7:0]; + usr_c_cnt_hi <= slave_writedata[15:8]; + usr_c_cnt_bypass_en <= slave_writedata[16]; + usr_c_cnt_odd_duty_div_en <= slave_writedata[17]; + usr_cnt_sel <= slave_writedata[22:18]; + any_c_cnt_changed <= 1'b1; + all_c_cnt_done_q <= 0; + dprio_start <= 1'b1; + end + BWCTRL_REG: + begin + usr_bwctrl_value <= slave_writedata[3:0]; + bwctrl_changed <= 1'b1; + bwctrl_done_q <= 0; + dprio_start <= 1'b1; + operation_address <= BWCTRL_REG; + end + CP_CURRENT_REG: + begin + usr_cp_current_value <= slave_writedata[2:0]; + cp_current_changed <= 1'b1; + cp_current_done_q <= 0; + dprio_start <= 1'b1; + operation_address <= CP_CURRENT_REG; + end + VCO_REG: + begin + usr_vco_value <= slave_writedata[0]; + vco_changed <= 1'b1; + vco_done_q <= 0; + dprio_start <= 1'b1; + operation_address <= VCO_REG; + end + ANY_DPRIO: + begin + operation_address <= ANY_DPRIO; + manual_dprio_changed <= 1'b1; + usr_dprio_address <= slave_writedata[5:0]; + usr_dprio_writedata_0 <= slave_writedata[21:6]; + usr_r_w <= slave_writedata[22]; + manual_dprio_done_q <= 0; + dprio_start <= 1'b1; + end + MIF_REG: + begin + mif_reg_asserted <= 1'b1; + mif_base_addr <= slave_writedata[ROM_ADDR_WIDTH-1:0]; + mif_start_assert <= 1'b1; + end + endcase + end + end + end + //C Counter assigning values to the 2-d array of values for each C counter + + reg [4:0] j; + always @(posedge clk) + begin + + if (reset) + begin + c_cnt_changed[17:0] <= 0; + for (j = 0; j < number_of_counters; j = j + 1'b1) + begin : c_cnt_reset + temp_c_cnt_bypass_en[j] <= 0; + temp_c_cnt_odd_duty_div_en[j] <= 0; + temp_c_cnt_lo[j][7:0] <= 0; + temp_c_cnt_hi[j][7:0] <= 0; + end + end + else + begin + if (dprio_write_done) + begin + c_cnt_changed <= 0; + end + if (any_c_cnt_changed && (operation_address == C_COUNTERS_REG)) + begin + case (cnt_sel) + CNT_0: + begin + temp_c_cnt_lo [0] <= usr_c_cnt_lo; + temp_c_cnt_hi [0] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [0] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [0] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [0] <= 1'b1; + end + CNT_1: + begin + temp_c_cnt_lo [1] <= usr_c_cnt_lo; + temp_c_cnt_hi [1] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [1] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [1] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [1] <= 1'b1; + end + CNT_2: + begin + temp_c_cnt_lo [2] <= usr_c_cnt_lo; + temp_c_cnt_hi [2] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [2] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [2] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [2] <= 1'b1; + end + CNT_3: + begin + temp_c_cnt_lo [3] <= usr_c_cnt_lo; + temp_c_cnt_hi [3] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [3] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [3] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [3] <= 1'b1; + end + CNT_4: + begin + temp_c_cnt_lo [4] <= usr_c_cnt_lo; + temp_c_cnt_hi [4] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [4] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [4] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [4] <= 1'b1; + end + CNT_5: + begin + temp_c_cnt_lo [5] <= usr_c_cnt_lo; + temp_c_cnt_hi [5] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [5] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [5] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [5] <= 1'b1; + end + CNT_6: + begin + temp_c_cnt_lo [6] <= usr_c_cnt_lo; + temp_c_cnt_hi [6] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [6] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [6] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [6] <= 1'b1; + end + CNT_7: + begin + temp_c_cnt_lo [7] <= usr_c_cnt_lo; + temp_c_cnt_hi [7] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [7] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [7] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [7] <= 1'b1; + end + CNT_8: + begin + temp_c_cnt_lo [8] <= usr_c_cnt_lo; + temp_c_cnt_hi [8] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [8] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [8] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [8] <= 1'b1; + end + CNT_9: + begin + temp_c_cnt_lo [9] <= usr_c_cnt_lo; + temp_c_cnt_hi [9] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [9] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [9] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [9] <= 1'b1; + end + CNT_10: + begin + temp_c_cnt_lo [10] <= usr_c_cnt_lo; + temp_c_cnt_hi [10] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [10] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [10] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [10] <= 1'b1; + end + CNT_11: + begin + temp_c_cnt_lo [11] <= usr_c_cnt_lo; + temp_c_cnt_hi [11] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [11] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [11] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [11] <= 1'b1; + end + CNT_12: + begin + temp_c_cnt_lo [12] <= usr_c_cnt_lo; + temp_c_cnt_hi [12] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [12] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [12] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [12] <= 1'b1; + end + CNT_13: + begin + temp_c_cnt_lo [13] <= usr_c_cnt_lo; + temp_c_cnt_hi [13] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [13] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [13] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [13] <= 1'b1; + end + CNT_14: + begin + temp_c_cnt_lo [14] <= usr_c_cnt_lo; + temp_c_cnt_hi [14] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [14] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [14] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [14] <= 1'b1; + end + CNT_15: + begin + temp_c_cnt_lo [15] <= usr_c_cnt_lo; + temp_c_cnt_hi [15] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [15] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [15] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [15] <= 1'b1; + end + CNT_16: + begin + temp_c_cnt_lo [16] <= usr_c_cnt_lo; + temp_c_cnt_hi [16] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [16] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [16] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [16] <= 1'b1; + end + CNT_17: + begin + temp_c_cnt_lo [17] <= usr_c_cnt_lo; + temp_c_cnt_hi [17] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [17] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [17] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [17] <= 1'b1; + end + endcase + + end + end + end + + + //logic to handle which writes the user indicated and wants to start. + assign usr_valid_changes =dsm_k_changed| any_c_cnt_changed |n_cnt_changed | m_cnt_changed | dps_changed_valid |manual_dprio_changed |cp_current_changed|bwctrl_changed|vco_changed; + + + //start the reconfig operations by writing to the DPRIO + reg break_loop; + reg [4:0] i; + always @(*) + begin + dprio_temp_read_1 = 0; + dprio_temp_read_2 = 0; + dprio_temp_m_n_c_readdata_1_d = 0; + dprio_temp_m_n_c_readdata_2_d = 0; + break_loop = 0; + dprio_next_state = DPRIO_IDLE; + avmm_dprio_write = 0; + avmm_dprio_read = 0; + avmm_dprio_address = 0; + avmm_dprio_writedata = 0; + avmm_dprio_byteen = 0; + dprio_write_done = 1; + manual_dprio_done_d = 0; + n_cnt_done_d = 0; + dsm_k_done_d = 0; + dsm_k_ready_false_done_d = 0; + m_cnt_done_d = 0; + c_cnt_done_d[17:0] = 0; + all_c_cnt_done_d = 0; + bwctrl_done_d = 0; + cp_current_done_d = 0; + vco_done_d = 0; + i = 0; + + // Deassert dprio_write_done so it doesn't reset mif_reg_asserted (toggled writes) + if (dprio_start | mif_start_assert) + dprio_write_done = 0; + + if (current_state == WAIT_ON_LOCK) + begin + case (dprio_cur_state) + ONE: + begin + if (n_cnt_changed & !n_cnt_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + dprio_next_state = TWO; + avmm_dprio_address = N_CNT_DIV_ADDR; + avmm_dprio_writedata[7:0] = usr_n_cnt_lo; + avmm_dprio_writedata[15:8] = usr_n_cnt_hi; + end + else if (m_cnt_changed & !m_cnt_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + dprio_next_state = TWO; + avmm_dprio_address = M_CNT_DIV_ADDR; + avmm_dprio_writedata[7:0] = usr_m_cnt_lo; + avmm_dprio_writedata[15:8] = usr_m_cnt_hi; + end + else if (any_c_cnt_changed & !all_c_cnt_done_q) + begin + + for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) + begin : c_cnt_write_hilo + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + dprio_write_done = 0; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + dprio_next_state = TWO; + if (fpll_1) avmm_dprio_address = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - i; + else avmm_dprio_address = C_CNT_0_DIV_ADDR + i; + avmm_dprio_writedata[7:0] = temp_c_cnt_lo[i]; + avmm_dprio_writedata[15:8] = temp_c_cnt_hi[i]; + //To break from the loop, since only one counter + //is addressed at a time + break_loop = 1'b1; + end + end + end + else if (dsm_k_changed & !dsm_k_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 0; + dprio_next_state = TWO; + end + else if (bwctrl_changed & !bwctrl_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 0; + dprio_next_state = TWO; + end + else if (cp_current_changed & !cp_current_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 0; + dprio_next_state = TWO; + end + else if (vco_changed & !vco_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 0; + dprio_next_state = TWO; + end + else if (manual_dprio_changed & !manual_dprio_done_q) + begin + dprio_write_done = 0; + avmm_dprio_byteen = 2'b11; + dprio_next_state = TWO; + avmm_dprio_write = usr_r_w; + avmm_dprio_address = usr_dprio_address; + avmm_dprio_writedata[15:0] = usr_dprio_writedata_0; + end + else dprio_next_state = DPRIO_IDLE; + end + + TWO: + begin + //handle reading the two setting bits on n_cnt, then + //writing them back while preserving other bits. + //Issue two consecutive reads then wait; readLatency=3 + dprio_write_done = 0; + dprio_next_state = THREE; + avmm_dprio_byteen = 2'b11; + avmm_dprio_read = 1'b1; + if (n_cnt_changed & !n_cnt_done_q) + begin + avmm_dprio_address = N_CNT_BYPASS_EN_ADDR; + end + else if (m_cnt_changed & !m_cnt_done_q) + begin + avmm_dprio_address = M_CNT_BYPASS_EN_ADDR; + end + + else if (any_c_cnt_changed & !all_c_cnt_done_q) + begin + for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) + begin : c_cnt_read_bypass + if (fpll_1) + begin + if (i > 13) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; + break_loop = 1'b1; + end + end + end + else + begin + if (i < 4) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; + break_loop = 1'b1; + end + end + end + end + end + //reading the K ready 16 bit word. Need to write 0 to it + //afterwards to indicate that K has not been done writing + else if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_address = DSM_K_READY_ADDR; + dprio_next_state = FOUR; + end + else if (bwctrl_changed & !bwctrl_done_q) + begin + avmm_dprio_address = BWCTRL_ADDR; + dprio_next_state = FOUR; + end + else if (cp_current_changed & !cp_current_done_q) + begin + avmm_dprio_address = CP_CURRENT_ADDR; + dprio_next_state = FOUR; + end + else if (vco_changed & !vco_done_q) + begin + avmm_dprio_address = VCO_ADDR; + dprio_next_state = FOUR; + end + else if (manual_dprio_changed & !manual_dprio_done_q) + begin + avmm_dprio_read = ~usr_r_w; + avmm_dprio_address = usr_dprio_address; + dprio_next_state = DPRIO_DONE; + end + else dprio_next_state = DPRIO_IDLE; + end + THREE: + begin + dprio_write_done = 0; + avmm_dprio_byteen = 2'b11; + avmm_dprio_read = 1'b1; + dprio_next_state = FOUR; + if (n_cnt_changed & !n_cnt_done_q) + begin + avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR; + end + else if (m_cnt_changed & !m_cnt_done_q) + begin + avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR; + end + else if (any_c_cnt_changed & !all_c_cnt_done_q) + begin + for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) + begin : c_cnt_read_odd_div + if (fpll_1) + begin + if (i > 13) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; + break_loop = 1'b1; + end + end + end + else + begin + if (i < 4) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; + break_loop = 1'b1; + end + end + end + end + end + else dprio_next_state = DPRIO_IDLE; + end + FOUR: + begin + dprio_temp_read_1 = 1'b1; + dprio_write_done = 0; + if (vco_changed|cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed) + begin + dprio_temp_m_n_c_readdata_1_d = dprio_readdata; + dprio_next_state = FIVE; + end + else dprio_next_state = DPRIO_IDLE; + end + FIVE: + begin + dprio_write_done = 0; + dprio_temp_read_2 = 1'b1; + if (vco_changed|cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed) + begin + //this is where DSM ready value comes. + //Need to store in a register to be used later + dprio_temp_m_n_c_readdata_2_d = dprio_readdata; + dprio_next_state = SIX; + end + else dprio_next_state = DPRIO_IDLE; + end + SIX: + begin + dprio_write_done = 0; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + dprio_next_state = SEVEN; + avmm_dprio_writedata = dprio_temp_m_n_c_readdata_1_q; + if (n_cnt_changed & !n_cnt_done_q) + begin + avmm_dprio_address = N_CNT_BYPASS_EN_ADDR; + avmm_dprio_writedata[5] = usr_n_cnt_bypass_en; + end + else if (m_cnt_changed & !m_cnt_done_q) + begin + avmm_dprio_address = M_CNT_BYPASS_EN_ADDR; + avmm_dprio_writedata[4] = usr_m_cnt_bypass_en; + end + else if (any_c_cnt_changed & !all_c_cnt_done_q) + begin + for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) + begin : c_cnt_write_bypass + if (fpll_1) + begin + if (i > 13) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; + avmm_dprio_writedata[i-14] = temp_c_cnt_bypass_en[i]; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; + avmm_dprio_writedata[i] = temp_c_cnt_bypass_en[i]; + break_loop = 1'b1; + end + end + end + else + begin + if (i < 4) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; + avmm_dprio_writedata[3-i] = temp_c_cnt_bypass_en[i]; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; + avmm_dprio_writedata[17-i] = temp_c_cnt_bypass_en[i]; + break_loop = 1'b1; + end + end + end + end + end + else if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_write = 0; + end + else if (bwctrl_changed & !bwctrl_done_q) + begin + avmm_dprio_write = 0; + end + else if (cp_current_changed & !cp_current_done_q) + begin + avmm_dprio_write = 0; + end + else if (vco_changed & !vco_done_q) + begin + avmm_dprio_write = 0; + end + else dprio_next_state = DPRIO_IDLE; + end + SEVEN: + begin + dprio_write_done = 0; + dprio_next_state = EIGHT; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q; + if (n_cnt_changed & !n_cnt_done_q) + begin + avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[5] = usr_n_cnt_odd_duty_div_en; + n_cnt_done_d = 1'b1; + end + else if (m_cnt_changed & !m_cnt_done_q) + begin + avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[4] = usr_m_cnt_odd_duty_div_en; + m_cnt_done_d = 1'b1; + end + + else if (any_c_cnt_changed & !all_c_cnt_done_q) + begin + for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) + begin : c_cnt_write_odd_div + if (fpll_1) + begin + if (i > 13) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[i-14] = temp_c_cnt_odd_duty_div_en[i]; + c_cnt_done_d[i] = 1'b1; + //have to OR the signals to prevent + //overwriting of previous dones + c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[i] = temp_c_cnt_odd_duty_div_en[i]; + c_cnt_done_d[i] = 1'b1; + c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; + break_loop = 1'b1; + end + end + end + else + begin + if (i < 4) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[3-i] = temp_c_cnt_odd_duty_div_en[i]; + c_cnt_done_d[i] = 1'b1; + //have to OR the signals to prevent + //overwriting of previous dones + c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[17-i] = temp_c_cnt_odd_duty_div_en[i]; + c_cnt_done_d[i] = 1'b1; + c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; + break_loop = 1'b1; + end + end + end + end + end + else if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_address = DSM_K_READY_ADDR; + avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b0; + dsm_k_ready_false_done_d = 1'b1; + end + else if (bwctrl_changed & !bwctrl_done_q) + begin + avmm_dprio_address = BWCTRL_ADDR; + avmm_dprio_writedata[3:0] = usr_bwctrl_value; + bwctrl_done_d = 1'b1; + end + else if (cp_current_changed & !cp_current_done_q) + begin + avmm_dprio_address = CP_CURRENT_ADDR; + avmm_dprio_writedata[2:0] = usr_cp_current_value; + cp_current_done_d = 1'b1; + end + else if (vco_changed & !vco_done_q) + begin + avmm_dprio_address = VCO_ADDR; + avmm_dprio_writedata[8] = usr_vco_value; + vco_done_d = 1'b1; + end + + + //if all C_cnt that were changed are done, then assert all_c_cnt_done + if (c_cnt_done_d == c_cnt_changed) + all_c_cnt_done_d = 1'b1; + if (n_cnt_changed & n_cnt_done_d) + dprio_next_state = DPRIO_DONE; + if (any_c_cnt_changed & !all_c_cnt_done_d & !all_c_cnt_done_q) + dprio_next_state = ONE; + else if (m_cnt_changed & !m_cnt_done_d & !m_cnt_done_q) + dprio_next_state = ONE; + else if (dsm_k_changed & !dsm_k_ready_false_done_d) + dprio_next_state = TWO; + else if (dsm_k_changed & !dsm_k_done_q) + dprio_next_state = EIGHT; + else if (bwctrl_changed & !bwctrl_done_d) + dprio_next_state = TWO; + else if (cp_current_changed & !cp_current_done_d) + dprio_next_state = TWO; + else if (vco_changed & !vco_done_d) + dprio_next_state = TWO; + else + begin + dprio_next_state = DPRIO_DONE; + dprio_write_done = 1'b1; + end + end + //finish the rest of the DSM reads/writes + //writing k value, writing k_ready to 1. + EIGHT: + begin + dprio_write_done = 0; + dprio_next_state = NINE; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_0; + avmm_dprio_writedata[15:0] = usr_k_value[15:0]; + end + end + NINE: + begin + dprio_write_done = 0; + dprio_next_state = TEN; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_1; + avmm_dprio_writedata[15:0] = usr_k_value[31:16]; + end + end + TEN: + begin + dprio_write_done = 0; + dprio_next_state = ONE; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_address = DSM_K_READY_ADDR; + //already have the readdata for DSM_K_READY_ADDR since we read it + //earlier. Just reuse here + avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q; + avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b1; + dsm_k_done_d = 1'b1; + end + end + DPRIO_DONE: + begin + dprio_write_done = 1'b1; + if (dprio_start) dprio_next_state = DPRIO_IDLE; + else dprio_next_state = DPRIO_DONE; + end + DPRIO_IDLE: + begin + if (dprio_start) dprio_next_state = ONE; + else dprio_next_state = DPRIO_IDLE; + end + default: dprio_next_state = 4'bxxxx; + endcase + end + + end + + + //assert the waitreq signal according to the state of the slave + assign slave_waitrequest = (slave_mode==mode_WR) ? ((locked === 1'b1) ? (((current_state==WAIT_ON_LOCK) & !dprio_write_done) | !dps_done |reset|!dprio_init_done) : 1'b1) : 1'b0; + + // Read operations + always @(*) + begin + status = 0; + if (slave_mode == mode_POLL) + //asserting status to 1 if the slave is done. + status = (current_state == LOCKED); + end + //************************************************************// + //************************************************************// + //******************** READ STATE MACHINE ********************// + //************************************************************// + //************************************************************// + reg [1:0] current_read_state; + reg [1:0] next_read_state; + reg [5:0] slave_address_int_d; + reg [5:0] slave_address_int_q; + reg dprio_read_1; + reg [5:0] dprio_address_1; + reg [1:0] dprio_byteen_1; + reg [4:0] usr_cnt_sel_1; + localparam READ = 2'b00, READ_WAIT = 2'b01, READ_IDLE = 2'b10, READ_POST_WAIT = 2'b11; + + always @(*) + begin + if(next_read_state == READ_IDLE) + begin + read_waitrequest <= 1'b0; + end + else + begin + read_waitrequest <= 1'b1; + end + end + + always @(posedge clk) + begin + if (reset) + begin + current_read_state <= READ_IDLE; + slave_address_int_q <= 0; + slave_readdata_q <= 0; + end + else + begin + current_read_state <= next_read_state; + slave_address_int_q <= slave_address_int_d; + slave_readdata_q <= slave_readdata_d; + end + end + always @(*) + begin + dprio_read_1 = 0; + dprio_address_1 = 0; + dprio_byteen_1 = 0; + slave_address_int_d = 0; + slave_readdata_d = 0; + status_read = 0; + usr_cnt_sel_1 = 0; + case(current_read_state) + READ_IDLE: + begin + slave_address_int_d = 0; + next_read_state = READ_IDLE; + if ((current_state != WAIT_ON_LOCK) && slave_read) + begin + slave_address_int_d = slave_address; + if ((slave_address >= CNT_BASE) && (slave_address < CNT_BASE+18)) + begin + next_read_state = READ_WAIT; + dprio_byteen_1 = 2'b11; + dprio_read_1 = 1'b1; + usr_cnt_sel_1 = (slave_address[4:0] - CNT_BASE); + if (fpll_1) dprio_address_1 = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - cnt_sel; + else dprio_address_1 = C_CNT_0_DIV_ADDR + cnt_sel; + end + else + begin + case (slave_address) + MODE_REG: + begin + next_read_state = READ_WAIT; + slave_readdata_d = slave_mode; + end + STATUS_REG: + begin + next_read_state = READ_WAIT; + status_read = 1'b1; + slave_readdata_d = status; + end + N_REG: + begin + dprio_byteen_1 = 2'b11; + dprio_read_1 = 1'b1; + dprio_address_1 = N_CNT_DIV_ADDR; + next_read_state = READ_WAIT; + end + M_REG: + begin + dprio_byteen_1 = 2'b11; + dprio_read_1 = 1'b1; + dprio_address_1 = M_CNT_DIV_ADDR; + next_read_state = READ_WAIT; + end + BWCTRL_REG: + begin + dprio_byteen_1 = 2'b11; + dprio_read_1 = 1'b1; + dprio_address_1 = BWCTRL_ADDR; + next_read_state = READ_WAIT; + end + CP_CURRENT_REG: + begin + dprio_byteen_1 = 2'b11; + dprio_read_1 = 1'b1; + dprio_address_1 = CP_CURRENT_ADDR; + next_read_state = READ_WAIT; + end + VCO_REG: + begin + dprio_byteen_1 = 2'b11; + dprio_read_1 = 1'b1; + dprio_address_1 = VCO_ADDR; + next_read_state = READ_WAIT; + end + ANY_DPRIO: + begin + dprio_byteen_1 = 2'b11; + dprio_read_1 = ~slave_writedata[22]; + dprio_address_1 = slave_writedata[5:0]; + next_read_state = READ_WAIT; + end + default : next_read_state = READ_IDLE; + endcase + end + end + else + next_read_state = READ_IDLE; + end + READ_WAIT: + begin + next_read_state = READ; + slave_address_int_d = slave_address_int_q; + case (slave_address_int_q) + MODE_REG: + begin + slave_readdata_d = slave_readdata_q; + end + STATUS_REG: + begin + slave_readdata_d = slave_readdata_q; + end + endcase + end + READ: + begin + next_read_state = READ_POST_WAIT; + slave_address_int_d = slave_address_int_q; + slave_readdata_d = dprio_readdata; + case (slave_address_int_q) + MODE_REG: + begin + slave_readdata_d = slave_readdata_q; + end + STATUS_REG: + begin + slave_readdata_d = slave_readdata_q; + end + BWCTRL_REG: + begin + slave_readdata_d = dprio_readdata[3:0]; + end + CP_CURRENT_REG: + begin + slave_readdata_d = dprio_readdata[2:0]; + end + VCO_REG: + begin + slave_readdata_d = dprio_readdata[8]; + end + ANY_DPRIO: + begin + slave_readdata_d = dprio_readdata; + end + endcase + end + READ_POST_WAIT: + begin + next_read_state = READ_IDLE; + end + default: next_read_state = 2'bxx; + endcase + end + + + dyn_phase_shift dyn_phase_shift_inst ( + .clk(clk), + .reset(reset), + .phase_done(phase_done), + .pll_start_valid(pll_start_valid), + .dps_changed(dps_changed), + .dps_changed_valid(dps_changed_valid), + .dprio_write_done(dprio_write_done), + .usr_num_shifts(usr_num_shifts), + .usr_cnt_sel(usr_cnt_sel|usr_cnt_sel_1), + .usr_up_dn(usr_up_dn), + .locked(locked), + .dps_done(dps_done), + .phase_en(phase_en), + .up_dn(up_dn), + .cnt_sel(cnt_sel)); + defparam dyn_phase_shift_inst.device_family = device_family; + + assign dprio_clk = clk; + self_reset self_reset_inst (mgmt_reset, clk, reset, dprio_init_reset); + + dprio_mux dprio_mux_inst ( + .init_dprio_address(init_dprio_address), + .init_dprio_read(init_dprio_read), + .init_dprio_byteen(init_dprio_byteen), + .init_dprio_write(init_dprio_write), + .init_dprio_writedata(init_dprio_writedata), + + + .init_atpgmode(init_atpgmode), + .init_mdio_dis(init_mdio_dis), + .init_scanen(init_scanen), + .init_ser_shift_load(init_ser_shift_load), + .dprio_init_done(dprio_init_done), + + // Inputs from avmm master + .avmm_dprio_address(avmm_dprio_address | dprio_address_1), + .avmm_dprio_read(avmm_dprio_read | dprio_read_1), + .avmm_dprio_byteen(avmm_dprio_byteen | dprio_byteen_1), + .avmm_dprio_write(avmm_dprio_write), + .avmm_dprio_writedata(avmm_dprio_writedata), + + .avmm_atpgmode(avmm_atpgmode), + .avmm_mdio_dis(avmm_mdio_dis), + .avmm_scanen(avmm_scanen), + + // Outputs to fpll + .dprio_address(dprio_address), + .dprio_read(dprio_read), + .dprio_byteen(dprio_byteen), + .dprio_write(dprio_write), + .dprio_writedata(dprio_writedata), + + .atpgmode(dprio_atpgmode), + .mdio_dis(dprio_mdio_dis), + .scanen(dprio_scanen), + .ser_shift_load(dprio_ser_shift_load) + ); + + + fpll_dprio_init fpll_dprio_init_inst ( + .clk(clk), + .reset_n(~reset), + .locked(locked), + + //outputs + .dprio_address(init_dprio_address), + .dprio_read(init_dprio_read), + .dprio_byteen(init_dprio_byteen), + .dprio_write(init_dprio_write), + .dprio_writedata(init_dprio_writedata), + + .atpgmode(init_atpgmode), + .mdio_dis(init_mdio_dis), + .scanen(init_scanen), + .ser_shift_load(init_ser_shift_load), + .dprio_init_done(dprio_init_done)); + + //address luts, to be reconfigged by the Fitter + //FPLL_1 or 0 address lut + generic_lcell_comb lcell_fpll_0_1 ( + .dataa(1'b0), + .combout (fpll_1)); + defparam lcell_fpll_0_1.lut_mask = 64'hAAAAAAAAAAAAAAAA; + defparam lcell_fpll_0_1.dont_touch = "on"; + defparam lcell_fpll_0_1.family = device_family; + + + wire dprio_read_combout; + generic_lcell_comb lcell_dprio_read ( + .dataa(fpll_1), + .datab(dprio_read), + .datac(1'b0), + .datad(1'b0), + .datae(1'b0), + .dataf(1'b0), + .combout (dprio_read_combout)); + defparam lcell_dprio_read.lut_mask = 64'hCCCCCCCCCCCCCCCC; + defparam lcell_dprio_read.dont_touch = "on"; + defparam lcell_dprio_read.family = device_family; + + + + + + //assign reconfig_to_pll signals + assign reconfig_to_pll[0] = dprio_clk; + assign reconfig_to_pll[1] = ~dprio_init_reset; + assign reconfig_to_pll[2] = dprio_write; + assign reconfig_to_pll[3] = dprio_read_combout; + assign reconfig_to_pll[9:4] = dprio_address; + assign reconfig_to_pll[25:10] = dprio_writedata; + assign reconfig_to_pll[27:26] = dprio_byteen; + assign reconfig_to_pll[28] = dprio_ser_shift_load; + assign reconfig_to_pll[29] = dprio_mdio_dis; + assign reconfig_to_pll[30] = phase_en; + assign reconfig_to_pll[31] = up_dn; + assign reconfig_to_pll[36:32] = cnt_sel; + assign reconfig_to_pll[37] = dprio_scanen; + assign reconfig_to_pll[38] = dprio_atpgmode; + //assign reconfig_to_pll[40:37] = clken; + assign reconfig_to_pll[63:39] = 0; + + //assign reconfig_from_pll signals + assign dprio_readdata = reconfig_from_pll [15:0]; + assign locked_orig = reconfig_from_pll [16]; + assign phase_done = reconfig_from_pll [17]; + +endmodule +module self_reset (input wire mgmt_reset, input wire clk, output wire reset, output wire init_reset); + + localparam RESET_COUNTER_VALUE = 3'd2; + localparam INITIAL_WAIT_VALUE = 9'd340; + reg [9:0]counter; + reg local_reset; + reg usr_mode_init_wait; + initial + begin + local_reset = 1'b1; + counter = 0; + usr_mode_init_wait = 0; + end + + always @(posedge clk) + begin + if (mgmt_reset) + begin + counter <= 0; + end + else + begin + if (!usr_mode_init_wait) + begin + if (counter == INITIAL_WAIT_VALUE) + begin + local_reset <= 0; + usr_mode_init_wait <= 1'b1; + counter <= 0; + end + else + begin + counter <= counter + 1'b1; + end + end + else + begin + if (counter == RESET_COUNTER_VALUE) + local_reset <= 0; + else + counter <= counter + 1'b1; + end + end + end + assign reset = mgmt_reset | local_reset; + assign init_reset = local_reset; +endmodule + +module dprio_mux ( + // Inputs from init block + input [ 5:0] init_dprio_address, + input init_dprio_read, + input [ 1:0] init_dprio_byteen, + input init_dprio_write, + input [15:0] init_dprio_writedata, + + input init_atpgmode, + input init_mdio_dis, + input init_scanen, + input init_ser_shift_load, + input dprio_init_done, + + // Inputs from avmm master + input [ 5:0] avmm_dprio_address, + input avmm_dprio_read, + input [ 1:0] avmm_dprio_byteen, + input avmm_dprio_write, + input [15:0] avmm_dprio_writedata, + + input avmm_atpgmode, + input avmm_mdio_dis, + input avmm_scanen, + input avmm_ser_shift_load, + + // Outputs to fpll + output [ 5:0] dprio_address, + output dprio_read, + output [ 1:0] dprio_byteen, + output dprio_write, + output [15:0] dprio_writedata, + + output atpgmode, + output mdio_dis, + output scanen, + output ser_shift_load +); + + assign dprio_address = dprio_init_done ? avmm_dprio_address : init_dprio_address; + assign dprio_read = dprio_init_done ? avmm_dprio_read : init_dprio_read; + assign dprio_byteen = dprio_init_done ? avmm_dprio_byteen : init_dprio_byteen; + assign dprio_write = dprio_init_done ? avmm_dprio_write : init_dprio_write; + assign dprio_writedata = dprio_init_done ? avmm_dprio_writedata : init_dprio_writedata; + + assign atpgmode = init_atpgmode; + assign scanen = init_scanen; + assign mdio_dis = init_mdio_dis; + assign ser_shift_load = init_ser_shift_load ; +endmodule +module fpll_dprio_init ( + input clk, + input reset_n, + input locked, + + output [ 5:0] dprio_address, + output dprio_read, + output [ 1:0] dprio_byteen, + output dprio_write, + output [15:0] dprio_writedata, + + output reg atpgmode, + output reg mdio_dis, + output reg scanen, + output reg ser_shift_load, + output reg dprio_init_done +); + + reg [1:0] rst_n = 2'b00; + reg [6:0] count = 7'd0; + reg init_done_forever; + + // Internal versions of control signals + wire int_mdio_dis; + wire int_ser_shift_load; + wire int_dprio_init_done; + wire int_atpgmode/*synthesis keep*/; + wire int_scanen/*synthesis keep*/; + + + assign dprio_address = count[6] ? 5'b0 : count[5:0] ; + assign dprio_byteen = 2'b11; // always enabled + assign dprio_write = ~count[6] & reset_n ; // write for first 64 cycles + assign dprio_read = 1'b0; + assign dprio_writedata = 16'd0; + + assign int_ser_shift_load = count[6] ? |count[2:1] : 1'b1; + assign int_mdio_dis = count[6] ? ~count[2] : 1'b1; + assign int_dprio_init_done = ~init_done_forever ? (count[6] ? &count[2:0] : 1'b0) + : 1'b1; + assign int_atpgmode = 0; + assign int_scanen = 0; + + initial begin + count = 7'd0; + init_done_forever = 0; + mdio_dis = 1'b1; + ser_shift_load = 1'b1; + dprio_init_done = 1'b0; + scanen = 1'b0; + atpgmode = 1'b0; + end + + // reset synch. + always @(posedge clk or negedge reset_n) + if(!reset_n) rst_n <= 2'b00; + else rst_n <= {rst_n[0],1'b1}; + + // counter + always @(posedge clk) + begin + if (!rst_n[1]) + init_done_forever <= 1'b0; + else + begin + if (count[6] && &count[1:0]) + init_done_forever <= 1'b1; + end + end + always @(posedge clk or negedge rst_n[1]) + begin + if(!rst_n[1]) + begin + count <= 7'd0; + end + else if(~int_dprio_init_done) + begin + count <= count + 7'd1; + end + else + begin + count <= count; + end + end + + // outputs + always @(posedge clk) begin + mdio_dis <= int_mdio_dis; + ser_shift_load <= int_ser_shift_load; + dprio_init_done <= int_dprio_init_done; + atpgmode <= int_atpgmode; + scanen <= int_scanen; + end + +endmodule +module dyn_phase_shift +#( + parameter device_family = "Stratix V" +) ( + + input wire clk, + input wire reset, + input wire phase_done, + input wire pll_start_valid, + input wire dps_changed, + input wire dprio_write_done, + input wire [15:0] usr_num_shifts, + input wire [4:0] usr_cnt_sel, + input wire usr_up_dn, + input wire locked, + + //output + output wire dps_done, + output reg phase_en, + output wire up_dn, + output wire dps_changed_valid, + output wire [4:0] cnt_sel); + + + + reg first_phase_shift_d; + reg first_phase_shift_q; + reg [15:0] phase_en_counter; + reg [3:0] dps_current_state; + reg [3:0] dps_next_state; + localparam DPS_START = 4'd0, DPS_WAIT_PHASE_DONE = 4'd1, DPS_DONE = 4'd2, DPS_WAIT_PHASE_EN = 4'd3, DPS_WAIT_DPRIO_WRITING = 4'd4, DPS_CHANGED = 4'd5; + localparam PHASE_EN_WAIT_COUNTER = 5'd1; + + reg [15:0] shifts_done_counter; + reg phase_done_final; + wire gnd /*synthesis keep*/; + + //fsm + //always block controlling the state regs + always @(posedge clk) + begin + if (reset) + begin + dps_current_state <= DPS_DONE; + end + else + begin + dps_current_state <= dps_next_state; + end + end + //the combinational part. assigning the next state + //this turns on the phase_done_final signal when phase_done does this: + //_____ ______ + // |______| + always @(*) + begin + phase_done_final = 0; + first_phase_shift_d = 0; + phase_en = 0; + dps_next_state = DPS_DONE; + case (dps_current_state) + DPS_START: + begin + phase_en = 1'b1; + dps_next_state = DPS_WAIT_PHASE_EN; + end + DPS_WAIT_PHASE_EN: + begin + phase_en = 1'b1; + if (first_phase_shift_q) + begin + first_phase_shift_d = 1'b1; + dps_next_state = DPS_WAIT_PHASE_EN; + end + else + begin + if (phase_en_counter == PHASE_EN_WAIT_COUNTER) + dps_next_state = DPS_WAIT_PHASE_DONE; + else dps_next_state = DPS_WAIT_PHASE_EN; + end + end + DPS_WAIT_PHASE_DONE: + begin + if (!phase_done | !locked) + begin + dps_next_state = DPS_WAIT_PHASE_DONE; + end + else + begin + if ((usr_num_shifts != shifts_done_counter) & (usr_num_shifts != 0)) + begin + dps_next_state = DPS_START; + phase_done_final = 1'b1; + end + else + begin + dps_next_state = DPS_DONE; + end + + end + end + DPS_DONE: + begin + phase_done_final = 0; + if (dps_changed) + dps_next_state = DPS_CHANGED; + else dps_next_state = DPS_DONE; + + end + DPS_CHANGED: + begin + if (pll_start_valid) + dps_next_state = DPS_WAIT_DPRIO_WRITING; + else + dps_next_state = DPS_CHANGED; + end + DPS_WAIT_DPRIO_WRITING: + begin + if (dprio_write_done) + dps_next_state = DPS_START; + else + dps_next_state = DPS_WAIT_DPRIO_WRITING; + end + + default: dps_next_state = 4'bxxxx; + endcase + + + end + + always @(posedge clk) + begin + + + if (dps_current_state == DPS_WAIT_PHASE_DONE) + phase_en_counter <= 0; + else if (dps_current_state == DPS_WAIT_PHASE_EN) + phase_en_counter <= phase_en_counter + 1'b1; + + if (reset) + begin + phase_en_counter <= 0; + shifts_done_counter <= 1'b1; + first_phase_shift_q <= 1; + end + else + begin + if (first_phase_shift_d) + first_phase_shift_q <= 0; + if (dps_done) + begin + shifts_done_counter <= 1'b1; + end + else + begin + if (phase_done_final & (dps_next_state!= DPS_DONE)) + shifts_done_counter <= shifts_done_counter + 1'b1; + else + shifts_done_counter <= shifts_done_counter; + end + end + end + + assign dps_changed_valid = (dps_current_state == DPS_CHANGED); + assign dps_done =(dps_current_state == DPS_DONE) | (dps_current_state == DPS_CHANGED); + assign up_dn = usr_up_dn; + assign gnd = 1'b0; + + //cnt select luts (5) + generic_lcell_comb lcell_cnt_sel_0 ( + .dataa(usr_cnt_sel[0]), + .datab(usr_cnt_sel[1]), + .datac(usr_cnt_sel[2]), + .datad(usr_cnt_sel[3]), + .datae(usr_cnt_sel[4]), + .dataf(gnd), + .combout (cnt_sel[0])); + defparam lcell_cnt_sel_0.lut_mask = 64'hAAAAAAAAAAAAAAAA; + defparam lcell_cnt_sel_0.dont_touch = "on"; + defparam lcell_cnt_sel_0.family = device_family; + generic_lcell_comb lcell_cnt_sel_1 ( + .dataa(usr_cnt_sel[0]), + .datab(usr_cnt_sel[1]), + .datac(usr_cnt_sel[2]), + .datad(usr_cnt_sel[3]), + .datae(usr_cnt_sel[4]), + .dataf(gnd), + .combout (cnt_sel[1])); + defparam lcell_cnt_sel_1.lut_mask = 64'hCCCCCCCCCCCCCCCC; + defparam lcell_cnt_sel_1.dont_touch = "on"; + defparam lcell_cnt_sel_1.family = device_family; + generic_lcell_comb lcell_cnt_sel_2 ( + .dataa(usr_cnt_sel[0]), + .datab(usr_cnt_sel[1]), + .datac(usr_cnt_sel[2]), + .datad(usr_cnt_sel[3]), + .datae(usr_cnt_sel[4]), + .dataf(gnd), + .combout (cnt_sel[2])); + defparam lcell_cnt_sel_2.lut_mask = 64'hF0F0F0F0F0F0F0F0; + defparam lcell_cnt_sel_2.dont_touch = "on"; + defparam lcell_cnt_sel_2.family = device_family; + generic_lcell_comb lcell_cnt_sel_3 ( + .dataa(usr_cnt_sel[0]), + .datab(usr_cnt_sel[1]), + .datac(usr_cnt_sel[2]), + .datad(usr_cnt_sel[3]), + .datae(usr_cnt_sel[4]), + .dataf(gnd), + .combout (cnt_sel[3])); + defparam lcell_cnt_sel_3.lut_mask = 64'hFF00FF00FF00FF00; + defparam lcell_cnt_sel_3.dont_touch = "on"; + defparam lcell_cnt_sel_3.family = device_family; + generic_lcell_comb lcell_cnt_sel_4 ( + .dataa(usr_cnt_sel[0]), + .datab(usr_cnt_sel[1]), + .datac(usr_cnt_sel[2]), + .datad(usr_cnt_sel[3]), + .datae(usr_cnt_sel[4]), + .dataf(gnd), + .combout (cnt_sel[4])); + defparam lcell_cnt_sel_4.lut_mask = 64'hFFFF0000FFFF0000; + defparam lcell_cnt_sel_4.dont_touch = "on"; + defparam lcell_cnt_sel_4.family = device_family; + + +endmodule + +module generic_lcell_comb +#( + //parameter + parameter family = "Stratix V", + parameter lut_mask = 64'hAAAAAAAAAAAAAAAA, + parameter dont_touch = "on" +) ( + + input dataa, + input datab, + input datac, + input datad, + input datae, + input dataf, + + output combout +); + + generate + if (family == "Stratix V") + begin + stratixv_lcell_comb lcell_inst ( + .dataa(dataa), + .datab(datab), + .datac(datac), + .datad(datad), + .datae(datae), + .dataf(dataf), + .combout (combout)); + defparam lcell_inst.lut_mask = lut_mask; + defparam lcell_inst.dont_touch = dont_touch; + end + else if (family == "Arria V") + begin + arriav_lcell_comb lcell_inst ( + .dataa(dataa), + .datab(datab), + .datac(datac), + .datad(datad), + .datae(datae), + .dataf(dataf), + .combout (combout)); + defparam lcell_inst.lut_mask = lut_mask; + defparam lcell_inst.dont_touch = dont_touch; + end + else if (family == "Arria V GZ") + begin + arriavgz_lcell_comb lcell_inst ( + .dataa(dataa), + .datab(datab), + .datac(datac), + .datad(datad), + .datae(datae), + .dataf(dataf), + .combout (combout)); + defparam lcell_inst.lut_mask = lut_mask; + defparam lcell_inst.dont_touch = dont_touch; + end + else if (family == "Cyclone V") + begin + cyclonev_lcell_comb lcell_inst ( + .dataa(dataa), + .datab(datab), + .datac(datac), + .datad(datad), + .datae(datae), + .dataf(dataf), + .combout (combout)); + defparam lcell_inst.lut_mask = lut_mask; + defparam lcell_inst.dont_touch = dont_touch; + end + endgenerate +endmodule diff --git a/src/fpga/core/pll_reconfig/altera_pll_reconfig_mif_reader.v b/src/fpga/core/pll_reconfig/altera_pll_reconfig_mif_reader.v new file mode 100644 index 0000000..631a684 --- /dev/null +++ b/src/fpga/core/pll_reconfig/altera_pll_reconfig_mif_reader.v @@ -0,0 +1,758 @@ +// (C) 2001-2022 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1ps/1ps + +module altera_pll_reconfig_mif_reader +#( + parameter RECONFIG_ADDR_WIDTH = 6, + parameter RECONFIG_DATA_WIDTH = 32, + + parameter MIF_ADDR_WIDTH = 6, + + parameter ROM_ADDR_WIDTH = 9, // 512 words x + parameter ROM_DATA_WIDTH = 32, // 32 bits per word = 20kB + parameter ROM_NUM_WORDS = 512, // Default 512 32-bit words = 1 M20K + + parameter DEVICE_FAMILY = "Stratix V", + parameter ENABLE_MIF = 0, + parameter MIF_FILE_NAME = "" +) ( + + // Inputs + input wire mif_clk, + input wire mif_rst, + + // Reconfig Module interface for internal register mapping + input wire reconfig_busy, // waitrequest + input wire [RECONFIG_DATA_WIDTH-1:0] reconfig_read_data, + output reg [RECONFIG_DATA_WIDTH-1:0] reconfig_write_data, + output reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_addr, + output reg reconfig_write, + output reg reconfig_read, + + // MIF Controller Interface + input wire [ROM_ADDR_WIDTH-1:0] mif_base_addr, + input wire mif_start, + output wire mif_busy + +); + +// NOTE: Assumes settings opcodes/registers are continguous and OP_MODE is 0 + +// ROM Interface ctlr states +localparam NUM_STATES = 5; +localparam STATE_REG_WIDTH = 32; +localparam MIF_IDLE = 32'd0; +localparam SET_INSTR_ADDR = 32'd1; +localparam FETCH_INSTR = 32'd2; +localparam WAIT_FOR_ROM_INSTR = 32'd3; +localparam STORE_INSTR = 32'd4; +localparam DECODE_ROM_INSTR = 32'd5; +localparam SET_DATA_ADDR = 32'd6; +localparam SET_DATA_ADDR_DLY = 32'd34; +localparam FETCH_DATA = 32'd7; +localparam WAIT_FOR_ROM_DATA = 32'd8; +localparam STORE_DATA = 32'd9; +localparam SET_INDEX = 32'd35; +localparam CHANGE_SETTINGS_REG = 32'd10; +localparam SET_MODE_REG_INFO = 32'd11; +localparam WAIT_MODE_REG = 32'd12; +localparam SAVE_MODE_REG = 32'd13; +localparam SET_WR_MODE = 32'd14; +localparam WAIT_WRITE_MODE = 32'd15; +localparam INIT_RECONFIG_PARAMS = 32'd16; +localparam CHECK_RECONFIG_SETTING = 32'd17; +localparam WRITE_RECONFIG_SETTING = 32'd18; +localparam DECREMENT_SETTING_NUM = 32'd19; +localparam CHECK_C_SETTINGS = 32'd20; +localparam WRITE_C_SETTINGS = 32'd21; +localparam DECREMENT_C_NUM = 32'd22; +localparam CHECK_DPS_SETTINGS = 32'd23; +localparam WRITE_DPS_SETTINGS = 32'd24; +localparam DECREMENT_DPS_NUM = 32'd25; +localparam START_RECONFIG_CHANGE = 32'd26; +localparam START_RECONFIG_DELAY = 32'd27; +localparam START_RECONFIG_DELAY2 = 32'd28; +localparam WAIT_DONE_SIGNAL = 32'd29; +localparam SET_MODE_REG = 32'd30; +localparam WRITE_FINAL_MODE = 32'd31; +localparam WAIT_FINAL_MODE = 32'd32; +localparam MIF_STREAMING_DONE = 32'd33; + + +// MIF Opcodes +// Addresses for settings from PLL Reconfig module +localparam OP_MODE = 6'b000000; +localparam OP_STATUS = 6'b000001; // Read only +localparam OP_START = 6'b000010; +localparam OP_N = 6'b000011; +localparam OP_M = 6'b000100; +localparam OP_C_COUNTERS = 6'b000101; +localparam OP_DPS = 6'b000110; +localparam OP_DSM = 6'b000111; +localparam OP_BWCTRL = 6'b001000; +localparam OP_CP_CURRENT = 6'b001001; + +localparam OP_SOM = 6'b111110; +localparam OP_EOM = 6'b111111; + +localparam INVAL_SETTING = 6'b111100; + +localparam MODE_WR = 1'b0; +localparam MODE_POLL = 1'b1; + +// Total MIF changeable settings = 8 +// + Total non-MIF changeable settings = 2 (status, start) +// + StartOfMif, EndOfMif, Invalid = 3 +// = 13 total settings +localparam NUM_SETTINGS = 6'd13; +localparam NUM_MIF_SETTINGS = 6'd10; // Mode = 0.. CP_Current=9 +localparam LOG2NUM_SETTINGS = 6; // Consistent with Reconfig addr width +localparam NUM_C_COUNTERS = 5'd18; +localparam LOG2NUM_C_COUNTERS = 3'd5; +localparam NUM_DPS_COUNTERS = 6'd32; +localparam LOG2NUM_DPS_COUNTERS = 3'd6; + +// Reconfig Module parameters +localparam WAITREQUEST_MODE = 1'b1; + +// Control flow registers +reg [STATE_REG_WIDTH-1:0] mif_curstate; +reg [STATE_REG_WIDTH-1:0] mif_nextstate; +wire is_done; + +// Internal data registers +reg [ROM_ADDR_WIDTH-1:0] reg_mif_base_addr; +reg [LOG2NUM_SETTINGS-1:0] reg_instr; +reg [RECONFIG_DATA_WIDTH-1:0] reg_data; +reg [RECONFIG_DATA_WIDTH-1:0] settings_reg [NUM_MIF_SETTINGS-1:0]; +reg [RECONFIG_DATA_WIDTH-1:0] c_settings_reg [NUM_C_COUNTERS-1:0]; +reg [RECONFIG_DATA_WIDTH-1:0] dps_settings_reg [NUM_DPS_COUNTERS-1:0]; +reg [4:0] c_cntr_index; // C cntr is data[22:18]; +reg [4:0] dps_index; // DPS is data[20:16]; + +reg [NUM_SETTINGS-1:0] is_setting_changed; // 1 bit per setting +reg [NUM_C_COUNTERS-1:0] is_c_cntr_changed; +reg [NUM_DPS_COUNTERS-1:0] is_dps_changed; + +reg user_mode_setting; // 0 for waitrequest mode, 1 for polling +reg mif_started; +reg saved_mode; +reg mode_reg; +reg [RECONFIG_ADDR_WIDTH-1:0] setting_number; +reg [LOG2NUM_C_COUNTERS-1:0] c_cntr_number; +reg [LOG2NUM_DPS_COUNTERS-1:0] dps_number; +reg c_done; +reg dps_done; +reg is_mode_changed; + +// ROM Interface +wire [ROM_DATA_WIDTH-1:0] rom_q; +reg [ROM_ADDR_WIDTH-1:0] rom_addr; + +assign mif_busy = (is_done) ? 1'b0 : 1'b1; + +// mif_started register +always @(posedge mif_clk) +begin + if (mif_curstate == MIF_IDLE) + mif_started <= 0; + else if (reg_instr == OP_SOM && mif_curstate == DECODE_ROM_INSTR) + mif_started <= 1; + else + mif_started <= mif_started; +end + +// is_done logic +assign is_done = (mif_curstate == MIF_IDLE && mif_nextstate == MIF_IDLE) ? 1'b1 : 1'b0; + +// State register +always @(posedge mif_clk) +begin + if (mif_rst) + mif_curstate <= MIF_IDLE; + else + mif_curstate <= mif_nextstate; +end + +// Next state logic +always @(*) +begin + case (mif_curstate) + MIF_IDLE: + begin + if (mif_start) + mif_nextstate = SET_INSTR_ADDR; + else + mif_nextstate = MIF_IDLE; + end + + // Set address for instruction to be fetched from ROM + SET_INSTR_ADDR: // SET_ROM_INFO + begin + mif_nextstate = FETCH_INSTR; + end + + FETCH_INSTR: + begin + mif_nextstate = WAIT_FOR_ROM_INSTR; + end + + WAIT_FOR_ROM_INSTR: + begin + mif_nextstate = STORE_INSTR; + end + + STORE_INSTR: + begin + mif_nextstate = DECODE_ROM_INSTR; + end + + DECODE_ROM_INSTR: + begin + if (reg_instr == OP_SOM) + mif_nextstate = SET_INSTR_ADDR; + else if (reg_instr == OP_EOM) + mif_nextstate = SET_MODE_REG_INFO; // Done reading MIF, send it to reconfig module + else + mif_nextstate = SET_DATA_ADDR; + end + + SET_DATA_ADDR: + begin + mif_nextstate = SET_DATA_ADDR_DLY; + end + + SET_DATA_ADDR_DLY: + begin + mif_nextstate = FETCH_DATA; + end + + FETCH_DATA: + begin + mif_nextstate = WAIT_FOR_ROM_DATA; + end + + WAIT_FOR_ROM_DATA: + begin + mif_nextstate = STORE_DATA; + end + + STORE_DATA: + begin + mif_nextstate = SET_INDEX; + end + + SET_INDEX: + begin + mif_nextstate = CHANGE_SETTINGS_REG; + end + + CHANGE_SETTINGS_REG: + begin + mif_nextstate = SET_INSTR_ADDR; // Loop back to read rest of MIF file + end + + // --- CHANGE RECONFIG REGISTERS --- // + // GENERAL STEPS FOR MANAGING WITH RECONFIG MODULE: + // 1) Save user's configured mode register, + // 2) Change mode to waitrequest mode, + // 3) Send all settings that have changed to + // 4) Start reconfig + // 5) Wait till PLL has locked again. + // 6) Restore user's mode register + SET_MODE_REG_INFO: + begin + mif_nextstate = WAIT_MODE_REG; + end + + WAIT_MODE_REG: + begin + mif_nextstate = SAVE_MODE_REG; + end + + SAVE_MODE_REG: + begin + mif_nextstate = SET_WR_MODE; + end + + SET_WR_MODE: + begin + mif_nextstate = WAIT_WRITE_MODE; + end + + WAIT_WRITE_MODE: + begin + mif_nextstate = INIT_RECONFIG_PARAMS; + end + + INIT_RECONFIG_PARAMS: + begin + mif_nextstate = CHECK_RECONFIG_SETTING; + end + + // PARENT LOOP (writing to reconfig) + CHECK_RECONFIG_SETTING: // Loop over changed settings until setting_num = 0 = MODE + begin + // Don't write the user's mode reg just yet + // Stay in WR mode till we're done with reconfig IP + // then restore the user's old mode/the new mode + // they wrote in the MIF + if (setting_number == 6'b0) + mif_nextstate = START_RECONFIG_CHANGE; + else + begin + if(is_setting_changed[setting_number]) + // C and DPS settings are different, + // since multiple can be reconfigured in + // one MIF. If they are changed, check them all. + // In their respective loops + if (setting_number == OP_C_COUNTERS) + begin + mif_nextstate = DECREMENT_C_NUM; + end + else if (setting_number == OP_DPS) + begin + mif_nextstate = DECREMENT_DPS_NUM; + end + else + begin + mif_nextstate = WRITE_RECONFIG_SETTING; + end + else + mif_nextstate = DECREMENT_SETTING_NUM; + end + end + + // C LOOP + // We need to check the 0th setting always (unlike the parent loop) so decrement first. + DECREMENT_C_NUM: + begin + if (c_done) + begin + // Done checking and writing C counters + // check next setting in parent loop + mif_nextstate = DECREMENT_SETTING_NUM; + end + else + mif_nextstate = CHECK_C_SETTINGS; + end + + CHECK_C_SETTINGS: + begin + if (is_c_cntr_changed[c_cntr_number]) + mif_nextstate = WRITE_C_SETTINGS; + else + mif_nextstate = DECREMENT_C_NUM; + end + + WRITE_C_SETTINGS: + begin + mif_nextstate = DECREMENT_C_NUM; + end + //End C Loop + + // DPS LOOP + // Same as C loop, decrement first. + DECREMENT_DPS_NUM: + begin + if (dps_done) + begin + // Done checking and writing DPS counters + // check next setting in parent loop + mif_nextstate = DECREMENT_SETTING_NUM; + end + else + mif_nextstate = CHECK_DPS_SETTINGS; // Check next DPS setting + end + + CHECK_DPS_SETTINGS: + begin + if(is_dps_changed[dps_number]) + mif_nextstate = WRITE_DPS_SETTINGS; + else + mif_nextstate = DECREMENT_DPS_NUM; + end + + WRITE_DPS_SETTINGS: + begin + mif_nextstate = DECREMENT_DPS_NUM; + end + //End DPS Loop + + + WRITE_RECONFIG_SETTING: + begin + mif_nextstate = DECREMENT_SETTING_NUM; + end + + DECREMENT_SETTING_NUM: + begin + mif_nextstate = CHECK_RECONFIG_SETTING; // Loop back + end + + // --- DONE CHANGING SETTINGS, START RECONFIG --- // + + START_RECONFIG_CHANGE: + begin + mif_nextstate = START_RECONFIG_DELAY; + end + + START_RECONFIG_DELAY: + begin + mif_nextstate = START_RECONFIG_DELAY2; + end + + START_RECONFIG_DELAY2: // register at top level before we mux into reconfig + begin + mif_nextstate = WAIT_DONE_SIGNAL; + end + + WAIT_DONE_SIGNAL: + begin + if (reconfig_busy) + mif_nextstate = WAIT_DONE_SIGNAL; + else + mif_nextstate = SET_MODE_REG; + end + + SET_MODE_REG: + begin + mif_nextstate = WRITE_FINAL_MODE; + end + + WRITE_FINAL_MODE: + begin + mif_nextstate = WAIT_FINAL_MODE; + end + + WAIT_FINAL_MODE: + begin + mif_nextstate = MIF_STREAMING_DONE; + end + + MIF_STREAMING_DONE: + begin + mif_nextstate = MIF_IDLE; + end + + default: + begin + mif_nextstate = MIF_IDLE; + end + endcase +end + +// Data flow +reg [LOG2NUM_SETTINGS-1:0] i; +reg [LOG2NUM_C_COUNTERS-1:0] j; +reg [LOG2NUM_DPS_COUNTERS-1:0] k; +always @(posedge mif_clk) +begin + if (mif_rst) + begin + reg_mif_base_addr <= 0; + is_setting_changed <= 0; + is_c_cntr_changed <= 0; + is_dps_changed <= 0; + rom_addr <= 0; + reg_instr <= 0; + reg_data <= 0; + for (i = 0; i < NUM_MIF_SETTINGS; i = i + 1'b1) + begin + settings_reg [i] <= 0; + end + for (j = 0; j < NUM_C_COUNTERS; j = j + 1'b1) + begin + c_settings_reg [j] <= 0; + end + for (k = 0; k < NUM_DPS_COUNTERS; k = k + 1'b1) + begin + dps_settings_reg [k] <= 0; + end + setting_number <= 0; + c_cntr_number <= 0; + dps_number <= 0; + c_done <= 0; + dps_done <= 0; + c_cntr_index <= 0; + dps_index <= 0; + reconfig_write_data <= 0; + reconfig_addr <= 0; + reconfig_write <= 0; + reconfig_read <= 0; + end + else + begin + case (mif_curstate) + MIF_IDLE: + begin + reg_mif_base_addr <= mif_base_addr; + is_setting_changed <= 0; + is_c_cntr_changed <= 0; + is_dps_changed <= 0; + rom_addr <= 0; + reg_instr <= 0; + reg_data <= 0; + for (i = 0; i < NUM_MIF_SETTINGS; i = i + 1'b1) + begin + settings_reg [i] <= 0; + end + for (j = 0; j < NUM_C_COUNTERS; j = j + 1'b1) + begin + c_settings_reg [j] <= 0; + end + for (k = 0; k < NUM_DPS_COUNTERS; k = k + 1'b1) + begin + dps_settings_reg [k] <= 0; + end + setting_number <= 0; + c_cntr_number <= 0; + dps_number <= 0; + c_done <= 0; + dps_done <= 0; + c_cntr_index <= 0; + dps_index <= 0; + reconfig_write_data <= 0; + reconfig_addr <= 0; + reconfig_write <= 0; + reconfig_read <= 0; + end + + // ----- ROM FLOW ----- // + SET_INSTR_ADDR: rom_addr <= (mif_started) ? rom_addr + 9'd1 : reg_mif_base_addr; // ROM_ADDR_WIDTH = 9 + FETCH_INSTR: ; + WAIT_FOR_ROM_INSTR: ; + STORE_INSTR: reg_instr <= rom_q [LOG2NUM_SETTINGS-1:0]; // Only the last 6 bits are instr bits, rest is reserved + DECODE_ROM_INSTR: ; + SET_DATA_ADDR: rom_addr <= rom_addr + 9'd1; // ROM_ADDR_WIDTH = 9 + SET_DATA_ADDR_DLY: ; + FETCH_DATA: ; + WAIT_FOR_ROM_DATA: ; + STORE_DATA: reg_data <= rom_q; // Data is 32 bits + + SET_INDEX: + begin + c_cntr_index <= reg_data[22:18]; + dps_index <= reg_data[20:16]; + end + + + CHANGE_SETTINGS_REG: + begin + if (reg_instr == OP_C_COUNTERS) + begin + c_settings_reg [c_cntr_index] <= reg_data; //22:18 is c cnt number + is_c_cntr_changed [c_cntr_index] <= 1'b1; + end + else if (reg_instr == OP_DPS) + begin + dps_settings_reg [dps_index] <= reg_data; //20:16 is DPS number + is_dps_changed [dps_index] <= 1'b1; + end + else + begin + c_settings_reg [c_cntr_index] <= c_settings_reg [c_cntr_index]; + is_c_cntr_changed [c_cntr_index] <= is_c_cntr_changed[c_cntr_index]; + dps_settings_reg [dps_index] <= dps_settings_reg [dps_index]; + is_dps_changed [dps_index] <= is_dps_changed [dps_index]; + end + + settings_reg [reg_instr] <= reg_data; + is_setting_changed [reg_instr] <= 1'b1; + end + + + // ---------- RECONFIG FLOW ---------- // + + // Reading/writing mode takes only one cycle + // (we don't know what mode its in initally) + SET_MODE_REG_INFO: + begin + reconfig_addr <= OP_MODE; + reconfig_read <= 1'b1; + reconfig_write <= 1'b0; + reconfig_write_data <= 0; + end + + WAIT_MODE_REG: reconfig_read <= 1'b0; + SAVE_MODE_REG: saved_mode <= reconfig_read_data[0]; + SET_WR_MODE: + begin + reconfig_addr <= OP_MODE; + reconfig_write <= 1'b1; + reconfig_write_data[0] <= MODE_WR; // Want WaitRequest Mode while MIF reader changes Reconfig regs + end + WAIT_WRITE_MODE: reconfig_write <= 1'b0; + + // Done saving the mode reg, start writing the reconfig regs + // Start with the highest setting and work our way down + INIT_RECONFIG_PARAMS: + begin + setting_number <= NUM_MIF_SETTINGS - 6'd1; + c_cntr_number <= NUM_C_COUNTERS; + dps_number <= NUM_DPS_COUNTERS; + end + + CHECK_RECONFIG_SETTING: ; + + // C LOOP + DECREMENT_C_NUM: + begin + c_cntr_number <= c_cntr_number - 5'd1; + reconfig_write <= 1'b0; + end + + CHECK_C_SETTINGS: + begin + if (c_cntr_number == 5'b0) + c_done <= 1'b1; + else + c_done <= c_done; + end + + WRITE_C_SETTINGS: + begin + reconfig_addr <= OP_C_COUNTERS; + reconfig_write_data <= c_settings_reg[c_cntr_number]; + reconfig_read <= 1'b0; + reconfig_write <= 1'b1; + end + //End C Loop + + // DPS LOOP + DECREMENT_DPS_NUM: + begin + dps_number <= dps_number - 5'd1; + reconfig_write <= 1'b0; + end + + CHECK_DPS_SETTINGS: + begin + if (dps_number == 5'b0) + dps_done <= 1'b1; + else + dps_done <= dps_done; + end + + WRITE_DPS_SETTINGS: + begin + reconfig_addr <= OP_DPS; + reconfig_write_data <= dps_settings_reg[dps_number]; + reconfig_read <= 1'b0; + reconfig_write <= 1'b1; + end + //End DPS Loop + + WRITE_RECONFIG_SETTING: + begin + reconfig_addr <= setting_number; // setting_number = OP_CODE + reconfig_write_data <= settings_reg[setting_number]; + reconfig_read <= 1'b0; + reconfig_write <= 1'b1; + end + + DECREMENT_SETTING_NUM: + begin + reconfig_write <= 1'b0; + setting_number <= setting_number - 6'd1; // Decrement for looping back + end + + // --- Wrote all the changed settings to the Reconfig IP except MODE + // --- Start the Reconfig process (write to start reg) and wait for + // --- waitrequest signal to deassert + + START_RECONFIG_CHANGE: + begin + reconfig_addr <= OP_START; + reconfig_write_data <= 1; + reconfig_read <= 1'b0; + reconfig_write <= 1'b1; + end + + START_RECONFIG_DELAY: + begin + reconfig_write <= 1'b0; + end + + WAIT_DONE_SIGNAL: ; + + // --- Restore saved MODE reg ONLY if mode hasn't been changed by MIF + SET_MODE_REG: + mode_reg <= (is_setting_changed[OP_MODE]) ? settings_reg [OP_MODE][0] : saved_mode; + + WRITE_FINAL_MODE: + begin + reconfig_addr <= OP_MODE; + reconfig_write_data[0] <= mode_reg; + reconfig_read <= 1'b0; + reconfig_write <= 1'b1; + end + + WAIT_FINAL_MODE: + begin + reconfig_write <= 1'b0; + end + + MIF_STREAMING_DONE: ; + + default : ; + + endcase + end +end + +// RAM block + altsyncram altsyncram_component ( + .address_a (rom_addr), + .clock0 (mif_clk), + .q_a (rom_q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_a ({32{1'b1}}), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_a (1'b0), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_a = "NONE", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = MIF_FILE_NAME, + altsyncram_component.intended_device_family = "Stratix V", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = ROM_NUM_WORDS, + altsyncram_component.operation_mode = "ROM", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.widthad_a = ROM_ADDR_WIDTH, + altsyncram_component.width_a = ROM_DATA_WIDTH, + altsyncram_component.width_byteena_a = 1; + +endmodule // mif_reader + diff --git a/src/fpga/core/pll_reconfig/altera_pll_reconfig_top.v b/src/fpga/core/pll_reconfig/altera_pll_reconfig_top.v new file mode 100644 index 0000000..2cf9ce5 --- /dev/null +++ b/src/fpga/core/pll_reconfig/altera_pll_reconfig_top.v @@ -0,0 +1,428 @@ +// (C) 2001-2022 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1ps/1ps + +module altera_pll_reconfig_top +#( + parameter reconf_width = 64, + parameter device_family = "Stratix V", + parameter RECONFIG_ADDR_WIDTH = 6, + parameter RECONFIG_DATA_WIDTH = 32, + + parameter ROM_ADDR_WIDTH = 9, + parameter ROM_DATA_WIDTH = 32, + parameter ROM_NUM_WORDS = 512, + + parameter ENABLE_MIF = 0, + parameter MIF_FILE_NAME = "", + + parameter ENABLE_BYTEENABLE = 0, + parameter BYTEENABLE_WIDTH = 4, + parameter WAIT_FOR_LOCK = 1 +) ( + + //input + input wire mgmt_clk, + input wire mgmt_reset, + + + //conduits + output wire [reconf_width-1:0] reconfig_to_pll, + input wire [reconf_width-1:0] reconfig_from_pll, + + // user data (avalon-MM slave interface) + output wire [RECONFIG_DATA_WIDTH-1:0] mgmt_readdata, + output wire mgmt_waitrequest, + input wire [RECONFIG_ADDR_WIDTH-1:0] mgmt_address, + input wire mgmt_read, + input wire mgmt_write, + input wire [RECONFIG_DATA_WIDTH-1:0] mgmt_writedata, + + //conditional input + input wire [BYTEENABLE_WIDTH-1:0] mgmt_byteenable +); + +localparam NM28_START_REG = 6'b000010; +localparam NM20_START_REG = 9'b000000000; +localparam NM20_MIFSTART_ADDR = 9'b000010000; + +localparam MIF_STATE_DONE = 2'b00; +localparam MIF_STATE_START = 2'b01; +localparam MIF_STATE_BUSY = 2'b10; + +wire mgmt_byteenable_write; +assign mgmt_byteenable_write = (ENABLE_BYTEENABLE == 1) ? + ((mgmt_byteenable == {BYTEENABLE_WIDTH{1'b1}}) ? mgmt_write : 1'b0) : + mgmt_write; + +generate +if (device_family == "Arria 10") +begin:nm20_reconfig + if(ENABLE_MIF == 1) + begin:mif_reconfig_20nm // Generate Reconfig with MIF + + // MIF-related regs/wires + reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr; + reg reconfig_mgmt_read; + reg reconfig_mgmt_write; + reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata; + wire reconfig_mgmt_waitrequest; + wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata; + + wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr; + wire mif_busy; + wire mif2reconfig_read; + wire mif2reconfig_write; + wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata; + wire [ROM_ADDR_WIDTH-1:0] mif_base_addr; + reg mif_select; + //wire mif_user_start; // start signal provided by user to start mif + //reg user_start; + + reg [1:0] mif_curstate; + reg [1:0] mif_nextstate; + + wire mif_start; //start signal to mif reader + + assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif_busy;// | user_start; + // Don't output readdata if MIF streaming is taking place + assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata; + + //user must lower this by the time mif streaming is done - suggest to lower after 1 cycle + assign mif_start = mgmt_byteenable_write & (mgmt_address == NM20_MIFSTART_ADDR); + + //mif base addr is initially specified by the user + assign mif_base_addr = mgmt_writedata[ROM_ADDR_WIDTH-1:0]; + + //MIF statemachine + always @(posedge mgmt_clk) + begin + if(mgmt_reset) + mif_curstate <= MIF_STATE_DONE; + else + mif_curstate <= mif_nextstate; + end + + always @(*) + begin + case (mif_curstate) + MIF_STATE_DONE: + begin + if(mif_start) + mif_nextstate <= MIF_STATE_START; + else + mif_nextstate <= MIF_STATE_DONE; + end + MIF_STATE_START: + begin + mif_nextstate <= MIF_STATE_BUSY; + end + MIF_STATE_BUSY: + begin + if(mif_busy) + mif_nextstate <= MIF_STATE_BUSY; + else + mif_nextstate <= MIF_STATE_DONE; + end + endcase + end + + //Mif muxes + always @(*) + begin + if (mgmt_reset) + begin + reconfig_mgmt_addr <= 0; + reconfig_mgmt_read <= 0; + reconfig_mgmt_write <= 0; + reconfig_mgmt_writedata <= 0; + //user_start <= 0; + end + else + begin + reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address; + reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read; + reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write; + reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata; + //user_start <= (mgmt_address == NM20_START_REG && mgmt_write == 1'b1) ? 1'b1 : 1'b0; + end + end + + always @(*) + begin + if (mgmt_reset) + begin + mif_select <= 0; + end + else + begin + mif_select <= (mif_start || mif_busy) ? 1'b1 : 1'b0; + end + end + + twentynm_pll_reconfig_mif_reader + #( + .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), + .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), + .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), + .ROM_DATA_WIDTH(ROM_DATA_WIDTH), + .ROM_NUM_WORDS(ROM_NUM_WORDS), + .DEVICE_FAMILY(device_family), + .ENABLE_MIF(ENABLE_MIF), + .MIF_FILE_NAME(MIF_FILE_NAME) + ) twentynm_pll_reconfig_mif_reader_inst0 ( + .mif_clk(mgmt_clk), + .mif_rst(mgmt_reset), + + //Altera_PLL Reconfig interface + //inputs + .reconfig_waitrequest(reconfig_mgmt_waitrequest), + //.reconfig_read_data(reconfig_mgmt_readdata), + //outputs + .reconfig_write_data(mif2reconfig_writedata), + .reconfig_addr(mif2reconfig_addr), + .reconfig_write(mif2reconfig_write), + .reconfig_read(mif2reconfig_read), + + //MIF Ctrl Interface + //inputs + .mif_base_addr(mif_base_addr), + .mif_start(mif_start), + //outputs + .mif_busy(mif_busy) + ); + + // ------ END MIF-RELATED MANAGEMENT ------ + + twentynm_iopll_reconfig_core + #( + .WAIT_FOR_LOCK(WAIT_FOR_LOCK) + ) twentynm_iopll_reconfig_core_inst ( + // Inputs + .mgmt_clk(mgmt_clk), + .mgmt_rst_n(~mgmt_reset), + .mgmt_read(reconfig_mgmt_read), + .mgmt_write(reconfig_mgmt_write), + .mgmt_address(reconfig_mgmt_addr), + .mgmt_writedata(reconfig_mgmt_writedata), + + // Outputs + .mgmt_readdata(reconfig_mgmt_readdata), + .mgmt_waitrequest(reconfig_mgmt_waitrequest), + + // PLL Conduits + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll) + ); + + end // End generate reconfig with MIF + else + begin:reconfig_core_20nm + twentynm_iopll_reconfig_core + #( + .WAIT_FOR_LOCK(WAIT_FOR_LOCK) + ) twentynm_iopll_reconfig_core_inst ( + // Inputs + .mgmt_clk(mgmt_clk), + .mgmt_rst_n(~mgmt_reset), + .mgmt_read(mgmt_read), + .mgmt_write(mgmt_byteenable_write), + .mgmt_address(mgmt_address), + .mgmt_writedata(mgmt_writedata), + + // Outputs + .mgmt_readdata(mgmt_readdata), + .mgmt_waitrequest(mgmt_waitrequest), + + // PLL Conduits + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll) + ); + end +end // 20nm reconfig +else +begin:NM28_reconfig + if (ENABLE_MIF == 1) + begin:mif_reconfig // Generate Reconfig with MIF + + // MIF-related regs/wires + reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr; + reg reconfig_mgmt_read; + reg reconfig_mgmt_write; + reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata; + wire reconfig_mgmt_waitrequest; + wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata; + + wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr; + wire mif2reconfig_busy; + wire mif2reconfig_read; + wire mif2reconfig_write; + wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata; + wire [ROM_ADDR_WIDTH-1:0] mif_base_addr; + reg mif_select; + reg user_start; + + wire reconfig2mif_start_out; + + assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif2reconfig_busy | user_start; + // Don't output readdata if MIF streaming is taking place + assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata; + + always @(posedge mgmt_clk) + begin + if (mgmt_reset) + begin + reconfig_mgmt_addr <= 0; + reconfig_mgmt_read <= 0; + reconfig_mgmt_write <= 0; + reconfig_mgmt_writedata <= 0; + user_start <= 0; + end + else + begin + reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address; + reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read; + reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write; + reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata; + user_start <= (mgmt_address == NM28_START_REG && mgmt_byteenable_write == 1'b1) ? 1'b1 : 1'b0; + end + end + + always @(*) + begin + if (mgmt_reset) + begin + mif_select <= 0; + end + else + begin + mif_select <= (reconfig2mif_start_out || mif2reconfig_busy) ? 1'b1 : 1'b0; + end + end + + altera_pll_reconfig_mif_reader + #( + .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), + .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), + .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), + .ROM_DATA_WIDTH(ROM_DATA_WIDTH), + .ROM_NUM_WORDS(ROM_NUM_WORDS), + .DEVICE_FAMILY(device_family), + .ENABLE_MIF(ENABLE_MIF), + .MIF_FILE_NAME(MIF_FILE_NAME) + ) altera_pll_reconfig_mif_reader_inst0 ( + .mif_clk(mgmt_clk), + .mif_rst(mgmt_reset), + + //Altera_PLL Reconfig interface + //inputs + .reconfig_busy(reconfig_mgmt_waitrequest), + .reconfig_read_data(reconfig_mgmt_readdata), + //outputs + .reconfig_write_data(mif2reconfig_writedata), + .reconfig_addr(mif2reconfig_addr), + .reconfig_write(mif2reconfig_write), + .reconfig_read(mif2reconfig_read), + + //MIF Ctrl Interface + //inputs + .mif_base_addr(mif_base_addr), + .mif_start(reconfig2mif_start_out), + //outputs + .mif_busy(mif2reconfig_busy) + ); + + // ------ END MIF-RELATED MANAGEMENT ------ + + + altera_pll_reconfig_core + #( + .reconf_width(reconf_width), + .device_family(device_family), + .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), + .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), + .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), + .ROM_DATA_WIDTH(ROM_DATA_WIDTH), + .ROM_NUM_WORDS(ROM_NUM_WORDS) + ) altera_pll_reconfig_core_inst0 ( + //inputs + .mgmt_clk(mgmt_clk), + .mgmt_reset(mgmt_reset), + + //PLL interface conduits + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll), + + //User data outputs + .mgmt_readdata(reconfig_mgmt_readdata), + .mgmt_waitrequest(reconfig_mgmt_waitrequest), + + //User data inputs + .mgmt_address(reconfig_mgmt_addr), + .mgmt_read(reconfig_mgmt_read), + .mgmt_write(reconfig_mgmt_write), + .mgmt_writedata(reconfig_mgmt_writedata), + + // other + .mif_start_out(reconfig2mif_start_out), + .mif_base_addr(mif_base_addr) + ); + + end // End generate reconfig with MIF + else + begin:reconfig_core // Generate Reconfig core only + + wire reconfig2mif_start_out; + wire [ROM_ADDR_WIDTH-1:0] mif_base_addr; + + altera_pll_reconfig_core + #( + .reconf_width(reconf_width), + .device_family(device_family), + .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), + .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), + .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), + .ROM_DATA_WIDTH(ROM_DATA_WIDTH), + .ROM_NUM_WORDS(ROM_NUM_WORDS) + ) altera_pll_reconfig_core_inst0 ( + //inputs + .mgmt_clk(mgmt_clk), + .mgmt_reset(mgmt_reset), + + //PLL interface conduits + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll), + + //User data outputs + .mgmt_readdata(mgmt_readdata), + .mgmt_waitrequest(mgmt_waitrequest), + + //User data inputs + .mgmt_address(mgmt_address), + .mgmt_read(mgmt_read), + .mgmt_write(mgmt_byteenable_write), + .mgmt_writedata(mgmt_writedata), + + // other + .mif_start_out(reconfig2mif_start_out), + .mif_base_addr(mif_base_addr) + ); + + + end // End generate reconfig core only +end // End 28nm Reconfig +endgenerate + +endmodule + diff --git a/src/fpga/core/pll_reconfig/altera_std_synchronizer.v b/src/fpga/core/pll_reconfig/altera_std_synchronizer.v new file mode 100644 index 0000000..47135c2 --- /dev/null +++ b/src/fpga/core/pll_reconfig/altera_std_synchronizer.v @@ -0,0 +1,159 @@ +// (C) 2001-2022 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/21.1std/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#1 $ +// $Revision: #1 $ +// $Date: 2020/06/22 $ +// $Author: psgswbuild $ +//----------------------------------------------------------------------------- +// +// File: altera_std_synchronizer.v +// +// Abstract: Single bit clock domain crossing synchronizer. +// Composed of two or more flip flops connected in series. +// Random metastable condition is simulated when the +// __ALTERA_STD__METASTABLE_SIM macro is defined. +// Use +define+__ALTERA_STD__METASTABLE_SIM argument +// on the Verilog simulator compiler command line to +// enable this mode. In addition, dfine the macro +// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output +// with every metastable event generated in the synchronizer. +// +// Copyright (C) Altera Corporation 2009, All Rights Reserved +//----------------------------------------------------------------------------- + +`timescale 1ns / 1ns + +module altera_std_synchronizer ( + clk, + reset_n, + din, + dout + ); + + parameter depth = 3; // This value must be >= 2 ! + + input clk; + input reset_n; + input din; + output dout; + + // QuartusII synthesis directives: + // 1. Preserve all registers ie. do not touch them. + // 2. Do not merge other flip-flops with synchronizer flip-flops. + // QuartusII TimeQuest directives: + // 1. Identify all flip-flops in this module as members of the synchronizer + // to enable automatic metastability MTBF analysis. + // 2. Cut all timing paths terminating on data input pin of the first flop din_s1. + + (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON; -name SDC_STATEMENT \"set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]\" "} *) reg din_s1; + + (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg; + + //synthesis translate_off + initial begin + if (depth <2) begin + $display("%m: Error: synchronizer length: %0d less than 2.", depth); + end + end + + // the first synchronizer register is either a simple D flop for synthesis + // and non-metastable simulation or a D flop with a method to inject random + // metastable events resulting in random delay of [0,1] cycles + +`ifdef __ALTERA_STD__METASTABLE_SIM + + reg[31:0] RANDOM_SEED = 123456; + wire next_din_s1; + wire dout; + reg din_last; + reg random; + event metastable_event; // hook for debug monitoring + + initial begin + $display("%m: Info: Metastable event injection simulation mode enabled"); + end + + always @(posedge clk) begin + if (reset_n == 0) + random <= $random(RANDOM_SEED); + else + random <= $random; + end + + assign next_din_s1 = (din_last ^ din) ? random : din; + + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + din_last <= 1'b0; + else + din_last <= din; + end + + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + din_s1 <= 1'b0; + else + din_s1 <= next_din_s1; + end + +`else + + //synthesis translate_on + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + din_s1 <= 1'b0; + else + din_s1 <= din; + end + //synthesis translate_off + +`endif + +`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE + always @(*) begin + if (reset_n && (din_last != din) && (random != din)) begin + $display("%m: Verbose Info: metastable event @ time %t", $time); + ->metastable_event; + end + end +`endif + + //synthesis translate_on + + // the remaining synchronizer registers form a simple shift register + // of length depth-1 + generate + if (depth < 3) begin + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + dreg <= {depth-1{1'b0}}; + else + dreg <= din_s1; + end + end else begin + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + dreg <= {depth-1{1'b0}}; + else + dreg <= {dreg[depth-3:0], din_s1}; + end + end + endgenerate + + assign dout = dreg[depth-2]; + +endmodule + + + diff --git a/src/fpga/core/pll_reconfig_sim.f b/src/fpga/core/pll_reconfig_sim.f new file mode 100644 index 0000000..a56337d --- /dev/null +++ b/src/fpga/core/pll_reconfig_sim.f @@ -0,0 +1,5 @@ +pll_reconfig_sim/pll_reconfig.v +pll_reconfig_sim/altera_pll_reconfig/altera_pll_reconfig_top.v +pll_reconfig_sim/altera_pll_reconfig/altera_pll_reconfig_mif_reader.v +pll_reconfig_sim/altera_pll_reconfig/altera_pll_reconfig_core.v +pll_reconfig_sim/altera_pll_reconfig/altera_std_synchronizer.v diff --git a/src/fpga/core/pll_reconfig_sim/aldec/rivierapro_setup.tcl b/src/fpga/core/pll_reconfig_sim/aldec/rivierapro_setup.tcl new file mode 100644 index 0000000..1960b33 --- /dev/null +++ b/src/fpga/core/pll_reconfig_sim/aldec/rivierapro_setup.tcl @@ -0,0 +1,283 @@ + +# (C) 2001-2022 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions and +# other software and tools, and its AMPP partner logic functions, and +# any output files any of the foregoing (including device programming +# or simulation files), and any associated documentation or information +# are expressly subject to the terms and conditions of the Altera +# Program License Subscription Agreement, Altera MegaCore Function +# License Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by Altera +# or its authorized distributors. Please refer to the applicable +# agreement for further details. + +# ACDS 21.1 850 win32 2022.10.28.07:55:18 +# ---------------------------------------- +# Auto-generated simulation script rivierapro_setup.tcl +# ---------------------------------------- +# This script provides commands to simulate the following IP detected in +# your Quartus project: +# pll_reconfig +# +# Altera recommends that you source this Quartus-generated IP simulation +# script from your own customized top-level script, and avoid editing this +# generated script. +# +# To write a top-level script that compiles Altera simulation libraries and +# the Quartus-generated IP in your project, along with your design and +# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below +# into a new file, e.g. named "aldec.do", and modify the text as directed. +# +# ---------------------------------------- +# # TOP-LEVEL TEMPLATE - BEGIN +# # +# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to +# # construct paths to the files required to simulate the IP in your Quartus +# # project. By default, the IP script assumes that you are launching the +# # simulator from the IP script location. If launching from another +# # location, set QSYS_SIMDIR to the output directory you specified when you +# # generated the IP script, relative to the directory from which you launch +# # the simulator. +# # +# set QSYS_SIMDIR