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written in Verilog
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opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.githu…
NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards
NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.
Global Dark Mode for ALL apps on ANY platforms.