-
Notifications
You must be signed in to change notification settings - Fork 1.5k
/
Copy pathdtrmm_kernel_4x4.S
1398 lines (1040 loc) · 25.8 KB
/
dtrmm_kernel_4x4.S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*******************************************************************************
Copyright (c) 2015, The OpenBLAS Project
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
3. Neither the name of the OpenBLAS project nor the names of
its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#define ASSEMBLER
#include "common.h"
/* X0 X1 X2 s0 X3 x4 x5 x6 x7*/
/*int CNAME(BLASLONG bm,BLASLONG bn,BLASLONG bk,FLOAT alpha0,FLOAT* ba,FLOAT* bb,FLOAT* C,BLASLONG ldc, BLASLONG offset) */
#define origM x0
#define origN x1
#define origK x2
#define origPA x3
#define origPB x4
#define pC x5
#define LDC x6
#define offset x7
#define counterL x8
#define counterI x9
#define counterJ x10
#define pB x11
#define pCRow0 x12
#define pCRow1 x13
#define pCRow2 x14
#define pA x15
#define temp x16
#define tempOffset x17
#define tempK x18
#define alpha0 d10
#define alphaV0 v10.d[0]
#define alpha1 d11
#define alphaV1 v11.d[0]
#define alpha2 d14
#define alphaV2 v14.d[0]
#define alpha3 d15
#define alphaV3 v15.d[0]
// 00 origM
// 01 origN
// 02 origK
// 03 origPA
// 04 origPB
// 05 pC
// 06 origLDC -> LDC
// 07 offset
// 08 counterL
// 09 counterI
// 10 counterJ
// 11 pB
// 12 pCRow0
// 13 pCRow1
// 14 pCRow2
// 15 pA
// 16 temp
// 17 tempOffset
// 18 must save tempK
// 19 must save
// 20 must save
// 21 must save
// 22 must save
// 23 must save
// 24 must save
// 25 must save
// 26 must save
// 27 must save
// 28 must save
// 29 frame
// 30 link
// 31 sp
//v00 ALPHA -> pA00, pA01
//v01 pA02, pA03
//v02
//v03
//v04 pA10, pA11
//v05 pA12, pA13
//v06
//v07
//v08 must save pB00, pB01
//v09 must save pB02, pB03
//v10 must save ALPHA0
//v11 must save ALPHA1
//v12 must save pB10, pB11
//v13 must save pB12, pB13
//v14 must save ALPHA2
//v15 must save ALPHA3
//v16 must save C00, C01
//v17 must save C02, C03
//v18
//v19
//v20 C10, C11
//v21 C12, C13
//v22
//v23
//v24 C20, C21
//v25 C22, C23
//v26
//v27
//v28 C30, C31
//v29 C32, C33
//v30
//v31
/*******************************************************************************
* Macro definitions
*******************************************************************************/
.macro INIT4x4
fmov d16, xzr
fmov d17, d16
fmov d20, d17
fmov d21, d16
fmov d24, d17
fmov d25, d16
fmov d28, d17
fmov d29, d16
.endm
.macro KERNEL4x4_I
ld1 {v8.2d, v9.2d}, [pB]
add pB, pB, #32
ld1 {v0.2d, v1.2d}, [pA]
add pA, pA, #32
fmul v16.2d, v0.2d, v8.d[0]
fmul v29.2d, v1.2d, v9.d[1]
fmul v20.2d, v0.2d, v8.d[1]
fmul v25.2d, v1.2d, v9.d[0]
fmul v24.2d, v0.2d, v9.d[0]
fmul v21.2d, v1.2d, v8.d[1]
fmul v28.2d, v0.2d, v9.d[1]
fmul v17.2d, v1.2d, v8.d[0]
ld1 {v12.2d, v13.2d}, [pB]
add pB, pB, #32
ld1 {v4.2d, v5.2d}, [pA]
add pA, pA, #32
.endm
.macro KERNEL4x4_M1
fmla v16.2d, v0.2d, v8.d[0]
fmla v29.2d, v1.2d, v9.d[1]
ld1 {v12.2d, v13.2d}, [pB] // For next round
add pB, pB, #32
fmla v20.2d, v0.2d, v8.d[1]
fmla v25.2d, v1.2d, v9.d[0]
ld1 {v4.2d, v5.2d}, [pA] // For next round
add pA, pA, #32
fmla v24.2d, v0.2d, v9.d[0]
fmla v21.2d, v1.2d, v8.d[1]
prfm PLDL1KEEP, [pA, #512]
fmla v28.2d, v0.2d, v9.d[1]
fmla v17.2d, v1.2d, v8.d[0]
.endm
.macro KERNEL4x4_M2
fmla v16.2d, v4.2d, v12.d[0]
fmla v29.2d, v5.2d, v13.d[1]
ld1 {v8.2d, v9.2d}, [pB] // For next round
add pB, pB, #32
fmla v20.2d, v4.2d, v12.d[1]
fmla v25.2d, v5.2d, v13.d[0]
ld1 {v0.2d, v1.2d}, [pA] // For next round
add pA, pA, #32
fmla v24.2d, v4.2d, v13.d[0]
fmla v21.2d, v5.2d, v12.d[1]
prfm PLDL1KEEP, [pB, #512]
fmla v28.2d, v4.2d, v13.d[1]
fmla v17.2d, v5.2d, v12.d[0]
.endm
.macro KERNEL4x4_E
fmla v16.2d, v4.2d, v12.d[0]
fmla v29.2d, v5.2d, v13.d[1]
fmla v20.2d, v4.2d, v12.d[1]
fmla v25.2d, v5.2d, v13.d[0]
fmla v24.2d, v4.2d, v13.d[0]
fmla v21.2d, v5.2d, v12.d[1]
fmla v28.2d, v4.2d, v13.d[1]
fmla v17.2d, v5.2d, v12.d[0]
.endm
.macro KERNEL4x4_SUB
ld1 {v8.2d, v9.2d}, [pB]
add pB, pB, #32
ld1 {v0.2d, v1.2d}, [pA]
add pA, pA, #32
fmla v16.2d, v0.2d, v8.d[0]
fmla v29.2d, v1.2d, v9.d[1]
fmla v20.2d, v0.2d, v8.d[1]
fmla v25.2d, v1.2d, v9.d[0]
fmla v24.2d, v0.2d, v9.d[0]
fmla v21.2d, v1.2d, v8.d[1]
fmla v28.2d, v0.2d, v9.d[1]
fmla v17.2d, v1.2d, v8.d[0]
.endm
.macro SAVE4x4
fmul v8.2d, v16.2d, alphaV0
fmul v9.2d, v17.2d, alphaV1
st1 {v8.2d, v9.2d}, [pCRow0]
add pCRow1, pCRow0, LDC
fmul v12.2d, v20.2d, alphaV2
fmul v13.2d, v21.2d, alphaV3
st1 {v12.2d, v13.2d}, [pCRow1]
add pCRow2, pCRow1, LDC
fmul v8.2d, v24.2d, alphaV0
fmul v9.2d, v25.2d, alphaV1
st1 {v8.2d, v9.2d}, [pCRow2]
add pCRow1, pCRow2, LDC
fmul v12.2d, v28.2d, alphaV2
fmul v13.2d, v29.2d, alphaV3
st1 {v12.2d, v13.2d}, [pCRow1]
add pCRow0, pCRow0, #32
.endm
/******************************************************************************/
.macro INIT2x4
fmov d16, xzr
fmov d20, d16
fmov d24, d20
fmov d28, d16
.endm
.macro KERNEL2x4_SUB
ld1 {v8.2d, v9.2d}, [pB]
add pB, pB, #32
ld1 {v0.2d}, [pA]
add pA, pA, #16
fmla v16.2d, v0.2d, v8.d[0]
fmla v20.2d, v0.2d, v8.d[1]
fmla v24.2d, v0.2d, v9.d[0]
fmla v28.2d, v0.2d, v9.d[1]
.endm
.macro SAVE2x4
fmul v8.2d, v16.2d, alphaV0
st1 {v8.2d}, [pCRow0]
add pCRow1, pCRow0, LDC
fmul v12.2d, v20.2d, alphaV1
st1 {v12.2d}, [pCRow1]
add pCRow2, pCRow1, LDC
fmul v8.2d, v24.2d, alphaV2
st1 {v8.2d}, [pCRow2]
add pCRow1, pCRow2, LDC
fmul v12.2d, v28.2d, alphaV3
st1 {v12.2d}, [pCRow1]
add pCRow0, pCRow0, #16
.endm
/******************************************************************************/
.macro INIT1x4
fmov d16, xzr
fmov d20, d16
.endm
.macro KERNEL1x4_SUB
ldr d0, [pA]
add pA, pA, #8
ld1 {v8.2d, v9.2d}, [pB]
add pB, pB, #32
fmla v16.2d, v8.2d, v0.d[0]
fmla v20.2d, v9.2d, v0.d[0]
.endm
.macro SAVE1x4
add pCRow1, pCRow0, LDC
fmul v8.2d, v16.2d, alphaV0
st1 {v8.d}[0], [pCRow0]
st1 {v8.d}[1], [pCRow1]
add pCRow2, pCRow1, LDC
add pCRow1, pCRow2, LDC
fmul v12.2d, v20.2d, alphaV1
st1 {v12.d}[0], [pCRow2]
st1 {v12.d}[1], [pCRow1]
add pCRow0, pCRow0, #8
.endm
/******************************************************************************/
.macro INIT4x2
fmov d16, xzr
fmov d17, d16
fmov d20, d17
fmov d21, d16
.endm
.macro KERNEL4x2_SUB
ld1 {v8.2d}, [pB]
add pB, pB, #16
ld1 {v0.2d, v1.2d}, [pA]
add pA, pA, #32
fmla v16.2d, v0.2d, v8.d[0]
fmla v17.2d, v1.2d, v8.d[0]
fmla v20.2d, v0.2d, v8.d[1]
fmla v21.2d, v1.2d, v8.d[1]
.endm
.macro SAVE4x2
fmul v8.2d, v16.2d, alphaV0
fmul v9.2d, v17.2d, alphaV1
st1 {v8.2d, v9.2d}, [pCRow0]
add pCRow1, pCRow0, LDC
fmul v12.2d, v20.2d, alphaV2
fmul v13.2d, v21.2d, alphaV3
st1 {v12.2d, v13.2d}, [pCRow1]
add pCRow0, pCRow0, #32
.endm
/******************************************************************************/
.macro INIT2x2
fmov d16, xzr
fmov d20, d16
.endm
.macro KERNEL2x2_SUB
ld1 {v8.2d}, [pB]
add pB, pB, #16
ld1 {v0.2d}, [pA]
add pA, pA, #16
fmla v16.2d, v0.2d, v8.d[0]
fmla v20.2d, v0.2d, v8.d[1]
.endm
.macro SAVE2x2
fmul v8.2d, v16.2d, alphaV0
st1 {v8.2d}, [pCRow0]
add pCRow1 , pCRow0, LDC
fmul v12.2d, v20.2d, alphaV1
st1 {v12.2d}, [pCRow1]
add pCRow0, pCRow0, #16
.endm
/******************************************************************************/
.macro INIT1x2
fmov d16, xzr
.endm
.macro KERNEL1x2_SUB
ld1 {v8.2d} , [pB]
add pB , pB, #16
ldr d0 , [pA]
add pA, pA, #8
fmla v16.2d, v8.2d, v0.d[0]
.endm
.macro SAVE1x2
add pCRow1 , pCRow0, LDC
fmul v8.2d, v16.2d, alphaV0
st1 {v8.d}[0], [pCRow0]
st1 {v8.d}[1], [pCRow1]
add pCRow0, pCRow0, #8
.endm
/******************************************************************************/
.macro INIT4x1
fmov d16, xzr
fmov d17, d16
.endm
.macro KERNEL4x1_SUB
ldr d8, [pB]
add pB , pB, #8
ld1 {v0.2d, v1.2d}, [pA]
add pA , pA, #32
fmla v16.2d, v0.2d, v8.d[0]
fmla v17.2d, v1.2d, v8.d[0]
.endm
.macro SAVE4x1
fmul v8.2d, v16.2d, alphaV0
fmul v9.2d, v17.2d, alphaV1
st1 {v8.2d, v9.2d}, [pCRow0]
add pCRow0, pCRow0, #32
.endm
/******************************************************************************/
.macro INIT2x1
fmov d16, xzr
.endm
.macro KERNEL2x1_SUB
ldr d8, [pB]
add pB , pB, #8
ld1 {v0.2d}, [pA]
add pA , pA, #16
fmla v16.2d, v0.2d, v8.d[0]
.endm
.macro SAVE2x1
fmul v8.2d, v16.2d, alphaV0
st1 {v8.2d}, [pCRow0]
add pCRow0, pCRow0, #16
.endm
/******************************************************************************/
.macro INIT1x1
fmov d16, xzr
.endm
.macro KERNEL1x1_SUB
ldr d8, [pB]
add pB , pB, #8
ldr d0, [pA]
add pA , pA, #8
fmadd d16, d0, d8, d16
.endm
.macro SAVE1x1
fmul d8, d16, alpha0
str d8, [pCRow0]
add pCRow0, pCRow0, #8
.endm
/*******************************************************************************
* End of macro definitions
*******************************************************************************/
PROLOGUE
.align 5
add sp, sp, #-(11 * 16)
stp d8, d9, [sp, #(0 * 16)]
stp d10, d11, [sp, #(1 * 16)]
stp d12, d13, [sp, #(2 * 16)]
stp d14, d15, [sp, #(3 * 16)]
stp d16, d17, [sp, #(4 * 16)]
stp x18, x19, [sp, #(5 * 16)]
stp x20, x21, [sp, #(6 * 16)]
stp x22, x23, [sp, #(7 * 16)]
stp x24, x25, [sp, #(8 * 16)]
stp x26, x27, [sp, #(9 * 16)]
str x28, [sp, #(10 * 16)]
fmov alpha0, d0
fmov alpha1, d0
fmov alpha2, d0
fmov alpha3, d0
lsl LDC, LDC, #3 // ldc = ldc * 8
#if !defined(LEFT)
neg tempOffset, offset
#endif
mov pB, origPB
mov counterJ, origN
asr counterJ, counterJ, #2 // J = J / 4
cmp counterJ, #0
ble .Ldtrmm_kernel_L2_BEGIN
/******************************************************************************/
.Ldtrmm_kernel_L4_BEGIN:
mov pCRow0, pC // pCRow0 = C
add pC, pC, LDC, lsl #2
#if defined(LEFT)
mov tempOffset, offset
#endif
mov pA, origPA // pA = start of A array
.Ldtrmm_kernel_L4_M4_BEGIN:
mov counterI, origM
asr counterI, counterI, #2 // counterI = counterI / 4
cmp counterI, #0
ble .Ldtrmm_kernel_L4_M2_BEGIN
.Ldtrmm_kernel_L4_M4_20:
#if (defined(LEFT) && defined(TRANSA)) || (!defined(LEFT) && !defined(TRANSA))
mov pB, origPB
#else
mov pB, origPB
lsl temp, tempOffset, #5
add pB, pB, temp
add pA, pA, temp
#endif
#if (defined(LEFT) && !defined(TRANSA)) || (!defined(LEFT) && defined(TRANSA))
sub tempK, origK, tempOffset
#elif defined(LEFT)
add tempK, tempOffset, #4
#else
add tempK, tempOffset, #4
#endif
asr counterL , tempK, #1 // L = K / 2
cmp counterL , #2 // is there at least 4 to do?
blt .Ldtrmm_kernel_L4_M4_32
KERNEL4x4_I // do one in the K
KERNEL4x4_M2 // do another in the K
subs counterL, counterL, #2
ble .Ldtrmm_kernel_L4_M4_22a
.align 5
.Ldtrmm_kernel_L4_M4_22:
KERNEL4x4_M1
KERNEL4x4_M2
subs counterL, counterL, #1
bgt .Ldtrmm_kernel_L4_M4_22
.Ldtrmm_kernel_L4_M4_22a:
KERNEL4x4_M1
KERNEL4x4_E
b .Ldtrmm_kernel_L4_M4_44
.Ldtrmm_kernel_L4_M4_32:
tst counterL, #1
ble .Ldtrmm_kernel_L4_M4_40
KERNEL4x4_I
KERNEL4x4_E
b .Ldtrmm_kernel_L4_M4_44
.Ldtrmm_kernel_L4_M4_40:
INIT4x4
.Ldtrmm_kernel_L4_M4_44:
ands counterL , tempK, #1
ble .Ldtrmm_kernel_L4_M4_100
.Ldtrmm_kernel_L4_M4_46:
KERNEL4x4_SUB
.Ldtrmm_kernel_L4_M4_100:
SAVE4x4
#if (defined(LEFT) && defined(TRANSA)) || (!defined(LEFT) && !defined(TRANSA))
sub tempK, origK, tempOffset
#if defined(LEFT)
sub tempK, tempK, #4
#else
sub tempK, tempK, #4
#endif
lsl temp, tempK, #5
add pA, pA, temp
add pB, pB, temp
#endif
#if defined(LEFT)
add tempOffset, tempOffset, #4
#endif
.Ldtrmm_kernel_L4_M4_END:
subs counterI, counterI, #1
bne .Ldtrmm_kernel_L4_M4_20
.Ldtrmm_kernel_L4_M2_BEGIN:
mov counterI, origM
tst counterI , #3
ble .Ldtrmm_kernel_L4_END
tst counterI, #2 // counterI = counterI / 2
ble .Ldtrmm_kernel_L4_M1_BEGIN
.Ldtrmm_kernel_L4_M2_20:
INIT2x4
#if (defined(LEFT) && defined(TRANSA)) || (!defined(LEFT) && !defined(TRANSA))
mov pB, origPB
#else
mov pB, origPB
lsl temp, tempOffset, #4
add pA, pA, temp
lsl temp, tempOffset, #5
add pB, pB, temp
#endif
#if (defined(LEFT) && !defined(TRANSA)) || (!defined(LEFT) && defined(TRANSA))
sub tempK, origK, tempOffset
#elif defined(LEFT)
add tempK, tempOffset, #2
#else
add tempK, tempOffset, #4
#endif
asr counterL , tempK, #3 // counterL = counterL / 8
cmp counterL , #0
ble .Ldtrmm_kernel_L4_M2_40
.Ldtrmm_kernel_L4_M2_22:
KERNEL2x4_SUB
KERNEL2x4_SUB
KERNEL2x4_SUB
KERNEL2x4_SUB
KERNEL2x4_SUB
KERNEL2x4_SUB
KERNEL2x4_SUB
KERNEL2x4_SUB
subs counterL, counterL, #1
bgt .Ldtrmm_kernel_L4_M2_22
.Ldtrmm_kernel_L4_M2_40:
ands counterL , tempK, #7 // counterL = counterL % 8
ble .Ldtrmm_kernel_L4_M2_100
.Ldtrmm_kernel_L4_M2_42:
KERNEL2x4_SUB
subs counterL, counterL, #1
bgt .Ldtrmm_kernel_L4_M2_42
.Ldtrmm_kernel_L4_M2_100:
SAVE2x4
#if (defined(LEFT) && defined(TRANSA)) || (!defined(LEFT) && !defined(TRANSA))
sub tempK, origK, tempOffset
#if defined(LEFT)
sub tempK, tempK, #2
#else
sub tempK, tempK, #4
#endif
lsl temp, tempK, #4
add pA, pA, temp
lsl temp, tempK, #5
add pB, pB, temp
#endif
#if defined(LEFT)
add tempOffset, tempOffset, #2
#endif
.Ldtrmm_kernel_L4_M2_END:
.Ldtrmm_kernel_L4_M1_BEGIN:
tst counterI, #1 // counterI = counterI % 2
ble .Ldtrmm_kernel_L4_END
.Ldtrmm_kernel_L4_M1_20:
INIT1x4
#if (defined(LEFT) && defined(TRANSA)) || (!defined(LEFT) && !defined(TRANSA))
mov pB, origPB
#else
mov pB, origPB
lsl temp, tempOffset, #5
add pB, pB, temp
lsl temp, tempOffset, #3
add pA, pA, temp
#endif
#if (defined(LEFT) && !defined(TRANSA)) || (!defined(LEFT) && defined(TRANSA))
sub tempK, origK, tempOffset
#elif defined(LEFT)
add tempK, tempOffset, #1
#else
add tempK, tempOffset, #4
#endif
asr counterL , tempK, #3 // counterL = counterL / 8
cmp counterL , #0
ble .Ldtrmm_kernel_L4_M1_40
.Ldtrmm_kernel_L4_M1_22:
KERNEL1x4_SUB
KERNEL1x4_SUB
KERNEL1x4_SUB
KERNEL1x4_SUB
KERNEL1x4_SUB
KERNEL1x4_SUB
KERNEL1x4_SUB
KERNEL1x4_SUB
subs counterL, counterL, #1
bgt .Ldtrmm_kernel_L4_M1_22
.Ldtrmm_kernel_L4_M1_40:
ands counterL , tempK, #7 // counterL = counterL % 8
ble .Ldtrmm_kernel_L4_M1_100
.Ldtrmm_kernel_L4_M1_42:
KERNEL1x4_SUB
subs counterL, counterL, #1
bgt .Ldtrmm_kernel_L4_M1_42
.Ldtrmm_kernel_L4_M1_100:
SAVE1x4
#if (defined(LEFT) && defined(TRANSA)) || (!defined(LEFT) && !defined(TRANSA))
sub tempK, origK, tempOffset
#if defined(LEFT)
sub tempK, tempK, #1
#else
sub tempK, tempK, #4
#endif
lsl temp, tempK, #3
add pA, pA, temp
lsl temp, tempK, #5
add pB, pB, temp
#endif
#if defined(LEFT)
add tempOffset, tempOffset, #1
#endif
.Ldtrmm_kernel_L4_END:
lsl temp, origK, #5
add origPB, origPB, temp // B = B + K * 4 * 8
#if !defined(LEFT)
add tempOffset, tempOffset, #4
#endif
subs counterJ, counterJ , #1 // j--
bgt .Ldtrmm_kernel_L4_BEGIN
/******************************************************************************/
.Ldtrmm_kernel_L2_BEGIN: // less than 2 left in N direction
mov counterJ , origN
tst counterJ , #3
ble .Ldtrmm_kernel_L999 // error, N was less than 4?
tst counterJ , #2
ble .Ldtrmm_kernel_L1_BEGIN
mov pCRow0, pC // pCRow0 = pC
add pC,pC,LDC, lsl #1
#if defined(LEFT)
mov tempOffset, offset
#endif
mov pA, origPA // pA = A
.Ldtrmm_kernel_L2_M4_BEGIN:
mov counterI, origM
asr counterI, counterI, #2 // counterI = counterI / 4
cmp counterI,#0
ble .Ldtrmm_kernel_L2_M2_BEGIN
.Ldtrmm_kernel_L2_M4_20:
INIT4x2
#if (defined(LEFT) && defined(TRANSA)) || (!defined(LEFT) && !defined(TRANSA))
mov pB, origPB
#else
mov pB, origPB
lsl temp, tempOffset, #4
add pB, pB, temp
lsl temp, tempOffset, #5
add pA, pA, temp
#endif
#if (defined(LEFT) && !defined(TRANSA)) || (!defined(LEFT) && defined(TRANSA))
sub tempK, origK, tempOffset
#elif defined(LEFT)
add tempK, tempOffset, #4
#else
add tempK, tempOffset, #2
#endif
asr counterL , tempK, #3 // counterL = counterL / 8
cmp counterL,#0
ble .Ldtrmm_kernel_L2_M4_40
.align 5
.Ldtrmm_kernel_L2_M4_22:
KERNEL4x2_SUB
KERNEL4x2_SUB
KERNEL4x2_SUB
KERNEL4x2_SUB
KERNEL4x2_SUB
KERNEL4x2_SUB
KERNEL4x2_SUB
KERNEL4x2_SUB
subs counterL, counterL, #1
bgt .Ldtrmm_kernel_L2_M4_22
.Ldtrmm_kernel_L2_M4_40:
ands counterL , tempK, #7 // counterL = counterL % 8
ble .Ldtrmm_kernel_L2_M4_100
.Ldtrmm_kernel_L2_M4_42:
KERNEL4x2_SUB
subs counterL, counterL, #1
bgt .Ldtrmm_kernel_L2_M4_42
.Ldtrmm_kernel_L2_M4_100:
SAVE4x2
#if (defined(LEFT) && defined(TRANSA)) || (!defined(LEFT) && !defined(TRANSA))
sub tempK, origK, tempOffset
#if defined(LEFT)
sub tempK, tempK, #4
#else
sub tempK, tempK, #2
#endif
lsl temp, tempK, #5
add pA, pA, temp
lsl temp, tempK, #4
add pB, pB, temp
#endif
#if defined(LEFT)
add tempOffset, tempOffset, #4
#endif
.Ldtrmm_kernel_L2_M4_END:
subs counterI, counterI, #1
bgt .Ldtrmm_kernel_L2_M4_20
.Ldtrmm_kernel_L2_M2_BEGIN:
mov counterI, origM
tst counterI , #3
ble .Ldtrmm_kernel_L2_END
tst counterI, #2 // counterI = counterI / 2
ble .Ldtrmm_kernel_L2_M1_BEGIN
.Ldtrmm_kernel_L2_M2_20:
INIT2x2
#if (defined(LEFT) && defined(TRANSA)) || (!defined(LEFT) && !defined(TRANSA))
mov pB, origPB
#else
mov pB, origPB
lsl temp, tempOffset, #4
add pB, pB, temp
lsl temp, tempOffset, #4
add pA, pA, temp
#endif
#if (defined(LEFT) && !defined(TRANSA)) || (!defined(LEFT) && defined(TRANSA))
sub tempK, origK, tempOffset
#elif defined(LEFT)
add tempK, tempOffset, #2
#else
add tempK, tempOffset, #2
#endif
asr counterL , tempK, #3 // counterL = counterL / 8
cmp counterL,#0
ble .Ldtrmm_kernel_L2_M2_40
.Ldtrmm_kernel_L2_M2_22:
KERNEL2x2_SUB
KERNEL2x2_SUB
KERNEL2x2_SUB
KERNEL2x2_SUB
KERNEL2x2_SUB
KERNEL2x2_SUB
KERNEL2x2_SUB
KERNEL2x2_SUB
subs counterL, counterL, #1