diff --git a/.github/workflows/MarkdwonLinksCheck.yml b/.github/workflows/MarkdwonLinksCheck.yml
index 5525a3050d..5f2220b8ad 100644
--- a/.github/workflows/MarkdwonLinksCheck.yml
+++ b/.github/workflows/MarkdwonLinksCheck.yml
@@ -11,6 +11,9 @@ on:
- '**.md'
# Allows you to run this workflow manually from the Actions tab
workflow_dispatch:
+ schedule:
+ # Run every day at 12 AM UTC to check url.
+ - cron: "0 11 * * *"
jobs:
linkinator:
runs-on: ubuntu-latest
diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json
index c47e35a460..7cdc1022ca 100644
--- a/CI/build/conf/cores_config.json
+++ b/CI/build/conf/cores_config.json
@@ -760,6 +760,7 @@
"GENERIC_L412K8UX",
"GENERIC_L412KBTX",
"GENERIC_L412KBUX",
+ "GENERIC_L412RBIXP",
"GENERIC_L422KBTX",
"GENERIC_L431CBTX",
"GENERIC_L431CBUX",
@@ -823,6 +824,8 @@
"GENERIC_L4S5VITX",
"GENERIC_L4S5ZITX",
"GENERIC_L4S5ZIYX",
+ "GENERIC_L552QCIXQ",
+ "GENERIC_L552QEIXQ",
"GENERIC_L552ZCTXQ",
"GENERIC_L552ZETXQ",
"GENERIC_MP153AACX",
diff --git a/CI/build/conf/cores_config_ci.json b/CI/build/conf/cores_config_ci.json
index 8dff66d592..267c32f85c 100644
--- a/CI/build/conf/cores_config_ci.json
+++ b/CI/build/conf/cores_config_ci.json
@@ -760,6 +760,7 @@
"GENERIC_L412K8UX",
"GENERIC_L412KBTX",
"GENERIC_L412KBUX",
+ "GENERIC_L412RBIXP",
"GENERIC_L422KBTX",
"GENERIC_L431CBTX",
"GENERIC_L431CBUX",
@@ -823,6 +824,8 @@
"GENERIC_L4S5VITX",
"GENERIC_L4S5ZITX",
"GENERIC_L4S5ZIYX",
+ "GENERIC_L552QCIXQ",
+ "GENERIC_L552QEIXQ",
"GENERIC_L552ZCTXQ",
"GENERIC_L552ZETXQ",
"GENERIC_MP153AACX",
diff --git a/README.md b/README.md
index f8b7b0bd73..f65e8c74ed 100644
--- a/README.md
+++ b/README.md
@@ -121,6 +121,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :green_heart: | STM32L4R5ZI-P | [Nucleo L4R5ZI-P](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi-p.html) | *1.4.0* | |
| :green_heart: | STM32L552ZE-Q | [Nucleo L552ZE-Q](https://www.st.com/en/evaluation-tools/nucleo-l552ze-q.html) | *2.0.0* | |
| :green_heart: | STM32U575ZI-Q | [NUCLEO-U575ZI-Q](https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html) | *2.1.0* | |
+| :yellow_heart: | STM32U5A5ZJ-Q | [NUCLEO-U5A5ZJ-Q](https://www.st.com/en/evaluation-tools/nucleo-u5a5zj-q.html) | **2.11.0** | |
### [Nucleo 64](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-nucleo-boards.html) boards
@@ -136,6 +137,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :green_heart: | STM32F302R8 | [Nucleo F302R8](http://www.st.com/en/evaluation-tools/nucleo-f302r8.html) | *1.1.0* | |
| :green_heart: | STM32F303RE | [Nucleo F303RE](http://www.st.com/en/evaluation-tools/nucleo-f303re.html) | *0.1.0* | |
| :green_heart: | STM32F401RE | [Nucleo F401RE](http://www.st.com/en/evaluation-tools/nucleo-f401re.html) | *0.2.1* | |
+| :yellow_heart: | STM32F410RB | [Nucleo F410RB](http://www.st.com/en/evaluation-tools/nucleo-f410rb.html) | **2.11.0** | |
| :green_heart: | STM32F411RE | [Nucleo F411RE](http://www.st.com/en/evaluation-tools/nucleo-f411re.html) | *0.2.1* | |
| :green_heart: | STM32F446RE | [Nucleo F446RE](http://www.st.com/en/evaluation-tools/nucleo-f446re.html) | *1.1.1* | |
| :green_heart: | STM32G070RB | [Nucleo G070RB](https://www.st.com/en/evaluation-tools/nucleo-g070rb.html) | *2.3.0* | |
@@ -148,6 +150,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :green_heart: | STM32L053R8 | [Nucleo L053R8](http://www.st.com/en/evaluation-tools/nucleo-l053r8.html) | *0.1.0* | |
| :green_heart: | STM32L073RZ | [Nucleo L073RZ](http://www.st.com/en/evaluation-tools/nucleo-l073rz.html) | *1.4.0* | |
| :green_heart: | STM32L152RE | [Nucleo L152RE](http://www.st.com/en/evaluation-tools/nucleo-l152re.html) | *1.0.0* | |
+| :yellow_heart: | STM32L412RB-P | [Nucleo L412RC-P](https://www.st.com/en/evaluation-tools/nucleo-l412rb-p.html) | **2.11.0** | |
| :green_heart: | STM32L433RC-P | [Nucleo L433RC-P](https://www.st.com/en/evaluation-tools/nucleo-l433rc-p.html) | *1.9.0* | |
| :green_heart: | STM32L452RE | [Nucleo L452RE](http://www.st.com/en/evaluation-tools/nucleo-l452re.html) | *1.5.0* | |
| :green_heart: | STM32L452RE-P | [Nucleo L452RE-P](http://www.st.com/en/evaluation-tools/nucleo-l452re-p.html) | *1.8.0* | |
@@ -219,6 +222,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :green_heart: | STM32C011J4
STM32C011J6 | Generic Board | *2.8.0* | |
| :green_heart: | STM32C031C4
STM32C031C6 | Generic Board | *2.5.0* | |
| :green_heart: | STM32C031F4
STM32C031F6 | Generic Board | *2.6.0* | |
+| :yellow_heart: | STM32C071G8
STM32C071GB | Generic Board | **2.11.0** | |
| :green_heart: | STM32C071R8
STM32C071RB | Generic Board | *2.9.0* | |
### Generic STM32F0 boards
@@ -704,6 +708,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| Status | Device(s) | Name | Release | Notes |
| :----: | :-------: | ---- | :-----: | :---- |
| :green_heart: | STM32L412K8
STM32L412KB
STM32L422KB | Generic Board | *2.0.0* | |
+| :yellow_heart: | STM32L412RBIxP
STM32L412RBTxP | Generic Board | **2.11.0** | |
| :green_heart: | STM32L431CB
STM32L431CC | Generic Board | *2.8.1* | |
| :green_heart: | STM32L431RB
STM32L431RC | Generic Board | *2.3.0* | |
| :green_heart: | STM32L432KB
STM32L432KC
STM32L442KC | Generic Board | *2.0.0* | |
@@ -774,6 +779,11 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :green_heart: | STM32U585AIIxQ | Generic Board | *2.1.0* | |
| :green_heart: | STM32U585CIx | Generic Board | *2.7.0* | |
| :green_heart: | STM32U585ZITxQ | Generic Board | *2.1.0* | |
+| :yellow_heart: | STM32U595ZITxQ
STM32U595ZJTxQ | Generic Board | **2.11.0** | |
+| :yellow_heart: | STM32U599ZITxQ
STM32U599ZJTxQ | Generic Board | **2.11.0** | |
+| :yellow_heart: | STM32U5A5ZJTxQ | Generic Board | **2.11.0** | |
+| :yellow_heart: | STM32U5A9ZJTxQ | Generic Board | **2.11.0** | |
+
### Generic STM32WB boards
@@ -818,7 +828,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :green_heart: | STM32F446VE | [RUMBA32](https://github.com/Aus3D/RUMBA32) | *1.5.0* | |
| :green_heart: | STM32F401VE | [STEVAL-3DP001V1](https://www.st.com/en/evaluation-tools/steval-3dp001v1.html) | *1.6.0* | |
| :green_heart: | STM32F446RE | VAkE v1.0 | *1.6.0* | |
-| :green_heart: | STM32F446VE | [FYSETC_S6](https://wiki.fysetc.com/FYSETC_S6/) | *1.9.0* | |
+| :green_heart: | STM32F446VE | [FYSETC_S6](https://wiki.fysetc.com/docs/FYSETCS6) | *1.9.0* | |
| :green_heart: | STM32G0B1CB | [BTT EBB42 CAN V1.1](https://github.com/bigtreetech/EBB/tree/master) | *2.4.0* | |
### [Blues](https://blues.com/) boards
diff --git a/boards.txt b/boards.txt
index aaebef7be9..25340dc5d2 100644
--- a/boards.txt
+++ b/boards.txt
@@ -380,6 +380,22 @@ Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.build.peripheral_pins=-DCUSTOM_PERIPHERAL_P
Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.openocd.target=stm32u5x
Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U575.svd
+# NUCLEO_U5A5ZJ_Q board
+Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q=Nucleo U5A5ZJ-Q
+Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.node=NOD_U5A5ZJ
+Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.upload.maximum_size=4194304
+Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.upload.maximum_data_size=2555904
+Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.build.mcu=cortex-m33
+Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.build.fpu=-mfpu=fpv4-sp-d16
+Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.build.float-abi=-mfloat-abi=hard
+Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.build.board=NUCLEO_U5A5ZJ_Q
+Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.build.series=STM32U5xx
+Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.build.product_line=STM32U5A5xx
+Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.build.variant=STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ
+Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS
+Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.openocd.target=stm32u5x
+Nucleo_144.menu.pnum.NUCLEO_U5A5ZJ_Q.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5A5.svd
+
# Upload menu
Nucleo_144.menu.upload_method.MassStorage=Mass Storage
Nucleo_144.menu.upload_method.MassStorage.upload.protocol=
@@ -586,6 +602,21 @@ Nucleo_64.menu.pnum.NUCLEO_F401RE.build.variant=STM32F4xx/F401R(B-C-D-E)T
Nucleo_64.menu.pnum.NUCLEO_F401RE.openocd.target=stm32f4x
Nucleo_64.menu.pnum.NUCLEO_F401RE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F401.svd
+# NUCLEO_F410RB board
+Nucleo_64.menu.pnum.NUCLEO_F410RB=Nucleo F410RB
+Nucleo_64.menu.pnum.NUCLEO_F410RB.node="NOD_F410RB,NUCLEO"
+Nucleo_64.menu.pnum.NUCLEO_F410RB.upload.maximum_size=131072
+Nucleo_64.menu.pnum.NUCLEO_F410RB.upload.maximum_data_size=32768
+Nucleo_64.menu.pnum.NUCLEO_F410RB.build.mcu=cortex-m4
+Nucleo_64.menu.pnum.NUCLEO_F410RB.build.fpu=-mfpu=fpv4-sp-d16
+Nucleo_64.menu.pnum.NUCLEO_F410RB.build.float-abi=-mfloat-abi=hard
+Nucleo_64.menu.pnum.NUCLEO_F410RB.build.board=NUCLEO_F410RB
+Nucleo_64.menu.pnum.NUCLEO_F410RB.build.series=STM32F4xx
+Nucleo_64.menu.pnum.NUCLEO_F410RB.build.product_line=STM32F410Rx
+Nucleo_64.menu.pnum.NUCLEO_F410RB.build.variant=STM32F4xx/F410R(8-B)(I-T)
+Nucleo_64.menu.pnum.NUCLEO_F410RB.openocd.target=stm32f4x
+Nucleo_64.menu.pnum.NUCLEO_F410RB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F410.svd
+
# NUCLEO_F411RE board
Nucleo_64.menu.pnum.NUCLEO_F411RE=Nucleo F411RE
Nucleo_64.menu.pnum.NUCLEO_F411RE.node="NODE_F411RE,NUCLEO"
@@ -758,6 +789,21 @@ Nucleo_64.menu.pnum.NUCLEO_L152RE.build.variant=STM32L1xx/L151RET_L152RET_L162RE
Nucleo_64.menu.pnum.NUCLEO_L152RE.openocd.target=stm32l1
Nucleo_64.menu.pnum.NUCLEO_L152RE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd
+# NUCLEO_L412RB_P board
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P=Nucleo L412RB-P
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.node=NODE_L412RB
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.upload.maximum_size=131072
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.upload.maximum_data_size=40960
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.build.mcu=cortex-m4
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.build.fpu=-mfpu=fpv4-sp-d16
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.build.float-abi=-mfloat-abi=hard
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.build.board=NUCLEO_L412RB_P
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.build.series=STM32L4xx
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.build.product_line=STM32L412xx
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.build.variant=STM32L4xx/L412RB(I-T)xP
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.openocd.target=stm32l4x
+Nucleo_64.menu.pnum.NUCLEO_L412RB_P.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L412.svd
+
# NUCLEO_L433RC_P board
Nucleo_64.menu.pnum.NUCLEO_L433RC_P=Nucleo L433RC-P
Nucleo_64.menu.pnum.NUCLEO_L433RC_P.node=NODE_L433RC
@@ -1629,7 +1675,7 @@ GenC0.build.core=arduino
GenC0.build.board=GenC0
GenC0.build.mcu=cortex-m0plus
GenC0.build.series=STM32C0xx
-GenC0.build.st_extra_flags=-D{build.product_line} {build.xSerial} -D__CORTEX_SC=0
+GenC0.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0
GenC0.build.flash_offset=0x0
GenC0.upload.maximum_size=0
GenC0.upload.maximum_data_size=0
@@ -1752,6 +1798,24 @@ GenC0.menu.pnum.GENERIC_C031F6PX.build.product_line=STM32C031xx
GenC0.menu.pnum.GENERIC_C031F6PX.build.variant=STM32C0xx/C031F(4-6)P
GenC0.menu.pnum.GENERIC_C031F6PX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C031.svd
+# Generic C071G8Ux
+GenC0.menu.pnum.GENERIC_C071G8UX=Generic C071G8Ux
+GenC0.menu.pnum.GENERIC_C071G8UX.upload.maximum_size=65536
+GenC0.menu.pnum.GENERIC_C071G8UX.upload.maximum_data_size=24576
+GenC0.menu.pnum.GENERIC_C071G8UX.build.board=GENERIC_C071G8UX
+GenC0.menu.pnum.GENERIC_C071G8UX.build.product_line=STM32C071xx
+GenC0.menu.pnum.GENERIC_C071G8UX.build.variant=STM32C0xx/C071G(8-B)U
+GenC0.menu.pnum.GENERIC_C071G8UX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C071.svd
+
+# Generic C071GBUx
+GenC0.menu.pnum.GENERIC_C071GBUX=Generic C071GBUx
+GenC0.menu.pnum.GENERIC_C071GBUX.upload.maximum_size=131072
+GenC0.menu.pnum.GENERIC_C071GBUX.upload.maximum_data_size=24576
+GenC0.menu.pnum.GENERIC_C071GBUX.build.board=GENERIC_C071GBUX
+GenC0.menu.pnum.GENERIC_C071GBUX.build.product_line=STM32C071xx
+GenC0.menu.pnum.GENERIC_C071GBUX.build.variant=STM32C0xx/C071G(8-B)U
+GenC0.menu.pnum.GENERIC_C071GBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C071.svd
+
# Generic C071R8Tx
GenC0.menu.pnum.GENERIC_C071R8TX=Generic C071R8Tx
GenC0.menu.pnum.GENERIC_C071R8TX.upload.maximum_size=65536
@@ -1786,6 +1850,11 @@ GenC0.menu.upload_method.serialMethod.upload.protocol=serial
GenC0.menu.upload_method.serialMethod.upload.options=-c {serial.port.file}
GenC0.menu.upload_method.serialMethod.upload.tool=stm32CubeProg
+GenC0.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU)
+GenC0.menu.upload_method.dfuMethod.upload.protocol=dfu
+GenC0.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid}
+GenC0.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg
+
GenC0.menu.upload_method.bmpMethod=BMP (Black Magic Probe)
GenC0.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp
GenC0.menu.upload_method.bmpMethod.upload.tool=bmp_upload
@@ -11471,6 +11540,24 @@ GenL4.menu.pnum.GENERIC_L412KBUX.build.product_line=STM32L412xx
GenL4.menu.pnum.GENERIC_L412KBUX.build.variant=STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)
GenL4.menu.pnum.GENERIC_L412KBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L412.svd
+# Generic L412RBIxP
+GenL4.menu.pnum.GENERIC_L412RBIXP=Generic L412RBIxP
+GenL4.menu.pnum.GENERIC_L412RBIXP.upload.maximum_size=131072
+GenL4.menu.pnum.GENERIC_L412RBIXP.upload.maximum_data_size=40960
+GenL4.menu.pnum.GENERIC_L412RBIXP.build.board=GENERIC_L412RBIXP
+GenL4.menu.pnum.GENERIC_L412RBIXP.build.product_line=STM32L412xx
+GenL4.menu.pnum.GENERIC_L412RBIXP.build.variant=STM32L4xx/L412RB(I-T)xP
+GenL4.menu.pnum.GENERIC_L412RBIXP.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L412.svd
+
+# Generic L412RBTxP
+GenL4.menu.pnum.GENERIC_L412RBTXP=Generic L412RBTxP
+GenL4.menu.pnum.GENERIC_L412RBTXP.upload.maximum_size=131072
+GenL4.menu.pnum.GENERIC_L412RBTXP.upload.maximum_data_size=40960
+GenL4.menu.pnum.GENERIC_L412RBTXP.build.board=GENERIC_L412RBTXP
+GenL4.menu.pnum.GENERIC_L412RBTXP.build.product_line=STM32L412xx
+GenL4.menu.pnum.GENERIC_L412RBTXP.build.variant=STM32L4xx/L412RB(I-T)xP
+GenL4.menu.pnum.GENERIC_L412RBTXP.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L412.svd
+
# Generic L422KBTx
GenL4.menu.pnum.GENERIC_L422KBTX=Generic L422KBTx
GenL4.menu.pnum.GENERIC_L422KBTX.upload.maximum_size=131072
@@ -12686,6 +12773,60 @@ GenU5.menu.pnum.GENERIC_U585ZITXQ.build.product_line=STM32U585xx
GenU5.menu.pnum.GENERIC_U585ZITXQ.build.variant=STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ
GenU5.menu.pnum.GENERIC_U585ZITXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U585.svd
+# Generic U595ZITxQ
+GenU5.menu.pnum.GENERIC_U595ZITXQ=Generic U595ZITxQ
+GenU5.menu.pnum.GENERIC_U595ZITXQ.upload.maximum_size=2097152
+GenU5.menu.pnum.GENERIC_U595ZITXQ.upload.maximum_data_size=2555904
+GenU5.menu.pnum.GENERIC_U595ZITXQ.build.board=GENERIC_U595ZITXQ
+GenU5.menu.pnum.GENERIC_U595ZITXQ.build.product_line=STM32U595xx
+GenU5.menu.pnum.GENERIC_U595ZITXQ.build.variant=STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ
+GenU5.menu.pnum.GENERIC_U595ZITXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U595.svd
+
+# Generic U595ZJTxQ
+GenU5.menu.pnum.GENERIC_U595ZJTXQ=Generic U595ZJTxQ
+GenU5.menu.pnum.GENERIC_U595ZJTXQ.upload.maximum_size=4194304
+GenU5.menu.pnum.GENERIC_U595ZJTXQ.upload.maximum_data_size=2555904
+GenU5.menu.pnum.GENERIC_U595ZJTXQ.build.board=GENERIC_U595ZJTXQ
+GenU5.menu.pnum.GENERIC_U595ZJTXQ.build.product_line=STM32U595xx
+GenU5.menu.pnum.GENERIC_U595ZJTXQ.build.variant=STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ
+GenU5.menu.pnum.GENERIC_U595ZJTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U595.svd
+
+# Generic U599ZITxQ
+GenU5.menu.pnum.GENERIC_U599ZITXQ=Generic U599ZITxQ
+GenU5.menu.pnum.GENERIC_U599ZITXQ.upload.maximum_size=2097152
+GenU5.menu.pnum.GENERIC_U599ZITXQ.upload.maximum_data_size=2555904
+GenU5.menu.pnum.GENERIC_U599ZITXQ.build.board=GENERIC_U599ZITXQ
+GenU5.menu.pnum.GENERIC_U599ZITXQ.build.product_line=STM32U599xx
+GenU5.menu.pnum.GENERIC_U599ZITXQ.build.variant=STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ
+GenU5.menu.pnum.GENERIC_U599ZITXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U599.svd
+
+# Generic U599ZJTxQ
+GenU5.menu.pnum.GENERIC_U599ZJTXQ=Generic U599ZJTxQ
+GenU5.menu.pnum.GENERIC_U599ZJTXQ.upload.maximum_size=4194304
+GenU5.menu.pnum.GENERIC_U599ZJTXQ.upload.maximum_data_size=2555904
+GenU5.menu.pnum.GENERIC_U599ZJTXQ.build.board=GENERIC_U599ZJTXQ
+GenU5.menu.pnum.GENERIC_U599ZJTXQ.build.product_line=STM32U599xx
+GenU5.menu.pnum.GENERIC_U599ZJTXQ.build.variant=STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ
+GenU5.menu.pnum.GENERIC_U599ZJTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U599.svd
+
+# Generic U5A5ZJTxQ
+GenU5.menu.pnum.GENERIC_U5A5ZJTXQ=Generic U5A5ZJTxQ
+GenU5.menu.pnum.GENERIC_U5A5ZJTXQ.upload.maximum_size=4194304
+GenU5.menu.pnum.GENERIC_U5A5ZJTXQ.upload.maximum_data_size=2555904
+GenU5.menu.pnum.GENERIC_U5A5ZJTXQ.build.board=GENERIC_U5A5ZJTXQ
+GenU5.menu.pnum.GENERIC_U5A5ZJTXQ.build.product_line=STM32U5A5xx
+GenU5.menu.pnum.GENERIC_U5A5ZJTXQ.build.variant=STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ
+GenU5.menu.pnum.GENERIC_U5A5ZJTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5A5.svd
+
+# Generic U5A9ZJTxQ
+GenU5.menu.pnum.GENERIC_U5A9ZJTXQ=Generic U5A9ZJTxQ
+GenU5.menu.pnum.GENERIC_U5A9ZJTXQ.upload.maximum_size=4194304
+GenU5.menu.pnum.GENERIC_U5A9ZJTXQ.upload.maximum_data_size=2555904
+GenU5.menu.pnum.GENERIC_U5A9ZJTXQ.build.board=GENERIC_U5A9ZJTXQ
+GenU5.menu.pnum.GENERIC_U5A9ZJTXQ.build.product_line=STM32U5A9xx
+GenU5.menu.pnum.GENERIC_U5A9ZJTXQ.build.variant=STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ
+GenU5.menu.pnum.GENERIC_U5A9ZJTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U5A9.svd
+
# Upload menu
GenU5.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD)
GenU5.menu.upload_method.swdMethod.upload.protocol=swd
diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake
index 24a946c9dd..89e79e252b 100644
--- a/cmake/boards_db.cmake
+++ b/cmake/boards_db.cmake
@@ -93548,6 +93548,170 @@ target_compile_options(GENERIC_L412KBUX_xusb_HSFS INTERFACE
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
)
+# GENERIC_L412RBIXP
+# -----------------------------------------------------------------------------
+
+set(GENERIC_L412RBIXP_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L4xx/L412RB(I-T)xP")
+set(GENERIC_L412RBIXP_MAXSIZE 131072)
+set(GENERIC_L412RBIXP_MAXDATASIZE 40960)
+set(GENERIC_L412RBIXP_MCU cortex-m4)
+set(GENERIC_L412RBIXP_FPCONF "-")
+add_library(GENERIC_L412RBIXP INTERFACE)
+target_compile_options(GENERIC_L412RBIXP INTERFACE
+ "SHELL:-DSTM32L412xx "
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_L412RBIXP_MCU}
+)
+target_compile_definitions(GENERIC_L412RBIXP INTERFACE
+ "STM32L4xx"
+ "ARDUINO_GENERIC_L412RBIXP"
+ "BOARD_NAME=\"GENERIC_L412RBIXP\""
+ "BOARD_ID=GENERIC_L412RBIXP"
+ "VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_L412RBIXP INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L4xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/
+ ${GENERIC_L412RBIXP_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_L412RBIXP INTERFACE
+ "LINKER:--default-script=${GENERIC_L412RBIXP_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=131072"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=40960"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_L412RBIXP_MCU}
+)
+
+add_library(GENERIC_L412RBIXP_serial_disabled INTERFACE)
+target_compile_options(GENERIC_L412RBIXP_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L412RBIXP_serial_generic INTERFACE)
+target_compile_options(GENERIC_L412RBIXP_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_L412RBIXP_serial_none INTERFACE)
+target_compile_options(GENERIC_L412RBIXP_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_L412RBIXP_usb_CDC INTERFACE)
+target_compile_options(GENERIC_L412RBIXP_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_L412RBIXP_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_L412RBIXP_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_L412RBIXP_usb_HID INTERFACE)
+target_compile_options(GENERIC_L412RBIXP_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_L412RBIXP_usb_none INTERFACE)
+target_compile_options(GENERIC_L412RBIXP_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L412RBIXP_xusb_FS INTERFACE)
+target_compile_options(GENERIC_L412RBIXP_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L412RBIXP_xusb_HS INTERFACE)
+target_compile_options(GENERIC_L412RBIXP_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_L412RBIXP_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_L412RBIXP_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
+# GENERIC_L412RBTXP
+# -----------------------------------------------------------------------------
+
+set(GENERIC_L412RBTXP_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L4xx/L412RB(I-T)xP")
+set(GENERIC_L412RBTXP_MAXSIZE 131072)
+set(GENERIC_L412RBTXP_MAXDATASIZE 40960)
+set(GENERIC_L412RBTXP_MCU cortex-m4)
+set(GENERIC_L412RBTXP_FPCONF "-")
+add_library(GENERIC_L412RBTXP INTERFACE)
+target_compile_options(GENERIC_L412RBTXP INTERFACE
+ "SHELL:-DSTM32L412xx "
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_L412RBTXP_MCU}
+)
+target_compile_definitions(GENERIC_L412RBTXP INTERFACE
+ "STM32L4xx"
+ "ARDUINO_GENERIC_L412RBTXP"
+ "BOARD_NAME=\"GENERIC_L412RBTXP\""
+ "BOARD_ID=GENERIC_L412RBTXP"
+ "VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_L412RBTXP INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L4xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/
+ ${GENERIC_L412RBTXP_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_L412RBTXP INTERFACE
+ "LINKER:--default-script=${GENERIC_L412RBTXP_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=131072"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=40960"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_L412RBTXP_MCU}
+)
+
+add_library(GENERIC_L412RBTXP_serial_disabled INTERFACE)
+target_compile_options(GENERIC_L412RBTXP_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L412RBTXP_serial_generic INTERFACE)
+target_compile_options(GENERIC_L412RBTXP_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_L412RBTXP_serial_none INTERFACE)
+target_compile_options(GENERIC_L412RBTXP_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_L412RBTXP_usb_CDC INTERFACE)
+target_compile_options(GENERIC_L412RBTXP_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_L412RBTXP_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_L412RBTXP_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_L412RBTXP_usb_HID INTERFACE)
+target_compile_options(GENERIC_L412RBTXP_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_L412RBTXP_usb_none INTERFACE)
+target_compile_options(GENERIC_L412RBTXP_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L412RBTXP_xusb_FS INTERFACE)
+target_compile_options(GENERIC_L412RBTXP_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L412RBTXP_xusb_HS INTERFACE)
+target_compile_options(GENERIC_L412RBTXP_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_L412RBTXP_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_L412RBTXP_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
# GENERIC_L422KBTX
# -----------------------------------------------------------------------------
@@ -100108,6 +100272,170 @@ target_compile_options(GENERIC_L4S9ZIYX_xusb_HSFS INTERFACE
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
)
+# GENERIC_L552QCIXQ
+# -----------------------------------------------------------------------------
+
+set(GENERIC_L552QCIXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ")
+set(GENERIC_L552QCIXQ_MAXSIZE 262144)
+set(GENERIC_L552QCIXQ_MAXDATASIZE 262144)
+set(GENERIC_L552QCIXQ_MCU cortex-m33)
+set(GENERIC_L552QCIXQ_FPCONF "-")
+add_library(GENERIC_L552QCIXQ INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ INTERFACE
+ "SHELL:-DSTM32L552xx "
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_L552QCIXQ_MCU}
+)
+target_compile_definitions(GENERIC_L552QCIXQ INTERFACE
+ "STM32L5xx"
+ "ARDUINO_GENERIC_L552QCIXQ"
+ "BOARD_NAME=\"GENERIC_L552QCIXQ\""
+ "BOARD_ID=GENERIC_L552QCIXQ"
+ "VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_L552QCIXQ INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L5xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/
+ ${GENERIC_L552QCIXQ_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_L552QCIXQ INTERFACE
+ "LINKER:--default-script=${GENERIC_L552QCIXQ_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=262144"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=262144"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_L552QCIXQ_MCU}
+)
+
+add_library(GENERIC_L552QCIXQ_serial_disabled INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L552QCIXQ_serial_generic INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_L552QCIXQ_serial_none INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_L552QCIXQ_usb_CDC INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_L552QCIXQ_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_L552QCIXQ_usb_HID INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_L552QCIXQ_usb_none INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L552QCIXQ_xusb_FS INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L552QCIXQ_xusb_HS INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_L552QCIXQ_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_L552QCIXQ_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
+# GENERIC_L552QEIXQ
+# -----------------------------------------------------------------------------
+
+set(GENERIC_L552QEIXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ")
+set(GENERIC_L552QEIXQ_MAXSIZE 524288)
+set(GENERIC_L552QEIXQ_MAXDATASIZE 262144)
+set(GENERIC_L552QEIXQ_MCU cortex-m33)
+set(GENERIC_L552QEIXQ_FPCONF "-")
+add_library(GENERIC_L552QEIXQ INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ INTERFACE
+ "SHELL:-DSTM32L552xx "
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_L552QEIXQ_MCU}
+)
+target_compile_definitions(GENERIC_L552QEIXQ INTERFACE
+ "STM32L5xx"
+ "ARDUINO_GENERIC_L552QEIXQ"
+ "BOARD_NAME=\"GENERIC_L552QEIXQ\""
+ "BOARD_ID=GENERIC_L552QEIXQ"
+ "VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_L552QEIXQ INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L5xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/
+ ${GENERIC_L552QEIXQ_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_L552QEIXQ INTERFACE
+ "LINKER:--default-script=${GENERIC_L552QEIXQ_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=524288"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=262144"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_L552QEIXQ_MCU}
+)
+
+add_library(GENERIC_L552QEIXQ_serial_disabled INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L552QEIXQ_serial_generic INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_L552QEIXQ_serial_none INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_L552QEIXQ_usb_CDC INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_L552QEIXQ_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_L552QEIXQ_usb_HID INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_L552QEIXQ_usb_none INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L552QEIXQ_xusb_FS INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L552QEIXQ_xusb_HS INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_L552QEIXQ_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_L552QEIXQ_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
# GENERIC_L552ZCTXQ
# -----------------------------------------------------------------------------
@@ -100272,6 +100600,88 @@ target_compile_options(GENERIC_L552ZETXQ_xusb_HSFS INTERFACE
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
)
+# GENERIC_L562QEIXQ
+# -----------------------------------------------------------------------------
+
+set(GENERIC_L562QEIXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ")
+set(GENERIC_L562QEIXQ_MAXSIZE 524288)
+set(GENERIC_L562QEIXQ_MAXDATASIZE 196608)
+set(GENERIC_L562QEIXQ_MCU cortex-m33)
+set(GENERIC_L562QEIXQ_FPCONF "-")
+add_library(GENERIC_L562QEIXQ INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ INTERFACE
+ "SHELL:-DSTM32L562xx "
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_L562QEIXQ_MCU}
+)
+target_compile_definitions(GENERIC_L562QEIXQ INTERFACE
+ "STM32L5xx"
+ "ARDUINO_GENERIC_L562QEIXQ"
+ "BOARD_NAME=\"GENERIC_L562QEIXQ\""
+ "BOARD_ID=GENERIC_L562QEIXQ"
+ "VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_L562QEIXQ INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L5xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/
+ ${GENERIC_L562QEIXQ_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_L562QEIXQ INTERFACE
+ "LINKER:--default-script=${GENERIC_L562QEIXQ_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=524288"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=196608"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_L562QEIXQ_MCU}
+)
+
+add_library(GENERIC_L562QEIXQ_serial_disabled INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L562QEIXQ_serial_generic INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_L562QEIXQ_serial_none INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_L562QEIXQ_usb_CDC INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_L562QEIXQ_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_L562QEIXQ_usb_HID INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_L562QEIXQ_usb_none INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L562QEIXQ_xusb_FS INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_L562QEIXQ_xusb_HS INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_L562QEIXQ_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_L562QEIXQ_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
# GENERIC_L562ZETXQ
# -----------------------------------------------------------------------------
@@ -102241,180 +102651,672 @@ add_library(GENERIC_U585CITX_usb_none INTERFACE)
target_compile_options(GENERIC_U585CITX_usb_none INTERFACE
"SHELL:"
)
-add_library(GENERIC_U585CITX_xusb_FS INTERFACE)
-target_compile_options(GENERIC_U585CITX_xusb_FS INTERFACE
+add_library(GENERIC_U585CITX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_U585CITX_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_U585CITX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_U585CITX_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_U585CITX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_U585CITX_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
+# GENERIC_U585CIUX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_U585CIUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)")
+set(GENERIC_U585CIUX_MAXSIZE 2097152)
+set(GENERIC_U585CIUX_MAXDATASIZE 786432)
+set(GENERIC_U585CIUX_MCU cortex-m33)
+set(GENERIC_U585CIUX_FPCONF "-")
+add_library(GENERIC_U585CIUX INTERFACE)
+target_compile_options(GENERIC_U585CIUX INTERFACE
+ "SHELL:-DSTM32U585xx "
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_U585CIUX_MCU}
+)
+target_compile_definitions(GENERIC_U585CIUX INTERFACE
+ "STM32U5xx"
+ "ARDUINO_GENERIC_U585CIUX"
+ "BOARD_NAME=\"GENERIC_U585CIUX\""
+ "BOARD_ID=GENERIC_U585CIUX"
+ "VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_U585CIUX INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U5xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/
+ ${GENERIC_U585CIUX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_U585CIUX INTERFACE
+ "LINKER:--default-script=${GENERIC_U585CIUX_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=2097152"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=786432"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_U585CIUX_MCU}
+)
+
+add_library(GENERIC_U585CIUX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_U585CIUX_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_U585CIUX_serial_generic INTERFACE)
+target_compile_options(GENERIC_U585CIUX_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_U585CIUX_serial_none INTERFACE)
+target_compile_options(GENERIC_U585CIUX_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_U585CIUX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_U585CIUX_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_U585CIUX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_U585CIUX_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_U585CIUX_usb_HID INTERFACE)
+target_compile_options(GENERIC_U585CIUX_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_U585CIUX_usb_none INTERFACE)
+target_compile_options(GENERIC_U585CIUX_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_U585CIUX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_U585CIUX_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_U585CIUX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_U585CIUX_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_U585CIUX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_U585CIUX_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
+# GENERIC_U585ZITXQ
+# -----------------------------------------------------------------------------
+
+set(GENERIC_U585ZITXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ")
+set(GENERIC_U585ZITXQ_MAXSIZE 2097152)
+set(GENERIC_U585ZITXQ_MAXDATASIZE 786432)
+set(GENERIC_U585ZITXQ_MCU cortex-m33)
+set(GENERIC_U585ZITXQ_FPCONF "-")
+add_library(GENERIC_U585ZITXQ INTERFACE)
+target_compile_options(GENERIC_U585ZITXQ INTERFACE
+ "SHELL:-DSTM32U585xx "
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_U585ZITXQ_MCU}
+)
+target_compile_definitions(GENERIC_U585ZITXQ INTERFACE
+ "STM32U5xx"
+ "ARDUINO_GENERIC_U585ZITXQ"
+ "BOARD_NAME=\"GENERIC_U585ZITXQ\""
+ "BOARD_ID=GENERIC_U585ZITXQ"
+ "VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_U585ZITXQ INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U5xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/
+ ${GENERIC_U585ZITXQ_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_U585ZITXQ INTERFACE
+ "LINKER:--default-script=${GENERIC_U585ZITXQ_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=2097152"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=786432"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_U585ZITXQ_MCU}
+)
+
+add_library(GENERIC_U585ZITXQ_serial_disabled INTERFACE)
+target_compile_options(GENERIC_U585ZITXQ_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_U585ZITXQ_serial_generic INTERFACE)
+target_compile_options(GENERIC_U585ZITXQ_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_U585ZITXQ_serial_none INTERFACE)
+target_compile_options(GENERIC_U585ZITXQ_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_U585ZITXQ_usb_CDC INTERFACE)
+target_compile_options(GENERIC_U585ZITXQ_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_U585ZITXQ_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_U585ZITXQ_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_U585ZITXQ_usb_HID INTERFACE)
+target_compile_options(GENERIC_U585ZITXQ_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_U585ZITXQ_usb_none INTERFACE)
+target_compile_options(GENERIC_U585ZITXQ_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_U585ZITXQ_xusb_FS INTERFACE)
+target_compile_options(GENERIC_U585ZITXQ_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_U585ZITXQ_xusb_HS INTERFACE)
+target_compile_options(GENERIC_U585ZITXQ_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_U585ZITXQ_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_U585ZITXQ_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
+# GENERIC_U595ZITXQ
+# -----------------------------------------------------------------------------
+
+set(GENERIC_U595ZITXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ")
+set(GENERIC_U595ZITXQ_MAXSIZE 2097152)
+set(GENERIC_U595ZITXQ_MAXDATASIZE 2555904)
+set(GENERIC_U595ZITXQ_MCU cortex-m33)
+set(GENERIC_U595ZITXQ_FPCONF "-")
+add_library(GENERIC_U595ZITXQ INTERFACE)
+target_compile_options(GENERIC_U595ZITXQ INTERFACE
+ "SHELL:-DSTM32U595xx "
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_U595ZITXQ_MCU}
+)
+target_compile_definitions(GENERIC_U595ZITXQ INTERFACE
+ "STM32U5xx"
+ "ARDUINO_GENERIC_U595ZITXQ"
+ "BOARD_NAME=\"GENERIC_U595ZITXQ\""
+ "BOARD_ID=GENERIC_U595ZITXQ"
+ "VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_U595ZITXQ INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U5xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/
+ ${GENERIC_U595ZITXQ_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_U595ZITXQ INTERFACE
+ "LINKER:--default-script=${GENERIC_U595ZITXQ_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=2097152"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=2555904"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_U595ZITXQ_MCU}
+)
+
+add_library(GENERIC_U595ZITXQ_serial_disabled INTERFACE)
+target_compile_options(GENERIC_U595ZITXQ_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_U595ZITXQ_serial_generic INTERFACE)
+target_compile_options(GENERIC_U595ZITXQ_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_U595ZITXQ_serial_none INTERFACE)
+target_compile_options(GENERIC_U595ZITXQ_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_U595ZITXQ_usb_CDC INTERFACE)
+target_compile_options(GENERIC_U595ZITXQ_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_U595ZITXQ_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_U595ZITXQ_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_U595ZITXQ_usb_HID INTERFACE)
+target_compile_options(GENERIC_U595ZITXQ_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_U595ZITXQ_usb_none INTERFACE)
+target_compile_options(GENERIC_U595ZITXQ_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_U595ZITXQ_xusb_FS INTERFACE)
+target_compile_options(GENERIC_U595ZITXQ_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_U595ZITXQ_xusb_HS INTERFACE)
+target_compile_options(GENERIC_U595ZITXQ_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_U595ZITXQ_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_U595ZITXQ_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
+# GENERIC_U595ZJTXQ
+# -----------------------------------------------------------------------------
+
+set(GENERIC_U595ZJTXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ")
+set(GENERIC_U595ZJTXQ_MAXSIZE 4194304)
+set(GENERIC_U595ZJTXQ_MAXDATASIZE 2555904)
+set(GENERIC_U595ZJTXQ_MCU cortex-m33)
+set(GENERIC_U595ZJTXQ_FPCONF "-")
+add_library(GENERIC_U595ZJTXQ INTERFACE)
+target_compile_options(GENERIC_U595ZJTXQ INTERFACE
+ "SHELL:-DSTM32U595xx "
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_U595ZJTXQ_MCU}
+)
+target_compile_definitions(GENERIC_U595ZJTXQ INTERFACE
+ "STM32U5xx"
+ "ARDUINO_GENERIC_U595ZJTXQ"
+ "BOARD_NAME=\"GENERIC_U595ZJTXQ\""
+ "BOARD_ID=GENERIC_U595ZJTXQ"
+ "VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_U595ZJTXQ INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U5xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/
+ ${GENERIC_U595ZJTXQ_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_U595ZJTXQ INTERFACE
+ "LINKER:--default-script=${GENERIC_U595ZJTXQ_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=4194304"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=2555904"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_U595ZJTXQ_MCU}
+)
+
+add_library(GENERIC_U595ZJTXQ_serial_disabled INTERFACE)
+target_compile_options(GENERIC_U595ZJTXQ_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_U595ZJTXQ_serial_generic INTERFACE)
+target_compile_options(GENERIC_U595ZJTXQ_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_U595ZJTXQ_serial_none INTERFACE)
+target_compile_options(GENERIC_U595ZJTXQ_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_U595ZJTXQ_usb_CDC INTERFACE)
+target_compile_options(GENERIC_U595ZJTXQ_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_U595ZJTXQ_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_U595ZJTXQ_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_U595ZJTXQ_usb_HID INTERFACE)
+target_compile_options(GENERIC_U595ZJTXQ_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_U595ZJTXQ_usb_none INTERFACE)
+target_compile_options(GENERIC_U595ZJTXQ_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_U595ZJTXQ_xusb_FS INTERFACE)
+target_compile_options(GENERIC_U595ZJTXQ_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_U595ZJTXQ_xusb_HS INTERFACE)
+target_compile_options(GENERIC_U595ZJTXQ_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_U595ZJTXQ_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_U595ZJTXQ_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
+# GENERIC_U599ZITXQ
+# -----------------------------------------------------------------------------
+
+set(GENERIC_U599ZITXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ")
+set(GENERIC_U599ZITXQ_MAXSIZE 2097152)
+set(GENERIC_U599ZITXQ_MAXDATASIZE 2555904)
+set(GENERIC_U599ZITXQ_MCU cortex-m33)
+set(GENERIC_U599ZITXQ_FPCONF "-")
+add_library(GENERIC_U599ZITXQ INTERFACE)
+target_compile_options(GENERIC_U599ZITXQ INTERFACE
+ "SHELL:-DSTM32U599xx "
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_U599ZITXQ_MCU}
+)
+target_compile_definitions(GENERIC_U599ZITXQ INTERFACE
+ "STM32U5xx"
+ "ARDUINO_GENERIC_U599ZITXQ"
+ "BOARD_NAME=\"GENERIC_U599ZITXQ\""
+ "BOARD_ID=GENERIC_U599ZITXQ"
+ "VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_U599ZITXQ INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U5xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/
+ ${GENERIC_U599ZITXQ_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_U599ZITXQ INTERFACE
+ "LINKER:--default-script=${GENERIC_U599ZITXQ_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=2097152"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=2555904"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_U599ZITXQ_MCU}
+)
+
+add_library(GENERIC_U599ZITXQ_serial_disabled INTERFACE)
+target_compile_options(GENERIC_U599ZITXQ_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_U599ZITXQ_serial_generic INTERFACE)
+target_compile_options(GENERIC_U599ZITXQ_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_U599ZITXQ_serial_none INTERFACE)
+target_compile_options(GENERIC_U599ZITXQ_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_U599ZITXQ_usb_CDC INTERFACE)
+target_compile_options(GENERIC_U599ZITXQ_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_U599ZITXQ_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_U599ZITXQ_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_U599ZITXQ_usb_HID INTERFACE)
+target_compile_options(GENERIC_U599ZITXQ_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_U599ZITXQ_usb_none INTERFACE)
+target_compile_options(GENERIC_U599ZITXQ_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_U599ZITXQ_xusb_FS INTERFACE)
+target_compile_options(GENERIC_U599ZITXQ_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_U599ZITXQ_xusb_HS INTERFACE)
+target_compile_options(GENERIC_U599ZITXQ_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_U599ZITXQ_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_U599ZITXQ_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
+# GENERIC_U599ZJTXQ
+# -----------------------------------------------------------------------------
+
+set(GENERIC_U599ZJTXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ")
+set(GENERIC_U599ZJTXQ_MAXSIZE 4194304)
+set(GENERIC_U599ZJTXQ_MAXDATASIZE 2555904)
+set(GENERIC_U599ZJTXQ_MCU cortex-m33)
+set(GENERIC_U599ZJTXQ_FPCONF "-")
+add_library(GENERIC_U599ZJTXQ INTERFACE)
+target_compile_options(GENERIC_U599ZJTXQ INTERFACE
+ "SHELL:-DSTM32U599xx "
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_U599ZJTXQ_MCU}
+)
+target_compile_definitions(GENERIC_U599ZJTXQ INTERFACE
+ "STM32U5xx"
+ "ARDUINO_GENERIC_U599ZJTXQ"
+ "BOARD_NAME=\"GENERIC_U599ZJTXQ\""
+ "BOARD_ID=GENERIC_U599ZJTXQ"
+ "VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_U599ZJTXQ INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U5xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/
+ ${GENERIC_U599ZJTXQ_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_U599ZJTXQ INTERFACE
+ "LINKER:--default-script=${GENERIC_U599ZJTXQ_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=4194304"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=2555904"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_U599ZJTXQ_MCU}
+)
+
+add_library(GENERIC_U599ZJTXQ_serial_disabled INTERFACE)
+target_compile_options(GENERIC_U599ZJTXQ_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_U599ZJTXQ_serial_generic INTERFACE)
+target_compile_options(GENERIC_U599ZJTXQ_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_U599ZJTXQ_serial_none INTERFACE)
+target_compile_options(GENERIC_U599ZJTXQ_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_U599ZJTXQ_usb_CDC INTERFACE)
+target_compile_options(GENERIC_U599ZJTXQ_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_U599ZJTXQ_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_U599ZJTXQ_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_U599ZJTXQ_usb_HID INTERFACE)
+target_compile_options(GENERIC_U599ZJTXQ_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_U599ZJTXQ_usb_none INTERFACE)
+target_compile_options(GENERIC_U599ZJTXQ_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_U599ZJTXQ_xusb_FS INTERFACE)
+target_compile_options(GENERIC_U599ZJTXQ_xusb_FS INTERFACE
"SHELL:"
)
-add_library(GENERIC_U585CITX_xusb_HS INTERFACE)
-target_compile_options(GENERIC_U585CITX_xusb_HS INTERFACE
+add_library(GENERIC_U599ZJTXQ_xusb_HS INTERFACE)
+target_compile_options(GENERIC_U599ZJTXQ_xusb_HS INTERFACE
"SHELL:-DUSE_USB_HS"
)
-add_library(GENERIC_U585CITX_xusb_HSFS INTERFACE)
-target_compile_options(GENERIC_U585CITX_xusb_HSFS INTERFACE
+add_library(GENERIC_U599ZJTXQ_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_U599ZJTXQ_xusb_HSFS INTERFACE
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
)
-# GENERIC_U585CIUX
+# GENERIC_U5A5ZJTXQ
# -----------------------------------------------------------------------------
-set(GENERIC_U585CIUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)")
-set(GENERIC_U585CIUX_MAXSIZE 2097152)
-set(GENERIC_U585CIUX_MAXDATASIZE 786432)
-set(GENERIC_U585CIUX_MCU cortex-m33)
-set(GENERIC_U585CIUX_FPCONF "-")
-add_library(GENERIC_U585CIUX INTERFACE)
-target_compile_options(GENERIC_U585CIUX INTERFACE
- "SHELL:-DSTM32U585xx "
+set(GENERIC_U5A5ZJTXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ")
+set(GENERIC_U5A5ZJTXQ_MAXSIZE 4194304)
+set(GENERIC_U5A5ZJTXQ_MAXDATASIZE 2555904)
+set(GENERIC_U5A5ZJTXQ_MCU cortex-m33)
+set(GENERIC_U5A5ZJTXQ_FPCONF "-")
+add_library(GENERIC_U5A5ZJTXQ INTERFACE)
+target_compile_options(GENERIC_U5A5ZJTXQ INTERFACE
+ "SHELL:-DSTM32U5A5xx "
"SHELL:"
"SHELL:"
"SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
- -mcpu=${GENERIC_U585CIUX_MCU}
+ -mcpu=${GENERIC_U5A5ZJTXQ_MCU}
)
-target_compile_definitions(GENERIC_U585CIUX INTERFACE
+target_compile_definitions(GENERIC_U5A5ZJTXQ INTERFACE
"STM32U5xx"
- "ARDUINO_GENERIC_U585CIUX"
- "BOARD_NAME=\"GENERIC_U585CIUX\""
- "BOARD_ID=GENERIC_U585CIUX"
+ "ARDUINO_GENERIC_U5A5ZJTXQ"
+ "BOARD_NAME=\"GENERIC_U5A5ZJTXQ\""
+ "BOARD_ID=GENERIC_U5A5ZJTXQ"
"VARIANT_H=\"variant_generic.h\""
)
-target_include_directories(GENERIC_U585CIUX INTERFACE
+target_include_directories(GENERIC_U5A5ZJTXQ INTERFACE
${CMAKE_CURRENT_LIST_DIR}/../system/STM32U5xx
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/
- ${GENERIC_U585CIUX_VARIANT_PATH}
+ ${GENERIC_U5A5ZJTXQ_VARIANT_PATH}
)
-target_link_options(GENERIC_U585CIUX INTERFACE
- "LINKER:--default-script=${GENERIC_U585CIUX_VARIANT_PATH}/ldscript.ld"
+target_link_options(GENERIC_U5A5ZJTXQ INTERFACE
+ "LINKER:--default-script=${GENERIC_U5A5ZJTXQ_VARIANT_PATH}/ldscript.ld"
"LINKER:--defsym=LD_FLASH_OFFSET=0x0"
- "LINKER:--defsym=LD_MAX_SIZE=2097152"
- "LINKER:--defsym=LD_MAX_DATA_SIZE=786432"
+ "LINKER:--defsym=LD_MAX_SIZE=4194304"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=2555904"
"SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
- -mcpu=${GENERIC_U585CIUX_MCU}
+ -mcpu=${GENERIC_U5A5ZJTXQ_MCU}
)
-add_library(GENERIC_U585CIUX_serial_disabled INTERFACE)
-target_compile_options(GENERIC_U585CIUX_serial_disabled INTERFACE
+add_library(GENERIC_U5A5ZJTXQ_serial_disabled INTERFACE)
+target_compile_options(GENERIC_U5A5ZJTXQ_serial_disabled INTERFACE
"SHELL:"
)
-add_library(GENERIC_U585CIUX_serial_generic INTERFACE)
-target_compile_options(GENERIC_U585CIUX_serial_generic INTERFACE
+add_library(GENERIC_U5A5ZJTXQ_serial_generic INTERFACE)
+target_compile_options(GENERIC_U5A5ZJTXQ_serial_generic INTERFACE
"SHELL:-DHAL_UART_MODULE_ENABLED"
)
-add_library(GENERIC_U585CIUX_serial_none INTERFACE)
-target_compile_options(GENERIC_U585CIUX_serial_none INTERFACE
+add_library(GENERIC_U5A5ZJTXQ_serial_none INTERFACE)
+target_compile_options(GENERIC_U5A5ZJTXQ_serial_none INTERFACE
"SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
)
-add_library(GENERIC_U585CIUX_usb_CDC INTERFACE)
-target_compile_options(GENERIC_U585CIUX_usb_CDC INTERFACE
+add_library(GENERIC_U5A5ZJTXQ_usb_CDC INTERFACE)
+target_compile_options(GENERIC_U5A5ZJTXQ_usb_CDC INTERFACE
"SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
)
-add_library(GENERIC_U585CIUX_usb_CDCgen INTERFACE)
-target_compile_options(GENERIC_U585CIUX_usb_CDCgen INTERFACE
+add_library(GENERIC_U5A5ZJTXQ_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_U5A5ZJTXQ_usb_CDCgen INTERFACE
"SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
)
-add_library(GENERIC_U585CIUX_usb_HID INTERFACE)
-target_compile_options(GENERIC_U585CIUX_usb_HID INTERFACE
+add_library(GENERIC_U5A5ZJTXQ_usb_HID INTERFACE)
+target_compile_options(GENERIC_U5A5ZJTXQ_usb_HID INTERFACE
"SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
)
-add_library(GENERIC_U585CIUX_usb_none INTERFACE)
-target_compile_options(GENERIC_U585CIUX_usb_none INTERFACE
+add_library(GENERIC_U5A5ZJTXQ_usb_none INTERFACE)
+target_compile_options(GENERIC_U5A5ZJTXQ_usb_none INTERFACE
"SHELL:"
)
-add_library(GENERIC_U585CIUX_xusb_FS INTERFACE)
-target_compile_options(GENERIC_U585CIUX_xusb_FS INTERFACE
+add_library(GENERIC_U5A5ZJTXQ_xusb_FS INTERFACE)
+target_compile_options(GENERIC_U5A5ZJTXQ_xusb_FS INTERFACE
"SHELL:"
)
-add_library(GENERIC_U585CIUX_xusb_HS INTERFACE)
-target_compile_options(GENERIC_U585CIUX_xusb_HS INTERFACE
+add_library(GENERIC_U5A5ZJTXQ_xusb_HS INTERFACE)
+target_compile_options(GENERIC_U5A5ZJTXQ_xusb_HS INTERFACE
"SHELL:-DUSE_USB_HS"
)
-add_library(GENERIC_U585CIUX_xusb_HSFS INTERFACE)
-target_compile_options(GENERIC_U585CIUX_xusb_HSFS INTERFACE
+add_library(GENERIC_U5A5ZJTXQ_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_U5A5ZJTXQ_xusb_HSFS INTERFACE
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
)
-# GENERIC_U585ZITXQ
+# GENERIC_U5A9ZJTXQ
# -----------------------------------------------------------------------------
-set(GENERIC_U585ZITXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ")
-set(GENERIC_U585ZITXQ_MAXSIZE 2097152)
-set(GENERIC_U585ZITXQ_MAXDATASIZE 786432)
-set(GENERIC_U585ZITXQ_MCU cortex-m33)
-set(GENERIC_U585ZITXQ_FPCONF "-")
-add_library(GENERIC_U585ZITXQ INTERFACE)
-target_compile_options(GENERIC_U585ZITXQ INTERFACE
- "SHELL:-DSTM32U585xx "
+set(GENERIC_U5A9ZJTXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ")
+set(GENERIC_U5A9ZJTXQ_MAXSIZE 4194304)
+set(GENERIC_U5A9ZJTXQ_MAXDATASIZE 2555904)
+set(GENERIC_U5A9ZJTXQ_MCU cortex-m33)
+set(GENERIC_U5A9ZJTXQ_FPCONF "-")
+add_library(GENERIC_U5A9ZJTXQ INTERFACE)
+target_compile_options(GENERIC_U5A9ZJTXQ INTERFACE
+ "SHELL:-DSTM32U5A9xx "
"SHELL:"
"SHELL:"
"SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
- -mcpu=${GENERIC_U585ZITXQ_MCU}
+ -mcpu=${GENERIC_U5A9ZJTXQ_MCU}
)
-target_compile_definitions(GENERIC_U585ZITXQ INTERFACE
+target_compile_definitions(GENERIC_U5A9ZJTXQ INTERFACE
"STM32U5xx"
- "ARDUINO_GENERIC_U585ZITXQ"
- "BOARD_NAME=\"GENERIC_U585ZITXQ\""
- "BOARD_ID=GENERIC_U585ZITXQ"
+ "ARDUINO_GENERIC_U5A9ZJTXQ"
+ "BOARD_NAME=\"GENERIC_U5A9ZJTXQ\""
+ "BOARD_ID=GENERIC_U5A9ZJTXQ"
"VARIANT_H=\"variant_generic.h\""
)
-target_include_directories(GENERIC_U585ZITXQ INTERFACE
+target_include_directories(GENERIC_U5A9ZJTXQ INTERFACE
${CMAKE_CURRENT_LIST_DIR}/../system/STM32U5xx
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/
- ${GENERIC_U585ZITXQ_VARIANT_PATH}
+ ${GENERIC_U5A9ZJTXQ_VARIANT_PATH}
)
-target_link_options(GENERIC_U585ZITXQ INTERFACE
- "LINKER:--default-script=${GENERIC_U585ZITXQ_VARIANT_PATH}/ldscript.ld"
+target_link_options(GENERIC_U5A9ZJTXQ INTERFACE
+ "LINKER:--default-script=${GENERIC_U5A9ZJTXQ_VARIANT_PATH}/ldscript.ld"
"LINKER:--defsym=LD_FLASH_OFFSET=0x0"
- "LINKER:--defsym=LD_MAX_SIZE=2097152"
- "LINKER:--defsym=LD_MAX_DATA_SIZE=786432"
+ "LINKER:--defsym=LD_MAX_SIZE=4194304"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=2555904"
"SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
- -mcpu=${GENERIC_U585ZITXQ_MCU}
+ -mcpu=${GENERIC_U5A9ZJTXQ_MCU}
)
-add_library(GENERIC_U585ZITXQ_serial_disabled INTERFACE)
-target_compile_options(GENERIC_U585ZITXQ_serial_disabled INTERFACE
+add_library(GENERIC_U5A9ZJTXQ_serial_disabled INTERFACE)
+target_compile_options(GENERIC_U5A9ZJTXQ_serial_disabled INTERFACE
"SHELL:"
)
-add_library(GENERIC_U585ZITXQ_serial_generic INTERFACE)
-target_compile_options(GENERIC_U585ZITXQ_serial_generic INTERFACE
+add_library(GENERIC_U5A9ZJTXQ_serial_generic INTERFACE)
+target_compile_options(GENERIC_U5A9ZJTXQ_serial_generic INTERFACE
"SHELL:-DHAL_UART_MODULE_ENABLED"
)
-add_library(GENERIC_U585ZITXQ_serial_none INTERFACE)
-target_compile_options(GENERIC_U585ZITXQ_serial_none INTERFACE
+add_library(GENERIC_U5A9ZJTXQ_serial_none INTERFACE)
+target_compile_options(GENERIC_U5A9ZJTXQ_serial_none INTERFACE
"SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
)
-add_library(GENERIC_U585ZITXQ_usb_CDC INTERFACE)
-target_compile_options(GENERIC_U585ZITXQ_usb_CDC INTERFACE
+add_library(GENERIC_U5A9ZJTXQ_usb_CDC INTERFACE)
+target_compile_options(GENERIC_U5A9ZJTXQ_usb_CDC INTERFACE
"SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
)
-add_library(GENERIC_U585ZITXQ_usb_CDCgen INTERFACE)
-target_compile_options(GENERIC_U585ZITXQ_usb_CDCgen INTERFACE
+add_library(GENERIC_U5A9ZJTXQ_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_U5A9ZJTXQ_usb_CDCgen INTERFACE
"SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
)
-add_library(GENERIC_U585ZITXQ_usb_HID INTERFACE)
-target_compile_options(GENERIC_U585ZITXQ_usb_HID INTERFACE
+add_library(GENERIC_U5A9ZJTXQ_usb_HID INTERFACE)
+target_compile_options(GENERIC_U5A9ZJTXQ_usb_HID INTERFACE
"SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
)
-add_library(GENERIC_U585ZITXQ_usb_none INTERFACE)
-target_compile_options(GENERIC_U585ZITXQ_usb_none INTERFACE
+add_library(GENERIC_U5A9ZJTXQ_usb_none INTERFACE)
+target_compile_options(GENERIC_U5A9ZJTXQ_usb_none INTERFACE
"SHELL:"
)
-add_library(GENERIC_U585ZITXQ_xusb_FS INTERFACE)
-target_compile_options(GENERIC_U585ZITXQ_xusb_FS INTERFACE
+add_library(GENERIC_U5A9ZJTXQ_xusb_FS INTERFACE)
+target_compile_options(GENERIC_U5A9ZJTXQ_xusb_FS INTERFACE
"SHELL:"
)
-add_library(GENERIC_U585ZITXQ_xusb_HS INTERFACE)
-target_compile_options(GENERIC_U585ZITXQ_xusb_HS INTERFACE
+add_library(GENERIC_U5A9ZJTXQ_xusb_HS INTERFACE)
+target_compile_options(GENERIC_U5A9ZJTXQ_xusb_HS INTERFACE
"SHELL:-DUSE_USB_HS"
)
-add_library(GENERIC_U585ZITXQ_xusb_HSFS INTERFACE)
-target_compile_options(GENERIC_U585ZITXQ_xusb_HSFS INTERFACE
+add_library(GENERIC_U5A9ZJTXQ_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_U5A9ZJTXQ_xusb_HSFS INTERFACE
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
)
@@ -106718,6 +107620,88 @@ target_compile_options(NUCLEO_F401RE_xusb_HSFS INTERFACE
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
)
+# NUCLEO_F410RB
+# -----------------------------------------------------------------------------
+
+set(NUCLEO_F410RB_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F4xx/F410R(8-B)(I-T)")
+set(NUCLEO_F410RB_MAXSIZE 131072)
+set(NUCLEO_F410RB_MAXDATASIZE 32768)
+set(NUCLEO_F410RB_MCU cortex-m4)
+set(NUCLEO_F410RB_FPCONF "fpv4-sp-d16-hard")
+add_library(NUCLEO_F410RB INTERFACE)
+target_compile_options(NUCLEO_F410RB INTERFACE
+ "SHELL:-DSTM32F410Rx "
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${NUCLEO_F410RB_MCU}
+)
+target_compile_definitions(NUCLEO_F410RB INTERFACE
+ "STM32F4xx"
+ "ARDUINO_NUCLEO_F410RB"
+ "BOARD_NAME=\"NUCLEO_F410RB\""
+ "BOARD_ID=NUCLEO_F410RB"
+ "VARIANT_H=\"variant_NUCLEO_F410RB.h\""
+)
+target_include_directories(NUCLEO_F410RB INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32F4xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/
+ ${NUCLEO_F410RB_VARIANT_PATH}
+)
+
+target_link_options(NUCLEO_F410RB INTERFACE
+ "LINKER:--default-script=${NUCLEO_F410RB_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=131072"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=32768"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${NUCLEO_F410RB_MCU}
+)
+
+add_library(NUCLEO_F410RB_serial_disabled INTERFACE)
+target_compile_options(NUCLEO_F410RB_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(NUCLEO_F410RB_serial_generic INTERFACE)
+target_compile_options(NUCLEO_F410RB_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(NUCLEO_F410RB_serial_none INTERFACE)
+target_compile_options(NUCLEO_F410RB_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(NUCLEO_F410RB_usb_CDC INTERFACE)
+target_compile_options(NUCLEO_F410RB_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(NUCLEO_F410RB_usb_CDCgen INTERFACE)
+target_compile_options(NUCLEO_F410RB_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(NUCLEO_F410RB_usb_HID INTERFACE)
+target_compile_options(NUCLEO_F410RB_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(NUCLEO_F410RB_usb_none INTERFACE)
+target_compile_options(NUCLEO_F410RB_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(NUCLEO_F410RB_xusb_FS INTERFACE)
+target_compile_options(NUCLEO_F410RB_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(NUCLEO_F410RB_xusb_HS INTERFACE)
+target_compile_options(NUCLEO_F410RB_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(NUCLEO_F410RB_xusb_HSFS INTERFACE)
+target_compile_options(NUCLEO_F410RB_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
# NUCLEO_F411RE
# -----------------------------------------------------------------------------
@@ -109260,6 +110244,88 @@ target_compile_options(NUCLEO_L412KB_xusb_HSFS INTERFACE
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
)
+# NUCLEO_L412RB_P
+# -----------------------------------------------------------------------------
+
+set(NUCLEO_L412RB_P_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L4xx/L412RB(I-T)xP")
+set(NUCLEO_L412RB_P_MAXSIZE 131072)
+set(NUCLEO_L412RB_P_MAXDATASIZE 40960)
+set(NUCLEO_L412RB_P_MCU cortex-m4)
+set(NUCLEO_L412RB_P_FPCONF "fpv4-sp-d16-hard")
+add_library(NUCLEO_L412RB_P INTERFACE)
+target_compile_options(NUCLEO_L412RB_P INTERFACE
+ "SHELL:-DSTM32L412xx "
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${NUCLEO_L412RB_P_MCU}
+)
+target_compile_definitions(NUCLEO_L412RB_P INTERFACE
+ "STM32L4xx"
+ "ARDUINO_NUCLEO_L412RB_P"
+ "BOARD_NAME=\"NUCLEO_L412RB_P\""
+ "BOARD_ID=NUCLEO_L412RB_P"
+ "VARIANT_H=\"variant_NUCLEO_L412RB_P.h\""
+)
+target_include_directories(NUCLEO_L412RB_P INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L4xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/
+ ${NUCLEO_L412RB_P_VARIANT_PATH}
+)
+
+target_link_options(NUCLEO_L412RB_P INTERFACE
+ "LINKER:--default-script=${NUCLEO_L412RB_P_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=131072"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=40960"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${NUCLEO_L412RB_P_MCU}
+)
+
+add_library(NUCLEO_L412RB_P_serial_disabled INTERFACE)
+target_compile_options(NUCLEO_L412RB_P_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(NUCLEO_L412RB_P_serial_generic INTERFACE)
+target_compile_options(NUCLEO_L412RB_P_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(NUCLEO_L412RB_P_serial_none INTERFACE)
+target_compile_options(NUCLEO_L412RB_P_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(NUCLEO_L412RB_P_usb_CDC INTERFACE)
+target_compile_options(NUCLEO_L412RB_P_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(NUCLEO_L412RB_P_usb_CDCgen INTERFACE)
+target_compile_options(NUCLEO_L412RB_P_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(NUCLEO_L412RB_P_usb_HID INTERFACE)
+target_compile_options(NUCLEO_L412RB_P_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(NUCLEO_L412RB_P_usb_none INTERFACE)
+target_compile_options(NUCLEO_L412RB_P_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(NUCLEO_L412RB_P_xusb_FS INTERFACE)
+target_compile_options(NUCLEO_L412RB_P_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(NUCLEO_L412RB_P_xusb_HS INTERFACE)
+target_compile_options(NUCLEO_L412RB_P_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(NUCLEO_L412RB_P_xusb_HSFS INTERFACE)
+target_compile_options(NUCLEO_L412RB_P_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
# NUCLEO_L432KC
# -----------------------------------------------------------------------------
@@ -110326,6 +111392,88 @@ target_compile_options(NUCLEO_U575ZI_Q_xusb_HSFS INTERFACE
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
)
+# NUCLEO_U5A5ZJ_Q
+# -----------------------------------------------------------------------------
+
+set(NUCLEO_U5A5ZJ_Q_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ")
+set(NUCLEO_U5A5ZJ_Q_MAXSIZE 4194304)
+set(NUCLEO_U5A5ZJ_Q_MAXDATASIZE 2555904)
+set(NUCLEO_U5A5ZJ_Q_MCU cortex-m33)
+set(NUCLEO_U5A5ZJ_Q_FPCONF "fpv4-sp-d16-hard")
+add_library(NUCLEO_U5A5ZJ_Q INTERFACE)
+target_compile_options(NUCLEO_U5A5ZJ_Q INTERFACE
+ "SHELL:-DSTM32U5A5xx "
+ "SHELL:-DCUSTOM_PERIPHERAL_PINS"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${NUCLEO_U5A5ZJ_Q_MCU}
+)
+target_compile_definitions(NUCLEO_U5A5ZJ_Q INTERFACE
+ "STM32U5xx"
+ "ARDUINO_NUCLEO_U5A5ZJ_Q"
+ "BOARD_NAME=\"NUCLEO_U5A5ZJ_Q\""
+ "BOARD_ID=NUCLEO_U5A5ZJ_Q"
+ "VARIANT_H=\"variant_NUCLEO_U5A5ZJ_Q.h\""
+)
+target_include_directories(NUCLEO_U5A5ZJ_Q INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U5xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U5xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/
+ ${NUCLEO_U5A5ZJ_Q_VARIANT_PATH}
+)
+
+target_link_options(NUCLEO_U5A5ZJ_Q INTERFACE
+ "LINKER:--default-script=${NUCLEO_U5A5ZJ_Q_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=4194304"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=2555904"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${NUCLEO_U5A5ZJ_Q_MCU}
+)
+
+add_library(NUCLEO_U5A5ZJ_Q_serial_disabled INTERFACE)
+target_compile_options(NUCLEO_U5A5ZJ_Q_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(NUCLEO_U5A5ZJ_Q_serial_generic INTERFACE)
+target_compile_options(NUCLEO_U5A5ZJ_Q_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(NUCLEO_U5A5ZJ_Q_serial_none INTERFACE)
+target_compile_options(NUCLEO_U5A5ZJ_Q_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(NUCLEO_U5A5ZJ_Q_usb_CDC INTERFACE)
+target_compile_options(NUCLEO_U5A5ZJ_Q_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(NUCLEO_U5A5ZJ_Q_usb_CDCgen INTERFACE)
+target_compile_options(NUCLEO_U5A5ZJ_Q_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(NUCLEO_U5A5ZJ_Q_usb_HID INTERFACE)
+target_compile_options(NUCLEO_U5A5ZJ_Q_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(NUCLEO_U5A5ZJ_Q_usb_none INTERFACE)
+target_compile_options(NUCLEO_U5A5ZJ_Q_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(NUCLEO_U5A5ZJ_Q_xusb_FS INTERFACE)
+target_compile_options(NUCLEO_U5A5ZJ_Q_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(NUCLEO_U5A5ZJ_Q_xusb_HS INTERFACE)
+target_compile_options(NUCLEO_U5A5ZJ_Q_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(NUCLEO_U5A5ZJ_Q_xusb_HSFS INTERFACE)
+target_compile_options(NUCLEO_U5A5ZJ_Q_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
# NUCLEO_WB15CC
# -----------------------------------------------------------------------------
@@ -112664,6 +113812,88 @@ target_compile_options(STM32H747I_DISCO_xusb_HSFS INTERFACE
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
)
+# STM32L562E_DK
+# -----------------------------------------------------------------------------
+
+set(STM32L562E_DK_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ")
+set(STM32L562E_DK_MAXSIZE 524288)
+set(STM32L562E_DK_MAXDATASIZE 196608)
+set(STM32L562E_DK_MCU cortex-m33)
+set(STM32L562E_DK_FPCONF "fpv4-sp-d16-hard")
+add_library(STM32L562E_DK INTERFACE)
+target_compile_options(STM32L562E_DK INTERFACE
+ "SHELL:-DSTM32L562xx "
+ "SHELL:-DCUSTOM_PERIPHERAL_PINS"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${STM32L562E_DK_MCU}
+)
+target_compile_definitions(STM32L562E_DK INTERFACE
+ "STM32L5xx"
+ "ARDUINO_STM32L562E_DK"
+ "BOARD_NAME=\"STM32L562E_DK\""
+ "BOARD_ID=STM32L562E_DK"
+ "VARIANT_H=\"variant_STM32L562E_DK.h\""
+)
+target_include_directories(STM32L562E_DK INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L5xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/
+ ${STM32L562E_DK_VARIANT_PATH}
+)
+
+target_link_options(STM32L562E_DK INTERFACE
+ "LINKER:--default-script=${STM32L562E_DK_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=524288"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=196608"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${STM32L562E_DK_MCU}
+)
+
+add_library(STM32L562E_DK_serial_disabled INTERFACE)
+target_compile_options(STM32L562E_DK_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(STM32L562E_DK_serial_generic INTERFACE)
+target_compile_options(STM32L562E_DK_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(STM32L562E_DK_serial_none INTERFACE)
+target_compile_options(STM32L562E_DK_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(STM32L562E_DK_usb_CDC INTERFACE)
+target_compile_options(STM32L562E_DK_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(STM32L562E_DK_usb_CDCgen INTERFACE)
+target_compile_options(STM32L562E_DK_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(STM32L562E_DK_usb_HID INTERFACE)
+target_compile_options(STM32L562E_DK_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(STM32L562E_DK_usb_none INTERFACE)
+target_compile_options(STM32L562E_DK_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(STM32L562E_DK_xusb_FS INTERFACE)
+target_compile_options(STM32L562E_DK_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(STM32L562E_DK_xusb_HS INTERFACE)
+target_compile_options(STM32L562E_DK_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(STM32L562E_DK_xusb_HSFS INTERFACE)
+target_compile_options(STM32L562E_DK_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
# STM32MP157A_DK1
# -----------------------------------------------------------------------------
diff --git a/cores/arduino/HardwareSerial.cpp b/cores/arduino/HardwareSerial.cpp
index 4dd8fd02a4..cde5cab7e0 100644
--- a/cores/arduino/HardwareSerial.cpp
+++ b/cores/arduino/HardwareSerial.cpp
@@ -446,13 +446,17 @@ void HardwareSerial::begin(unsigned long baud, byte config)
break;
}
- uart_init(&_serial, (uint32_t)baud, databits, parity, stopbits, _rx_invert, _tx_invert, _data_invert);
- enableHalfDuplexRx();
- uart_attach_rx_callback(&_serial, _rx_complete_irq);
+ _ready = uart_init(&_serial, (uint32_t)baud, databits, parity, stopbits, _rx_invert, _tx_invert, _data_invert);
+ if (_ready) {
+ enableHalfDuplexRx();
+ uart_attach_rx_callback(&_serial, _rx_complete_irq);
+ }
}
void HardwareSerial::end()
{
+ _ready = false;
+
// wait for transmission of outgoing data
flush(TX_TIMEOUT);
diff --git a/cores/arduino/HardwareSerial.h b/cores/arduino/HardwareSerial.h
index 3ed29a873d..be670e9540 100644
--- a/cores/arduino/HardwareSerial.h
+++ b/cores/arduino/HardwareSerial.h
@@ -146,7 +146,7 @@ class HardwareSerial : public Stream {
using Print::write; // pull in write(str) from Print
operator bool()
{
- return true;
+ return _ready;
}
void setRx(uint32_t _rx);
@@ -189,6 +189,7 @@ class HardwareSerial : public Stream {
#endif // HAL_UART_MODULE_ENABLED && !HAL_UART_MODULE_ONLY
private:
+ bool _ready;
bool _rx_enabled;
uint8_t _config;
unsigned long _baud;
diff --git a/libraries/SrcWrapper/inc/uart.h b/libraries/SrcWrapper/inc/uart.h
index 7f99d498e7..5d681407f8 100644
--- a/libraries/SrcWrapper/inc/uart.h
+++ b/libraries/SrcWrapper/inc/uart.h
@@ -255,7 +255,7 @@ struct serial_s {
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
-void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t parity, uint32_t stopbits, bool rx_invert, bool tx_invert, bool data_invert);
+bool uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t parity, uint32_t stopbits, bool rx_invert, bool tx_invert, bool data_invert);
void uart_deinit(serial_t *obj);
#if defined(HAL_PWR_MODULE_ENABLED) && (defined(UART_IT_WUF) || defined(LPUART1_BASE))
void uart_config_lowpower(serial_t *obj);
diff --git a/libraries/SrcWrapper/src/stm32/uart.c b/libraries/SrcWrapper/src/stm32/uart.c
index 4aaa3f0e2e..d854061655 100644
--- a/libraries/SrcWrapper/src/stm32/uart.c
+++ b/libraries/SrcWrapper/src/stm32/uart.c
@@ -113,12 +113,12 @@ serial_t *get_serial_obj(UART_HandleTypeDef *huart)
/**
* @brief Function called to initialize the uart interface
* @param obj : pointer to serial_t structure
- * @retval None
+ * @retval boolean status
*/
-void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t parity, uint32_t stopbits, bool rx_invert, bool tx_invert, bool data_invert)
+bool uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t parity, uint32_t stopbits, bool rx_invert, bool tx_invert, bool data_invert)
{
if (obj == NULL) {
- return;
+ return false;
}
UART_HandleTypeDef *huart = &(obj->handle);
@@ -143,28 +143,28 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par
if (obj != &serial_debug) {
core_debug("ERROR: [U(S)ART] Tx pin has no peripheral!\n");
}
- return;
+ return false;
}
/* Pin Rx must not be NP if not half-duplex */
if ((obj->pin_rx != NC) && (uart_rx == NP) && (uart_rx_swap == NP)) {
if (obj != &serial_debug) {
core_debug("ERROR: [U(S)ART] Rx pin has no peripheral!\n");
}
- return;
+ return false;
}
/* Pin RTS must not be NP if flow control is enabled */
if ((obj->pin_rts != NC) && (uart_rts == NP)) {
if (obj != &serial_debug) {
core_debug("ERROR: [U(S)ART] RTS pin has no peripheral!\n");
}
- return;
+ return false;
}
/* Pin CTS must not be NP if flow control is enabled */
if ((obj->pin_cts != NC) && (uart_cts == NP)) {
if (obj != &serial_debug) {
core_debug("ERROR: [U(S)ART] CTS pin has no peripheral!\n");
}
- return;
+ return false;
}
/*
@@ -184,7 +184,7 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par
if (obj != &serial_debug) {
core_debug("ERROR: [U(S)ART] Rx/Tx/RTS/CTS pins peripherals mismatch!\n");
}
- return;
+ return false;
}
/* Enable USART clock */
@@ -364,6 +364,12 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par
obj->irq = UART12_IRQn;
}
#endif
+ else {
+ if (obj != &serial_debug) {
+ core_debug("ERROR: [U(S)ART] Peripheral not supported!\n");
+ }
+ return false;
+ }
/* Configure UART GPIO pins */
#if defined(UART_ADVFEATURE_SWAP_INIT)
uint32_t pin_swap = UART_ADVFEATURE_SWAP_DISABLE;
@@ -432,6 +438,10 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par
huart->AdvancedInit.DataInvert = UART_ADVFEATURE_DATAINV_ENABLE;
}
#endif
+#else /* UART_ADVFEATURE_NO_INIT */
+ UNUSED(rx_invert);
+ UNUSED(tx_invert);
+ UNUSED(data_invert);
#endif
#ifdef UART_ONE_BIT_SAMPLE_DISABLE
huart->Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
@@ -468,10 +478,10 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par
/* Trying default LPUART clock source */
if ((uart_rx == NP) && (uart_rx_swap == NP)) {
if (HAL_HalfDuplex_Init(huart) == HAL_OK) {
- return;
+ return true;
}
} else if (HAL_UART_Init(huart) == HAL_OK) {
- return;
+ return true;
}
/* Trying to change LPUART clock source */
/* If baudrate is lower than or equal to 9600 try to change to LSE */
@@ -494,10 +504,10 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par
#endif
if ((uart_rx == NP) && (uart_rx_swap == NP)) {
if (HAL_HalfDuplex_Init(huart) == HAL_OK) {
- return;
+ return true;
}
} else if (HAL_UART_Init(huart) == HAL_OK) {
- return;
+ return true;
}
}
}
@@ -517,10 +527,10 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par
#endif
if ((uart_rx == NP) && (uart_rx_swap == NP)) {
if (HAL_HalfDuplex_Init(huart) == HAL_OK) {
- return;
+ return true;
}
} else if (HAL_UART_Init(huart) == HAL_OK) {
- return;
+ return true;
}
}
if (obj->uart == LPUART1) {
@@ -544,10 +554,10 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par
#endif
if ((uart_rx == NP) && (uart_rx_swap == NP)) {
if (HAL_HalfDuplex_Init(huart) == HAL_OK) {
- return;
+ return true;
}
} else if (HAL_UART_Init(huart) == HAL_OK) {
- return;
+ return true;
}
#if defined(RCC_LPUART1CLKSOURCE_SYSCLK)
if (obj->uart == LPUART1) {
@@ -569,11 +579,12 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par
if ((uart_rx == NP) && (uart_rx_swap == NP)) {
if (HAL_HalfDuplex_Init(huart) != HAL_OK) {
- return;
+ return false;
}
} else if (HAL_UART_Init(huart) != HAL_OK) {
- return;
+ return false;
}
+ return true;
}
/**
@@ -821,10 +832,11 @@ void uart_config_lowpower(serial_t *obj)
* @note Call only if debug U(S)ART peripheral is not already initialized
* by a Serial instance
* Default config: 8N1
- * @retval None
+ * @retval boolean status
*/
-void uart_debug_init(void)
+bool uart_debug_init(void)
{
+ bool status = false;
if (DEBUG_UART != NP) {
#if defined(DEBUG_PINNAME_TX)
serial_debug.pin_tx = DEBUG_PINNAME_TX;
@@ -832,8 +844,9 @@ void uart_debug_init(void)
serial_debug.pin_tx = pinmap_pin(DEBUG_UART, PinMap_UART_TX);
#endif
/* serial_debug.pin_rx set by default to NC to configure in half duplex mode */
- uart_init(&serial_debug, DEBUG_UART_BAUDRATE, UART_WORDLENGTH_8B, UART_PARITY_NONE, UART_STOPBITS_1, false, false, false);
+ status = uart_init(&serial_debug, DEBUG_UART_BAUDRATE, UART_WORDLENGTH_8B, UART_PARITY_NONE, UART_STOPBITS_1, false, false, false);
}
+ return status;
}
/**
@@ -863,8 +876,7 @@ size_t uart_debug_write(uint8_t *data, uint32_t size)
if (serial_debug.index >= UART_NUM) {
/* DEBUG_UART not initialized */
- uart_debug_init();
- if (serial_debug.index >= UART_NUM) {
+ if (!uart_debug_init()) {
return 0;
}
}
diff --git a/libraries/USBDevice/inc/usbd_conf.h b/libraries/USBDevice/inc/usbd_conf.h
index 14189cff20..a6bac515dd 100644
--- a/libraries/USBDevice/inc/usbd_conf.h
+++ b/libraries/USBDevice/inc/usbd_conf.h
@@ -71,7 +71,7 @@ extern "C" {
#define USB_WKUP_IRQHandler USB_FS_WKUP_IRQHandler
#endif
#endif
-#elif defined(STM32G0xx)
+#elif defined(STM32G0B1xx) || defined(STM32G0C1xx)
#define USB_IRQn USB_UCPD1_2_IRQn
#define USB_IRQHandler USB_UCPD1_2_IRQHandler
#elif defined(STM32C0xx) || defined(STM32H5xx) || defined(STM32U0xx)
diff --git a/variants/STM32C0xx/C071G(8-B)U/generic_clock.c b/variants/STM32C0xx/C071G(8-B)U/generic_clock.c
index 2949052fd4..c20147de69 100644
--- a/variants/STM32C0xx/C071G(8-B)U/generic_clock.c
+++ b/variants/STM32C0xx/C071G(8-B)U/generic_clock.c
@@ -12,6 +12,7 @@
*/
#if defined(ARDUINO_GENERIC_C071G8UX) || defined(ARDUINO_GENERIC_C071GBUX)
#include "pins_arduino.h"
+#include "stm32yyxx_ll_utils.h"
/**
* @brief System Clock Configuration
@@ -20,8 +21,38 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ LL_FLASH_SetLatency(LL_FLASH_LATENCY_1);
+
+ /* HSI configuration and activation */
+ LL_RCC_HSI_Enable();
+ while (LL_RCC_HSI_IsReady() != 1) {
+ }
+
+ LL_RCC_HSI_SetCalibTrimming(64);
+ LL_RCC_SetHSIDiv(LL_RCC_HSI_DIV_1);
+ LL_RCC_HSI48_Enable();
+
+ /* Wait till HSI48 is ready */
+ while (LL_RCC_HSI48_IsReady() != 1) {
+ }
+
+ /* Set AHB prescaler*/
+ LL_RCC_SetAHBPrescaler(LL_RCC_HCLK_DIV_1);
+
+ /* Sysclk activation on the HSI */
+ LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
+ while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
+ }
+
+ /* Set APB1 prescaler*/
+ LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+ /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+ LL_SetSystemCoreClock(48000000);
+
+ /* Update the time base */
+ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32C0xx/C071G(8-B)U/ldscript.ld b/variants/STM32C0xx/C071G(8-B)U/ldscript.ld
new file mode 100644
index 0000000000..9b17805ade
--- /dev/null
+++ b/variants/STM32C0xx/C071G(8-B)U/ldscript.ld
@@ -0,0 +1,187 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32C071G8Ux Device from STM32C0 series
+** 64KBytes FLASH
+** 24KBytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2025 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32F4xx/F410R(8-B)(I-T)/CMakeLists.txt b/variants/STM32F4xx/F410R(8-B)(I-T)/CMakeLists.txt
index 2a4d55b6b1..14f4ef4bc2 100644
--- a/variants/STM32F4xx/F410R(8-B)(I-T)/CMakeLists.txt
+++ b/variants/STM32F4xx/F410R(8-B)(I-T)/CMakeLists.txt
@@ -22,6 +22,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL
generic_clock.c
PeripheralPins.c
variant_generic.cpp
+ variant_NUCLEO_F410RB.cpp
)
target_link_libraries(variant_bin PUBLIC variant_usage)
diff --git a/variants/STM32F4xx/F410R(8-B)(I-T)/variant_NUCLEO_F410RB.cpp b/variants/STM32F4xx/F410R(8-B)(I-T)/variant_NUCLEO_F410RB.cpp
new file mode 100644
index 0000000000..18c8d1d098
--- /dev/null
+++ b/variants/STM32F4xx/F410R(8-B)(I-T)/variant_NUCLEO_F410RB.cpp
@@ -0,0 +1,150 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2025, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#if defined(ARDUINO_NUCLEO_F410RB)
+#include "pins_arduino.h"
+
+// Digital PinName array
+const PinName digitalPin[] = {
+ PA_3,
+ PA_2,
+ PA_10,
+ PB_3,
+ PB_5,
+ PB_4,
+ PB_10,
+ PA_8,
+ PA_9,
+ PC_7,
+ PB_6,
+ PA_7,
+ PA_6,
+ PA_5,
+ PB_9,
+ PB_8,
+ // ST Morpho
+ // CN7 Left Side
+ PC_10,
+ PC_12,
+ NC, //D18 - BOOT0
+ PA_13,
+ PA_14,
+ PA_15,
+ PB_7,
+ PC_13,
+ PC_14,
+ PC_15,
+ PH_0,
+ PH_1,
+ PC_2,
+ PC_3,
+ // CN7 Right Side
+ PC_11,
+ PB_11,
+ // CN10 Left Side
+ PC_9,
+ // CN10 Right side
+ PC_8,
+ PC_6,
+ PC_5,
+ PA_12,
+ PA_11,
+ PB_12,
+ NC, //D39
+ PB_2,
+ PB_1,
+ PB_15,
+ PB_14,
+ PB_13,
+ PC_4,
+ PA_0,
+ PA_1,
+ PA_4,
+ PB_0,
+ PC_1,
+ PC_0
+};
+
+// Analog (Ax) pin number array
+const uint32_t analogInputPin[] = {
+ 46, //A0
+ 47, //A1
+ 48, //A2
+ 49, //A3
+ 50, //A4
+ 51, //A5
+ 11, //A6
+ 12, //A7
+ 13, //A8
+ 28, //A9
+ 29, //A10
+ 35, //A11
+ 41, //A12
+ 45, //A13
+ 0, //A14
+ 1 //A15
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**
+ * @brief System Clock Configuration
+ * SYSCLK = 100MHz for ARDUINO_NUCLEO_F410RB
+ * @param None
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 4;
+ RCC_OscInitStruct.PLL.PLLN = 100;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = 4;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ Error_Handler();
+ }
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32F4xx/F410R(8-B)(I-T)/variant_NUCLEO_F410RB.h b/variants/STM32F4xx/F410R(8-B)(I-T)/variant_NUCLEO_F410RB.h
new file mode 100644
index 0000000000..8e05086ea0
--- /dev/null
+++ b/variants/STM32F4xx/F410R(8-B)(I-T)/variant_NUCLEO_F410RB.h
@@ -0,0 +1,140 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2025, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#pragma once
+
+/*----------------------------------------------------------------------------
+ * STM32 pins number
+ *----------------------------------------------------------------------------*/
+#define PA3 PIN_A14
+#define PA2 PIN_A15
+#define PA10 2
+#define PB3 3
+#define PB5 4
+#define PB4 5
+#define PB10 6
+#define PA8 7
+#define PA9 8
+#define PC7 9
+#define PB6 10
+#define PA7 PIN_A6
+#define PA6 PIN_A7
+#define PA5 PIN_A8 // LD2
+#define PB9 14
+#define PB8 15
+// ST Morpho
+// CN7 Left Side
+#define PC10 16
+#define PC12 17
+// 18 is NC - BOOT0
+#define PA13 19 // SWD
+#define PA14 20 // SWD
+#define PA15 21
+#define PB7 22
+#define PC13 23 // USER_BTN
+#define PC14 24
+#define PC15 25
+#define PH0 26
+#define PH1 27
+#define PC2 PIN_A9
+#define PC3 PIN_A10
+// CN7 Right Side
+#define PC11 30
+#define PB11 31
+// CN10 Left Side
+#define PC9 32
+// CN10 Right side
+#define PC8 33
+#define PC6 34
+#define PC5 PIN_A11
+#define PA12 36
+#define PA11 37
+#define PB12 38
+// 39 is NC
+#define PB2 40
+#define PB1 PIN_A12
+#define PB15 42
+#define PB14 43
+#define PB13 44
+#define PC4 PIN_A13
+#define PA0 PIN_A0
+#define PA1 PIN_A1
+#define PA4 PIN_A2
+#define PB0 PIN_A3
+#define PC1 PIN_A4
+#define PC0 PIN_A5
+
+// Alternate pins number
+#define PA2_ALT1 = (PA2 | ALT1)
+#define PA3_ALT1 = (PA3 | ALT1)
+#define PB9_ALT1 = (PB9 | ALT1)
+
+#define NUM_DIGITAL_PINS 52
+#define NUM_ANALOG_INPUTS 16
+
+// On-board LED pin number
+#ifndef LED_BUILTIN
+ #define LED_BUILTIN PA5
+#endif
+
+// On-board user button
+#ifndef USER_BTN
+ #define USER_BTN PC13
+#endif
+
+
+// Timer Definitions
+// Use TIM9/TIM11 when possible as servo and tone don't need GPIO output pin
+#ifndef TIMER_TONE
+ #define TIMER_TONE TIM6
+#endif
+#ifndef TIMER_SERVO
+ #define TIMER_SERVO TIM11
+#endif
+
+// UART Definitions
+#ifndef SERIAL_UART_INSTANCE
+ #define SERIAL_UART_INSTANCE 2 //Connected to ST-Link
+#endif
+
+// Default pin used for 'Serial' instance (ex: ST-Link)
+// Mandatory for Firmata
+#ifndef PIN_SERIAL_RX
+ #define PIN_SERIAL_RX PA3
+#endif
+#ifndef PIN_SERIAL_TX
+ #define PIN_SERIAL_TX PA2
+#endif
+
+/*----------------------------------------------------------------------------
+ * Arduino objects - C++ only
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ // These serial port names are intended to allow libraries and architecture-neutral
+ // sketches to automatically default to the correct port name for a particular type
+ // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
+ // the first hardware serial port whose RX/TX pins are not dedicated to another use.
+ //
+ // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor
+ //
+ // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial
+ //
+ // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library
+ //
+ // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins.
+ //
+ // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX
+ // pins are NOT connected to anything by default.
+ #define SERIAL_PORT_MONITOR Serial
+ #define SERIAL_PORT_HARDWARE Serial
+#endif
diff --git a/variants/STM32G0xx/G0B0CET/generic_clock.c b/variants/STM32G0xx/G0B0CET/generic_clock.c
index 879550021d..6099312c0a 100644
--- a/variants/STM32G0xx/G0B0CET/generic_clock.c
+++ b/variants/STM32G0xx/G0B0CET/generic_clock.c
@@ -22,6 +22,7 @@ WEAK void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
/** Configure the main internal regulator output voltage
*/
@@ -37,9 +38,9 @@ WEAK void SystemClock_Config(void)
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
- RCC_OscInitStruct.PLL.PLLN = 9;
+ RCC_OscInitStruct.PLL.PLLN = 12;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
- RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV3;
+ RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV3;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Error_Handler();
@@ -53,7 +54,13 @@ WEAK void SystemClock_Config(void)
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+ Error_Handler();
+ }
+
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
Error_Handler();
}
}
diff --git a/variants/STM32G0xx/G0B0RET/generic_clock.c b/variants/STM32G0xx/G0B0RET/generic_clock.c
index 700dc8bcb4..cbeccfbdbe 100644
--- a/variants/STM32G0xx/G0B0RET/generic_clock.c
+++ b/variants/STM32G0xx/G0B0RET/generic_clock.c
@@ -22,6 +22,7 @@ WEAK void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
/** Configure the main internal regulator output voltage
*/
@@ -37,9 +38,9 @@ WEAK void SystemClock_Config(void)
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
- RCC_OscInitStruct.PLL.PLLN = 9;
+ RCC_OscInitStruct.PLL.PLLN = 12;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
- RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV3;
+ RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV3;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Error_Handler();
@@ -53,7 +54,13 @@ WEAK void SystemClock_Config(void)
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+ Error_Handler();
+ }
+
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
Error_Handler();
}
}
diff --git a/variants/STM32G0xx/G0B0VET/generic_clock.c b/variants/STM32G0xx/G0B0VET/generic_clock.c
index 7f53a17a13..742f699b19 100644
--- a/variants/STM32G0xx/G0B0VET/generic_clock.c
+++ b/variants/STM32G0xx/G0B0VET/generic_clock.c
@@ -22,6 +22,7 @@ WEAK void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
/** Configure the main internal regulator output voltage
*/
@@ -37,9 +38,9 @@ WEAK void SystemClock_Config(void)
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
- RCC_OscInitStruct.PLL.PLLN = 9;
+ RCC_OscInitStruct.PLL.PLLN = 12;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
- RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV3;
+ RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV3;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Error_Handler();
@@ -53,7 +54,13 @@ WEAK void SystemClock_Config(void)
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+ Error_Handler();
+ }
+
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
Error_Handler();
}
}
diff --git a/variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)/variant_NUCLEO_G431RB.h b/variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)/variant_NUCLEO_G431RB.h
index f96d84e54e..a5969200c3 100644
--- a/variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)/variant_NUCLEO_G431RB.h
+++ b/variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)/variant_NUCLEO_G431RB.h
@@ -172,6 +172,7 @@
#define HAL_DAC_MODULE_ENABLED
#endif
+#define HSE_VALUE 24000000
/*----------------------------------------------------------------------------
* Arduino objects - C++ only
*----------------------------------------------------------------------------*/
diff --git a/variants/STM32L4xx/L412RB(I-T)xP/CMakeLists.txt b/variants/STM32L4xx/L412RB(I-T)xP/CMakeLists.txt
index 2a4d55b6b1..3eab75f214 100644
--- a/variants/STM32L4xx/L412RB(I-T)xP/CMakeLists.txt
+++ b/variants/STM32L4xx/L412RB(I-T)xP/CMakeLists.txt
@@ -22,6 +22,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL
generic_clock.c
PeripheralPins.c
variant_generic.cpp
+ variant_NUCLEO_L412RB_P.cpp
)
target_link_libraries(variant_bin PUBLIC variant_usage)
diff --git a/variants/STM32L4xx/L412RB(I-T)xP/ldscript.ld b/variants/STM32L4xx/L412RB(I-T)xP/ldscript.ld
new file mode 100644
index 0000000000..9eb56d5d17
--- /dev/null
+++ b/variants/STM32L4xx/L412RB(I-T)xP/ldscript.ld
@@ -0,0 +1,208 @@
+/*
+******************************************************************************
+**
+
+** File : LinkerScript.ld
+**
+** Author : STM32CubeMX
+**
+** Abstract : Linker script for STM32L412RBTxP series
+** 128Kbytes FLASH and 40Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : STMicroelectronics STM32
+** Distribution: The file is distributed “as is,” without any warranty
+** of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** © COPYRIGHT(c) 2025 STMicroelectronics
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+** 1. Redistributions of source code must retain the above copyright notice,
+** this list of conditions and the following disclaimer.
+** 2. Redistributions in binary form must reproduce the above copyright notice,
+** this list of conditions and the following disclaimer in the documentation
+** and/or other materials provided with the distribution.
+** 3. Neither the name of STMicroelectronics nor the names of its contributors
+** may be used to endorse or promote products derived from this software
+** without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+RAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 8K
+FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(8);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(8);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(8);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(8);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(8);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(8);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(8);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(8);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(8);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(8);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(8);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(8);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(8);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(8);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+
+ {
+ . = ALIGN(8);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(8);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(8);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(8);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+}
+
+
diff --git a/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.cpp b/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.cpp
new file mode 100644
index 0000000000..9b79190615
--- /dev/null
+++ b/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.cpp
@@ -0,0 +1,162 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2021, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#if defined(ARDUINO_NUCLEO_L412RB_P)
+#include "pins_arduino.h"
+
+// Digital PinName array
+const PinName digitalPin[] = {
+ PA_10,
+ PA_9,
+ PA_12,
+ PB_3,
+ PB_5,
+ PA_15,
+ PB_10,
+ PC_7,
+ PB_6,
+ PA_8,
+ PA_11,
+ PB_15,
+ PB_14,
+ PB_13, // LED
+ PB_7,
+ PB_8,
+ // ST Morpho
+ // CN5 Left Side
+ PC_10,
+ PC_12,
+ PB_12,
+ PA_13,
+ PA_14,
+ PC_13, // User Button
+ PC_14,
+ PC_15,
+ PH_0,
+ PH_1,
+ PB_4,
+ PB_9,
+ // CN5 Right Side
+ PC_11,
+ // CN6 Left Side
+ PC_9,
+ // CN6 Right Side
+ PC_8,
+ PC_6,
+ PB_0,
+ PB_11,
+ PB_2,
+ PB_1,
+ PA_7,
+ PA_6,
+ PA_5,
+ PA_4,
+ PC_4,
+ PA_3, // STLink Rx
+ PA_2, // STLink Tx
+ PA_0,
+ PA_1,
+ PC_3,
+ PC_2,
+ PC_1,
+ PC_0,
+ PH_3
+};
+
+// Analog (Ax) pin number array
+const uint32_t analogInputPin[] = {
+ 43, //A0
+ 44, //A1
+ 45, //A2
+ 46, //A3
+ 47, //A4
+ 48, //A5
+ 32, //A6
+ 35, //A7
+ 36, //A8
+ 37, //A9
+ 38, //A10
+ 39, //A11
+ 40 //A12
+};
+
+
+// ----------------------------------------------------------------------------
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+/**
+ * @brief System Clock Configuration
+ * @param None
+ * @retval None
+ */
+WEAK void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
+
+ /* Configure LSE Drive Capability */
+ HAL_PWR_EnableBkUpAccess();
+ __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
+ /*
+ * Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ /* MSI is enabled after System reset, activate PLL with MSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+ RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+ RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+ RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+ RCC_OscInitStruct.PLL.PLLM = 1;
+ RCC_OscInitStruct.PLL.PLLN = 40;
+ RCC_OscInitStruct.PLL.PLLR = RCC_PLLQ_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
+ clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+ Error_Handler();
+ }
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
+ Error_Handler();
+ }
+ /* Configure the main internal regulator output voltage */
+ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
+ Error_Handler();
+ }
+ /* Enable MSI Auto calibration */
+ HAL_RCCEx_EnableMSIPLLMode();
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ARDUINO_NUCLEO_L412RB_P */
diff --git a/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.h b/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.h
new file mode 100644
index 0000000000..a3bb945b4a
--- /dev/null
+++ b/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.h
@@ -0,0 +1,155 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2021, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#pragma once
+
+/*----------------------------------------------------------------------------
+ * Pins
+ *----------------------------------------------------------------------------*/
+
+#define PA10 0 // SB33 ON / SB32 OFF
+#define PA9 1 // SB35 ON / SB34 OFF
+#define PA12 2
+#define PB3 3
+#define PB5 4
+#define PA15 5
+#define PB10 6
+#define PC7 7
+#define PB6 8
+#define PA8 9
+#define PA11 10
+#define PB15 11
+#define PB14 12
+#define PB13 13 // LED
+#define PB7 14
+#define PB8 15
+// ST Morpho
+// CN5 Left Side
+#define PC10 16
+#define PC12 17
+#define PB12 18
+#define PA13 19
+#define PA14 20
+#define PC13 21 // User Button
+#define PC14 22
+#define PC15 23
+#define PH0 24
+#define PH1 25
+#define PB4 26
+#define PB9 27
+// CN5 Right Side
+#define PC11 28
+// CN6 Left Side
+#define PC9 29
+// CN6 Right Side
+#define PC8 30
+#define PC6 31
+#define PB0 PIN_A6
+#define PB11 33
+#define PB2 34
+#define PB1 PIN_A7
+#define PA7 PIN_A8
+#define PA6 PIN_A9
+#define PA5 PIN_A10
+#define PA4 PIN_A11
+#define PC4 PIN_A12
+#define PA3 41 // STLink Rx
+#define PA2 42 // STLink Tx
+#define PA0 PIN_A0
+#define PA1 PIN_A1
+#define PC3 PIN_A2
+#define PC2 PIN_A3
+#define PC1 PIN_A4
+#define PC0 PIN_A5
+#define PH3 49
+
+// Alternate pins number
+#define PA1_ALT1 (PA1 | ALT1)
+#define PA2_ALT1 (PA2 | ALT1)
+#define PA3_ALT1 (PA3 | ALT1)
+#define PA4_ALT1 (PA4 | ALT1)
+#define PA6_ALT1 (PA6 | ALT1)
+#define PA15_ALT1 (PA15 | ALT1)
+#define PB1_ALT1 (PB1 | ALT1)
+#define PB3_ALT1 (PB3 | ALT1)
+#define PB4_ALT1 (PB4 | ALT1)
+#define PB5_ALT1 (PB5 | ALT1)
+#define PB13_ALT1 (PB13 | ALT1)
+#define PB14_ALT1 (PB14 | ALT1)
+#define PB15_ALT1 (PB15 | ALT1)
+
+#define NUM_DIGITAL_PINS 50
+#define NUM_ANALOG_INPUTS 13
+
+// On-board LED pin number
+#ifndef LED_BUILTIN
+ #define LED_BUILTIN PB13
+#endif
+#ifndef LED_GREEN
+ #define LED_GREEN LED_BUILTIN
+#endif
+
+// On-board user button
+#ifndef USER_BTN
+ #define USER_BTN PC13
+#endif
+
+// Timer Definitions (optional)
+// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin
+#ifndef TIMER_TONE
+ #define TIMER_TONE TIM6
+#endif
+#ifndef TIMER_SERVO
+ #define TIMER_SERVO TIM16
+#endif
+
+// UART Definitions
+// Define here Serial instance number to map on Serial generic name
+#define SERIAL_UART_INSTANCE 101
+
+// Default pin used for 'Serial' instance (ex: ST-Link)
+// Mandatory for Firmata
+#ifndef PIN_SERIAL_RX
+ #define PIN_SERIAL_RX PA3
+#endif
+#ifndef PIN_SERIAL_TX
+ #define PIN_SERIAL_TX PA2
+#endif
+
+// Enable QSPI
+#if !defined(HAL_QSPI_MODULE_DISABLED)
+ #define HAL_QSPI_MODULE_ENABLED
+#endif
+
+/*----------------------------------------------------------------------------
+ * Arduino objects - C++ only
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ // These serial port names are intended to allow libraries and architecture-neutral
+ // sketches to automatically default to the correct port name for a particular type
+ // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
+ // the first hardware serial port whose RX/TX pins are not dedicated to another use.
+ //
+ // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor
+ //
+ // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial
+ //
+ // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library
+ //
+ // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins.
+ //
+ // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX
+ // pins are NOT connected to anything by default.
+ #define SERIAL_PORT_MONITOR Serial
+ #define SERIAL_PORT_HARDWARE Serial
+#endif
diff --git a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/CMakeLists.txt b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/CMakeLists.txt
index 2a4d55b6b1..656acd547b 100644
--- a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/CMakeLists.txt
+++ b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/CMakeLists.txt
@@ -21,7 +21,9 @@ target_link_libraries(variant INTERFACE variant_usage)
add_library(variant_bin STATIC EXCLUDE_FROM_ALL
generic_clock.c
PeripheralPins.c
+ PeripheralPins_STM32L562E_DK.c
variant_generic.cpp
+ variant_STM32L562E_DK.cpp
)
target_link_libraries(variant_bin PUBLIC variant_usage)
diff --git a/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/CMakeLists.txt b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/CMakeLists.txt
index 2a4d55b6b1..c91cbe25e0 100644
--- a/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/CMakeLists.txt
+++ b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/CMakeLists.txt
@@ -21,7 +21,9 @@ target_link_libraries(variant INTERFACE variant_usage)
add_library(variant_bin STATIC EXCLUDE_FROM_ALL
generic_clock.c
PeripheralPins.c
+ PeripheralPins_NUCLEO_U5A5ZJ_Q.c
variant_generic.cpp
+ variant_NUCLEO_U5A5ZJ_Q.cpp
)
target_link_libraries(variant_bin PUBLIC variant_usage)
diff --git a/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins_NUCLEO_U5A5ZJ_Q.c b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins_NUCLEO_U5A5ZJ_Q.c
new file mode 100644
index 0000000000..602a9e73cd
--- /dev/null
+++ b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins_NUCLEO_U5A5ZJ_Q.c
@@ -0,0 +1,675 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+/*
+ * Automatically generated from STM32U595ZITxQ.xml, STM32U595ZJTxQ.xml
+ * STM32U599ZITxQ.xml, STM32U599ZJTxQ.xml
+ * STM32U5A5ZJTxQ.xml, STM32U5A9ZJTxQ.xml
+ * CubeMX DB release 6.0.140
+ */
+#if defined(ARDUINO_NUCLEO_U5A5ZJ_Q)
+#include "Arduino.h"
+#include "PeripheralPins.h"
+
+/* =====
+ * Notes:
+ * - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+ * HW peripheral instances. You can use them the same way as any other "normal"
+ * pin (i.e. analogWrite(PA7_ALT1, 128);).
+ *
+ * - Commented lines are alternative possibilities which are not used per default.
+ * If you change them, you will have to know what you do
+ * =====
+ */
+
+//*** ADC ***
+
+#ifdef HAL_ADC_MODULE_ENABLED
+WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5
+ {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6
+ {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7
+ {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+ {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8
+ {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9
+ {PA_4_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC4_IN9
+ {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+ {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10
+ {PA_5_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC4_IN10
+ {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11
+ {PA_6_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC4_IN11
+ {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12
+ {PA_7_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC4_IN20
+ {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+ {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15
+ {PB_0_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC4_IN18
+ {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16
+ {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16
+ {PB_1_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC4_IN19
+ {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17
+ {PB_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC2_IN17
+ {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1
+ {PC_0_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC4_IN1
+ {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2
+ {PC_1_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC4_IN2
+ {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3
+ {PC_2_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC4_IN3
+ {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4
+ {PC_3_ALT2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC4_IN4
+ {PD_11, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC4_IN15
+ {PD_12, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC4_IN16
+ {PD_13, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC4_IN17
+ {PF_14, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC4_IN5
+ {PF_15, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC4_IN6
+ {PG_0, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC4_IN7
+ {PG_1, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC4_IN8
+ {NC, NP, 0}
+};
+#endif
+
+//*** DAC ***
+
+#ifdef HAL_DAC_MODULE_ENABLED
+WEAK const PinMap PinMap_DAC[] = {
+ {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1
+ {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2
+ {NC, NP, 0}
+};
+#endif
+
+//*** I2C ***
+
+#ifdef HAL_I2C_MODULE_ENABLED
+WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)},
+ {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PB_11_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)},
+ {PB_14, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PD_0, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C5)},
+ {PD_0_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)},
+ {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+ {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PF_0_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)},
+ {PF_15, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+ {PG_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PG_13, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_I2C_MODULE_ENABLED
+WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)},
+ {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PB_10_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)},
+ {PB_13, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PD_1, I2C5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C5)},
+ {PD_1_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)},
+ {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+ {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {PF_1_ALT1, I2C6, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C6)},
+ {PF_14, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+ {PG_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PG_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {NC, NP, 0}
+};
+#endif
+
+//*** No I3C ***
+
+//*** TIM ***
+
+#ifdef HAL_TIM_MODULE_ENABLED
+WEAK const PinMap PinMap_TIM[] = {
+ {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+ {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N
+ {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+ {PA_2_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1
+ {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+ {PA_3_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2
+ {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1
+ {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+ {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1
+ {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+ {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N
+ {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N
+ {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N
+ {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1
+ {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1
+ {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+ {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N
+ {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_14_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+ {PB_14_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1
+ {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+ {PB_15_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2
+ {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+ {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
+ {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+ {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+ {PD_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N
+ {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PE_0, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1
+ {PE_1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1
+ {PE_3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PE_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PE_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PE_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PE_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N
+ {PF_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PF_7, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+ {PF_8, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+ {PF_9, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+ {PF_9_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1
+ {PF_10, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2
+ {PG_9, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N
+ {PG_10, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1
+ {NC, NP, 0}
+};
+#endif
+
+//*** UART ***
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_7, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PC_3, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+ {PC_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+ {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PE_1, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+ {PF_0, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+ {PF_3, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PG_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PG_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PA_3_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)},
+ {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PC_2, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+ {PC_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+ {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PE_0, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+ {PF_1, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+ {PF_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PG_8, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PG_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PA_15_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PB_1_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PD_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+ {PE_4, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+ {PF_4, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+ {PG_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PG_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PA_6_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+ {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+ {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PC_0, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+ {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+ {PD_13, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+ {PE_3, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+ {PF_3, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)},
+ {PG_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+ {NC, NP, 0}
+};
+#endif
+
+//*** SPI ***
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)},
+ {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PD_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)},
+ {PE_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PG_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PE_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PG_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PG_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)},
+ {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PD_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)},
+ {PE_13, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PG_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PG_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PD_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PE_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PG_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PG_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NP, 0}
+};
+#endif
+
+//*** FDCAN ***
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+WEAK const PinMap PinMap_CAN_RD[] = {
+ {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)},
+ {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)},
+ {PD_0, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)},
+ {PF_7, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)},
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+WEAK const PinMap PinMap_CAN_TD[] = {
+ {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)},
+ {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)},
+ {PD_1, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)},
+ {PF_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)},
+ {NC, NP, 0}
+};
+#endif
+
+//*** No ETHERNET ***
+
+//*** OCTOSPI ***
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_DATA0[] = {
+ {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO0
+ {PE_12, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO0
+ {PF_0, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO0
+ {PF_8, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO0
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_DATA1[] = {
+ {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO1
+ {PE_13, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO1
+ {PF_1, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO1
+ {PF_9, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO1
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_DATA2[] = {
+ {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO2
+ {PE_14, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO2
+ {PF_2, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO2
+ {PF_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO2
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_DATA3[] = {
+ {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO3
+ {PE_15, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO3
+ {PF_3, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO3
+ {PF_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO3
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_DATA4[] = {
+ {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO4
+ {PD_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO4
+ {PG_0, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO4
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_DATA5[] = {
+ {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO5
+ {PD_5, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO5
+ {PG_1, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO5
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_DATA6[] = {
+ {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO6
+ {PD_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO6
+ {PG_9, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO6
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_DATA7[] = {
+ {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_IO7
+ {PD_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_IO7
+ {PG_10, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_IO7
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_SCLK[] = {
+ {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK
+ {PB_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK
+ {PE_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_CLK
+ {PF_4, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_CLK
+ {PF_10, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_CLK
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+WEAK const PinMap PinMap_OCTOSPI_SSEL[] = {
+ {PA_0, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI2)}, // OCTOSPIM_P2_NCS
+ {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS
+ {PA_4, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPIM_P1_NCS
+ {PA_12, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI2)}, // OCTOSPIM_P2_NCS
+ {PB_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS
+ {PC_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI1)}, // OCTOSPIM_P1_NCS
+ {PD_3, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI2)}, // OCTOSPIM_P2_NCS
+ {PE_11, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPIM_P1_NCS
+ {PF_6, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_NCS
+ {PG_12, OCTOSPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPI2)}, // OCTOSPIM_P2_NCS
+ {NC, NP, 0}
+};
+#endif
+
+//*** USB ***
+
+#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED)
+WEAK const PinMap PinMap_USB_OTG_HS[] = {
+#ifdef USE_USB_HS_IN_FS
+ // {PA_8, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_SOF
+ // {PA_9, USB_OTG_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS
+ // {PA_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_ID
+ {PA_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DM
+ {PA_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DP
+ // {PA_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_HS)}, // USB_OTG_HS_SOF
+#endif /* USE_USB_HS_IN_FS */
+ {NC, NP, 0}
+};
+#endif
+
+//*** SD ***
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_CMD[] = {
+ {PA_0, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC2)}, // SDMMC2_CMD
+ {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD
+ {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CMD
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_CK[] = {
+ {PC_1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC2)}, // SDMMC2_CK
+ {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK
+ {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_SDMMC2)}, // SDMMC2_CK
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA0[] = {
+ {PB_14, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D0
+ {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA1[] = {
+ {PB_15, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D1
+ {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA2[] = {
+ {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D2
+ {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA3[] = {
+ {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC2)}, // SDMMC2_D3
+ {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA4[] = {
+ {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4
+ {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D4
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA5[] = {
+ {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5
+ {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D5
+ {PC_0, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA6[] = {
+ {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6
+ {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D6
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_DATA7[] = {
+ {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7
+ {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_SDMMC2)}, // SDMMC2_D7
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_CKIN[] = {
+ {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_CKIN
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_CDIR[] = {
+ {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_CDIR
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_D0DIR[] = {
+ {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D0DIR
+ {NC, NP, 0}
+};
+#endif
+
+#ifdef HAL_SD_MODULE_ENABLED
+WEAK const PinMap PinMap_SD_D123DIR[] = {
+ {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SDMMC1)}, // SDMMC1_D123DIR
+ {NC, NP, 0}
+};
+#endif
+
+#endif /* ARDUINO_NUCLEO_U5A5ZJ_Q */
diff --git a/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/generic_clock.c b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/generic_clock.c
index 92586599f3..ea9b2d2688 100644
--- a/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/generic_clock.c
+++ b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/generic_clock.c
@@ -22,8 +22,65 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI
+ | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_MSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+ RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_0;
+ RCC_OscInitStruct.LSIDiv = RCC_LSI_DIV1;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+ RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV4;
+ RCC_OscInitStruct.PLL.PLLM = 3;
+ RCC_OscInitStruct.PLL.PLLN = 10;
+ RCC_OscInitStruct.PLL.PLLP = 4;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 1;
+ RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1;
+ RCC_OscInitStruct.PLL.PLLFRACN = 0;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
+ | RCC_CLOCKTYPE_PCLK3;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+ Error_Handler();
+ }
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC1
+ | RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_LPUART1;
+ PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
+ PeriphClkInit.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HSI;
+ PeriphClkInit.Dac1ClockSelection = RCC_DAC1CLKSOURCE_LSI;
+ PeriphClkInit.IclkClockSelection = RCC_CLK48CLKSOURCE_HSI48;
+
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/ldscript.ld b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/ldscript.ld
new file mode 100644
index 0000000000..25ad08b557
--- /dev/null
+++ b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/ldscript.ld
@@ -0,0 +1,166 @@
+/*
+******************************************************************************
+**
+** File : LinkerScript.ld
+**
+** Author : STM32CubeIDE
+**
+** Abstract : Linker script for STM32U595xI Device from STM32U5 series
+** 2048Kbytes FLASH
+** 2512Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is without any warranty
+** of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** Copyright (c) 2024 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K
+ FLASH (rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ KEEP(*(.isr_vector)) /* Startup code */
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } >FLASH
+ .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+
+ .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/variant_NUCLEO_U5A5ZJ_Q.cpp b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/variant_NUCLEO_U5A5ZJ_Q.cpp
new file mode 100644
index 0000000000..32dad1ca28
--- /dev/null
+++ b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/variant_NUCLEO_U5A5ZJ_Q.cpp
@@ -0,0 +1,270 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2021, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#if defined(ARDUINO_NUCLEO_U5A5ZJ_Q)
+#include "pins_arduino.h"
+
+// Digital PinName array
+const PinName digitalPin[] = {
+ PG_8, // D0
+ PG_7, // D1
+ PF_15, // D2/A9
+ PE_13, // D3
+ PF_14, // D4/A10
+ PE_11, // D5
+ PE_9, // D6
+ PF_13, // D7
+ PF_12, // D8
+ PD_15, // D9
+ PD_14, // D10
+ PA_7, // D11/A11
+ PA_6, // D12/A12
+ PA_5, // D13/A13
+ PB_9, // D14
+ PB_8, // D15
+ PC_6, // D16
+ PD_11, // D17/A14
+ PB_13, // D18
+ PD_12, // D19/A15
+ PA_4, // D20/A16
+ PB_4, // D21
+ PB_5, // D22
+ PB_3, // D23
+ PA_4, // D24
+ PB_4, // D25
+ PA_2, // D26
+ PB_10, // D27
+ PE_15, // D28
+ PB_0, // D29
+ PE_12, // D30
+ PE_14, // D31
+ PA_0, // D32/A17
+ PA_8, // D33
+ PE_0, // D34
+ PB_11, // D35
+ PB_10, // D36
+ PE_15, // D37
+ PE_14, // D38
+ PE_12, // D39
+ PE_10, // D40
+ PE_7, // D41
+ PE_8, // D42
+ PC_8, // D43
+ PC_9, // D44
+ PC_10, // D45
+ PC_11, // D46
+ PC_12, // D47
+ PD_2, // D48
+ PF_3, // D49
+ PF_5, // D50
+ PD_7, // D51
+ PD_6, // D52
+ PD_5, // D53
+ PD_4, // D54
+ PD_3, // D55
+ PE_2, // D56
+ PE_4, // D57
+ PE_5, // D58
+ PE_6, // D59
+ PE_3, // D60
+ PF_8, // D61
+ PF_7, // D62
+ PF_9, // D63
+ PG_1, // D64/A18
+ PG_0, // D65/A19
+ PD_1, // D66
+ PD_0, // D67
+ PF_0, // D68
+ PF_1, // D69
+ PF_2, // D70
+ PB_6, // D71
+ PB_2, // D72/A20
+ PA_3, // D73/A0
+ PA_2, // D74/A1
+ PC_3, // D75/A2
+ PB_0, // D76/A3
+ PC_1, // D77/A4
+ PC_0, // D78/A5
+ PB_1, // D79/A6
+ PC_2, // D80/A7
+ PA_1, // D81/A8
+ PA_9, // D82
+ PA_10, // D83
+ PA_11, // D84
+ PA_12, // D85
+ PA_13, // D86
+ PA_14, // D87
+ PA_15, // D88
+ PB_7, // D89
+ PB_14, // D90
+ PB_15, // D91
+ PC_7, // D92
+ PC_13, // D93
+ PC_14, // D94
+ PC_15, // D95
+ PD_8, // D96
+ PD_9, // D97
+ PD_10, // D98
+ PD_13, // D99/A21
+ PE_1, // D100
+ PF_4, // D101
+ PF_6, // D102
+ PF_10, // D103
+ PF_11, // D104
+ PG_2, // D105
+ PG_3, // D106
+ PG_4, // D107
+ PG_5, // D108
+ PG_6, // D109
+ PG_9, // D110
+ PG_10, // D111
+ PG_12, // D112
+ PG_13, // D113
+ PG_14, // D114
+ PG_15, // D115
+ PH_0, // D116
+ PH_1, // D117
+ PH_3 // D118
+};
+
+// Analog (Ax) pin number array
+const uint32_t analogInputPin[] = {
+ 73, // A0, PA3
+ 74, // A1, PA2
+ 75, // A2, PC3
+ 76, // A3, PB0
+ 77, // A4, PC1
+ 78, // A5, PC0
+ 79, // A6, PB1
+ 80, // A7, PC2
+ 81, // A8, PA1
+ 2, // A9, PF15
+ 4, // A10, PF14
+ 11, // A11, PA7
+ 12, // A12, PA6
+ 13, // A13, PA5
+ 17, // A14, PD11
+ 19, // A15, PD12
+ 20, // A16, PA4
+ 32, // A17, PA0
+ 64, // A18, PG1
+ 65, // A19, PG0
+ 72, // A20, PB2
+ 99 // A21, PD13
+};
+
+// ----------------------------------------------------------------------------
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** System Clock Configuration
+*/
+WEAK void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_CRSInitTypeDef RCC_CRSInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
+
+ /*
+ * Switch to SMPS regulator instead of LDO
+ */
+ if (HAL_PWREx_ConfigSupply(PWR_SMPS_SUPPLY) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Configure the main internal regulator output voltage
+ */
+ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Configure LSE Drive Capability
+ */
+ HAL_PWR_EnableBkUpAccess();
+ __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI
+ | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1;
+ RCC_OscInitStruct.PLL.PLLM = 1;
+ RCC_OscInitStruct.PLL.PLLN = 20;
+ RCC_OscInitStruct.PLL.PLLP = 8;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1;
+ RCC_OscInitStruct.PLL.PLLFRACN = 0;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
+ | RCC_CLOCKTYPE_PCLK3;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Enable the SYSCFG APB clock
+ */
+ __HAL_RCC_CRS_CLK_ENABLE();
+
+ /** Configures CRS
+ */
+ RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+ RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_LSE;
+ RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+ RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 32768);
+ RCC_CRSInitStruct.ErrorLimitValue = 34;
+ RCC_CRSInitStruct.HSI48CalibrationValue = 32;
+
+ HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_ADCDAC
+ | RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_LPUART1
+ | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_CLK48
+ | RCC_PERIPHCLK_USBPHY;
+ PeriphClkInit.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_SYSCLK;
+ PeriphClkInit.Dac1ClockSelection = RCC_DAC1CLKSOURCE_LSE;
+ PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
+ PeriphClkInit.IclkClockSelection = RCC_CLK48CLKSOURCE_HSI48;
+ PeriphClkInit.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_CLK48;
+ PeriphClkInit.UsbPhyClockSelection = RCC_USBPHYCLKSOURCE_HSE;
+
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
+ Error_Handler();
+ }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ARDUINO_NUCLEO_U5A5ZJ_Q */
diff --git a/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/variant_NUCLEO_U5A5ZJ_Q.h b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/variant_NUCLEO_U5A5ZJ_Q.h
new file mode 100644
index 0000000000..e6f8bd4f05
--- /dev/null
+++ b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/variant_NUCLEO_U5A5ZJ_Q.h
@@ -0,0 +1,296 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2021, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#pragma once
+
+/*----------------------------------------------------------------------------
+ * STM32 pins number
+ *----------------------------------------------------------------------------*/
+#define PG8 0
+#define PG7 1
+#define PF15 PIN_A9
+#define PE13 3
+#define PF14 PIN_A10
+#define PE11 5
+#define PE9 6
+#define PF13 7
+#define PF12 8
+#define PD15 9
+#define PD14 10
+#define PA7 PIN_A11
+#define PA6 PIN_A12
+#define PA5 PIN_A13
+#define PB9 14
+#define PB8 15
+#define PC6 16
+#define PD11 PIN_A14
+#define PB13 18
+#define PD12 PIN_A15
+#define PA4 PIN_A16 // SB35 ON
+#define PB4 21 // SB36 ON
+#define PB5 22 // UCPD TCPP
+#define PB3 23
+// 24 is PA4 (20) as default SB38 ON
+// 25 is PB4 (21) as default SB43 ON
+// 26 is PA2 (A1) as default SB57 ON
+#define PB10 27 // SB61 ON
+#define PE15 28 // SB66 ON
+// 29 is PB0 (A3) as default SB63 ON
+#define PE12 30 // SB68 ON
+#define PE14 31 // SB70 ON
+#define PA0 PIN_A17
+#define PA8 33
+#define PE0 34
+#define PB11 35
+// 36 is PB10 (27) as default SB62 ON
+// 37 is PE15 (28) as default SB67 ON
+// 38 is PE14 (31) as default SB71 ON
+// 39 is PE12 (30) as default SB69 ON
+#define PE10 40
+#define PE7 41
+#define PE8 42
+#define PC8 43
+#define PC9 44
+#define PC10 45
+#define PC11 46
+#define PC12 47
+#define PD2 48
+#define PF3 49
+#define PF5 50
+#define PD7 51
+#define PD6 52
+#define PD5 53
+#define PD4 54
+#define PD3 55
+#define PE2 56
+#define PE4 57
+#define PE5 58
+#define PE6 59
+#define PE3 60
+#define PF8 61
+#define PF7 62
+#define PF9 63
+#define PG1 PIN_A18
+#define PG0 PIN_A19
+#define PD1 66
+#define PD0 67
+#define PF0 68
+#define PF1 69
+#define PF2 70
+#define PB6 71
+#define PB2 PIN_A20
+#define PA3 PIN_A0
+#define PA2 PIN_A1 // SB57 ON
+#define PC3 PIN_A2
+#define PB0 PIN_A3 // SB64 ON
+#define PC1 PIN_A4
+#define PC0 PIN_A5
+#define PB1 PIN_A6
+#define PC2 PIN_A7
+#define PA1 PIN_A8
+
+#define PA9 82
+#define PA10 83
+#define PA11 84
+#define PA12 85
+#define PA13 86
+#define PA14 87
+#define PA15 88
+#define PB7 89
+#define PB14 90
+#define PB15 91
+#define PC7 92
+#define PC13 93
+#define PC14 94
+#define PC15 95
+#define PD8 96
+#define PD9 97
+#define PD10 98
+#define PD13 PIN_A21
+#define PE1 100
+#define PF4 101
+#define PF6 102
+#define PF10 103
+#define PF11 104
+#define PG2 105
+#define PG3 106
+#define PG4 107
+#define PG5 108
+#define PG6 109
+#define PG9 110
+#define PG10 111
+#define PG12 112
+#define PG13 113
+#define PG14 114
+#define PG15 115
+#define PH0 116
+#define PH1 117
+#define PH3 118 // BOOT0
+
+// Alternate pins number
+#define PA0_ALT1 (PA0 | ALT1)
+#define PA1_ALT1 (PA1 | ALT1)
+#define PA1_ALT2 (PA1 | ALT2)
+#define PA2_ALT1 (PA2 | ALT1)
+#define PA2_ALT2 (PA2 | ALT2)
+#define PA3_ALT1 (PA3 | ALT1)
+#define PA3_ALT2 (PA3 | ALT2)
+#define PA4_ALT1 (PA4 | ALT1)
+#define PA5_ALT1 (PA5 | ALT1)
+#define PA6_ALT1 (PA6 | ALT1)
+#define PA7_ALT1 (PA7 | ALT1)
+#define PA7_ALT2 (PA7 | ALT2)
+#define PA7_ALT3 (PA7 | ALT3)
+#define PA15_ALT1 (PA15 | ALT1)
+#define PB0_ALT1 (PB0 | ALT1)
+#define PB0_ALT2 (PB0 | ALT2)
+#define PB1_ALT1 (PB1 | ALT1)
+#define PB1_ALT2 (PB1 | ALT2)
+#define PB3_ALT1 (PB3 | ALT1)
+#define PB4_ALT1 (PB4 | ALT1)
+#define PB5_ALT1 (PB5 | ALT1)
+#define PB6_ALT1 (PB6 | ALT1)
+#define PB7_ALT1 (PB7 | ALT1)
+#define PB8_ALT1 (PB8 | ALT1)
+#define PB8_ALT2 (PB8 | ALT2)
+#define PB9_ALT1 (PB9 | ALT1)
+#define PB9_ALT2 (PB9 | ALT2)
+#define PB10_ALT1 (PB10 | ALT1)
+#define PB11_ALT1 (PB11 | ALT1)
+#define PB13_ALT1 (PB13 | ALT1)
+#define PB14_ALT1 (PB14 | ALT1)
+#define PB14_ALT2 (PB14 | ALT2)
+#define PB15_ALT1 (PB15 | ALT1)
+#define PB15_ALT2 (PB15 | ALT2)
+#define PC0_ALT1 (PC0 | ALT1)
+#define PC1_ALT1 (PC1 | ALT1)
+#define PC2_ALT1 (PC2 | ALT1)
+#define PC3_ALT1 (PC3 | ALT1)
+#define PC6_ALT1 (PC6 | ALT1)
+#define PC6_ALT2 (PC6 | ALT2)
+#define PC7_ALT1 (PC7 | ALT1)
+#define PC7_ALT2 (PC7 | ALT2)
+#define PC8_ALT1 (PC8 | ALT1)
+#define PC9_ALT1 (PC9 | ALT1)
+#define PC10_ALT1 (PC10 | ALT1)
+#define PC11_ALT1 (PC11 | ALT1)
+#define PF9_ALT1 (PF9 | ALT1)
+
+#define NUM_DIGITAL_PINS 119
+#define NUM_ANALOG_INPUTS 22
+
+// On-board LED pin number
+#ifndef LED_LD1
+ // SB21 ON/SB23 OFF (default) else PA5 with SB21 OFF/SB23 ON
+ #define LED_LD1 PC7
+#endif
+#define LED_LD2 PB7
+#define LED_LD3 PG2
+
+#define LED_GREEN LED_LD1
+#define LED_BLUE LED_LD2
+#define LED_RED LED_LD3
+
+#ifndef LED_BUILTIN
+ #define LED_BUILTIN LED_GREEN
+#endif
+
+// On-board user button
+#ifndef B1_USER
+ // SB58 ON/SB59 OFF (default) else PA0 with SB58 OFF/SB59 ON
+ #define B1_USER PC13
+#endif
+#ifndef USER_BTN
+ #define USER_BTN B1_USER
+#endif
+
+// Timer Definitions
+// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin
+#ifndef TIMER_TONE
+ #define TIMER_TONE TIM6
+#endif
+#ifndef TIMER_SERVO
+ #define TIMER_SERVO TIM7
+#endif
+
+// UART Definitions
+#ifndef SERIAL_UART_INSTANCE
+ #define SERIAL_UART_INSTANCE 1
+#endif
+
+// Default pin used for generic 'Serial' instance
+// Mandatory for Firmata
+#ifndef PIN_SERIAL_RX
+ #define PIN_SERIAL_RX PA10
+#endif
+#ifndef PIN_SERIAL_TX
+ #define PIN_SERIAL_TX PA9
+#endif
+
+// Pin UCPD to configure TCPP in default Type-C legacy state (UCPD_DBn for TCPP01)
+#define PIN_UCPD_TCPP PB5
+
+// Extra HAL modules
+#if !defined(HAL_DAC_MODULE_DISABLED)
+ #define HAL_DAC_MODULE_ENABLED
+#endif
+#if !defined(HAL_OSPI_MODULE_DISABLED)
+ #define HAL_OSPI_MODULE_ENABLED
+#endif
+#if !defined(HAL_SD_MODULE_DISABLED)
+ #define HAL_SD_MODULE_ENABLED
+#endif
+
+// Alternate SYS_WKUP definition
+#define PWR_WAKEUP_PIN1_1
+#define PWR_WAKEUP_PIN1_2
+#define PWR_WAKEUP_PIN2_1
+#define PWR_WAKEUP_PIN2_2
+#define PWR_WAKEUP_PIN3_1
+#define PWR_WAKEUP_PIN3_2
+#define PWR_WAKEUP_PIN4_1
+#define PWR_WAKEUP_PIN4_2
+#define PWR_WAKEUP_PIN5_1
+#define PWR_WAKEUP_PIN6_1
+#define PWR_WAKEUP_PIN6_2
+#define PWR_WAKEUP_PIN7_1
+#define PWR_WAKEUP_PIN7_2
+#define PWR_WAKEUP_PIN8_1
+#define PWR_WAKEUP_PIN8_2
+
+/*----------------------------------------------------------------------------
+ * Arduino objects - C++ only
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ // These serial port names are intended to allow libraries and architecture-neutral
+ // sketches to automatically default to the correct port name for a particular type
+ // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
+ // the first hardware serial port whose RX/TX pins are not dedicated to another use.
+ //
+ // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor
+ //
+ // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial
+ //
+ // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library
+ //
+ // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins.
+ //
+ // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX
+ // pins are NOT connected to anything by default.
+ #ifndef SERIAL_PORT_MONITOR
+ #define SERIAL_PORT_MONITOR Serial
+ #endif
+ #ifndef SERIAL_PORT_HARDWARE
+ #define SERIAL_PORT_HARDWARE Serial
+ #endif
+#endif